Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18149

1

T7

55

T8

14

T13

37

auto[1]

12475

1

T1

14

T27

84

T28

255

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3475	1			T27	81		T28	40		T156	12
values[1]	3963	1			T28	42		T40	40		T17	28
values[2]	3664	1			T26	10		T28	55		T78	10
values[3]	4241	1			T1	14		T28	180		T39	10
values[4]	4072	1			T7	55		T27	25		T37	24
values[5]	3327	1			T8	14		T27	40		T40	20
values[6]	3891	1			T13	37		T27	55		T28	27
values[7]	3991	1			T27	52		T28	52		T208	4

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3168	1			T1	14		T8	14		T27	20
values[1]	3424	1			T27	20		T209	6		T100	4
values[2]	3813	1			T13	37		T26	10		T28	27
values[3]	4059	1			T7	55		T27	20		T28	40
values[4]	3982	1			T27	55		T28	40		T37	24
values[5]	4045	1			T27	113		T28	193		T39	10
values[6]	3402	1			T27	25		T28	54		T40	20
values[7]	4731	1			T28	20		T184	16		T40	40

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	346	1			T19	13		T53	19		T177	16
auto[0]	values[0]	values[1]	214	1			T100	4		T42	7		T20	12
auto[0]	values[0]	values[2]	198	1			T210	13		T165	9		T211	10
auto[0]	values[0]	values[3]	132	1			T28	7		T156	12		T205	18
auto[0]	values[0]	values[4]	109	1			T28	13		T18	5		T171	10
auto[0]	values[0]	values[5]	396	1			T27	64		T74	10		T20	14
auto[0]	values[0]	values[6]	189	1			T77	12		T170	13		T76	6
auto[0]	values[0]	values[7]	385	1			T191	13		T212	6		T172	13
auto[0]	values[1]	values[0]	190	1			T28	14		T40	10		T178	10
auto[0]	values[1]	values[1]	187	1			T41	11		T53	9		T48	13
auto[0]	values[1]	values[2]	336	1			T17	13		T41	16		T48	10
auto[0]	values[1]	values[3]	369	1			T28	12		T42	12		T213	14
auto[0]	values[1]	values[4]	337	1			T19	20		T48	14		T183	92
auto[0]	values[1]	values[5]	277	1			T42	9		T20	11		T177	14
auto[0]	values[1]	values[6]	277	1			T40	16		T20	14		T169	11
auto[0]	values[1]	values[7]	354	1			T41	8		T20	13		T153	9
auto[0]	values[2]	values[0]	221	1			T51	12		T170	13		T214	6
auto[0]	values[2]	values[1]	189	1			T19	10		T20	17		T48	10
auto[0]	values[2]	values[2]	425	1			T26	10		T78	10		T42	59
auto[0]	values[2]	values[3]	333	1			T18	11		T42	7		T142	14
auto[0]	values[2]	values[4]	222	1			T154	11		T215	14		T179	8
auto[0]	values[2]	values[5]	273	1			T28	27		T216	4		T19	53
auto[0]	values[2]	values[6]	201	1			T28	13		T41	12		T77	16
auto[0]	values[2]	values[7]	192	1			T40	11		T57	6		T75	16
auto[0]	values[3]	values[0]	202	1			T177	5		T217	6		T77	15
auto[0]	values[3]	values[1]	336	1			T40	8		T20	14		T153	7
auto[0]	values[3]	values[2]	280	1			T40	11		T153	15		T77	12
auto[0]	values[3]	values[3]	389	1			T40	15		T19	55		T173	8
auto[0]	values[3]	values[4]	452	1			T28	12		T48	10		T154	17
auto[0]	values[3]	values[5]	254	1			T28	10		T79	20		T48	13
auto[0]	values[3]	values[6]	263	1			T53	28		T114	9		T177	10
auto[0]	values[3]	values[7]	361	1			T184	16		T207	6		T165	12
auto[0]	values[4]	values[0]	259	1			T40	15		T42	11		T169	11
auto[0]	values[4]	values[1]	180	1			T19	13		T218	18		T191	10
auto[0]	values[4]	values[2]	161	1			T177	10		T77	22		T171	13
auto[0]	values[4]	values[3]	482	1			T7	55		T40	28		T42	146
auto[0]	values[4]	values[4]	305	1			T153	18		T219	6		T191	10
auto[0]	values[4]	values[5]	276	1			T20	17		T191	14		T170	14
auto[0]	values[4]	values[6]	250	1			T27	19		T18	8		T53	12
auto[0]	values[4]	values[7]	653	1			T41	15		T220	14		T154	10
auto[0]	values[5]	values[0]	138	1			T8	14		T53	19		T221	10
auto[0]	values[5]	values[1]	300	1			T27	7		T20	17		T204	14
auto[0]	values[5]	values[2]	162	1			T48	8		T169	11		T77	15
auto[0]	values[5]	values[3]	182	1			T27	11		T40	15		T48	14
auto[0]	values[5]	values[4]	295	1			T191	12		T77	12		T170	9
auto[0]	values[5]	values[5]	278	1			T19	11		T153	27		T179	6
auto[0]	values[5]	values[6]	244	1			T202	18		T20	9		T169	7
auto[0]	values[5]	values[7]	361	1			T20	13		T48	11		T153	12
auto[0]	values[6]	values[0]	366	1			T27	11		T155	24		T222	6
auto[0]	values[6]	values[1]	298	1			T41	27		T153	50		T171	17
auto[0]	values[6]	values[2]	494	1			T13	37		T28	9		T223	4
auto[0]	values[6]	values[3]	298	1			T20	11		T53	13		T179	11
auto[0]	values[6]	values[4]	348	1			T27	25		T20	10		T165	10
auto[0]	values[6]	values[5]	268	1			T153	17		T224	2		T172	17
auto[0]	values[6]	values[6]	204	1			T149	17		T153	12		T154	11
auto[0]	values[6]	values[7]	320	1			T40	15		T17	7		T18	27
auto[0]	values[7]	values[0]	185	1			T208	4		T18	9		T19	80
auto[0]	values[7]	values[1]	173	1			T48	20		T154	9		T170	8
auto[0]	values[7]	values[2]	207	1			T41	10		T77	14		T203	21
auto[0]	values[7]	values[3]	273	1			T18	8		T153	30		T154	12
auto[0]	values[7]	values[4]	325	1			T27	10		T41	11		T48	14
auto[0]	values[7]	values[5]	374	1			T27	22		T41	23		T191	13
auto[0]	values[7]	values[6]	345	1			T28	10		T171	6		T165	6
auto[0]	values[7]	values[7]	256	1			T28	14		T19	22		T200	4
auto[1]	values[0]	values[0]	209	1			T19	7		T53	7		T177	4
auto[1]	values[0]	values[1]	125	1			T42	13		T20	9		T179	13
auto[1]	values[0]	values[2]	245	1			T210	7		T165	11		T203	9
auto[1]	values[0]	values[3]	150	1			T28	13		T177	5		T171	9
auto[1]	values[0]	values[4]	99	1			T28	7		T18	23		T171	10
auto[1]	values[0]	values[5]	193	1			T27	17		T20	15		T153	5
auto[1]	values[0]	values[6]	113	1			T77	8		T170	7		T225	11
auto[1]	values[0]	values[7]	372	1			T191	7		T172	7		T193	6
auto[1]	values[1]	values[0]	104	1			T28	8		T40	10		T170	6
auto[1]	values[1]	values[1]	230	1			T41	9		T53	27		T48	7
auto[1]	values[1]	values[2]	178	1			T17	15		T41	11		T48	10
auto[1]	values[1]	values[3]	217	1			T28	8		T42	113		T213	12
auto[1]	values[1]	values[4]	294	1			T19	5		T48	38		T177	9
auto[1]	values[1]	values[5]	188	1			T42	33		T20	9		T177	9
auto[1]	values[1]	values[6]	200	1			T40	4		T20	12		T169	13
auto[1]	values[1]	values[7]	225	1			T41	27		T20	7		T153	18
auto[1]	values[2]	values[0]	112	1			T170	9		T210	6		T172	9
auto[1]	values[2]	values[1]	156	1			T19	10		T20	7		T48	10
auto[1]	values[2]	values[2]	198	1			T42	11		T77	10		T179	10
auto[1]	values[2]	values[3]	452	1			T18	9		T42	71		T142	73
auto[1]	values[2]	values[4]	131	1			T154	9		T226	8		T179	12
auto[1]	values[2]	values[5]	217	1			T28	6		T19	6		T48	9
auto[1]	values[2]	values[6]	188	1			T28	9		T41	8		T77	4
auto[1]	values[2]	values[7]	154	1			T40	9		T179	6		T142	7
auto[1]	values[3]	values[0]	200	1			T1	14		T177	22		T77	5
auto[1]	values[3]	values[1]	254	1			T40	12		T20	6		T153	13
auto[1]	values[3]	values[2]	245	1			T40	9		T153	35		T77	8
auto[1]	values[3]	values[3]	152	1			T40	5		T19	7		T169	10
auto[1]	values[3]	values[4]	190	1			T28	8		T48	10		T154	3
auto[1]	values[3]	values[5]	352	1			T28	150		T39	10		T48	8
auto[1]	values[3]	values[6]	126	1			T53	6		T114	11		T177	15
auto[1]	values[3]	values[7]	185	1			T165	8		T146	7		T227	4
auto[1]	values[4]	values[0]	224	1			T40	5		T42	78		T169	9
auto[1]	values[4]	values[1]	133	1			T19	7		T191	10		T228	2
auto[1]	values[4]	values[2]	189	1			T177	10		T77	18		T171	7
auto[1]	values[4]	values[3]	159	1			T40	12		T42	11		T146	7
auto[1]	values[4]	values[4]	190	1			T37	24		T153	2		T191	10
auto[1]	values[4]	values[5]	171	1			T20	9		T191	6		T170	20
auto[1]	values[4]	values[6]	182	1			T27	6		T18	13		T53	8
auto[1]	values[4]	values[7]	258	1			T41	54		T220	6		T154	10
auto[1]	values[5]	values[0]	51	1			T53	8		T198	14		T229	8
auto[1]	values[5]	values[1]	236	1			T27	13		T20	4		T77	9
auto[1]	values[5]	values[2]	157	1			T48	30		T169	9		T77	5
auto[1]	values[5]	values[3]	109	1			T27	9		T40	5		T48	10
auto[1]	values[5]	values[4]	154	1			T191	8		T77	8		T170	11
auto[1]	values[5]	values[5]	175	1			T19	10		T153	6		T179	18
auto[1]	values[5]	values[6]	187	1			T20	11		T169	13		T170	13
auto[1]	values[5]	values[7]	298	1			T20	7		T48	9		T153	8
auto[1]	values[6]	values[0]	172	1			T27	9		T186	8		T230	12
auto[1]	values[6]	values[1]	203	1			T209	6		T41	7		T153	8
auto[1]	values[6]	values[2]	201	1			T28	18		T18	8		T42	7
auto[1]	values[6]	values[3]	162	1			T20	13		T53	7		T179	29
auto[1]	values[6]	values[4]	154	1			T27	10		T20	10		T231	12
auto[1]	values[6]	values[5]	153	1			T153	87		T172	3		T146	13
auto[1]	values[6]	values[6]	99	1			T149	9		T153	27		T154	9
auto[1]	values[6]	values[7]	151	1			T40	5		T17	18		T18	13
auto[1]	values[7]	values[0]	189	1			T18	21		T151	2		T19	13
auto[1]	values[7]	values[1]	210	1			T48	3		T154	29		T170	12
auto[1]	values[7]	values[2]	137	1			T41	10		T77	6		T203	7
auto[1]	values[7]	values[3]	200	1			T18	13		T153	7		T154	8
auto[1]	values[7]	values[4]	377	1			T27	10		T41	9		T48	6
auto[1]	values[7]	values[5]	200	1			T27	10		T41	8		T191	7
auto[1]	values[7]	values[6]	334	1			T28	22		T171	99		T165	14
auto[1]	values[7]	values[7]	206	1			T28	6		T19	4		T172	9