Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	406	1			T27	1		T28	4		T78	2
auto[ReadAddrCrossIntoMailbox]	330	1			T27	1		T28	5		T40	5
auto[ReadAddrCrossOutOfMailbox]	325	1			T27	4		T28	7		T40	2
auto[ReadAddrCrossAllMailbox]	196	1			T28	2		T40	3		T18	2
auto[ReadAddrOutsideMailbox]	3485	1			T1	4		T7	2		T8	4

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2399

1

T1

2

T7

1

T8

2

auto[1]

2343

1

T1

2

T7

1

T8

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	780	1			T8	2		T27	8		T28	13
read_ops[0x0b]	787	1			T7	2		T26	2		T27	8
read_ops[0x3b]	790	1			T8	2		T26	2		T27	1
read_ops[0x6b]	787	1			T1	2		T27	4		T28	3
read_ops[0xbb]	817	1			T1	2		T27	5		T28	11
read_ops[0xeb]	781	1			T27	11		T28	8		T100	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	31	1			T154	1		T201	1		T194	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	29	1			T28	1		T40	2		T20	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	20	1			T48	2		T177	1		T170	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	27	1			T77	1		T142	1		T165	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	27	1			T28	2		T48	1		T154	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	16	1			T48	1		T153	1		T177	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T42	1		T194	1		T179	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T191	1		T77	2		T170	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	303	1			T8	1		T27	1		T28	7
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	294	1			T8	1		T27	7		T28	3
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	32	1			T27	1		T28	1		T78	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	39	1			T28	1		T78	1		T18	3
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	22	1			T28	1		T40	1		T20	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	28	1			T27	1		T48	2		T154	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	25	1			T27	1		T48	1		T77	2
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	32	1			T28	1		T20	2		T191	2
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	13	1			T28	1		T77	1		T142	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	23	1			T48	1		T154	2		T172	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	301	1			T7	1		T26	1		T27	3
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	272	1			T7	1		T26	1		T27	2
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	23	1			T40	1		T20	1		T169	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	43	1			T154	1		T191	1		T177	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	37	1			T28	1		T40	1		T42	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	42	1			T40	1		T18	1		T153	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	22	1			T28	1		T153	1		T191	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	25	1			T28	1		T40	1		T18	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	11	1			T203	1		T232	1		T233	2
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T28	1		T40	1		T42	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	276	1			T8	1		T26	1		T28	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	295	1			T8	1		T26	1		T27	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	37	1			T40	1		T216	1		T153	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	23	1			T40	1		T41	1		T18	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	26	1			T40	1		T42	4		T20	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	24	1			T28	1		T194	1		T142	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	35	1			T40	1		T19	1		T20	2
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	28	1			T42	1		T20	1		T48	2
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T20	1		T177	1		T75	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	22	1			T40	1		T20	1		T154	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	275	1			T1	1		T27	4		T28	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	302	1			T1	1		T28	1		T37	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	37	1			T42	1		T177	1		T75	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	39	1			T20	1		T153	4		T177	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	33	1			T42	2		T20	2		T53	2
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	22	1			T48	1		T234	1		T210	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	33	1			T27	1		T28	1		T153	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	19	1			T75	1		T77	1		T142	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T18	2		T42	1		T20	2
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	14	1			T40	1		T234	1		T142	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	311	1			T1	1		T27	2		T28	7
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	290	1			T1	1		T27	2		T28	3
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	37	1			T28	1		T100	1		T40	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	36	1			T100	1		T42	1		T48	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	24	1			T28	2		T41	1		T48	2
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	25	1			T40	1		T191	1		T170	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	35	1			T27	2		T28	1		T41	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	28	1			T48	1		T154	1		T191	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T142	2		T144	1		T235	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	14	1			T53	1		T153	1		T154	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	306	1			T27	7		T28	2		T40	2
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	260	1			T27	2		T28	2		T40	5