| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING | 
| 100.00 | 1 | 100 | 1 | 64 | 64 | 
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 8 | 0 | 8 | 100.00 | 
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_flip_position | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
| cp_opcode | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 | 
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 2 | 0 | 2 | 100.00 | 
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| auto[0] | 108 | 1 | T3 | 8 | T84 | 1 | T115 | 1 | ||||
| auto[1] | 39 | 1 | T3 | 3 | T271 | 1 | T272 | 4 | 
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 6 | 0 | 6 | 100.00 | 
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| read_ops[0x03] | 28 | 1 | T3 | 8 | T271 | 2 | T273 | 2 | ||||
| read_ops[0x0b] | 27 | 1 | T84 | 1 | T115 | 1 | T271 | 2 | ||||
| read_ops[0x3b] | 15 | 1 | T272 | 2 | T274 | 2 | T275 | 6 | ||||
| read_ops[0x6b] | 23 | 1 | T3 | 1 | T272 | 4 | T275 | 6 | ||||
| read_ops[0xbb] | 26 | 1 | T3 | 2 | T275 | 1 | T276 | 2 | ||||
| read_ops[0xeb] | 28 | 1 | T272 | 8 | T275 | 2 | T277 | 3 | 
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |