Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	893	1			T14	21		T15	10		T16	21
all_values[1]	893	1			T14	21		T15	10		T16	21
all_values[2]	893	1			T14	21		T15	10		T16	21
all_values[3]	893	1			T14	21		T15	10		T16	21
all_values[4]	893	1			T14	21		T15	10		T16	21
all_values[5]	893	1			T14	21		T15	10		T16	21
all_values[6]	893	1			T14	21		T15	10		T16	21
all_values[7]	893	1			T14	21		T15	10		T16	21

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3815

1

T14

92

T15

38

T16

93

auto[1]

3329

1

T14

76

T15

42

T16

75

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2781

1

T14

60

T15

26

T16

70

auto[1]

4363

1

T14

108

T15

54

T16

98

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4030

1

T14

95

T15

44

T16

103

auto[1]

3114

1

T14

73

T15

36

T16

65

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	190	1			T14	4		T15	2		T16	2
all_values[0]	auto[0]	auto[0]	auto[1]	87	1			T14	3		T16	5		T17	3
all_values[0]	auto[0]	auto[1]	auto[0]	156	1			T14	5		T15	1		T16	1
all_values[0]	auto[0]	auto[1]	auto[1]	82	1			T15	3		T16	4		T17	3
all_values[0]	auto[1]	auto[0]	auto[1]	197	1			T14	6		T15	1		T16	6
all_values[0]	auto[1]	auto[1]	auto[1]	181	1			T14	3		T15	3		T16	3
all_values[1]	auto[0]	auto[0]	auto[0]	182	1			T14	4		T16	3		T17	9
all_values[1]	auto[0]	auto[0]	auto[1]	90	1			T14	2		T15	2		T16	5
all_values[1]	auto[0]	auto[1]	auto[0]	127	1			T14	5		T15	2		T16	2
all_values[1]	auto[0]	auto[1]	auto[1]	90	1			T14	4		T15	2		T16	1
all_values[1]	auto[1]	auto[0]	auto[1]	222	1			T14	5		T15	1		T16	6
all_values[1]	auto[1]	auto[1]	auto[1]	182	1			T14	1		T15	3		T16	4
all_values[2]	auto[0]	auto[0]	auto[0]	203	1			T14	7		T15	4		T16	8
all_values[2]	auto[0]	auto[0]	auto[1]	87	1			T14	2		T15	2		T16	1
all_values[2]	auto[0]	auto[1]	auto[0]	157	1			T14	4		T16	4		T17	2
all_values[2]	auto[0]	auto[1]	auto[1]	76	1			T15	2		T16	2		T17	2
all_values[2]	auto[1]	auto[0]	auto[1]	216	1			T14	4		T15	1		T16	3
all_values[2]	auto[1]	auto[1]	auto[1]	154	1			T14	4		T15	1		T16	3
all_values[3]	auto[0]	auto[0]	auto[0]	156	1			T14	1		T15	2		T16	6
all_values[3]	auto[0]	auto[0]	auto[1]	104	1			T14	3		T17	2		T143	2
all_values[3]	auto[0]	auto[1]	auto[0]	135	1			T14	1		T15	1		T16	3
all_values[3]	auto[0]	auto[1]	auto[1]	101	1			T14	5		T15	1		T16	5
all_values[3]	auto[1]	auto[0]	auto[1]	210	1			T14	7		T15	3		T16	5
all_values[3]	auto[1]	auto[1]	auto[1]	187	1			T14	4		T15	3		T16	2
all_values[4]	auto[0]	auto[0]	auto[0]	172	1			T14	3		T15	2		T16	7
all_values[4]	auto[0]	auto[0]	auto[1]	83	1			T14	4		T15	1		T16	2
all_values[4]	auto[0]	auto[1]	auto[0]	173	1			T14	3		T15	4		T16	2
all_values[4]	auto[0]	auto[1]	auto[1]	96	1			T14	2		T16	1		T17	1
all_values[4]	auto[1]	auto[0]	auto[1]	190	1			T14	5		T16	7		T17	5
all_values[4]	auto[1]	auto[1]	auto[1]	179	1			T14	4		T15	3		T16	2
all_values[5]	auto[0]	auto[0]	auto[0]	239	1			T14	7		T15	3		T16	7
all_values[5]	auto[0]	auto[1]	auto[0]	250	1			T14	4		T15	2		T16	6
all_values[5]	auto[1]	auto[0]	auto[1]	210	1			T14	3		T15	3		T16	3
all_values[5]	auto[1]	auto[1]	auto[1]	194	1			T14	7		T15	2		T16	5
all_values[6]	auto[0]	auto[0]	auto[0]	172	1			T16	4		T17	6		T19	2
all_values[6]	auto[0]	auto[0]	auto[1]	81	1			T14	3		T15	1		T16	3
all_values[6]	auto[0]	auto[1]	auto[0]	152	1			T14	4		T15	1		T16	5
all_values[6]	auto[0]	auto[1]	auto[1]	81	1			T14	2		T15	1		T16	2
all_values[6]	auto[1]	auto[0]	auto[1]	219	1			T14	7		T15	4		T16	3
all_values[6]	auto[1]	auto[1]	auto[1]	188	1			T14	5		T15	3		T16	4
all_values[7]	auto[0]	auto[0]	auto[0]	194	1			T14	4		T15	2		T16	5
all_values[7]	auto[0]	auto[0]	auto[1]	102	1			T14	3		T15	1		T17	2
all_values[7]	auto[0]	auto[1]	auto[0]	123	1			T14	4		T16	5		T17	2
all_values[7]	auto[0]	auto[1]	auto[1]	89	1			T14	2		T15	2		T16	2
all_values[7]	auto[1]	auto[0]	auto[1]	209	1			T14	5		T15	3		T16	2
all_values[7]	auto[1]	auto[1]	auto[1]	176	1			T14	3		T15	2		T16	7

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal