Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1837

1

T4

8

T6

1

T12

10

auto[1]

1788

1

T4

11

T6

1

T12

2

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1995

1

T4

10

T24

4

T28

4

auto[1]

1630

1

T4

9

T6

2

T12

12

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2877

1

T4

17

T6

2

T12

12

auto[1]

748

1

T4

2

T24

2

T28

1

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	726	1			T4	3		T12	5		T24	2
valid[1]	701	1			T4	2		T24	1		T25	2
valid[2]	744	1			T4	3		T6	2		T12	1
valid[3]	705	1			T4	4		T12	3		T24	1
valid[4]	749	1			T4	7		T12	3		T24	1

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	129	1			T4	1		T24	1		T43	2
auto[0]	auto[0]	valid[0]	auto[1]	164	1			T12	3		T25	1		T30	1
auto[0]	auto[0]	valid[1]	auto[0]	112	1			T29	1		T43	4		T46	1
auto[0]	auto[0]	valid[1]	auto[1]	167	1			T4	1		T25	1		T30	1
auto[0]	auto[0]	valid[2]	auto[0]	128	1			T33	2		T45	1		T15	3
auto[0]	auto[0]	valid[2]	auto[1]	144	1			T6	1		T12	1		T34	3
auto[0]	auto[0]	valid[3]	auto[0]	133	1			T4	1		T33	1		T45	1
auto[0]	auto[0]	valid[3]	auto[1]	171	1			T4	1		T12	3		T28	1
auto[0]	auto[0]	valid[4]	auto[0]	118	1			T4	2		T33	1		T15	2
auto[0]	auto[0]	valid[4]	auto[1]	167	1			T4	2		T12	3		T24	1
auto[0]	auto[1]	valid[0]	auto[0]	121	1			T4	2		T15	4		T17	1
auto[0]	auto[1]	valid[0]	auto[1]	159	1			T12	2		T25	2		T30	2
auto[0]	auto[1]	valid[1]	auto[0]	127	1			T4	1		T28	1		T33	1
auto[0]	auto[1]	valid[1]	auto[1]	150	1			T25	1		T34	1		T72	1
auto[0]	auto[1]	valid[2]	auto[0]	132	1			T4	1		T24	1		T28	1
auto[0]	auto[1]	valid[2]	auto[1]	182	1			T4	1		T6	1		T24	1
auto[0]	auto[1]	valid[3]	auto[0]	124	1			T43	1		T15	5		T16	1
auto[0]	auto[1]	valid[3]	auto[1]	146	1			T4	2		T24	1		T34	2
auto[0]	auto[1]	valid[4]	auto[0]	123	1			T28	1		T44	2		T15	3
auto[0]	auto[1]	valid[4]	auto[1]	180	1			T4	2		T28	1		T30	1
auto[1]	auto[0]	valid[0]	auto[0]	79	1			T43	2		T45	1		T18	3
auto[1]	auto[0]	valid[1]	auto[0]	81	1			T24	1		T15	1		T18	2
auto[1]	auto[0]	valid[2]	auto[0]	84	1			T43	1		T45	1		T15	1
auto[1]	auto[0]	valid[3]	auto[0]	72	1			T16	1		T18	2		T286	1
auto[1]	auto[0]	valid[4]	auto[0]	88	1			T44	1		T15	1		T17	1
auto[1]	auto[1]	valid[0]	auto[0]	74	1			T24	1		T33	1		T43	1
auto[1]	auto[1]	valid[1]	auto[0]	64	1			T28	1		T33	1		T44	1
auto[1]	auto[1]	valid[2]	auto[0]	74	1			T4	1		T33	1		T44	1
auto[1]	auto[1]	valid[3]	auto[0]	59	1			T29	1		T43	1		T15	1
auto[1]	auto[1]	valid[4]	auto[0]	73	1			T4	1		T43	2		T44	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal