Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

50042

1

T4

335

T6

22

T24

120

auto[1]

16639

1

T4

69

T6

9

T12

12

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48437

1

T4

260

T6

18

T12

12

auto[1]

18244

1

T4

144

T6

13

T24

45

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	34218	1			T4	189		T6	16		T12	12
others[1]	5581	1			T4	35		T6	1		T24	13
others[2]	5542	1			T4	38		T6	4		T24	16
others[3]	6493	1			T4	41		T6	2		T24	11
interest[1]	3786	1			T4	19		T6	4		T24	7
interest[4]	22516	1			T4	132		T6	7		T12	12
interest[64]	11061	1			T4	82		T6	4		T24	17

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	16086	1			T4	86		T6	6		T24	38
auto[0]	auto[0]	others[1]	2726	1			T4	20		T24	8		T28	9
auto[0]	auto[0]	others[2]	2608	1			T4	13		T24	10		T28	10
auto[0]	auto[0]	others[3]	3109	1			T4	21		T6	1		T24	7
auto[0]	auto[0]	interest[1]	1830	1			T4	8		T6	1		T24	3
auto[0]	auto[0]	interest[4]	10568	1			T4	66		T6	2		T24	27
auto[0]	auto[0]	interest[64]	5439	1			T4	43		T6	1		T24	9
auto[0]	auto[1]	others[0]	8686	1			T4	33		T6	4		T12	12
auto[0]	auto[1]	others[1]	1333	1			T4	6		T24	1		T28	4
auto[0]	auto[1]	others[2]	1355	1			T4	8		T6	3		T24	1
auto[0]	auto[1]	others[3]	1609	1			T4	7		T24	1		T28	6
auto[0]	auto[1]	interest[1]	915	1			T4	2		T6	1		T24	1
auto[0]	auto[1]	interest[4]	5808	1			T4	25		T6	2		T12	12
auto[0]	auto[1]	interest[64]	2741	1			T4	13		T6	1		T24	3
auto[1]	auto[0]	others[0]	9446	1			T4	70		T6	6		T24	25
auto[1]	auto[0]	others[1]	1522	1			T4	9		T6	1		T24	4
auto[1]	auto[0]	others[2]	1579	1			T4	17		T6	1		T24	5
auto[1]	auto[0]	others[3]	1775	1			T4	13		T6	1		T24	3
auto[1]	auto[0]	interest[1]	1041	1			T4	9		T6	2		T24	3
auto[1]	auto[0]	interest[4]	6140	1			T4	41		T6	3		T24	20
auto[1]	auto[0]	interest[64]	2881	1			T4	26		T6	2		T24	5

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal