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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.03 98.38 94.02 98.62 89.36 97.19 95.45 99.21


Total test records in report: 1131
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T96 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.3081752232 Jul 23 07:24:35 PM PDT 24 Jul 23 07:24:44 PM PDT 24 579934600 ps
T1031 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.3569470964 Jul 23 07:25:06 PM PDT 24 Jul 23 07:25:08 PM PDT 24 32196346 ps
T1032 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.3625184205 Jul 23 07:24:15 PM PDT 24 Jul 23 07:24:18 PM PDT 24 103565684 ps
T1033 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.3224373245 Jul 23 07:24:58 PM PDT 24 Jul 23 07:25:00 PM PDT 24 17793948 ps
T98 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2227700499 Jul 23 07:24:41 PM PDT 24 Jul 23 07:24:45 PM PDT 24 146434610 ps
T83 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.687251971 Jul 23 07:24:26 PM PDT 24 Jul 23 07:24:29 PM PDT 24 101466512 ps
T1034 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.1357810364 Jul 23 07:23:58 PM PDT 24 Jul 23 07:23:59 PM PDT 24 13424210 ps
T1035 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.3469298908 Jul 23 07:25:05 PM PDT 24 Jul 23 07:25:07 PM PDT 24 31765826 ps
T93 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2103698768 Jul 23 07:23:59 PM PDT 24 Jul 23 07:24:02 PM PDT 24 81455840 ps
T108 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.528292955 Jul 23 07:24:41 PM PDT 24 Jul 23 07:24:44 PM PDT 24 161572489 ps
T1036 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.1719646973 Jul 23 07:24:26 PM PDT 24 Jul 23 07:24:28 PM PDT 24 14802328 ps
T86 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.767952215 Jul 23 07:24:39 PM PDT 24 Jul 23 07:24:41 PM PDT 24 60464178 ps
T140 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.3286857595 Jul 23 07:24:47 PM PDT 24 Jul 23 07:24:50 PM PDT 24 209326467 ps
T1037 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.753712554 Jul 23 07:23:58 PM PDT 24 Jul 23 07:24:00 PM PDT 24 28091698 ps
T162 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.128348452 Jul 23 07:24:44 PM PDT 24 Jul 23 07:25:02 PM PDT 24 1692844906 ps
T1038 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3234034934 Jul 23 07:24:44 PM PDT 24 Jul 23 07:24:47 PM PDT 24 20581984 ps
T163 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.3478982650 Jul 23 07:24:43 PM PDT 24 Jul 23 07:24:52 PM PDT 24 448701075 ps
T1039 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3545272101 Jul 23 07:24:39 PM PDT 24 Jul 23 07:24:42 PM PDT 24 104543479 ps
T1040 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3092109629 Jul 23 07:24:49 PM PDT 24 Jul 23 07:24:53 PM PDT 24 86040861 ps
T88 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.283383171 Jul 23 07:24:45 PM PDT 24 Jul 23 07:24:51 PM PDT 24 460064649 ps
T69 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.262365305 Jul 23 07:24:17 PM PDT 24 Jul 23 07:24:19 PM PDT 24 142642996 ps
T85 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.2136003276 Jul 23 07:24:12 PM PDT 24 Jul 23 07:24:15 PM PDT 24 359504386 ps
T157 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.2082225600 Jul 23 07:24:42 PM PDT 24 Jul 23 07:25:01 PM PDT 24 829214615 ps
T109 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3146018224 Jul 23 07:24:13 PM PDT 24 Jul 23 07:24:36 PM PDT 24 323812923 ps
T1041 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.2673561231 Jul 23 07:24:26 PM PDT 24 Jul 23 07:24:29 PM PDT 24 530135528 ps
T89 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.4117593714 Jul 23 07:24:14 PM PDT 24 Jul 23 07:24:18 PM PDT 24 218887288 ps
T1042 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.1725568 Jul 23 07:24:03 PM PDT 24 Jul 23 07:24:40 PM PDT 24 7843189928 ps
T1043 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.487760734 Jul 23 07:25:05 PM PDT 24 Jul 23 07:25:07 PM PDT 24 14327100 ps
T1044 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.3006738650 Jul 23 07:24:05 PM PDT 24 Jul 23 07:24:06 PM PDT 24 76046057 ps
T87 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.1357502833 Jul 23 07:24:47 PM PDT 24 Jul 23 07:24:51 PM PDT 24 346323043 ps
T1045 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.2815361591 Jul 23 07:24:15 PM PDT 24 Jul 23 07:24:17 PM PDT 24 11144555 ps
T141 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.2597286278 Jul 23 07:24:16 PM PDT 24 Jul 23 07:24:21 PM PDT 24 608191369 ps
T160 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.967685227 Jul 23 07:24:36 PM PDT 24 Jul 23 07:25:01 PM PDT 24 5162639527 ps
T1046 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.441359037 Jul 23 07:25:02 PM PDT 24 Jul 23 07:25:04 PM PDT 24 11875968 ps
T161 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.2398524111 Jul 23 07:24:25 PM PDT 24 Jul 23 07:24:46 PM PDT 24 596894836 ps
T1047 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.3677098624 Jul 23 07:25:00 PM PDT 24 Jul 23 07:25:02 PM PDT 24 12367054 ps
T70 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1426394765 Jul 23 07:24:14 PM PDT 24 Jul 23 07:24:17 PM PDT 24 228427271 ps
T110 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2803623479 Jul 23 07:24:14 PM PDT 24 Jul 23 07:24:18 PM PDT 24 74865027 ps
T95 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3939346403 Jul 23 07:24:37 PM PDT 24 Jul 23 07:24:41 PM PDT 24 434178181 ps
T97 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.18100836 Jul 23 07:24:53 PM PDT 24 Jul 23 07:24:58 PM PDT 24 140923264 ps
T1048 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.46775788 Jul 23 07:25:02 PM PDT 24 Jul 23 07:25:04 PM PDT 24 19528252 ps
T1049 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.4150358871 Jul 23 07:24:07 PM PDT 24 Jul 23 07:24:10 PM PDT 24 54612471 ps
T111 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.266145946 Jul 23 07:24:49 PM PDT 24 Jul 23 07:24:54 PM PDT 24 146219567 ps
T1050 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.460074381 Jul 23 07:24:38 PM PDT 24 Jul 23 07:24:41 PM PDT 24 231185411 ps
T1051 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.3939381559 Jul 23 07:24:43 PM PDT 24 Jul 23 07:24:47 PM PDT 24 38612626 ps
T1052 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.4052460248 Jul 23 07:24:35 PM PDT 24 Jul 23 07:24:39 PM PDT 24 141728101 ps
T1053 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2087740542 Jul 23 07:25:07 PM PDT 24 Jul 23 07:25:08 PM PDT 24 19389121 ps
T1054 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.4015615624 Jul 23 07:24:26 PM PDT 24 Jul 23 07:24:30 PM PDT 24 107744803 ps
T1055 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2056390328 Jul 23 07:24:42 PM PDT 24 Jul 23 07:24:45 PM PDT 24 581070224 ps
T158 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2095097602 Jul 23 07:24:45 PM PDT 24 Jul 23 07:25:08 PM PDT 24 615369126 ps
T92 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.2359545687 Jul 23 07:24:34 PM PDT 24 Jul 23 07:24:36 PM PDT 24 50713918 ps
T1056 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2757677538 Jul 23 07:24:14 PM PDT 24 Jul 23 07:24:17 PM PDT 24 204608468 ps
T1057 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.771681927 Jul 23 07:24:24 PM PDT 24 Jul 23 07:24:30 PM PDT 24 630153102 ps
T1058 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1244721157 Jul 23 07:24:52 PM PDT 24 Jul 23 07:24:59 PM PDT 24 317762577 ps
T1059 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.1169461683 Jul 23 07:24:06 PM PDT 24 Jul 23 07:24:08 PM PDT 24 12896758 ps
T71 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.1738119812 Jul 23 07:24:04 PM PDT 24 Jul 23 07:24:06 PM PDT 24 103523916 ps
T1060 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3953280609 Jul 23 07:24:42 PM PDT 24 Jul 23 07:24:49 PM PDT 24 73245516 ps
T1061 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2974147402 Jul 23 07:23:59 PM PDT 24 Jul 23 07:24:03 PM PDT 24 134057833 ps
T1062 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2626607481 Jul 23 07:24:52 PM PDT 24 Jul 23 07:24:56 PM PDT 24 517161617 ps
T1063 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.622708710 Jul 23 07:25:02 PM PDT 24 Jul 23 07:25:04 PM PDT 24 16454916 ps
T1064 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.1410483554 Jul 23 07:24:45 PM PDT 24 Jul 23 07:24:48 PM PDT 24 50729639 ps
T1065 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1742844562 Jul 23 07:24:25 PM PDT 24 Jul 23 07:24:27 PM PDT 24 24230890 ps
T1066 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2673896265 Jul 23 07:24:14 PM PDT 24 Jul 23 07:24:43 PM PDT 24 1233331801 ps
T1067 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.2976657006 Jul 23 07:24:38 PM PDT 24 Jul 23 07:24:42 PM PDT 24 111233550 ps
T1068 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.1959933256 Jul 23 07:24:45 PM PDT 24 Jul 23 07:24:51 PM PDT 24 66559324 ps
T1069 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.2898463029 Jul 23 07:25:07 PM PDT 24 Jul 23 07:25:08 PM PDT 24 48834477 ps
T1070 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.1861790054 Jul 23 07:23:56 PM PDT 24 Jul 23 07:23:59 PM PDT 24 261452117 ps
T1071 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.4066408493 Jul 23 07:24:59 PM PDT 24 Jul 23 07:25:01 PM PDT 24 25615768 ps
T1072 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1711071958 Jul 23 07:25:00 PM PDT 24 Jul 23 07:25:03 PM PDT 24 14694267 ps
T1073 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.1241664909 Jul 23 07:24:58 PM PDT 24 Jul 23 07:25:00 PM PDT 24 51515395 ps
T1074 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.2013012351 Jul 23 07:24:59 PM PDT 24 Jul 23 07:25:00 PM PDT 24 18335751 ps
T1075 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3082284591 Jul 23 07:25:00 PM PDT 24 Jul 23 07:25:02 PM PDT 24 69492165 ps
T1076 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.1739137170 Jul 23 07:25:00 PM PDT 24 Jul 23 07:25:02 PM PDT 24 51312123 ps
T1077 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3925773218 Jul 23 07:23:57 PM PDT 24 Jul 23 07:23:59 PM PDT 24 55574528 ps
T1078 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.940654582 Jul 23 07:24:49 PM PDT 24 Jul 23 07:24:53 PM PDT 24 69066294 ps
T1079 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3727034611 Jul 23 07:24:12 PM PDT 24 Jul 23 07:24:16 PM PDT 24 392148865 ps
T1080 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.1593795658 Jul 23 07:24:44 PM PDT 24 Jul 23 07:24:47 PM PDT 24 17282620 ps
T1081 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.300636728 Jul 23 07:24:45 PM PDT 24 Jul 23 07:24:51 PM PDT 24 581073987 ps
T1082 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.872630085 Jul 23 07:24:43 PM PDT 24 Jul 23 07:24:46 PM PDT 24 59906219 ps
T1083 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2933627856 Jul 23 07:24:57 PM PDT 24 Jul 23 07:24:59 PM PDT 24 61369593 ps
T90 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.754400963 Jul 23 07:24:44 PM PDT 24 Jul 23 07:25:07 PM PDT 24 3180014006 ps
T1084 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.2152900469 Jul 23 07:25:04 PM PDT 24 Jul 23 07:25:06 PM PDT 24 16612127 ps
T1085 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2402206008 Jul 23 07:24:42 PM PDT 24 Jul 23 07:24:44 PM PDT 24 40126813 ps
T1086 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.270013685 Jul 23 07:25:00 PM PDT 24 Jul 23 07:25:03 PM PDT 24 18071306 ps
T159 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.2895992307 Jul 23 07:24:51 PM PDT 24 Jul 23 07:25:10 PM PDT 24 2182773274 ps
T1087 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.883390574 Jul 23 07:24:45 PM PDT 24 Jul 23 07:24:49 PM PDT 24 80569001 ps
T1088 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.2119154288 Jul 23 07:24:16 PM PDT 24 Jul 23 07:24:18 PM PDT 24 33543465 ps
T1089 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.147466829 Jul 23 07:24:25 PM PDT 24 Jul 23 07:24:30 PM PDT 24 160504940 ps
T1090 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.4181658362 Jul 23 07:25:01 PM PDT 24 Jul 23 07:25:04 PM PDT 24 11780133 ps
T1091 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3746320424 Jul 23 07:24:29 PM PDT 24 Jul 23 07:24:32 PM PDT 24 99536821 ps
T1092 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.4093971556 Jul 23 07:24:06 PM PDT 24 Jul 23 07:24:07 PM PDT 24 11520128 ps
T1093 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.923092866 Jul 23 07:24:05 PM PDT 24 Jul 23 07:24:09 PM PDT 24 191463032 ps
T1094 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1382306791 Jul 23 07:24:06 PM PDT 24 Jul 23 07:24:21 PM PDT 24 832517347 ps
T1095 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2390043772 Jul 23 07:24:13 PM PDT 24 Jul 23 07:24:15 PM PDT 24 25062520 ps
T1096 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.955469454 Jul 23 07:25:00 PM PDT 24 Jul 23 07:25:02 PM PDT 24 29624732 ps
T1097 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.1777375458 Jul 23 07:25:09 PM PDT 24 Jul 23 07:25:10 PM PDT 24 16159066 ps
T1098 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2397666064 Jul 23 07:23:57 PM PDT 24 Jul 23 07:24:02 PM PDT 24 163026321 ps
T1099 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2200027343 Jul 23 07:24:45 PM PDT 24 Jul 23 07:24:48 PM PDT 24 27114678 ps
T1100 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.2105127788 Jul 23 07:24:49 PM PDT 24 Jul 23 07:24:54 PM PDT 24 46120016 ps
T1101 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.2175257799 Jul 23 07:24:26 PM PDT 24 Jul 23 07:24:30 PM PDT 24 421364497 ps
T1102 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.426183745 Jul 23 07:24:14 PM PDT 24 Jul 23 07:24:17 PM PDT 24 29505539 ps
T1103 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.3839664917 Jul 23 07:24:51 PM PDT 24 Jul 23 07:24:53 PM PDT 24 12427812 ps
T1104 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1833120946 Jul 23 07:23:55 PM PDT 24 Jul 23 07:23:57 PM PDT 24 206949642 ps
T1105 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3593845989 Jul 23 07:24:00 PM PDT 24 Jul 23 07:24:02 PM PDT 24 1090834894 ps
T1106 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.3627091418 Jul 23 07:24:37 PM PDT 24 Jul 23 07:24:39 PM PDT 24 28047372 ps
T1107 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1105470568 Jul 23 07:24:26 PM PDT 24 Jul 23 07:24:30 PM PDT 24 68886106 ps
T91 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.99090457 Jul 23 07:23:56 PM PDT 24 Jul 23 07:24:12 PM PDT 24 1210952085 ps
T1108 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1393000832 Jul 23 07:24:51 PM PDT 24 Jul 23 07:24:55 PM PDT 24 35854604 ps
T1109 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3971661266 Jul 23 07:24:47 PM PDT 24 Jul 23 07:24:49 PM PDT 24 21525452 ps
T1110 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3856245846 Jul 23 07:24:24 PM PDT 24 Jul 23 07:24:46 PM PDT 24 3312702825 ps
T1111 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1965641364 Jul 23 07:24:13 PM PDT 24 Jul 23 07:24:26 PM PDT 24 1152532216 ps
T1112 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1207325691 Jul 23 07:24:50 PM PDT 24 Jul 23 07:25:14 PM PDT 24 1029560865 ps
T1113 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.745089014 Jul 23 07:24:52 PM PDT 24 Jul 23 07:24:56 PM PDT 24 60434678 ps
T1114 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1293669866 Jul 23 07:24:52 PM PDT 24 Jul 23 07:24:57 PM PDT 24 99256513 ps
T1115 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.2523637839 Jul 23 07:23:55 PM PDT 24 Jul 23 07:24:18 PM PDT 24 2283084780 ps
T1116 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.2344070658 Jul 23 07:24:05 PM PDT 24 Jul 23 07:24:11 PM PDT 24 661241656 ps
T1117 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1121257841 Jul 23 07:24:37 PM PDT 24 Jul 23 07:24:38 PM PDT 24 15510156 ps
T1118 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.4027274121 Jul 23 07:25:00 PM PDT 24 Jul 23 07:25:03 PM PDT 24 13119616 ps
T1119 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.3636404049 Jul 23 07:24:15 PM PDT 24 Jul 23 07:24:34 PM PDT 24 5592784941 ps
T1120 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.3436116192 Jul 23 07:24:25 PM PDT 24 Jul 23 07:24:44 PM PDT 24 585829686 ps
T1121 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.1583891896 Jul 23 07:24:35 PM PDT 24 Jul 23 07:24:38 PM PDT 24 26165100 ps
T1122 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.737618407 Jul 23 07:24:05 PM PDT 24 Jul 23 07:24:29 PM PDT 24 7552415834 ps
T1123 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.4166313532 Jul 23 07:24:42 PM PDT 24 Jul 23 07:24:46 PM PDT 24 697963835 ps
T1124 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.2544554777 Jul 23 07:25:00 PM PDT 24 Jul 23 07:25:03 PM PDT 24 41199162 ps
T1125 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.826656355 Jul 23 07:24:13 PM PDT 24 Jul 23 07:24:15 PM PDT 24 22832163 ps
T1126 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1260471534 Jul 23 07:24:13 PM PDT 24 Jul 23 07:24:18 PM PDT 24 61759343 ps
T1127 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.1207262933 Jul 23 07:24:25 PM PDT 24 Jul 23 07:24:28 PM PDT 24 1410506348 ps
T1128 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.1979794969 Jul 23 07:24:59 PM PDT 24 Jul 23 07:25:01 PM PDT 24 14290074 ps
T1129 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.3896369581 Jul 23 07:24:41 PM PDT 24 Jul 23 07:24:44 PM PDT 24 269452130 ps
T1130 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.938004014 Jul 23 07:24:27 PM PDT 24 Jul 23 07:24:46 PM PDT 24 306662142 ps
T1131 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.3673956629 Jul 23 07:24:43 PM PDT 24 Jul 23 07:24:46 PM PDT 24 194733381 ps

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.3747270612
Short name T4
Test name
Test status
Simulation time 90348713090 ps
CPU time 267.48 seconds
Started Jul 23 07:08:08 PM PDT 24
Finished Jul 23 07:12:36 PM PDT 24
Peak memory 263856 kb
Host smart-cdabf0e4-c561-4c55-99d0-9be6d5fa2852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747270612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.3747270612
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.2813423465
Short name T28
Test name
Test status
Simulation time 3600287164 ps
CPU time 91.16 seconds
Started Jul 23 07:08:21 PM PDT 24
Finished Jul 23 07:09:53 PM PDT 24
Peak memory 253516 kb
Host smart-9f183545-1566-4781-bc89-739948f07da6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813423465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.2813423465
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.1960689007
Short name T15
Test name
Test status
Simulation time 45874191332 ps
CPU time 160.24 seconds
Started Jul 23 07:06:01 PM PDT 24
Finished Jul 23 07:08:43 PM PDT 24
Peak memory 265816 kb
Host smart-e68f3722-a844-4e8f-9922-d827200714cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960689007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.1960689007
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2227700499
Short name T98
Test name
Test status
Simulation time 146434610 ps
CPU time 3.74 seconds
Started Jul 23 07:24:41 PM PDT 24
Finished Jul 23 07:24:45 PM PDT 24
Peak memory 218456 kb
Host smart-0718a5fb-b57c-4e58-b76b-6cd4ad11c9c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227700499 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.2227700499
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.2137767385
Short name T20
Test name
Test status
Simulation time 56228281917 ps
CPU time 596.81 seconds
Started Jul 23 07:06:56 PM PDT 24
Finished Jul 23 07:16:54 PM PDT 24
Peak memory 264444 kb
Host smart-d5c8b896-0e45-4090-ad86-1fb618fb92a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137767385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.2137767385
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.3150024067
Short name T63
Test name
Test status
Simulation time 18667405 ps
CPU time 0.77 seconds
Started Jul 23 07:04:53 PM PDT 24
Finished Jul 23 07:04:55 PM PDT 24
Peak memory 216104 kb
Host smart-5b39f8cc-7262-4e4c-ac60-5d8028ef8077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150024067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.3150024067
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.3591330413
Short name T18
Test name
Test status
Simulation time 313669983439 ps
CPU time 738.28 seconds
Started Jul 23 07:07:02 PM PDT 24
Finished Jul 23 07:19:22 PM PDT 24
Peak memory 265116 kb
Host smart-8031f335-0080-471f-9ee7-edafd48af36a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591330413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.3591330413
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.783023364
Short name T153
Test name
Test status
Simulation time 149933432606 ps
CPU time 531.42 seconds
Started Jul 23 07:07:45 PM PDT 24
Finished Jul 23 07:16:38 PM PDT 24
Peak memory 268312 kb
Host smart-024cdb55-2044-4144-a09c-40bb132477fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783023364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.783023364
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.681722625
Short name T144
Test name
Test status
Simulation time 223121647759 ps
CPU time 453.65 seconds
Started Jul 23 07:06:18 PM PDT 24
Finished Jul 23 07:13:54 PM PDT 24
Peak memory 282268 kb
Host smart-8128192a-4f1e-4805-a8f5-6d771f468a54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681722625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stres
s_all.681722625
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.3961013745
Short name T9
Test name
Test status
Simulation time 177743280 ps
CPU time 0.95 seconds
Started Jul 23 07:05:14 PM PDT 24
Finished Jul 23 07:05:18 PM PDT 24
Peak memory 235744 kb
Host smart-b15d3da5-1017-4d33-affb-a9a3fa59676e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961013745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.3961013745
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.2755255924
Short name T77
Test name
Test status
Simulation time 3730636953 ps
CPU time 96.51 seconds
Started Jul 23 07:06:57 PM PDT 24
Finished Jul 23 07:08:34 PM PDT 24
Peak memory 254492 kb
Host smart-f0a7ade9-aef8-4b3c-bc61-0770e46cc58d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755255924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmd
s.2755255924
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.200324580
Short name T3
Test name
Test status
Simulation time 26722269731 ps
CPU time 70.42 seconds
Started Jul 23 07:06:50 PM PDT 24
Finished Jul 23 07:08:03 PM PDT 24
Peak memory 250988 kb
Host smart-a9be74ee-1675-4172-a751-a4333714b76f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200324580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.200324580
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.1916420381
Short name T48
Test name
Test status
Simulation time 82965392678 ps
CPU time 679.13 seconds
Started Jul 23 07:06:01 PM PDT 24
Finished Jul 23 07:17:22 PM PDT 24
Peak memory 264800 kb
Host smart-315e77ff-ef15-4ee2-bf72-cf939ec1c645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916420381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.1916420381
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.2876069533
Short name T146
Test name
Test status
Simulation time 6635000944 ps
CPU time 142.26 seconds
Started Jul 23 07:06:45 PM PDT 24
Finished Jul 23 07:09:09 PM PDT 24
Peak memory 265816 kb
Host smart-09eab266-828c-42a3-90de-62471c787e46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876069533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.2876069533
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.149624315
Short name T62
Test name
Test status
Simulation time 1297530286 ps
CPU time 15.17 seconds
Started Jul 23 07:24:44 PM PDT 24
Finished Jul 23 07:25:01 PM PDT 24
Peak memory 215600 kb
Host smart-f80e47c9-9746-4ddc-bc2d-27c15c139e8b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149624315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device
_tl_intg_err.149624315
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.262365305
Short name T69
Test name
Test status
Simulation time 142642996 ps
CPU time 1.26 seconds
Started Jul 23 07:24:17 PM PDT 24
Finished Jul 23 07:24:19 PM PDT 24
Peak memory 207204 kb
Host smart-2ad0df58-6787-4fd6-9e29-79fddba52497
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262365305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_hw_reset.262365305
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.1595209274
Short name T186
Test name
Test status
Simulation time 320717514020 ps
CPU time 695.76 seconds
Started Jul 23 07:07:10 PM PDT 24
Finished Jul 23 07:18:47 PM PDT 24
Peak memory 265576 kb
Host smart-3fbc6c24-4181-4070-b960-916393a1abfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595209274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.1595209274
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3939346403
Short name T95
Test name
Test status
Simulation time 434178181 ps
CPU time 4.06 seconds
Started Jul 23 07:24:37 PM PDT 24
Finished Jul 23 07:24:41 PM PDT 24
Peak memory 215612 kb
Host smart-96dcfe9f-40b7-4d02-92d8-54854bcdfc83
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939346403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
3939346403
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.1578969965
Short name T233
Test name
Test status
Simulation time 6431950831 ps
CPU time 154.42 seconds
Started Jul 23 07:05:52 PM PDT 24
Finished Jul 23 07:08:27 PM PDT 24
Peak memory 273972 kb
Host smart-023806f0-9ed9-40d3-8770-9e237978a9d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578969965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.1578969965
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.1455306745
Short name T177
Test name
Test status
Simulation time 484070418419 ps
CPU time 923.91 seconds
Started Jul 23 07:05:13 PM PDT 24
Finished Jul 23 07:20:38 PM PDT 24
Peak memory 273244 kb
Host smart-8d2b6706-5f3d-4490-81a8-99c6f5dbfbd0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455306745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.1455306745
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.1775000898
Short name T27
Test name
Test status
Simulation time 44797229425 ps
CPU time 295.19 seconds
Started Jul 23 07:07:11 PM PDT 24
Finished Jul 23 07:12:09 PM PDT 24
Peak memory 253164 kb
Host smart-2d41ff53-1ae8-4860-9586-f5b9cb89d5aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775000898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.1775000898
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.3450845999
Short name T240
Test name
Test status
Simulation time 38416641035 ps
CPU time 302.48 seconds
Started Jul 23 07:05:41 PM PDT 24
Finished Jul 23 07:10:45 PM PDT 24
Peak memory 257644 kb
Host smart-d8533b36-98af-4747-8eb5-3f9d7058b6db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450845999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds
.3450845999
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.2722157968
Short name T112
Test name
Test status
Simulation time 16622812967 ps
CPU time 68.63 seconds
Started Jul 23 07:08:15 PM PDT 24
Finished Jul 23 07:09:26 PM PDT 24
Peak memory 257096 kb
Host smart-fffe4b05-7db2-4c0d-abe8-8c4a6c58baa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722157968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.2722157968
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.640065270
Short name T344
Test name
Test status
Simulation time 17508856 ps
CPU time 0.69 seconds
Started Jul 23 07:06:20 PM PDT 24
Finished Jul 23 07:06:22 PM PDT 24
Peak memory 205764 kb
Host smart-7af0479f-60c1-4b11-8a50-bd4e3934a31d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640065270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.640065270
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.4229508228
Short name T845
Test name
Test status
Simulation time 101729417845 ps
CPU time 1155.43 seconds
Started Jul 23 07:05:08 PM PDT 24
Finished Jul 23 07:24:25 PM PDT 24
Peak memory 323264 kb
Host smart-4e04e080-656c-4417-bae6-e5ed7cdafc0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229508228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.4229508228
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.301300972
Short name T40
Test name
Test status
Simulation time 19455717272 ps
CPU time 79.72 seconds
Started Jul 23 07:06:03 PM PDT 24
Finished Jul 23 07:07:24 PM PDT 24
Peak memory 255408 kb
Host smart-430cf8e5-a2f6-46cd-8622-fd6a76fadd3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301300972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmds
.301300972
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.770195463
Short name T165
Test name
Test status
Simulation time 135934495994 ps
CPU time 492.93 seconds
Started Jul 23 07:06:46 PM PDT 24
Finished Jul 23 07:15:01 PM PDT 24
Peak memory 264704 kb
Host smart-d016fb18-b77b-4bd4-af41-0f0fdc63e8b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770195463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmds
.770195463
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.754400963
Short name T90
Test name
Test status
Simulation time 3180014006 ps
CPU time 20.72 seconds
Started Jul 23 07:24:44 PM PDT 24
Finished Jul 23 07:25:07 PM PDT 24
Peak memory 215848 kb
Host smart-d311e947-4369-4e30-9820-cbc463a1038a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754400963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device
_tl_intg_err.754400963
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.1624830733
Short name T154
Test name
Test status
Simulation time 6064754275 ps
CPU time 80.03 seconds
Started Jul 23 07:05:53 PM PDT 24
Finished Jul 23 07:07:14 PM PDT 24
Peak memory 255048 kb
Host smart-d30d49a6-8e4e-4270-8679-068c65a9aae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624830733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.1624830733
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.1652315504
Short name T53
Test name
Test status
Simulation time 12885245593 ps
CPU time 99.93 seconds
Started Jul 23 07:05:56 PM PDT 24
Finished Jul 23 07:07:37 PM PDT 24
Peak memory 257668 kb
Host smart-34c2e2ae-ca8a-4f01-8bce-176b6d6b1dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652315504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.1652315504
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.3564619752
Short name T507
Test name
Test status
Simulation time 7410838421 ps
CPU time 25.02 seconds
Started Jul 23 07:06:03 PM PDT 24
Finished Jul 23 07:06:29 PM PDT 24
Peak memory 216520 kb
Host smart-8baa9c65-0ce3-4a51-9bf3-12055df3f36d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564619752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.3564619752
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.636641872
Short name T142
Test name
Test status
Simulation time 34757365114 ps
CPU time 356.97 seconds
Started Jul 23 07:07:10 PM PDT 24
Finished Jul 23 07:13:09 PM PDT 24
Peak memory 269832 kb
Host smart-6aa3aa67-bd6a-4ca8-934a-723bb5c4ed64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636641872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stres
s_all.636641872
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.1347021402
Short name T277
Test name
Test status
Simulation time 5325836352 ps
CPU time 37.9 seconds
Started Jul 23 07:07:25 PM PDT 24
Finished Jul 23 07:08:05 PM PDT 24
Peak memory 224816 kb
Host smart-b537f7e7-3b4e-4442-857b-104081f3bfeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347021402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.1347021402
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.4279780390
Short name T269
Test name
Test status
Simulation time 10324017128 ps
CPU time 97.67 seconds
Started Jul 23 07:07:48 PM PDT 24
Finished Jul 23 07:09:28 PM PDT 24
Peak memory 261032 kb
Host smart-b2b297c6-7a4b-4d38-8c7f-49f468980786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279780390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.4279780390
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.2292195464
Short name T73
Test name
Test status
Simulation time 6635361420 ps
CPU time 33.86 seconds
Started Jul 23 07:05:17 PM PDT 24
Finished Jul 23 07:05:54 PM PDT 24
Peak memory 249404 kb
Host smart-f7b685eb-df2a-430f-abc5-78e2985eb4b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292195464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds
.2292195464
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.1855455814
Short name T80
Test name
Test status
Simulation time 400668759 ps
CPU time 4.15 seconds
Started Jul 23 07:24:24 PM PDT 24
Finished Jul 23 07:24:29 PM PDT 24
Peak memory 215676 kb
Host smart-bac8e94c-94ac-4624-b723-2fd9c7db4162
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855455814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.1
855455814
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.422937549
Short name T299
Test name
Test status
Simulation time 28627177 ps
CPU time 0.86 seconds
Started Jul 23 07:06:00 PM PDT 24
Finished Jul 23 07:06:03 PM PDT 24
Peak memory 206300 kb
Host smart-e0c9dcb9-5bab-49bd-942c-3ab58da6be3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422937549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.422937549
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.2300395646
Short name T41
Test name
Test status
Simulation time 38091043089 ps
CPU time 285.64 seconds
Started Jul 23 07:06:31 PM PDT 24
Finished Jul 23 07:11:18 PM PDT 24
Peak memory 264116 kb
Host smart-6d1edb5d-ab7d-4f6f-a530-8019998e25fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300395646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.2300395646
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.2989384057
Short name T293
Test name
Test status
Simulation time 2803530378 ps
CPU time 61.37 seconds
Started Jul 23 07:08:35 PM PDT 24
Finished Jul 23 07:09:38 PM PDT 24
Peak memory 254488 kb
Host smart-a3c896a9-f6cd-4351-aca9-b9c577fe8457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989384057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.2989384057
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.99090457
Short name T91
Test name
Test status
Simulation time 1210952085 ps
CPU time 14.92 seconds
Started Jul 23 07:23:56 PM PDT 24
Finished Jul 23 07:24:12 PM PDT 24
Peak memory 223624 kb
Host smart-a8de774d-47f4-4489-8def-5ddc34e504ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99090457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_t
l_intg_err.99090457
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2095097602
Short name T158
Test name
Test status
Simulation time 615369126 ps
CPU time 20.73 seconds
Started Jul 23 07:24:45 PM PDT 24
Finished Jul 23 07:25:08 PM PDT 24
Peak memory 223588 kb
Host smart-60e8f94d-7546-489e-bb9e-6d17f7858a2f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095097602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.2095097602
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.322859182
Short name T254
Test name
Test status
Simulation time 4178815991 ps
CPU time 46.94 seconds
Started Jul 23 07:05:03 PM PDT 24
Finished Jul 23 07:05:52 PM PDT 24
Peak memory 256544 kb
Host smart-d884725b-3410-48d8-a59e-3e840b02ab22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322859182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.322859182
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.3146469676
Short name T187
Test name
Test status
Simulation time 7711849604 ps
CPU time 82.99 seconds
Started Jul 23 07:06:14 PM PDT 24
Finished Jul 23 07:07:38 PM PDT 24
Peak memory 264940 kb
Host smart-8ec2777f-5629-4556-9199-95c5d64d400b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146469676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmd
s.3146469676
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.3848292457
Short name T21
Test name
Test status
Simulation time 34681413067 ps
CPU time 116.91 seconds
Started Jul 23 07:06:26 PM PDT 24
Finished Jul 23 07:08:25 PM PDT 24
Peak memory 249432 kb
Host smart-15655ed3-b975-47de-8340-2e36ccd224cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848292457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.3848292457
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.2774168709
Short name T171
Test name
Test status
Simulation time 12474095394 ps
CPU time 116.28 seconds
Started Jul 23 07:06:30 PM PDT 24
Finished Jul 23 07:08:27 PM PDT 24
Peak memory 268064 kb
Host smart-c72c6c2b-3d09-49e6-9494-2e9aa7c124f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774168709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.2774168709
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.4198933435
Short name T174
Test name
Test status
Simulation time 51109230863 ps
CPU time 131.01 seconds
Started Jul 23 07:06:34 PM PDT 24
Finished Jul 23 07:08:45 PM PDT 24
Peak memory 273876 kb
Host smart-43358f3f-a57c-47c8-a587-a9d2335405ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198933435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmd
s.4198933435
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.3266162071
Short name T279
Test name
Test status
Simulation time 95758323125 ps
CPU time 242.18 seconds
Started Jul 23 07:06:34 PM PDT 24
Finished Jul 23 07:10:37 PM PDT 24
Peak memory 251476 kb
Host smart-99a3fb8c-53bb-45cb-9a4d-445e1eb0d17c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266162071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.3266162071
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.1564762473
Short name T252
Test name
Test status
Simulation time 98779869722 ps
CPU time 245.69 seconds
Started Jul 23 07:08:14 PM PDT 24
Finished Jul 23 07:12:22 PM PDT 24
Peak memory 251488 kb
Host smart-dd816843-e367-4cfa-9ae4-1b6ec681180e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564762473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.1564762473
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.3140805423
Short name T37
Test name
Test status
Simulation time 6454480154 ps
CPU time 9.66 seconds
Started Jul 23 07:05:03 PM PDT 24
Finished Jul 23 07:05:14 PM PDT 24
Peak memory 232920 kb
Host smart-e5f9426f-b984-4cb3-b17c-e877ccf3f904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140805423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.3140805423
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.283383171
Short name T88
Test name
Test status
Simulation time 460064649 ps
CPU time 3.69 seconds
Started Jul 23 07:24:45 PM PDT 24
Finished Jul 23 07:24:51 PM PDT 24
Peak memory 215608 kb
Host smart-7ac88610-a726-4bca-ae42-2b971af3ad9f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283383171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.283383171
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.2523637839
Short name T1115
Test name
Test status
Simulation time 2283084780 ps
CPU time 22.9 seconds
Started Jul 23 07:23:55 PM PDT 24
Finished Jul 23 07:24:18 PM PDT 24
Peak memory 215548 kb
Host smart-a35144b8-0d0a-4997-94ee-846e1d36f7b9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523637839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.2523637839
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3158669991
Short name T1023
Test name
Test status
Simulation time 192420392 ps
CPU time 11.28 seconds
Started Jul 23 07:23:59 PM PDT 24
Finished Jul 23 07:24:12 PM PDT 24
Peak memory 207272 kb
Host smart-f5b7e74a-9ff4-40c4-a856-fa382ece1bce
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158669991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.3158669991
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1833120946
Short name T1104
Test name
Test status
Simulation time 206949642 ps
CPU time 1.16 seconds
Started Jul 23 07:23:55 PM PDT 24
Finished Jul 23 07:23:57 PM PDT 24
Peak memory 216552 kb
Host smart-33e2e21d-0a56-4dbd-8395-5794cf3eebf0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833120946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.1833120946
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2397666064
Short name T1098
Test name
Test status
Simulation time 163026321 ps
CPU time 4.22 seconds
Started Jul 23 07:23:57 PM PDT 24
Finished Jul 23 07:24:02 PM PDT 24
Peak memory 218760 kb
Host smart-2e3c3f94-ec56-4b4c-be17-c796ce13ec32
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397666064 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.2397666064
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.1861790054
Short name T1070
Test name
Test status
Simulation time 261452117 ps
CPU time 2.25 seconds
Started Jul 23 07:23:56 PM PDT 24
Finished Jul 23 07:23:59 PM PDT 24
Peak memory 215552 kb
Host smart-895e4cc8-92d4-487d-af45-f44088a35a57
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861790054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.1
861790054
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.753712554
Short name T1037
Test name
Test status
Simulation time 28091698 ps
CPU time 0.75 seconds
Started Jul 23 07:23:58 PM PDT 24
Finished Jul 23 07:24:00 PM PDT 24
Peak memory 203984 kb
Host smart-5819d2b3-766f-45e6-99e1-502f85ecd173
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753712554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.753712554
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.2098937206
Short name T102
Test name
Test status
Simulation time 24830043 ps
CPU time 1.67 seconds
Started Jul 23 07:23:57 PM PDT 24
Finished Jul 23 07:23:59 PM PDT 24
Peak memory 215412 kb
Host smart-30ba3140-4d36-4933-b161-82d26ac5fdac
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098937206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.2098937206
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.1357810364
Short name T1034
Test name
Test status
Simulation time 13424210 ps
CPU time 0.68 seconds
Started Jul 23 07:23:58 PM PDT 24
Finished Jul 23 07:23:59 PM PDT 24
Peak memory 204248 kb
Host smart-a9f3ad83-6a6e-4ae7-aad4-1499199ef128
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357810364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.1357810364
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3593845989
Short name T1105
Test name
Test status
Simulation time 1090834894 ps
CPU time 1.87 seconds
Started Jul 23 07:24:00 PM PDT 24
Finished Jul 23 07:24:02 PM PDT 24
Peak memory 215476 kb
Host smart-bbe15dde-6001-4bf1-829a-952fca7e81b5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593845989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.3593845989
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2103698768
Short name T93
Test name
Test status
Simulation time 81455840 ps
CPU time 2.22 seconds
Started Jul 23 07:23:59 PM PDT 24
Finished Jul 23 07:24:02 PM PDT 24
Peak memory 215556 kb
Host smart-cabd290a-d11f-41f6-a199-51069fa2516b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103698768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.2
103698768
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1382306791
Short name T1094
Test name
Test status
Simulation time 832517347 ps
CPU time 14.42 seconds
Started Jul 23 07:24:06 PM PDT 24
Finished Jul 23 07:24:21 PM PDT 24
Peak memory 215472 kb
Host smart-9a2cc636-a402-4f88-851a-ab6318b33b10
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382306791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.1382306791
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.1725568
Short name T1042
Test name
Test status
Simulation time 7843189928 ps
CPU time 36.05 seconds
Started Jul 23 07:24:03 PM PDT 24
Finished Jul 23 07:24:40 PM PDT 24
Peak memory 207416 kb
Host smart-0d6b52c3-a7f4-4d07-8203-200e2be00d90
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_b
it_bash.1725568
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.1738119812
Short name T71
Test name
Test status
Simulation time 103523916 ps
CPU time 1.39 seconds
Started Jul 23 07:24:04 PM PDT 24
Finished Jul 23 07:24:06 PM PDT 24
Peak memory 216444 kb
Host smart-8f88c164-2a3b-4db8-8e48-27875498b132
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738119812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.1738119812
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.4150358871
Short name T1049
Test name
Test status
Simulation time 54612471 ps
CPU time 1.92 seconds
Started Jul 23 07:24:07 PM PDT 24
Finished Jul 23 07:24:10 PM PDT 24
Peak memory 216512 kb
Host smart-e4f5e8c0-8afd-4256-90f6-f85de48fd46f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150358871 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.4150358871
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.1147048943
Short name T1026
Test name
Test status
Simulation time 25449044 ps
CPU time 1.11 seconds
Started Jul 23 07:24:05 PM PDT 24
Finished Jul 23 07:24:08 PM PDT 24
Peak memory 215532 kb
Host smart-05912251-7b1b-48a5-a2e3-94388bc82438
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147048943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.1
147048943
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3925773218
Short name T1077
Test name
Test status
Simulation time 55574528 ps
CPU time 0.78 seconds
Started Jul 23 07:23:57 PM PDT 24
Finished Jul 23 07:23:59 PM PDT 24
Peak memory 204300 kb
Host smart-1b5e3164-4f9d-4dc4-89c7-0e460a6e251b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925773218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.3
925773218
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.623312618
Short name T1024
Test name
Test status
Simulation time 64797407 ps
CPU time 1.39 seconds
Started Jul 23 07:24:04 PM PDT 24
Finished Jul 23 07:24:06 PM PDT 24
Peak memory 215448 kb
Host smart-de4a80bc-be62-45f7-8b93-83c69671e24c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623312618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_
device_mem_partial_access.623312618
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.4093971556
Short name T1092
Test name
Test status
Simulation time 11520128 ps
CPU time 0.67 seconds
Started Jul 23 07:24:06 PM PDT 24
Finished Jul 23 07:24:07 PM PDT 24
Peak memory 204256 kb
Host smart-59d4f056-ebec-4785-9491-daaeebe50608
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093971556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.4093971556
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.923092866
Short name T1093
Test name
Test status
Simulation time 191463032 ps
CPU time 2.86 seconds
Started Jul 23 07:24:05 PM PDT 24
Finished Jul 23 07:24:09 PM PDT 24
Peak memory 215524 kb
Host smart-ae6a6c82-36a4-4e60-a8c9-f9ac4d2e5b13
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923092866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sp
i_device_same_csr_outstanding.923092866
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2974147402
Short name T1061
Test name
Test status
Simulation time 134057833 ps
CPU time 2.68 seconds
Started Jul 23 07:23:59 PM PDT 24
Finished Jul 23 07:24:03 PM PDT 24
Peak memory 215552 kb
Host smart-5ce75bc6-c97c-42f9-9429-c72b56bbd018
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974147402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.2
974147402
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.3672511045
Short name T82
Test name
Test status
Simulation time 755698798 ps
CPU time 12.16 seconds
Started Jul 23 07:23:56 PM PDT 24
Finished Jul 23 07:24:09 PM PDT 24
Peak memory 215552 kb
Host smart-bbc7d0a4-e802-41d4-a7d8-c5e808bc4f79
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672511045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.3672511045
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.872630085
Short name T1082
Test name
Test status
Simulation time 59906219 ps
CPU time 1.86 seconds
Started Jul 23 07:24:43 PM PDT 24
Finished Jul 23 07:24:46 PM PDT 24
Peak memory 216812 kb
Host smart-d1f619d4-f950-4ee0-bdc3-afcbd9f7c3c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872630085 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.872630085
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.889700698
Short name T1025
Test name
Test status
Simulation time 127534183 ps
CPU time 2.41 seconds
Started Jul 23 07:24:43 PM PDT 24
Finished Jul 23 07:24:47 PM PDT 24
Peak memory 215460 kb
Host smart-0ec32498-fb31-496f-bc0d-8c6c98c4c1c4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889700698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.889700698
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2402206008
Short name T1085
Test name
Test status
Simulation time 40126813 ps
CPU time 0.71 seconds
Started Jul 23 07:24:42 PM PDT 24
Finished Jul 23 07:24:44 PM PDT 24
Peak memory 204020 kb
Host smart-2a3acb8b-b2cc-46c4-b63e-f1c53b5383cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402206008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
2402206008
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2056390328
Short name T1055
Test name
Test status
Simulation time 581070224 ps
CPU time 1.82 seconds
Started Jul 23 07:24:42 PM PDT 24
Finished Jul 23 07:24:45 PM PDT 24
Peak memory 207172 kb
Host smart-421a8977-fa55-4a18-ac9f-b090301ab9a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056390328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.2056390328
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.2359545687
Short name T92
Test name
Test status
Simulation time 50713918 ps
CPU time 1.75 seconds
Started Jul 23 07:24:34 PM PDT 24
Finished Jul 23 07:24:36 PM PDT 24
Peak memory 215624 kb
Host smart-d531441b-c3f6-44f2-a926-251b7ed17321
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359545687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
2359545687
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.3478982650
Short name T163
Test name
Test status
Simulation time 448701075 ps
CPU time 7.41 seconds
Started Jul 23 07:24:43 PM PDT 24
Finished Jul 23 07:24:52 PM PDT 24
Peak memory 214740 kb
Host smart-e5131216-4d94-4233-b765-53edb35b34de
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478982650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.3478982650
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.3939381559
Short name T1051
Test name
Test status
Simulation time 38612626 ps
CPU time 2.44 seconds
Started Jul 23 07:24:43 PM PDT 24
Finished Jul 23 07:24:47 PM PDT 24
Peak memory 214540 kb
Host smart-ff757d57-0d6a-4a38-9a61-2b3acc5a98ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939381559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
3939381559
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1121257841
Short name T1117
Test name
Test status
Simulation time 15510156 ps
CPU time 0.78 seconds
Started Jul 23 07:24:37 PM PDT 24
Finished Jul 23 07:24:38 PM PDT 24
Peak memory 204304 kb
Host smart-4564d30e-c0de-4250-be7b-7691ede32499
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121257841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
1121257841
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3545272101
Short name T1039
Test name
Test status
Simulation time 104543479 ps
CPU time 2.75 seconds
Started Jul 23 07:24:39 PM PDT 24
Finished Jul 23 07:24:42 PM PDT 24
Peak memory 215476 kb
Host smart-2f143371-cd7b-4b80-ae41-0cb19fe24155
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545272101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.3545272101
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3953280609
Short name T1060
Test name
Test status
Simulation time 73245516 ps
CPU time 5.12 seconds
Started Jul 23 07:24:42 PM PDT 24
Finished Jul 23 07:24:49 PM PDT 24
Peak memory 215596 kb
Host smart-90147d70-d952-4f24-b1b0-e1b1e1b617db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953280609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
3953280609
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.967685227
Short name T160
Test name
Test status
Simulation time 5162639527 ps
CPU time 24.1 seconds
Started Jul 23 07:24:36 PM PDT 24
Finished Jul 23 07:25:01 PM PDT 24
Peak memory 216268 kb
Host smart-8efbf165-8f41-4fcc-be8b-b525de0e4dbc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967685227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device
_tl_intg_err.967685227
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.2976657006
Short name T1067
Test name
Test status
Simulation time 111233550 ps
CPU time 4.01 seconds
Started Jul 23 07:24:38 PM PDT 24
Finished Jul 23 07:24:42 PM PDT 24
Peak memory 217252 kb
Host smart-00bccf77-45ab-45f8-a993-b27e0b32e82d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976657006 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.2976657006
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.4052460248
Short name T1052
Test name
Test status
Simulation time 141728101 ps
CPU time 2.77 seconds
Started Jul 23 07:24:35 PM PDT 24
Finished Jul 23 07:24:39 PM PDT 24
Peak memory 215460 kb
Host smart-71bcd201-724b-4a17-b19d-4e244fb0cff6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052460248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
4052460248
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.3627091418
Short name T1106
Test name
Test status
Simulation time 28047372 ps
CPU time 0.7 seconds
Started Jul 23 07:24:37 PM PDT 24
Finished Jul 23 07:24:39 PM PDT 24
Peak memory 204300 kb
Host smart-369bb4fc-cdd3-4e76-bc87-3546278e6edb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627091418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
3627091418
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.920934167
Short name T124
Test name
Test status
Simulation time 167512309 ps
CPU time 2.94 seconds
Started Jul 23 07:24:42 PM PDT 24
Finished Jul 23 07:24:46 PM PDT 24
Peak memory 215532 kb
Host smart-974762f8-a7f7-40e8-8df1-7cf868978685
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920934167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.s
pi_device_same_csr_outstanding.920934167
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.2082225600
Short name T157
Test name
Test status
Simulation time 829214615 ps
CPU time 18.92 seconds
Started Jul 23 07:24:42 PM PDT 24
Finished Jul 23 07:25:01 PM PDT 24
Peak memory 215436 kb
Host smart-2e19797c-9658-4b5d-bd82-d8f05723b8f2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082225600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.2082225600
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.3286857595
Short name T140
Test name
Test status
Simulation time 209326467 ps
CPU time 1.81 seconds
Started Jul 23 07:24:47 PM PDT 24
Finished Jul 23 07:24:50 PM PDT 24
Peak memory 216508 kb
Host smart-f2e15807-6837-4fad-92af-84ca67c4f809
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286857595 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.3286857595
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.841488012
Short name T103
Test name
Test status
Simulation time 136916375 ps
CPU time 2.24 seconds
Started Jul 23 07:24:44 PM PDT 24
Finished Jul 23 07:24:49 PM PDT 24
Peak memory 207388 kb
Host smart-45720bb9-6f02-4888-82ac-103aeb8cd374
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841488012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.841488012
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3234034934
Short name T1038
Test name
Test status
Simulation time 20581984 ps
CPU time 0.78 seconds
Started Jul 23 07:24:44 PM PDT 24
Finished Jul 23 07:24:47 PM PDT 24
Peak memory 203960 kb
Host smart-ea8d1dc1-ed11-43b4-8e75-60d6f9a15428
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234034934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
3234034934
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3112086058
Short name T126
Test name
Test status
Simulation time 925425144 ps
CPU time 3.02 seconds
Started Jul 23 07:24:44 PM PDT 24
Finished Jul 23 07:24:49 PM PDT 24
Peak memory 215500 kb
Host smart-0b28b42d-ee8c-4f0f-8aa8-022b348d308c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112086058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.3112086058
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.1583891896
Short name T1121
Test name
Test status
Simulation time 26165100 ps
CPU time 1.96 seconds
Started Jul 23 07:24:35 PM PDT 24
Finished Jul 23 07:24:38 PM PDT 24
Peak memory 216564 kb
Host smart-9f2dc0eb-e385-48d5-8c28-f4824504fa58
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583891896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
1583891896
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.242568174
Short name T60
Test name
Test status
Simulation time 249767049 ps
CPU time 3.88 seconds
Started Jul 23 07:24:43 PM PDT 24
Finished Jul 23 07:24:49 PM PDT 24
Peak memory 217800 kb
Host smart-2ca6f2a9-2989-428c-bfce-b2ff5ef680bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242568174 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.242568174
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1388370253
Short name T101
Test name
Test status
Simulation time 128793291 ps
CPU time 2.59 seconds
Started Jul 23 07:24:45 PM PDT 24
Finished Jul 23 07:24:50 PM PDT 24
Peak memory 215468 kb
Host smart-bf2a1720-8ddb-41ba-bf1a-f9cac9390f9d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388370253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
1388370253
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2200027343
Short name T1099
Test name
Test status
Simulation time 27114678 ps
CPU time 0.77 seconds
Started Jul 23 07:24:45 PM PDT 24
Finished Jul 23 07:24:48 PM PDT 24
Peak memory 203976 kb
Host smart-dc432a6f-8135-4cfc-99ce-cc4d919531d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200027343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
2200027343
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.944984589
Short name T136
Test name
Test status
Simulation time 905637639 ps
CPU time 4.79 seconds
Started Jul 23 07:24:49 PM PDT 24
Finished Jul 23 07:24:56 PM PDT 24
Peak memory 215484 kb
Host smart-4021e991-360f-4d74-8dfa-8f71f5209efd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944984589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.s
pi_device_same_csr_outstanding.944984589
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.1357502833
Short name T87
Test name
Test status
Simulation time 346323043 ps
CPU time 2.33 seconds
Started Jul 23 07:24:47 PM PDT 24
Finished Jul 23 07:24:51 PM PDT 24
Peak memory 215536 kb
Host smart-2667a7e6-1077-4012-820c-8023407f5d5d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357502833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
1357502833
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.128348452
Short name T162
Test name
Test status
Simulation time 1692844906 ps
CPU time 15.33 seconds
Started Jul 23 07:24:44 PM PDT 24
Finished Jul 23 07:25:02 PM PDT 24
Peak memory 215544 kb
Host smart-6de132cd-9a0a-4922-9639-df424de41bcb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128348452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device
_tl_intg_err.128348452
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3092109629
Short name T1040
Test name
Test status
Simulation time 86040861 ps
CPU time 1.58 seconds
Started Jul 23 07:24:49 PM PDT 24
Finished Jul 23 07:24:53 PM PDT 24
Peak memory 215784 kb
Host smart-1780cdab-e15c-41a9-87ce-54bdde58f23c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092109629 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.3092109629
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.1593795658
Short name T1080
Test name
Test status
Simulation time 17282620 ps
CPU time 1.18 seconds
Started Jul 23 07:24:44 PM PDT 24
Finished Jul 23 07:24:47 PM PDT 24
Peak memory 207208 kb
Host smart-6c1be171-a70e-4dc7-bb0f-c2349f11dc43
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593795658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
1593795658
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.3673956629
Short name T1131
Test name
Test status
Simulation time 194733381 ps
CPU time 0.73 seconds
Started Jul 23 07:24:43 PM PDT 24
Finished Jul 23 07:24:46 PM PDT 24
Peak memory 204476 kb
Host smart-cf844660-b405-4095-aeb6-138cea36cb6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673956629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
3673956629
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.1801460182
Short name T1017
Test name
Test status
Simulation time 114719943 ps
CPU time 3.24 seconds
Started Jul 23 07:24:43 PM PDT 24
Finished Jul 23 07:24:48 PM PDT 24
Peak memory 216192 kb
Host smart-abb945e5-8635-45c1-8a90-5e74345d50ad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801460182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.1801460182
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.883390574
Short name T1087
Test name
Test status
Simulation time 80569001 ps
CPU time 1.51 seconds
Started Jul 23 07:24:45 PM PDT 24
Finished Jul 23 07:24:49 PM PDT 24
Peak memory 215596 kb
Host smart-a978ab6e-b8af-4487-9767-2c6244101dd9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883390574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.883390574
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.3779320694
Short name T81
Test name
Test status
Simulation time 809983977 ps
CPU time 13.64 seconds
Started Jul 23 07:24:44 PM PDT 24
Finished Jul 23 07:25:00 PM PDT 24
Peak memory 215528 kb
Host smart-8e3644e3-c8d6-46bb-81e8-c88ead7c2ac9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779320694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.3779320694
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.300636728
Short name T1081
Test name
Test status
Simulation time 581073987 ps
CPU time 3.3 seconds
Started Jul 23 07:24:45 PM PDT 24
Finished Jul 23 07:24:51 PM PDT 24
Peak memory 217596 kb
Host smart-451b699e-f473-4e97-ab80-ded5fa95a459
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300636728 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.300636728
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.940654582
Short name T1078
Test name
Test status
Simulation time 69066294 ps
CPU time 1.2 seconds
Started Jul 23 07:24:49 PM PDT 24
Finished Jul 23 07:24:53 PM PDT 24
Peak memory 215088 kb
Host smart-cd9fe848-c46d-414c-98f0-54233b9b3ff2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940654582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.940654582
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3971661266
Short name T1109
Test name
Test status
Simulation time 21525452 ps
CPU time 0.72 seconds
Started Jul 23 07:24:47 PM PDT 24
Finished Jul 23 07:24:49 PM PDT 24
Peak memory 204224 kb
Host smart-c4a99af0-616e-4c68-bd9e-ccb1ba841e82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971661266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
3971661266
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.2105127788
Short name T1100
Test name
Test status
Simulation time 46120016 ps
CPU time 2.95 seconds
Started Jul 23 07:24:49 PM PDT 24
Finished Jul 23 07:24:54 PM PDT 24
Peak memory 215096 kb
Host smart-6f50f901-8357-4cba-ac74-5584fabd2b86
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105127788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.2105127788
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1293669866
Short name T1114
Test name
Test status
Simulation time 99256513 ps
CPU time 2.78 seconds
Started Jul 23 07:24:52 PM PDT 24
Finished Jul 23 07:24:57 PM PDT 24
Peak memory 218372 kb
Host smart-0cb37edb-2731-473c-9a73-c7f04758555b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293669866 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.1293669866
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.745089014
Short name T1113
Test name
Test status
Simulation time 60434678 ps
CPU time 1.75 seconds
Started Jul 23 07:24:52 PM PDT 24
Finished Jul 23 07:24:56 PM PDT 24
Peak memory 207180 kb
Host smart-a23d1093-e381-47ea-9f93-88b560b67c99
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745089014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.745089014
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.1410483554
Short name T1064
Test name
Test status
Simulation time 50729639 ps
CPU time 0.71 seconds
Started Jul 23 07:24:45 PM PDT 24
Finished Jul 23 07:24:48 PM PDT 24
Peak memory 204268 kb
Host smart-35c75f5b-e2df-4ce6-b849-f82480e913c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410483554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
1410483554
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.990060074
Short name T138
Test name
Test status
Simulation time 283886422 ps
CPU time 1.98 seconds
Started Jul 23 07:24:49 PM PDT 24
Finished Jul 23 07:24:53 PM PDT 24
Peak memory 215448 kb
Host smart-900671d0-1160-4ca6-a080-40fd9e796ecc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990060074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.s
pi_device_same_csr_outstanding.990060074
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.1959933256
Short name T1068
Test name
Test status
Simulation time 66559324 ps
CPU time 3.34 seconds
Started Jul 23 07:24:45 PM PDT 24
Finished Jul 23 07:24:51 PM PDT 24
Peak memory 216660 kb
Host smart-24f92963-eddc-4a49-a6a4-9bb5366acdc2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959933256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
1959933256
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.3516266349
Short name T99
Test name
Test status
Simulation time 27888614 ps
CPU time 1.88 seconds
Started Jul 23 07:24:51 PM PDT 24
Finished Jul 23 07:24:55 PM PDT 24
Peak memory 215536 kb
Host smart-13d687e6-3aea-469a-a244-8c30c941f538
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516266349 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.3516266349
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1393000832
Short name T1108
Test name
Test status
Simulation time 35854604 ps
CPU time 2.36 seconds
Started Jul 23 07:24:51 PM PDT 24
Finished Jul 23 07:24:55 PM PDT 24
Peak memory 215508 kb
Host smart-585175d6-81da-4e6f-a2b8-8c9690c8b8d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393000832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
1393000832
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.2144042296
Short name T1014
Test name
Test status
Simulation time 76010280 ps
CPU time 0.73 seconds
Started Jul 23 07:24:55 PM PDT 24
Finished Jul 23 07:24:57 PM PDT 24
Peak memory 203984 kb
Host smart-22d97d34-596b-467f-a0c3-56d5667882df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144042296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
2144042296
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1244721157
Short name T1058
Test name
Test status
Simulation time 317762577 ps
CPU time 4.42 seconds
Started Jul 23 07:24:52 PM PDT 24
Finished Jul 23 07:24:59 PM PDT 24
Peak memory 215464 kb
Host smart-67d73e7a-97dd-485c-8084-1451bd3579c0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244721157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.1244721157
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.669048438
Short name T61
Test name
Test status
Simulation time 33023075 ps
CPU time 2.08 seconds
Started Jul 23 07:24:52 PM PDT 24
Finished Jul 23 07:24:56 PM PDT 24
Peak memory 215712 kb
Host smart-f6a23e25-9651-4aa8-aa7e-53a44607f671
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669048438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.669048438
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1207325691
Short name T1112
Test name
Test status
Simulation time 1029560865 ps
CPU time 22.94 seconds
Started Jul 23 07:24:50 PM PDT 24
Finished Jul 23 07:25:14 PM PDT 24
Peak memory 223648 kb
Host smart-cbebb036-e314-47d0-9439-a049c78867ad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207325691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.1207325691
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.1135014614
Short name T94
Test name
Test status
Simulation time 194020856 ps
CPU time 3.1 seconds
Started Jul 23 07:24:52 PM PDT 24
Finished Jul 23 07:24:57 PM PDT 24
Peak memory 217804 kb
Host smart-ecb81093-116a-4685-a679-28425fd96443
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135014614 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.1135014614
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.266145946
Short name T111
Test name
Test status
Simulation time 146219567 ps
CPU time 2.54 seconds
Started Jul 23 07:24:49 PM PDT 24
Finished Jul 23 07:24:54 PM PDT 24
Peak memory 215504 kb
Host smart-bdaded4f-843e-4c9a-af4b-c9149a857cd1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266145946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.266145946
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.3839664917
Short name T1103
Test name
Test status
Simulation time 12427812 ps
CPU time 0.77 seconds
Started Jul 23 07:24:51 PM PDT 24
Finished Jul 23 07:24:53 PM PDT 24
Peak memory 203972 kb
Host smart-902c2357-cedb-4017-81af-0181981565fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839664917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
3839664917
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2626607481
Short name T1062
Test name
Test status
Simulation time 517161617 ps
CPU time 2.69 seconds
Started Jul 23 07:24:52 PM PDT 24
Finished Jul 23 07:24:56 PM PDT 24
Peak memory 215676 kb
Host smart-13bec4df-9770-4326-9f1d-a67fe3496668
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626607481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.2626607481
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.18100836
Short name T97
Test name
Test status
Simulation time 140923264 ps
CPU time 2.86 seconds
Started Jul 23 07:24:53 PM PDT 24
Finished Jul 23 07:24:58 PM PDT 24
Peak memory 215664 kb
Host smart-1fdee84f-8021-440d-b36e-ac65642b7c0c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18100836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.18100836
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.2895992307
Short name T159
Test name
Test status
Simulation time 2182773274 ps
CPU time 17.48 seconds
Started Jul 23 07:24:51 PM PDT 24
Finished Jul 23 07:25:10 PM PDT 24
Peak memory 216032 kb
Host smart-3244cabc-1f07-4c25-b404-1aab34a944f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895992307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.2895992307
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3146018224
Short name T109
Test name
Test status
Simulation time 323812923 ps
CPU time 22.87 seconds
Started Jul 23 07:24:13 PM PDT 24
Finished Jul 23 07:24:36 PM PDT 24
Peak memory 215464 kb
Host smart-7a4a90b7-cb01-4223-a6b4-d7a2f02e109b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146018224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.3146018224
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3411203544
Short name T105
Test name
Test status
Simulation time 549150030 ps
CPU time 34.05 seconds
Started Jul 23 07:24:13 PM PDT 24
Finished Jul 23 07:24:47 PM PDT 24
Peak memory 215464 kb
Host smart-79e5006a-d89a-433b-8385-f4610d53aaf4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411203544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.3411203544
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2390043772
Short name T1095
Test name
Test status
Simulation time 25062520 ps
CPU time 0.94 seconds
Started Jul 23 07:24:13 PM PDT 24
Finished Jul 23 07:24:15 PM PDT 24
Peak memory 207096 kb
Host smart-193feafc-8a06-4603-8882-35c889902269
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390043772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.2390043772
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3727034611
Short name T1079
Test name
Test status
Simulation time 392148865 ps
CPU time 3.19 seconds
Started Jul 23 07:24:12 PM PDT 24
Finished Jul 23 07:24:16 PM PDT 24
Peak memory 216840 kb
Host smart-08593579-bae3-4e55-87dc-a9d686333399
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727034611 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.3727034611
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2803623479
Short name T110
Test name
Test status
Simulation time 74865027 ps
CPU time 1.93 seconds
Started Jul 23 07:24:14 PM PDT 24
Finished Jul 23 07:24:18 PM PDT 24
Peak memory 207220 kb
Host smart-207f0a59-6f4a-4067-8ecc-20869cc94be3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803623479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.2
803623479
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.3006738650
Short name T1044
Test name
Test status
Simulation time 76046057 ps
CPU time 0.71 seconds
Started Jul 23 07:24:05 PM PDT 24
Finished Jul 23 07:24:06 PM PDT 24
Peak memory 204016 kb
Host smart-0c8b7c99-d608-4e4c-86a3-ce2311bb8d89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006738650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.3
006738650
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2757677538
Short name T1056
Test name
Test status
Simulation time 204608468 ps
CPU time 1.84 seconds
Started Jul 23 07:24:14 PM PDT 24
Finished Jul 23 07:24:17 PM PDT 24
Peak memory 215412 kb
Host smart-795c603f-7967-4d98-bcae-4527f38d3970
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757677538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.2757677538
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.1169461683
Short name T1059
Test name
Test status
Simulation time 12896758 ps
CPU time 0.68 seconds
Started Jul 23 07:24:06 PM PDT 24
Finished Jul 23 07:24:08 PM PDT 24
Peak memory 203972 kb
Host smart-62466173-a9aa-47a0-b643-96ac24c8baa2
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169461683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.1169461683
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.4238954964
Short name T128
Test name
Test status
Simulation time 667370313 ps
CPU time 3.04 seconds
Started Jul 23 07:24:12 PM PDT 24
Finished Jul 23 07:24:16 PM PDT 24
Peak memory 215516 kb
Host smart-22884e50-88a3-428d-bfe7-8eee21fbf392
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238954964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.4238954964
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.2344070658
Short name T1116
Test name
Test status
Simulation time 661241656 ps
CPU time 5.2 seconds
Started Jul 23 07:24:05 PM PDT 24
Finished Jul 23 07:24:11 PM PDT 24
Peak memory 215600 kb
Host smart-3531fad3-71a9-4393-b57c-57bc4315d937
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344070658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.2
344070658
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.737618407
Short name T1122
Test name
Test status
Simulation time 7552415834 ps
CPU time 23.99 seconds
Started Jul 23 07:24:05 PM PDT 24
Finished Jul 23 07:24:29 PM PDT 24
Peak memory 215700 kb
Host smart-75e3307e-e970-4a77-a02e-9ff47b2a2cd1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737618407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_
tl_intg_err.737618407
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.3227327386
Short name T1030
Test name
Test status
Simulation time 54325881 ps
CPU time 0.76 seconds
Started Jul 23 07:25:01 PM PDT 24
Finished Jul 23 07:25:03 PM PDT 24
Peak memory 204228 kb
Host smart-0df72bb6-5c2d-4407-8d17-e4414313d8c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227327386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
3227327386
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.1241664909
Short name T1073
Test name
Test status
Simulation time 51515395 ps
CPU time 0.74 seconds
Started Jul 23 07:24:58 PM PDT 24
Finished Jul 23 07:25:00 PM PDT 24
Peak memory 203980 kb
Host smart-e07a34f8-2db0-43e3-a181-32766a86182c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241664909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
1241664909
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.2152900469
Short name T1084
Test name
Test status
Simulation time 16612127 ps
CPU time 0.75 seconds
Started Jul 23 07:25:04 PM PDT 24
Finished Jul 23 07:25:06 PM PDT 24
Peak memory 203988 kb
Host smart-f07317a4-9fe6-478a-9924-fcb9b3486c22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152900469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
2152900469
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.3469298908
Short name T1035
Test name
Test status
Simulation time 31765826 ps
CPU time 0.7 seconds
Started Jul 23 07:25:05 PM PDT 24
Finished Jul 23 07:25:07 PM PDT 24
Peak memory 203996 kb
Host smart-35cd7ffd-9f90-4900-8201-0b6e835a5bb0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469298908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
3469298908
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.2013012351
Short name T1074
Test name
Test status
Simulation time 18335751 ps
CPU time 0.73 seconds
Started Jul 23 07:24:59 PM PDT 24
Finished Jul 23 07:25:00 PM PDT 24
Peak memory 204300 kb
Host smart-db08a5aa-d30a-4865-ac89-5056b0b02b41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013012351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
2013012351
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.622708710
Short name T1063
Test name
Test status
Simulation time 16454916 ps
CPU time 0.76 seconds
Started Jul 23 07:25:02 PM PDT 24
Finished Jul 23 07:25:04 PM PDT 24
Peak memory 204296 kb
Host smart-cd011854-e660-46c2-8d0d-7cd2d51d5649
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622708710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.622708710
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.46775788
Short name T1048
Test name
Test status
Simulation time 19528252 ps
CPU time 0.7 seconds
Started Jul 23 07:25:02 PM PDT 24
Finished Jul 23 07:25:04 PM PDT 24
Peak memory 204108 kb
Host smart-70f408dc-67af-4682-bd12-621f113a775e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46775788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.46775788
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.955469454
Short name T1096
Test name
Test status
Simulation time 29624732 ps
CPU time 0.71 seconds
Started Jul 23 07:25:00 PM PDT 24
Finished Jul 23 07:25:02 PM PDT 24
Peak memory 203988 kb
Host smart-81ac7e93-22c8-41fe-a6ce-a960cab651e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955469454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.955469454
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.487760734
Short name T1043
Test name
Test status
Simulation time 14327100 ps
CPU time 0.73 seconds
Started Jul 23 07:25:05 PM PDT 24
Finished Jul 23 07:25:07 PM PDT 24
Peak memory 204308 kb
Host smart-a95ccb8f-bdc9-4554-b24e-da0341d4ec5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487760734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.487760734
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2933627856
Short name T1083
Test name
Test status
Simulation time 61369593 ps
CPU time 0.76 seconds
Started Jul 23 07:24:57 PM PDT 24
Finished Jul 23 07:24:59 PM PDT 24
Peak memory 204312 kb
Host smart-942ed544-c7d7-4f19-9b50-6e6551a6db06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933627856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
2933627856
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.1554697396
Short name T1022
Test name
Test status
Simulation time 617367811 ps
CPU time 22.51 seconds
Started Jul 23 07:24:15 PM PDT 24
Finished Jul 23 07:24:39 PM PDT 24
Peak memory 215524 kb
Host smart-683940c3-7eee-4a7c-8c72-5df4bd860259
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554697396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.1554697396
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2673896265
Short name T1066
Test name
Test status
Simulation time 1233331801 ps
CPU time 28.3 seconds
Started Jul 23 07:24:14 PM PDT 24
Finished Jul 23 07:24:43 PM PDT 24
Peak memory 215540 kb
Host smart-161919cd-cea4-4d7a-b8a1-9790c09e94fb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673896265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.2673896265
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1426394765
Short name T70
Test name
Test status
Simulation time 228427271 ps
CPU time 1.41 seconds
Started Jul 23 07:24:14 PM PDT 24
Finished Jul 23 07:24:17 PM PDT 24
Peak memory 215588 kb
Host smart-bf739026-6f9a-40a7-ac92-fc81cfb83a95
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426394765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.1426394765
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1260471534
Short name T1126
Test name
Test status
Simulation time 61759343 ps
CPU time 4.15 seconds
Started Jul 23 07:24:13 PM PDT 24
Finished Jul 23 07:24:18 PM PDT 24
Peak memory 217268 kb
Host smart-d7294b20-6791-475f-ae4f-c62c642e2397
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260471534 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.1260471534
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.217298253
Short name T1015
Test name
Test status
Simulation time 31182534 ps
CPU time 1.36 seconds
Started Jul 23 07:24:14 PM PDT 24
Finished Jul 23 07:24:17 PM PDT 24
Peak memory 215528 kb
Host smart-1d00ab5c-68dd-40ef-bd02-984630f7c43f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217298253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.217298253
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.2815361591
Short name T1045
Test name
Test status
Simulation time 11144555 ps
CPU time 0.78 seconds
Started Jul 23 07:24:15 PM PDT 24
Finished Jul 23 07:24:17 PM PDT 24
Peak memory 203968 kb
Host smart-72127e85-b4bd-48c4-9dff-a2e83a8ecc69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815361591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.2
815361591
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.426183745
Short name T1102
Test name
Test status
Simulation time 29505539 ps
CPU time 1.99 seconds
Started Jul 23 07:24:14 PM PDT 24
Finished Jul 23 07:24:17 PM PDT 24
Peak memory 215444 kb
Host smart-3b593069-7f0b-497d-8f5d-88a382e2d3a8
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426183745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_
device_mem_partial_access.426183745
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.826656355
Short name T1125
Test name
Test status
Simulation time 22832163 ps
CPU time 0.67 seconds
Started Jul 23 07:24:13 PM PDT 24
Finished Jul 23 07:24:15 PM PDT 24
Peak memory 203924 kb
Host smart-406c41b4-f66a-490a-b8f6-df4c24a92af9
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826656355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem
_walk.826656355
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2949699476
Short name T135
Test name
Test status
Simulation time 1086712667 ps
CPU time 4.44 seconds
Started Jul 23 07:24:14 PM PDT 24
Finished Jul 23 07:24:20 PM PDT 24
Peak memory 215476 kb
Host smart-cbc6bdd2-a259-4dd4-afb0-a2a33571d7c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949699476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.2949699476
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.2136003276
Short name T85
Test name
Test status
Simulation time 359504386 ps
CPU time 2.48 seconds
Started Jul 23 07:24:12 PM PDT 24
Finished Jul 23 07:24:15 PM PDT 24
Peak memory 215784 kb
Host smart-898a96f9-8771-4a2f-bf4c-b281aa9ebd01
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136003276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.2
136003276
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1965641364
Short name T1111
Test name
Test status
Simulation time 1152532216 ps
CPU time 11.7 seconds
Started Jul 23 07:24:13 PM PDT 24
Finished Jul 23 07:24:26 PM PDT 24
Peak memory 215484 kb
Host smart-833d6ba3-7bca-4d06-8f08-d392178361c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965641364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.1965641364
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.3224373245
Short name T1033
Test name
Test status
Simulation time 17793948 ps
CPU time 0.77 seconds
Started Jul 23 07:24:58 PM PDT 24
Finished Jul 23 07:25:00 PM PDT 24
Peak memory 203916 kb
Host smart-a936a5cf-cab0-49c3-9d1c-03bfebb3bc00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224373245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
3224373245
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.4027274121
Short name T1118
Test name
Test status
Simulation time 13119616 ps
CPU time 0.75 seconds
Started Jul 23 07:25:00 PM PDT 24
Finished Jul 23 07:25:03 PM PDT 24
Peak memory 203980 kb
Host smart-92d7a9e6-8c4c-4f45-acf4-01ab97d4fa5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027274121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
4027274121
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.4181658362
Short name T1090
Test name
Test status
Simulation time 11780133 ps
CPU time 0.75 seconds
Started Jul 23 07:25:01 PM PDT 24
Finished Jul 23 07:25:04 PM PDT 24
Peak memory 203952 kb
Host smart-2210d6c6-ab03-449c-8eb6-f7cb11a96e63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181658362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
4181658362
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.1739137170
Short name T1076
Test name
Test status
Simulation time 51312123 ps
CPU time 0.73 seconds
Started Jul 23 07:25:00 PM PDT 24
Finished Jul 23 07:25:02 PM PDT 24
Peak memory 204300 kb
Host smart-97196908-1a50-4ea0-bc44-3d00e148fd45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739137170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
1739137170
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.441359037
Short name T1046
Test name
Test status
Simulation time 11875968 ps
CPU time 0.76 seconds
Started Jul 23 07:25:02 PM PDT 24
Finished Jul 23 07:25:04 PM PDT 24
Peak memory 204124 kb
Host smart-7818b611-130d-4f07-92bb-0168ce1a4a9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441359037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.441359037
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.4154094354
Short name T1018
Test name
Test status
Simulation time 36995279 ps
CPU time 0.69 seconds
Started Jul 23 07:25:05 PM PDT 24
Finished Jul 23 07:25:07 PM PDT 24
Peak memory 203980 kb
Host smart-33668d06-8d30-4b1d-a30d-82e6ef0a7ce4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154094354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
4154094354
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.2981671618
Short name T1027
Test name
Test status
Simulation time 99734001 ps
CPU time 0.71 seconds
Started Jul 23 07:24:58 PM PDT 24
Finished Jul 23 07:25:00 PM PDT 24
Peak memory 204308 kb
Host smart-513c0f90-5008-473b-9f8e-11fef16ab2b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981671618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
2981671618
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.2544554777
Short name T1124
Test name
Test status
Simulation time 41199162 ps
CPU time 0.69 seconds
Started Jul 23 07:25:00 PM PDT 24
Finished Jul 23 07:25:03 PM PDT 24
Peak memory 204124 kb
Host smart-39dacc4b-69e2-46b4-870d-3a54e132381f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544554777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
2544554777
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.556196161
Short name T1016
Test name
Test status
Simulation time 112602018 ps
CPU time 0.77 seconds
Started Jul 23 07:25:00 PM PDT 24
Finished Jul 23 07:25:02 PM PDT 24
Peak memory 203976 kb
Host smart-bda6fd5c-48ce-4f06-a1f1-ba00e9c55337
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556196161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.556196161
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.270013685
Short name T1086
Test name
Test status
Simulation time 18071306 ps
CPU time 0.75 seconds
Started Jul 23 07:25:00 PM PDT 24
Finished Jul 23 07:25:03 PM PDT 24
Peak memory 204004 kb
Host smart-13f44fa6-eab0-4660-8ecf-30ab88e95b4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270013685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.270013685
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3220836452
Short name T106
Test name
Test status
Simulation time 3096773990 ps
CPU time 16.36 seconds
Started Jul 23 07:24:14 PM PDT 24
Finished Jul 23 07:24:32 PM PDT 24
Peak memory 207364 kb
Host smart-80fe738b-8e46-4538-b529-1541dd8e4440
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220836452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.3220836452
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.1635864591
Short name T1013
Test name
Test status
Simulation time 8574925878 ps
CPU time 35.82 seconds
Started Jul 23 07:24:16 PM PDT 24
Finished Jul 23 07:24:53 PM PDT 24
Peak memory 207192 kb
Host smart-b182d9f8-9787-4b4a-a4a0-dbc6073d7b29
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635864591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.1635864591
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.2597286278
Short name T141
Test name
Test status
Simulation time 608191369 ps
CPU time 3.91 seconds
Started Jul 23 07:24:16 PM PDT 24
Finished Jul 23 07:24:21 PM PDT 24
Peak memory 218076 kb
Host smart-2fc2e2f4-951c-45d0-9866-c7239650cdae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597286278 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.2597286278
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.3625184205
Short name T1032
Test name
Test status
Simulation time 103565684 ps
CPU time 2.13 seconds
Started Jul 23 07:24:15 PM PDT 24
Finished Jul 23 07:24:18 PM PDT 24
Peak memory 207276 kb
Host smart-0e0138ed-f799-4e4a-b097-d14135924e23
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625184205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.3
625184205
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.2119154288
Short name T1088
Test name
Test status
Simulation time 33543465 ps
CPU time 0.7 seconds
Started Jul 23 07:24:16 PM PDT 24
Finished Jul 23 07:24:18 PM PDT 24
Peak memory 204180 kb
Host smart-fd35994d-5338-47ab-8187-cda3e8f0d52f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119154288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.2
119154288
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.570775244
Short name T107
Test name
Test status
Simulation time 46578968 ps
CPU time 1.72 seconds
Started Jul 23 07:24:13 PM PDT 24
Finished Jul 23 07:24:15 PM PDT 24
Peak memory 215432 kb
Host smart-9d410c8a-61bf-4926-a20d-6b60f9904eb0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570775244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_
device_mem_partial_access.570775244
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.3162694096
Short name T1019
Test name
Test status
Simulation time 34968959 ps
CPU time 0.65 seconds
Started Jul 23 07:24:13 PM PDT 24
Finished Jul 23 07:24:15 PM PDT 24
Peak memory 203812 kb
Host smart-c98fd7a4-7fca-4665-8e69-a85299d74162
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162694096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.3162694096
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2971332053
Short name T125
Test name
Test status
Simulation time 282078079 ps
CPU time 1.99 seconds
Started Jul 23 07:24:12 PM PDT 24
Finished Jul 23 07:24:14 PM PDT 24
Peak memory 215460 kb
Host smart-79515b80-1183-40e9-a67d-bef6218627ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971332053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.2971332053
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.4117593714
Short name T89
Test name
Test status
Simulation time 218887288 ps
CPU time 2.22 seconds
Started Jul 23 07:24:14 PM PDT 24
Finished Jul 23 07:24:18 PM PDT 24
Peak memory 215624 kb
Host smart-b410fe72-d0b2-4790-9961-4a2f8dde5201
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117593714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.4
117593714
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.3636404049
Short name T1119
Test name
Test status
Simulation time 5592784941 ps
CPU time 17.69 seconds
Started Jul 23 07:24:15 PM PDT 24
Finished Jul 23 07:24:34 PM PDT 24
Peak memory 215564 kb
Host smart-a3abf19c-cb38-4778-8aef-984773590b38
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636404049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.3636404049
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.4066408493
Short name T1071
Test name
Test status
Simulation time 25615768 ps
CPU time 0.77 seconds
Started Jul 23 07:24:59 PM PDT 24
Finished Jul 23 07:25:01 PM PDT 24
Peak memory 204284 kb
Host smart-3130fce3-d9f5-4259-8394-593d7299312a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066408493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
4066408493
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.1979794969
Short name T1128
Test name
Test status
Simulation time 14290074 ps
CPU time 0.73 seconds
Started Jul 23 07:24:59 PM PDT 24
Finished Jul 23 07:25:01 PM PDT 24
Peak memory 203992 kb
Host smart-2d92ac9c-e057-49f1-9334-5a066c56d5aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979794969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
1979794969
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.1926547374
Short name T1029
Test name
Test status
Simulation time 64684608 ps
CPU time 0.76 seconds
Started Jul 23 07:25:00 PM PDT 24
Finished Jul 23 07:25:02 PM PDT 24
Peak memory 203964 kb
Host smart-e4536009-3897-4c9c-89c6-42fbdb8ddc52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926547374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
1926547374
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.3677098624
Short name T1047
Test name
Test status
Simulation time 12367054 ps
CPU time 0.71 seconds
Started Jul 23 07:25:00 PM PDT 24
Finished Jul 23 07:25:02 PM PDT 24
Peak memory 203936 kb
Host smart-e2b77c6e-7021-4b7f-9190-3a03a8a46d98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677098624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
3677098624
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1711071958
Short name T1072
Test name
Test status
Simulation time 14694267 ps
CPU time 0.77 seconds
Started Jul 23 07:25:00 PM PDT 24
Finished Jul 23 07:25:03 PM PDT 24
Peak memory 203956 kb
Host smart-3f9454d1-5bdd-47b0-bd44-53d3f0c83a69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711071958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
1711071958
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3082284591
Short name T1075
Test name
Test status
Simulation time 69492165 ps
CPU time 0.74 seconds
Started Jul 23 07:25:00 PM PDT 24
Finished Jul 23 07:25:02 PM PDT 24
Peak memory 203956 kb
Host smart-4deeb584-454f-4c9a-8497-ff05867da3de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082284591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
3082284591
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.1777375458
Short name T1097
Test name
Test status
Simulation time 16159066 ps
CPU time 0.77 seconds
Started Jul 23 07:25:09 PM PDT 24
Finished Jul 23 07:25:10 PM PDT 24
Peak memory 204036 kb
Host smart-d3b26761-8723-4925-975c-8ac649f46448
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777375458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
1777375458
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.3569470964
Short name T1031
Test name
Test status
Simulation time 32196346 ps
CPU time 0.76 seconds
Started Jul 23 07:25:06 PM PDT 24
Finished Jul 23 07:25:08 PM PDT 24
Peak memory 203968 kb
Host smart-0b2dc95f-676e-40c8-8c29-628f59e4e3e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569470964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
3569470964
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2087740542
Short name T1053
Test name
Test status
Simulation time 19389121 ps
CPU time 0.72 seconds
Started Jul 23 07:25:07 PM PDT 24
Finished Jul 23 07:25:08 PM PDT 24
Peak memory 203980 kb
Host smart-7833aedc-65a5-4ffb-9b4e-265929ca9ae9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087740542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
2087740542
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.2898463029
Short name T1069
Test name
Test status
Simulation time 48834477 ps
CPU time 0.7 seconds
Started Jul 23 07:25:07 PM PDT 24
Finished Jul 23 07:25:08 PM PDT 24
Peak memory 203976 kb
Host smart-a5a509d1-9b58-4347-b980-9e536877e6ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898463029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
2898463029
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1105470568
Short name T1107
Test name
Test status
Simulation time 68886106 ps
CPU time 2.84 seconds
Started Jul 23 07:24:26 PM PDT 24
Finished Jul 23 07:24:30 PM PDT 24
Peak memory 217172 kb
Host smart-82e8207a-d81f-4b66-8fe3-0634c9839487
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105470568 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.1105470568
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.1439010136
Short name T127
Test name
Test status
Simulation time 130762313 ps
CPU time 3 seconds
Started Jul 23 07:24:24 PM PDT 24
Finished Jul 23 07:24:27 PM PDT 24
Peak memory 207500 kb
Host smart-f9acb691-a462-4b55-a6ea-029413728afa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439010136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.1
439010136
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3931321964
Short name T1012
Test name
Test status
Simulation time 39594243 ps
CPU time 0.73 seconds
Started Jul 23 07:24:27 PM PDT 24
Finished Jul 23 07:24:29 PM PDT 24
Peak memory 203972 kb
Host smart-917cb0a9-e067-4182-8319-21dfe04ec0fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931321964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.3
931321964
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.147466829
Short name T1089
Test name
Test status
Simulation time 160504940 ps
CPU time 4.07 seconds
Started Jul 23 07:24:25 PM PDT 24
Finished Jul 23 07:24:30 PM PDT 24
Peak memory 215504 kb
Host smart-9d35ac40-691f-458b-97e2-44a3a941172c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147466829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sp
i_device_same_csr_outstanding.147466829
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.2673561231
Short name T1041
Test name
Test status
Simulation time 530135528 ps
CPU time 2.72 seconds
Started Jul 23 07:24:26 PM PDT 24
Finished Jul 23 07:24:29 PM PDT 24
Peak memory 215588 kb
Host smart-955234f1-4169-4c93-9afd-4508bfb7c63d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673561231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.2
673561231
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.938004014
Short name T1130
Test name
Test status
Simulation time 306662142 ps
CPU time 17.83 seconds
Started Jul 23 07:24:27 PM PDT 24
Finished Jul 23 07:24:46 PM PDT 24
Peak memory 215472 kb
Host smart-e34ed6db-fc9b-4ff8-aab8-5c5d1cd7a56d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938004014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_
tl_intg_err.938004014
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3746320424
Short name T1091
Test name
Test status
Simulation time 99536821 ps
CPU time 1.78 seconds
Started Jul 23 07:24:29 PM PDT 24
Finished Jul 23 07:24:32 PM PDT 24
Peak memory 215572 kb
Host smart-57f1406f-482f-4675-aa28-2e6975d44de8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746320424 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.3746320424
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.4015615624
Short name T1054
Test name
Test status
Simulation time 107744803 ps
CPU time 2.75 seconds
Started Jul 23 07:24:26 PM PDT 24
Finished Jul 23 07:24:30 PM PDT 24
Peak memory 215488 kb
Host smart-73cb8909-9a69-41f7-b1f3-ad0e32f0ac7b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015615624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.4
015615624
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.1719646973
Short name T1036
Test name
Test status
Simulation time 14802328 ps
CPU time 0.73 seconds
Started Jul 23 07:24:26 PM PDT 24
Finished Jul 23 07:24:28 PM PDT 24
Peak memory 203988 kb
Host smart-24775a59-cd57-4f8d-bd8b-f52b795d45bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719646973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.1
719646973
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.771681927
Short name T1057
Test name
Test status
Simulation time 630153102 ps
CPU time 4.73 seconds
Started Jul 23 07:24:24 PM PDT 24
Finished Jul 23 07:24:30 PM PDT 24
Peak memory 215564 kb
Host smart-c7a25ab9-3da0-419c-a838-0b7ff23c8959
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771681927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sp
i_device_same_csr_outstanding.771681927
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.3436116192
Short name T1120
Test name
Test status
Simulation time 585829686 ps
CPU time 17.61 seconds
Started Jul 23 07:24:25 PM PDT 24
Finished Jul 23 07:24:44 PM PDT 24
Peak memory 215612 kb
Host smart-23ad0ebe-6ef2-4abd-bcc5-9162cca2c6bc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436116192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.3436116192
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.2175257799
Short name T1101
Test name
Test status
Simulation time 421364497 ps
CPU time 3.77 seconds
Started Jul 23 07:24:26 PM PDT 24
Finished Jul 23 07:24:30 PM PDT 24
Peak memory 217544 kb
Host smart-f5472995-f974-447c-82d4-8fa24af90a01
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175257799 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.2175257799
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1334021568
Short name T137
Test name
Test status
Simulation time 48411619 ps
CPU time 1.41 seconds
Started Jul 23 07:24:26 PM PDT 24
Finished Jul 23 07:24:28 PM PDT 24
Peak memory 215508 kb
Host smart-aee02090-7d71-481d-8ee9-359f59c76b8b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334021568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.1
334021568
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.2575283488
Short name T1028
Test name
Test status
Simulation time 18219786 ps
CPU time 0.86 seconds
Started Jul 23 07:24:25 PM PDT 24
Finished Jul 23 07:24:27 PM PDT 24
Peak memory 203968 kb
Host smart-3d2854ca-380b-4309-92be-f38d6642e588
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575283488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.2
575283488
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3526948541
Short name T139
Test name
Test status
Simulation time 137410105 ps
CPU time 3.26 seconds
Started Jul 23 07:24:25 PM PDT 24
Finished Jul 23 07:24:29 PM PDT 24
Peak memory 207360 kb
Host smart-ec2baa0d-b68e-4f14-b0a7-ad449e595049
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526948541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.3526948541
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.687251971
Short name T83
Test name
Test status
Simulation time 101466512 ps
CPU time 2.68 seconds
Started Jul 23 07:24:26 PM PDT 24
Finished Jul 23 07:24:29 PM PDT 24
Peak memory 215552 kb
Host smart-2a54e377-bf00-46a9-b85a-8c17504b8d73
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687251971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.687251971
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.2398524111
Short name T161
Test name
Test status
Simulation time 596894836 ps
CPU time 20.3 seconds
Started Jul 23 07:24:25 PM PDT 24
Finished Jul 23 07:24:46 PM PDT 24
Peak memory 215544 kb
Host smart-38dcfb91-81f2-4575-adc6-b12bacc63331
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398524111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.2398524111
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.460074381
Short name T1050
Test name
Test status
Simulation time 231185411 ps
CPU time 2.45 seconds
Started Jul 23 07:24:38 PM PDT 24
Finished Jul 23 07:24:41 PM PDT 24
Peak memory 217660 kb
Host smart-8b3588b4-0a21-45b5-b72b-213ba7688c82
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460074381 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.460074381
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1662068024
Short name T104
Test name
Test status
Simulation time 146057925 ps
CPU time 2.03 seconds
Started Jul 23 07:24:42 PM PDT 24
Finished Jul 23 07:24:45 PM PDT 24
Peak memory 215476 kb
Host smart-751e6cfc-70c4-4626-8a7c-2a2060fd03f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662068024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.1
662068024
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1742844562
Short name T1065
Test name
Test status
Simulation time 24230890 ps
CPU time 0.74 seconds
Started Jul 23 07:24:25 PM PDT 24
Finished Jul 23 07:24:27 PM PDT 24
Peak memory 204300 kb
Host smart-6b36a6d6-8c27-4512-ac62-a442d0ef4435
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742844562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.1
742844562
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.3896369581
Short name T1129
Test name
Test status
Simulation time 269452130 ps
CPU time 1.88 seconds
Started Jul 23 07:24:41 PM PDT 24
Finished Jul 23 07:24:44 PM PDT 24
Peak memory 215504 kb
Host smart-3bffcf67-5e91-4c07-b845-8d7976aee7a0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896369581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.3896369581
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.1207262933
Short name T1127
Test name
Test status
Simulation time 1410506348 ps
CPU time 2.68 seconds
Started Jul 23 07:24:25 PM PDT 24
Finished Jul 23 07:24:28 PM PDT 24
Peak memory 215608 kb
Host smart-50d44885-f5ff-42ff-bcd1-a7ec9ca5b709
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207262933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.1
207262933
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3856245846
Short name T1110
Test name
Test status
Simulation time 3312702825 ps
CPU time 21.65 seconds
Started Jul 23 07:24:24 PM PDT 24
Finished Jul 23 07:24:46 PM PDT 24
Peak memory 216788 kb
Host smart-37d9dc4c-1769-4b8b-a795-47b3f41d4492
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856245846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.3856245846
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.4166313532
Short name T1123
Test name
Test status
Simulation time 697963835 ps
CPU time 3.71 seconds
Started Jul 23 07:24:42 PM PDT 24
Finished Jul 23 07:24:46 PM PDT 24
Peak memory 217892 kb
Host smart-b1741dd4-0c19-4857-8078-1e2590015416
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166313532 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.4166313532
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.528292955
Short name T108
Test name
Test status
Simulation time 161572489 ps
CPU time 2.39 seconds
Started Jul 23 07:24:41 PM PDT 24
Finished Jul 23 07:24:44 PM PDT 24
Peak memory 215512 kb
Host smart-e96ec232-383a-4c82-afed-aaa77bcac9a7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528292955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.528292955
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3864534931
Short name T1020
Test name
Test status
Simulation time 14454906 ps
CPU time 0.72 seconds
Started Jul 23 07:24:40 PM PDT 24
Finished Jul 23 07:24:42 PM PDT 24
Peak memory 204000 kb
Host smart-852a156f-c7c8-471b-ba5d-dee764182fde
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864534931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.3
864534931
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.1075148234
Short name T1021
Test name
Test status
Simulation time 226292782 ps
CPU time 1.88 seconds
Started Jul 23 07:24:36 PM PDT 24
Finished Jul 23 07:24:38 PM PDT 24
Peak memory 215520 kb
Host smart-52318513-4353-40a5-9548-6f454694dea7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075148234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.1075148234
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.767952215
Short name T86
Test name
Test status
Simulation time 60464178 ps
CPU time 1.81 seconds
Started Jul 23 07:24:39 PM PDT 24
Finished Jul 23 07:24:41 PM PDT 24
Peak memory 215688 kb
Host smart-0f29296c-10c6-44ac-bdb7-c48294a57063
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767952215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.767952215
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.3081752232
Short name T96
Test name
Test status
Simulation time 579934600 ps
CPU time 7.6 seconds
Started Jul 23 07:24:35 PM PDT 24
Finished Jul 23 07:24:44 PM PDT 24
Peak memory 216020 kb
Host smart-e9e04711-a265-4ef0-aa65-9cf1af132e3a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081752232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.3081752232
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.4135157109
Short name T659
Test name
Test status
Simulation time 50949263 ps
CPU time 0.74 seconds
Started Jul 23 07:05:04 PM PDT 24
Finished Jul 23 07:05:06 PM PDT 24
Peak memory 204992 kb
Host smart-1414001f-201c-4d8c-a649-ae00e4d18862
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135157109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.4
135157109
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.1956002396
Short name T723
Test name
Test status
Simulation time 63056442 ps
CPU time 2.27 seconds
Started Jul 23 07:04:56 PM PDT 24
Finished Jul 23 07:04:59 PM PDT 24
Peak memory 224628 kb
Host smart-3bc021be-fa0a-4756-8f14-7d0fe3a6a057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956002396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.1956002396
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.2614804609
Short name T480
Test name
Test status
Simulation time 14989577 ps
CPU time 0.75 seconds
Started Jul 23 07:04:52 PM PDT 24
Finished Jul 23 07:04:54 PM PDT 24
Peak memory 205716 kb
Host smart-16decbfb-5dee-4410-a37f-d9e8e5b38090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614804609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.2614804609
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.2869613703
Short name T811
Test name
Test status
Simulation time 21379227491 ps
CPU time 60.84 seconds
Started Jul 23 07:05:03 PM PDT 24
Finished Jul 23 07:06:05 PM PDT 24
Peak memory 235840 kb
Host smart-0b62d4e0-4ff5-4ea6-8462-ee6e63bfaf9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869613703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.2869613703
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.587123727
Short name T942
Test name
Test status
Simulation time 33271509750 ps
CPU time 286.44 seconds
Started Jul 23 07:05:15 PM PDT 24
Finished Jul 23 07:10:04 PM PDT 24
Peak memory 268068 kb
Host smart-9e5711da-58c8-4216-b936-c34001eef3ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587123727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle.
587123727
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.2140613033
Short name T974
Test name
Test status
Simulation time 12757251721 ps
CPU time 72.41 seconds
Started Jul 23 07:04:58 PM PDT 24
Finished Jul 23 07:06:12 PM PDT 24
Peak memory 249100 kb
Host smart-70021c1b-2693-4f53-abaf-210a513e4190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140613033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.2140613033
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.2115525937
Short name T761
Test name
Test status
Simulation time 72657001962 ps
CPU time 104.59 seconds
Started Jul 23 07:05:01 PM PDT 24
Finished Jul 23 07:06:46 PM PDT 24
Peak memory 256644 kb
Host smart-f8d27ee7-4f36-47c9-8f0f-08c93d977bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115525937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds
.2115525937
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_intercept.2663694816
Short name T684
Test name
Test status
Simulation time 1162400150 ps
CPU time 12.48 seconds
Started Jul 23 07:04:59 PM PDT 24
Finished Jul 23 07:05:12 PM PDT 24
Peak memory 232912 kb
Host smart-c646bd3f-2854-4620-beef-d5ea80bb9f10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663694816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.2663694816
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.2876970464
Short name T989
Test name
Test status
Simulation time 383962948 ps
CPU time 4.98 seconds
Started Jul 23 07:04:59 PM PDT 24
Finished Jul 23 07:05:04 PM PDT 24
Peak memory 232848 kb
Host smart-da16dc7e-8565-4341-b69a-4ea0724d470a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876970464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.2876970464
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.672836286
Short name T261
Test name
Test status
Simulation time 632191387 ps
CPU time 8.25 seconds
Started Jul 23 07:04:59 PM PDT 24
Finished Jul 23 07:05:08 PM PDT 24
Peak memory 224652 kb
Host smart-5fa875ad-ae50-465a-93e0-6330ebac4c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672836286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap.
672836286
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.4247364667
Short name T604
Test name
Test status
Simulation time 1086396092 ps
CPU time 9.24 seconds
Started Jul 23 07:05:00 PM PDT 24
Finished Jul 23 07:05:10 PM PDT 24
Peak memory 232900 kb
Host smart-639e7f53-aa09-40e9-b478-81d9fa4f26fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247364667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.4247364667
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.3615098487
Short name T401
Test name
Test status
Simulation time 420219942 ps
CPU time 5.93 seconds
Started Jul 23 07:05:01 PM PDT 24
Finished Jul 23 07:05:08 PM PDT 24
Peak memory 223392 kb
Host smart-782e884c-ce58-4891-a146-0f8a6b696f13
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3615098487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.3615098487
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.3050505234
Short name T66
Test name
Test status
Simulation time 237852710 ps
CPU time 1 seconds
Started Jul 23 07:05:03 PM PDT 24
Finished Jul 23 07:05:05 PM PDT 24
Peak memory 235472 kb
Host smart-92d5494f-e9a7-48c3-9d29-fddb1e9514a8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050505234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.3050505234
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.547483449
Short name T145
Test name
Test status
Simulation time 53681310589 ps
CPU time 62.58 seconds
Started Jul 23 07:05:03 PM PDT 24
Finished Jul 23 07:06:07 PM PDT 24
Peak memory 232968 kb
Host smart-6a617dec-ef7e-444f-a8d3-de60a44e9abf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547483449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stress
_all.547483449
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.2919402460
Short name T889
Test name
Test status
Simulation time 67082975 ps
CPU time 0.74 seconds
Started Jul 23 07:04:54 PM PDT 24
Finished Jul 23 07:04:56 PM PDT 24
Peak memory 205832 kb
Host smart-4e4e917c-4949-4b0b-9e14-f2b462ca61f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919402460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.2919402460
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.1545460614
Short name T839
Test name
Test status
Simulation time 5314552202 ps
CPU time 4.69 seconds
Started Jul 23 07:04:52 PM PDT 24
Finished Jul 23 07:04:57 PM PDT 24
Peak memory 216508 kb
Host smart-c596aa3e-b03c-416f-94c3-9d9c707f100a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545460614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.1545460614
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.1084867983
Short name T495
Test name
Test status
Simulation time 200498323 ps
CPU time 6.45 seconds
Started Jul 23 07:04:58 PM PDT 24
Finished Jul 23 07:05:05 PM PDT 24
Peak memory 216488 kb
Host smart-e2472f34-59e8-4681-9ffe-1c9c321c93f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084867983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.1084867983
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.1006226225
Short name T752
Test name
Test status
Simulation time 76054742 ps
CPU time 0.9 seconds
Started Jul 23 07:04:59 PM PDT 24
Finished Jul 23 07:05:01 PM PDT 24
Peak memory 206104 kb
Host smart-63fd4c1d-26dc-4935-a05b-b9f209a81cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006226225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.1006226225
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.633190312
Short name T451
Test name
Test status
Simulation time 1730622700 ps
CPU time 4.29 seconds
Started Jul 23 07:04:59 PM PDT 24
Finished Jul 23 07:05:04 PM PDT 24
Peak memory 224648 kb
Host smart-f99e8fc0-2032-4f64-9018-249e168e3e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633190312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.633190312
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.1525455271
Short name T896
Test name
Test status
Simulation time 23852554 ps
CPU time 0.69 seconds
Started Jul 23 07:05:09 PM PDT 24
Finished Jul 23 07:05:11 PM PDT 24
Peak memory 205584 kb
Host smart-57ec5758-a312-4da1-89e3-926ef3e11dca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525455271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.1
525455271
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.1431041999
Short name T413
Test name
Test status
Simulation time 1704958269 ps
CPU time 6.37 seconds
Started Jul 23 07:05:07 PM PDT 24
Finished Jul 23 07:05:14 PM PDT 24
Peak memory 233068 kb
Host smart-7de55a26-0646-4eaf-9fe8-3b1b519508c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431041999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.1431041999
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.2787009071
Short name T959
Test name
Test status
Simulation time 30141837 ps
CPU time 0.79 seconds
Started Jul 23 07:05:02 PM PDT 24
Finished Jul 23 07:05:04 PM PDT 24
Peak memory 206724 kb
Host smart-8366aede-8840-4c72-b88b-ab4447cdcd93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787009071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.2787009071
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.3952842432
Short name T257
Test name
Test status
Simulation time 8880300761 ps
CPU time 62.63 seconds
Started Jul 23 07:05:13 PM PDT 24
Finished Jul 23 07:06:16 PM PDT 24
Peak memory 249352 kb
Host smart-af370ce7-931d-4025-93ad-758bdb943f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952842432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.3952842432
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.3916730950
Short name T609
Test name
Test status
Simulation time 291634299588 ps
CPU time 557.86 seconds
Started Jul 23 07:05:08 PM PDT 24
Finished Jul 23 07:14:27 PM PDT 24
Peak memory 273704 kb
Host smart-61f2e682-4791-4a6d-a4c2-c7912d81fd60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916730950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.3916730950
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.2772195747
Short name T937
Test name
Test status
Simulation time 27018850357 ps
CPU time 166.37 seconds
Started Jul 23 07:05:08 PM PDT 24
Finished Jul 23 07:07:56 PM PDT 24
Peak memory 254548 kb
Host smart-642a32fa-4fe3-4599-8d2a-78a5603c8625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772195747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.2772195747
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.1062757431
Short name T274
Test name
Test status
Simulation time 4753029149 ps
CPU time 15.61 seconds
Started Jul 23 07:05:03 PM PDT 24
Finished Jul 23 07:05:20 PM PDT 24
Peak memory 235236 kb
Host smart-daa4aa3e-5f1d-45dd-89f6-3c3c58ed6c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062757431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.1062757431
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.685459835
Short name T611
Test name
Test status
Simulation time 15310068 ps
CPU time 0.77 seconds
Started Jul 23 07:05:02 PM PDT 24
Finished Jul 23 07:05:04 PM PDT 24
Peak memory 215908 kb
Host smart-b154133f-39ee-4f56-aeb9-a730ddc86c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685459835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds.
685459835
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_intercept.809345485
Short name T643
Test name
Test status
Simulation time 226191093 ps
CPU time 2.65 seconds
Started Jul 23 07:05:03 PM PDT 24
Finished Jul 23 07:05:07 PM PDT 24
Peak memory 224704 kb
Host smart-6fc9788a-4aad-47fe-93ac-787347897282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809345485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.809345485
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.3686292361
Short name T720
Test name
Test status
Simulation time 3413582664 ps
CPU time 6.3 seconds
Started Jul 23 07:05:15 PM PDT 24
Finished Jul 23 07:05:24 PM PDT 24
Peak memory 232964 kb
Host smart-2ef6453d-09a7-410f-8a35-1cb3c1daca2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686292361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.3686292361
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.573678638
Short name T535
Test name
Test status
Simulation time 560299516 ps
CPU time 9.8 seconds
Started Jul 23 07:05:03 PM PDT 24
Finished Jul 23 07:05:14 PM PDT 24
Peak memory 233888 kb
Host smart-eeb8b19a-d675-4f88-8145-bea3727665ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573678638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.573678638
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.1824732808
Short name T792
Test name
Test status
Simulation time 133768961 ps
CPU time 3.36 seconds
Started Jul 23 07:05:15 PM PDT 24
Finished Jul 23 07:05:21 PM PDT 24
Peak memory 220808 kb
Host smart-50c078a6-be85-4d7e-b588-200ceeb7e47e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1824732808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.1824732808
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.1640749451
Short name T65
Test name
Test status
Simulation time 192806894 ps
CPU time 1.05 seconds
Started Jul 23 07:05:09 PM PDT 24
Finished Jul 23 07:05:11 PM PDT 24
Peak memory 235872 kb
Host smart-cd5af442-f84e-4f61-8197-1db934ea82fc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640749451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.1640749451
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.2338375554
Short name T453
Test name
Test status
Simulation time 1176069106 ps
CPU time 5.41 seconds
Started Jul 23 07:05:03 PM PDT 24
Finished Jul 23 07:05:09 PM PDT 24
Peak memory 216388 kb
Host smart-11137b36-1b75-448e-bca8-2d1fb9359feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338375554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.2338375554
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.3895518052
Short name T152
Test name
Test status
Simulation time 10615231 ps
CPU time 0.75 seconds
Started Jul 23 07:05:01 PM PDT 24
Finished Jul 23 07:05:03 PM PDT 24
Peak memory 205700 kb
Host smart-2e2f349e-260a-4dbb-9b96-1bff50371fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895518052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.3895518052
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.2309438628
Short name T928
Test name
Test status
Simulation time 130631406 ps
CPU time 1.1 seconds
Started Jul 23 07:05:02 PM PDT 24
Finished Jul 23 07:05:05 PM PDT 24
Peak memory 208264 kb
Host smart-f699450a-ad98-47fc-a36d-231d8dda8b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309438628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.2309438628
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.744360294
Short name T392
Test name
Test status
Simulation time 14943864 ps
CPU time 0.74 seconds
Started Jul 23 07:05:06 PM PDT 24
Finished Jul 23 07:05:07 PM PDT 24
Peak memory 206088 kb
Host smart-5687366f-a126-4696-aa6a-802f414aca77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744360294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.744360294
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.2765010064
Short name T696
Test name
Test status
Simulation time 3667496418 ps
CPU time 9.89 seconds
Started Jul 23 07:05:06 PM PDT 24
Finished Jul 23 07:05:17 PM PDT 24
Peak memory 224896 kb
Host smart-19bd3a77-6445-42bb-bd47-2c03c85f857d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765010064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.2765010064
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.1263574662
Short name T557
Test name
Test status
Simulation time 14958634 ps
CPU time 0.7 seconds
Started Jul 23 07:05:50 PM PDT 24
Finished Jul 23 07:05:52 PM PDT 24
Peak memory 205612 kb
Host smart-06d4de1f-d009-48a9-a62b-8b2fcc56787d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263574662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
1263574662
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.3734023118
Short name T945
Test name
Test status
Simulation time 183475219 ps
CPU time 3.39 seconds
Started Jul 23 07:05:53 PM PDT 24
Finished Jul 23 07:05:58 PM PDT 24
Peak memory 224840 kb
Host smart-5d4d3694-7e8a-44a3-aae7-08abdeee1013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734023118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.3734023118
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.3466396487
Short name T321
Test name
Test status
Simulation time 29132426 ps
CPU time 0.74 seconds
Started Jul 23 07:05:46 PM PDT 24
Finished Jul 23 07:05:48 PM PDT 24
Peak memory 206044 kb
Host smart-8f6a967a-38e5-47e5-a24f-d877472d878c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466396487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.3466396487
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.3531901533
Short name T168
Test name
Test status
Simulation time 4462426641 ps
CPU time 44.93 seconds
Started Jul 23 07:05:51 PM PDT 24
Finished Jul 23 07:06:37 PM PDT 24
Peak memory 255696 kb
Host smart-c7a0f9b8-b109-410f-8b8a-ef881a462e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531901533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.3531901533
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.889201854
Short name T475
Test name
Test status
Simulation time 38307646585 ps
CPU time 165.73 seconds
Started Jul 23 07:05:51 PM PDT 24
Finished Jul 23 07:08:37 PM PDT 24
Peak memory 249408 kb
Host smart-587ff024-df78-4e98-a827-403d6b75da31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889201854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idle
.889201854
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.1626302999
Short name T724
Test name
Test status
Simulation time 445178384 ps
CPU time 17.23 seconds
Started Jul 23 07:05:50 PM PDT 24
Finished Jul 23 07:06:09 PM PDT 24
Peak memory 224688 kb
Host smart-cd62e0ad-9299-4e9f-a61b-3e171a67f863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626302999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.1626302999
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.3432107857
Short name T164
Test name
Test status
Simulation time 921269527 ps
CPU time 10.79 seconds
Started Jul 23 07:05:53 PM PDT 24
Finished Jul 23 07:06:05 PM PDT 24
Peak memory 232924 kb
Host smart-9ea13733-11c4-4ac3-8db2-035656f371bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432107857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmd
s.3432107857
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_intercept.1556369229
Short name T745
Test name
Test status
Simulation time 198923102 ps
CPU time 3.81 seconds
Started Jul 23 07:05:51 PM PDT 24
Finished Jul 23 07:05:56 PM PDT 24
Peak memory 224664 kb
Host smart-b0243ff2-3dbe-4dfc-b6e5-f7b276b7b632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556369229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.1556369229
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.4144001364
Short name T539
Test name
Test status
Simulation time 2673834332 ps
CPU time 25.12 seconds
Started Jul 23 07:05:54 PM PDT 24
Finished Jul 23 07:06:20 PM PDT 24
Peak memory 232952 kb
Host smart-50f4ce3a-95e5-4ffb-964e-4b39277e7d60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144001364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.4144001364
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.1993417098
Short name T772
Test name
Test status
Simulation time 746343894 ps
CPU time 4.68 seconds
Started Jul 23 07:05:54 PM PDT 24
Finished Jul 23 07:05:59 PM PDT 24
Peak memory 224652 kb
Host smart-ca1d375b-9877-4a52-a2cd-47757f1767df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993417098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.1993417098
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.4288841255
Short name T790
Test name
Test status
Simulation time 748372651 ps
CPU time 4.3 seconds
Started Jul 23 07:05:52 PM PDT 24
Finished Jul 23 07:05:58 PM PDT 24
Peak memory 232896 kb
Host smart-0efca4ac-b28f-4746-9f18-72cb9de7bbff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288841255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.4288841255
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.4167945051
Short name T912
Test name
Test status
Simulation time 217318875 ps
CPU time 5.35 seconds
Started Jul 23 07:05:52 PM PDT 24
Finished Jul 23 07:05:58 PM PDT 24
Peak memory 221044 kb
Host smart-eb6952c8-dc0b-4762-bef8-a53643de15cc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4167945051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.4167945051
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.1014465368
Short name T982
Test name
Test status
Simulation time 18632750227 ps
CPU time 119.43 seconds
Started Jul 23 07:05:53 PM PDT 24
Finished Jul 23 07:07:53 PM PDT 24
Peak memory 266732 kb
Host smart-cca74b0b-2ae7-477b-ad90-91a8b19b0221
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014465368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.1014465368
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.3011900335
Short name T631
Test name
Test status
Simulation time 2804821933 ps
CPU time 22.96 seconds
Started Jul 23 07:05:49 PM PDT 24
Finished Jul 23 07:06:13 PM PDT 24
Peak memory 220264 kb
Host smart-51cc683e-526c-4282-a57c-a1b60bf7d274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011900335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.3011900335
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.3310175218
Short name T884
Test name
Test status
Simulation time 25048414346 ps
CPU time 13.64 seconds
Started Jul 23 07:05:50 PM PDT 24
Finished Jul 23 07:06:04 PM PDT 24
Peak memory 218196 kb
Host smart-b1d8a159-5c3f-4ab7-8356-f88f73298846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310175218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.3310175218
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.1070525844
Short name T946
Test name
Test status
Simulation time 179479980 ps
CPU time 2.26 seconds
Started Jul 23 07:05:50 PM PDT 24
Finished Jul 23 07:05:53 PM PDT 24
Peak memory 216392 kb
Host smart-6987ebea-215b-4fca-b74a-ee51ed9983a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070525844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.1070525844
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.3268200973
Short name T780
Test name
Test status
Simulation time 346393953 ps
CPU time 0.91 seconds
Started Jul 23 07:05:47 PM PDT 24
Finished Jul 23 07:05:49 PM PDT 24
Peak memory 206376 kb
Host smart-9e356fac-877c-4d1c-8bac-a3da794b886b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268200973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.3268200973
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.2197382754
Short name T366
Test name
Test status
Simulation time 33014432577 ps
CPU time 7.42 seconds
Started Jul 23 07:05:51 PM PDT 24
Finished Jul 23 07:06:00 PM PDT 24
Peak memory 232940 kb
Host smart-ded32ffb-5976-4997-83d4-6f72f426a395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197382754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.2197382754
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.2202152240
Short name T843
Test name
Test status
Simulation time 42886876 ps
CPU time 0.71 seconds
Started Jul 23 07:05:56 PM PDT 24
Finished Jul 23 07:05:58 PM PDT 24
Peak memory 204972 kb
Host smart-41bd9eda-b895-46e2-8a17-e678b462171f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202152240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
2202152240
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.3611993955
Short name T693
Test name
Test status
Simulation time 18211812847 ps
CPU time 12.82 seconds
Started Jul 23 07:06:01 PM PDT 24
Finished Jul 23 07:06:16 PM PDT 24
Peak memory 232936 kb
Host smart-963adfc1-d8c7-4cac-9c5f-28b3976682a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611993955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.3611993955
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.662569019
Short name T647
Test name
Test status
Simulation time 21876502 ps
CPU time 0.76 seconds
Started Jul 23 07:05:51 PM PDT 24
Finished Jul 23 07:05:53 PM PDT 24
Peak memory 206780 kb
Host smart-c0d8b36f-27a1-4211-a411-cbca4750e07f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662569019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.662569019
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.959500568
Short name T42
Test name
Test status
Simulation time 9698160684 ps
CPU time 55.23 seconds
Started Jul 23 07:06:00 PM PDT 24
Finished Jul 23 07:06:57 PM PDT 24
Peak memory 273860 kb
Host smart-40c8cd95-45fa-4a29-9f2c-aaf83acc6a29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959500568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.959500568
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.3679108086
Short name T813
Test name
Test status
Simulation time 27606771991 ps
CPU time 69.65 seconds
Started Jul 23 07:05:58 PM PDT 24
Finished Jul 23 07:07:09 PM PDT 24
Peak memory 240152 kb
Host smart-e0fc4c5c-23c0-4436-8bd2-7e6f12063f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679108086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.3679108086
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.631905422
Short name T739
Test name
Test status
Simulation time 394423792 ps
CPU time 5.06 seconds
Started Jul 23 07:05:59 PM PDT 24
Finished Jul 23 07:06:06 PM PDT 24
Peak memory 235140 kb
Host smart-3977d901-32b3-492f-a968-7fac2bca53df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631905422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.631905422
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.2619716150
Short name T624
Test name
Test status
Simulation time 21758666218 ps
CPU time 28.88 seconds
Started Jul 23 07:05:57 PM PDT 24
Finished Jul 23 07:06:28 PM PDT 24
Peak memory 249392 kb
Host smart-ce19ce6c-321b-4004-bb09-fee80944a7a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619716150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmd
s.2619716150
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_intercept.2598608963
Short name T802
Test name
Test status
Simulation time 998174348 ps
CPU time 6.04 seconds
Started Jul 23 07:05:58 PM PDT 24
Finished Jul 23 07:06:06 PM PDT 24
Peak memory 219032 kb
Host smart-953245bb-b4d4-469c-bba8-951d06e877dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598608963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.2598608963
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.3220097814
Short name T234
Test name
Test status
Simulation time 4223607590 ps
CPU time 14.23 seconds
Started Jul 23 07:05:57 PM PDT 24
Finished Jul 23 07:06:12 PM PDT 24
Peak memory 224752 kb
Host smart-477f1aeb-2aa3-4ff8-8074-29e38643bf39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220097814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.3220097814
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.759796272
Short name T951
Test name
Test status
Simulation time 4867474298 ps
CPU time 14.18 seconds
Started Jul 23 07:05:57 PM PDT 24
Finished Jul 23 07:06:12 PM PDT 24
Peak memory 232984 kb
Host smart-fe241df6-c6c0-4b06-a67a-82310594b0ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759796272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swap
.759796272
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.1716474084
Short name T610
Test name
Test status
Simulation time 19053547206 ps
CPU time 11.73 seconds
Started Jul 23 07:05:58 PM PDT 24
Finished Jul 23 07:06:10 PM PDT 24
Peak memory 224732 kb
Host smart-da3b311e-cbc0-4bb0-91ea-6d5d554eb03e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716474084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.1716474084
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.2332939165
Short name T129
Test name
Test status
Simulation time 906786810 ps
CPU time 5.21 seconds
Started Jul 23 07:05:58 PM PDT 24
Finished Jul 23 07:06:05 PM PDT 24
Peak memory 223452 kb
Host smart-86c904c0-37db-460a-b8d1-e536e9350612
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2332939165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.2332939165
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.1746315059
Short name T749
Test name
Test status
Simulation time 1677905866 ps
CPU time 46.61 seconds
Started Jul 23 07:06:01 PM PDT 24
Finished Jul 23 07:06:50 PM PDT 24
Peak memory 252840 kb
Host smart-f45bc4e5-5f8c-4519-8f39-38a7797b405b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746315059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.1746315059
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.252339278
Short name T949
Test name
Test status
Simulation time 6420322336 ps
CPU time 36.6 seconds
Started Jul 23 07:05:54 PM PDT 24
Finished Jul 23 07:06:31 PM PDT 24
Peak memory 216572 kb
Host smart-0486b3d0-996f-45d6-94d0-c9cf824c7ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252339278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.252339278
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.3712486393
Short name T588
Test name
Test status
Simulation time 5717785155 ps
CPU time 9.65 seconds
Started Jul 23 07:05:52 PM PDT 24
Finished Jul 23 07:06:03 PM PDT 24
Peak memory 216496 kb
Host smart-92159969-cf02-4ab7-afc9-a31aca20ff6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712486393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.3712486393
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.1619159757
Short name T607
Test name
Test status
Simulation time 228824424 ps
CPU time 0.92 seconds
Started Jul 23 07:05:59 PM PDT 24
Finished Jul 23 07:06:01 PM PDT 24
Peak memory 207572 kb
Host smart-102fe3f4-3d31-4737-8612-2e541713285c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619159757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.1619159757
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.2910919821
Short name T767
Test name
Test status
Simulation time 39553689 ps
CPU time 0.7 seconds
Started Jul 23 07:05:59 PM PDT 24
Finished Jul 23 07:06:01 PM PDT 24
Peak memory 205716 kb
Host smart-58ff734d-ae8f-46cd-8155-bc686ba991b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910919821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.2910919821
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.1687140273
Short name T155
Test name
Test status
Simulation time 7109808178 ps
CPU time 27.11 seconds
Started Jul 23 07:05:58 PM PDT 24
Finished Jul 23 07:06:26 PM PDT 24
Peak memory 241136 kb
Host smart-d7dacb36-5155-4ad7-a1f5-5424bad238cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687140273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.1687140273
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.3668890138
Short name T817
Test name
Test status
Simulation time 12979839 ps
CPU time 0.71 seconds
Started Jul 23 07:06:05 PM PDT 24
Finished Jul 23 07:06:07 PM PDT 24
Peak memory 205028 kb
Host smart-e86bb613-b2f7-4e5d-8c12-da86b8d92287
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668890138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
3668890138
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.1931546250
Short name T841
Test name
Test status
Simulation time 5338766887 ps
CPU time 4.01 seconds
Started Jul 23 07:06:02 PM PDT 24
Finished Jul 23 07:06:08 PM PDT 24
Peak memory 232880 kb
Host smart-d255d760-64a5-4a7d-bc33-55e381b0c461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931546250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.1931546250
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.3050258472
Short name T816
Test name
Test status
Simulation time 37791166 ps
CPU time 0.78 seconds
Started Jul 23 07:05:57 PM PDT 24
Finished Jul 23 07:05:59 PM PDT 24
Peak memory 206684 kb
Host smart-03cbbffd-c65e-4255-a8bd-327a64df8800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050258472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.3050258472
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.431890348
Short name T830
Test name
Test status
Simulation time 17664148046 ps
CPU time 56.18 seconds
Started Jul 23 07:06:02 PM PDT 24
Finished Jul 23 07:07:00 PM PDT 24
Peak memory 255540 kb
Host smart-6d13489c-73ed-475b-a833-4c8a695e0792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431890348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.431890348
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.3776308312
Short name T788
Test name
Test status
Simulation time 28723568452 ps
CPU time 96.92 seconds
Started Jul 23 07:06:04 PM PDT 24
Finished Jul 23 07:07:42 PM PDT 24
Peak memory 253832 kb
Host smart-4714ca2a-82c1-4136-a16b-6f54d53d0cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776308312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.3776308312
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.4231005807
Short name T918
Test name
Test status
Simulation time 1356067748 ps
CPU time 22.32 seconds
Started Jul 23 07:06:04 PM PDT 24
Finished Jul 23 07:06:28 PM PDT 24
Peak memory 237488 kb
Host smart-088661fb-4d6b-4e4c-bac6-0e9604eee1e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231005807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.4231005807
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_intercept.57708401
Short name T766
Test name
Test status
Simulation time 5093536031 ps
CPU time 9.8 seconds
Started Jul 23 07:06:03 PM PDT 24
Finished Jul 23 07:06:15 PM PDT 24
Peak memory 224672 kb
Host smart-e1be0044-c937-464f-941a-ee7e10d7e096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57708401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.57708401
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.2841926931
Short name T182
Test name
Test status
Simulation time 1923691636 ps
CPU time 18.5 seconds
Started Jul 23 07:06:03 PM PDT 24
Finished Jul 23 07:06:24 PM PDT 24
Peak memory 232884 kb
Host smart-e593e562-d3ff-41fa-bd14-7db36e81d42e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841926931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.2841926931
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.2371627488
Short name T922
Test name
Test status
Simulation time 846933072 ps
CPU time 4.73 seconds
Started Jul 23 07:05:59 PM PDT 24
Finished Jul 23 07:06:05 PM PDT 24
Peak memory 232836 kb
Host smart-62542d87-115e-4b4e-ad72-d960d1bf30f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371627488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.2371627488
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.4284628748
Short name T219
Test name
Test status
Simulation time 14195263824 ps
CPU time 7.14 seconds
Started Jul 23 07:06:01 PM PDT 24
Finished Jul 23 07:06:10 PM PDT 24
Peak memory 224780 kb
Host smart-04536b4d-fdd2-4e9c-92f6-e19ecf1b9b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284628748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.4284628748
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.725055368
Short name T920
Test name
Test status
Simulation time 1461265746 ps
CPU time 4.03 seconds
Started Jul 23 07:06:03 PM PDT 24
Finished Jul 23 07:06:08 PM PDT 24
Peak memory 220252 kb
Host smart-682cefe0-a68d-49d0-9755-50863de2e43a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=725055368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dire
ct.725055368
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.2846130990
Short name T994
Test name
Test status
Simulation time 12683678808 ps
CPU time 31.59 seconds
Started Jul 23 07:05:57 PM PDT 24
Finished Jul 23 07:06:30 PM PDT 24
Peak memory 216532 kb
Host smart-eb4c0aa2-6cb4-459b-9fd4-b4bca3edaa47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846130990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.2846130990
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.2076431498
Short name T555
Test name
Test status
Simulation time 270698963 ps
CPU time 1.97 seconds
Started Jul 23 07:05:56 PM PDT 24
Finished Jul 23 07:05:59 PM PDT 24
Peak memory 208024 kb
Host smart-eb937297-8dd4-4abb-bc84-4d8f628b7026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076431498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.2076431498
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.2655119780
Short name T372
Test name
Test status
Simulation time 297694091 ps
CPU time 2.46 seconds
Started Jul 23 07:05:58 PM PDT 24
Finished Jul 23 07:06:02 PM PDT 24
Peak memory 216392 kb
Host smart-b7f82574-c12c-45da-b808-e4fb978a3054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655119780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.2655119780
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_upload.3857590531
Short name T518
Test name
Test status
Simulation time 930645669 ps
CPU time 3.09 seconds
Started Jul 23 07:06:05 PM PDT 24
Finished Jul 23 07:06:09 PM PDT 24
Peak memory 232904 kb
Host smart-f1649e56-22b8-4b5b-b519-762abf512480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857590531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.3857590531
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.414902955
Short name T389
Test name
Test status
Simulation time 14759904 ps
CPU time 0.73 seconds
Started Jul 23 07:06:08 PM PDT 24
Finished Jul 23 07:06:09 PM PDT 24
Peak memory 205924 kb
Host smart-3129b7c9-68ed-4b9f-bf4d-d0c273f1e7aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414902955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.414902955
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.3900127938
Short name T617
Test name
Test status
Simulation time 484532428 ps
CPU time 7.29 seconds
Started Jul 23 07:06:07 PM PDT 24
Finished Jul 23 07:06:15 PM PDT 24
Peak memory 232888 kb
Host smart-36f720d7-4b26-41ca-9ba2-4add904443f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900127938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.3900127938
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.3210304015
Short name T701
Test name
Test status
Simulation time 131192074 ps
CPU time 0.77 seconds
Started Jul 23 07:06:03 PM PDT 24
Finished Jul 23 07:06:06 PM PDT 24
Peak memory 206736 kb
Host smart-e356f075-61b5-47c0-9853-7520479a2638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210304015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.3210304015
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.4292602596
Short name T540
Test name
Test status
Simulation time 19271974701 ps
CPU time 74.8 seconds
Started Jul 23 07:06:09 PM PDT 24
Finished Jul 23 07:07:24 PM PDT 24
Peak memory 249332 kb
Host smart-eb64dcb6-1da8-452c-ad09-9483590f8605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292602596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.4292602596
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.1786719317
Short name T206
Test name
Test status
Simulation time 14323931979 ps
CPU time 99.49 seconds
Started Jul 23 07:06:08 PM PDT 24
Finished Jul 23 07:07:49 PM PDT 24
Peak memory 249788 kb
Host smart-2e5b015c-843a-47fb-9e89-4f7929eb713f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786719317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.1786719317
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.908724964
Short name T267
Test name
Test status
Simulation time 4745284814 ps
CPU time 58.48 seconds
Started Jul 23 07:06:05 PM PDT 24
Finished Jul 23 07:07:05 PM PDT 24
Peak memory 257352 kb
Host smart-e230b0bb-e654-4c2c-a170-59c1119b7132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908724964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idle
.908724964
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.2377046242
Short name T879
Test name
Test status
Simulation time 214707334 ps
CPU time 6.74 seconds
Started Jul 23 07:06:07 PM PDT 24
Finished Jul 23 07:06:14 PM PDT 24
Peak memory 224492 kb
Host smart-1a72e566-8117-4276-8fe8-0233eaeaa4af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377046242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.2377046242
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.912419579
Short name T503
Test name
Test status
Simulation time 6968675440 ps
CPU time 35.66 seconds
Started Jul 23 07:06:08 PM PDT 24
Finished Jul 23 07:06:45 PM PDT 24
Peak memory 250720 kb
Host smart-cfe19ba8-da58-45f5-9430-1de09f24d2d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912419579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmds
.912419579
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_intercept.2034463144
Short name T576
Test name
Test status
Simulation time 606237555 ps
CPU time 6.77 seconds
Started Jul 23 07:06:04 PM PDT 24
Finished Jul 23 07:06:13 PM PDT 24
Peak memory 228236 kb
Host smart-57525ca7-0b07-48f8-ae5c-dccc6bbb48d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034463144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.2034463144
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.2944659251
Short name T74
Test name
Test status
Simulation time 9287431932 ps
CPU time 22.45 seconds
Started Jul 23 07:06:01 PM PDT 24
Finished Jul 23 07:06:25 PM PDT 24
Peak memory 249260 kb
Host smart-da81e6c2-0012-47ca-8a3f-929765c402d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944659251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.2944659251
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.992084445
Short name T734
Test name
Test status
Simulation time 1663929296 ps
CPU time 5.8 seconds
Started Jul 23 07:06:03 PM PDT 24
Finished Jul 23 07:06:10 PM PDT 24
Peak memory 240160 kb
Host smart-b4402ba9-78f6-41d8-8de9-601cbc79b6d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992084445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swap
.992084445
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.2633387439
Short name T633
Test name
Test status
Simulation time 363927613 ps
CPU time 3.31 seconds
Started Jul 23 07:06:02 PM PDT 24
Finished Jul 23 07:06:07 PM PDT 24
Peak memory 224728 kb
Host smart-6308ae06-f691-4e54-b909-5768b0e9954e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633387439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.2633387439
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.1832550155
Short name T348
Test name
Test status
Simulation time 484912792 ps
CPU time 4.41 seconds
Started Jul 23 07:06:10 PM PDT 24
Finished Jul 23 07:06:15 PM PDT 24
Peak memory 223008 kb
Host smart-2e301ed1-77e5-41b8-9d49-faaeb48d7e12
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1832550155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.1832550155
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.1762678342
Short name T646
Test name
Test status
Simulation time 74795828 ps
CPU time 1.08 seconds
Started Jul 23 07:06:08 PM PDT 24
Finished Jul 23 07:06:10 PM PDT 24
Peak memory 215484 kb
Host smart-5b886cd6-81f4-45d6-8e83-e1fe9c50d73e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762678342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.1762678342
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.308178396
Short name T785
Test name
Test status
Simulation time 2311442439 ps
CPU time 7.55 seconds
Started Jul 23 07:06:04 PM PDT 24
Finished Jul 23 07:06:14 PM PDT 24
Peak memory 216476 kb
Host smart-654841a2-94a7-49ab-a175-9c78cf41bf84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308178396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.308178396
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.956532063
Short name T467
Test name
Test status
Simulation time 22120474 ps
CPU time 0.74 seconds
Started Jul 23 07:06:05 PM PDT 24
Finished Jul 23 07:06:07 PM PDT 24
Peak memory 206088 kb
Host smart-fcd7a6f0-74e8-435b-a593-5349eb32f39d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956532063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.956532063
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.2626768835
Short name T737
Test name
Test status
Simulation time 91688725 ps
CPU time 0.8 seconds
Started Jul 23 07:06:01 PM PDT 24
Finished Jul 23 07:06:04 PM PDT 24
Peak memory 206104 kb
Host smart-c005d3c7-c304-4594-b06b-81fa5a85f8c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626768835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.2626768835
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.222058005
Short name T378
Test name
Test status
Simulation time 7588153249 ps
CPU time 17.51 seconds
Started Jul 23 07:06:08 PM PDT 24
Finished Jul 23 07:06:27 PM PDT 24
Peak memory 238856 kb
Host smart-2d7624cd-c1b6-4305-987f-3c436aa3dc41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222058005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.222058005
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.1198891472
Short name T622
Test name
Test status
Simulation time 42645499 ps
CPU time 0.68 seconds
Started Jul 23 07:06:13 PM PDT 24
Finished Jul 23 07:06:15 PM PDT 24
Peak memory 205560 kb
Host smart-53bf17e7-aefd-4948-b64a-8ea5b8f5e25a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198891472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
1198891472
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.3526561776
Short name T820
Test name
Test status
Simulation time 339425900 ps
CPU time 2.87 seconds
Started Jul 23 07:06:12 PM PDT 24
Finished Jul 23 07:06:15 PM PDT 24
Peak memory 232864 kb
Host smart-ad320dac-1465-4cf7-89ea-6a063e3339da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526561776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.3526561776
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.1495527448
Short name T31
Test name
Test status
Simulation time 24628439 ps
CPU time 0.75 seconds
Started Jul 23 07:06:09 PM PDT 24
Finished Jul 23 07:06:10 PM PDT 24
Peak memory 207060 kb
Host smart-c6e0c276-26c1-4e7d-96ba-6a72fda98f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495527448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.1495527448
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.266990478
Short name T459
Test name
Test status
Simulation time 24832194041 ps
CPU time 48.28 seconds
Started Jul 23 07:06:15 PM PDT 24
Finished Jul 23 07:07:04 PM PDT 24
Peak memory 250376 kb
Host smart-e988ded1-ef78-44f0-bcd4-2901a8312f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266990478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.266990478
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.2450253616
Short name T250
Test name
Test status
Simulation time 63568725932 ps
CPU time 547.13 seconds
Started Jul 23 07:06:16 PM PDT 24
Finished Jul 23 07:15:25 PM PDT 24
Peak memory 285688 kb
Host smart-1e46dfad-6f9e-4272-8f6e-1c512175edfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450253616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.2450253616
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.2370047032
Short name T800
Test name
Test status
Simulation time 70515572330 ps
CPU time 98.48 seconds
Started Jul 23 07:06:13 PM PDT 24
Finished Jul 23 07:07:53 PM PDT 24
Peak memory 253388 kb
Host smart-76cef332-5120-47ff-b996-4f7f4350341d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370047032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.2370047032
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.3061301954
Short name T571
Test name
Test status
Simulation time 304622616 ps
CPU time 5.69 seconds
Started Jul 23 07:06:17 PM PDT 24
Finished Jul 23 07:06:24 PM PDT 24
Peak memory 232900 kb
Host smart-92a75565-1930-45dd-ad00-44bde93576a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061301954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.3061301954
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_intercept.1451607647
Short name T852
Test name
Test status
Simulation time 2354383959 ps
CPU time 3.84 seconds
Started Jul 23 07:06:17 PM PDT 24
Finished Jul 23 07:06:22 PM PDT 24
Peak memory 232956 kb
Host smart-f3410032-640c-461e-9313-f3cdcab6a886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451607647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.1451607647
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.310602979
Short name T917
Test name
Test status
Simulation time 7834416482 ps
CPU time 31.21 seconds
Started Jul 23 07:06:13 PM PDT 24
Finished Jul 23 07:06:45 PM PDT 24
Peak memory 232944 kb
Host smart-4093106a-20a7-4e9f-92c6-563f2d5da692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310602979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.310602979
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.458899205
Short name T242
Test name
Test status
Simulation time 745446383 ps
CPU time 3.73 seconds
Started Jul 23 07:06:18 PM PDT 24
Finished Jul 23 07:06:23 PM PDT 24
Peak memory 224536 kb
Host smart-227d96c7-a363-4508-a3e0-a28d15c53f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458899205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swap
.458899205
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.82808649
Short name T416
Test name
Test status
Simulation time 2046877887 ps
CPU time 8.38 seconds
Started Jul 23 07:06:13 PM PDT 24
Finished Jul 23 07:06:22 PM PDT 24
Peak memory 240664 kb
Host smart-35e93725-91ec-4c9e-9538-8442a628eff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82808649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.82808649
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.4241631113
Short name T330
Test name
Test status
Simulation time 507617436 ps
CPU time 5.19 seconds
Started Jul 23 07:06:18 PM PDT 24
Finished Jul 23 07:06:25 PM PDT 24
Peak memory 220980 kb
Host smart-76c7c30f-30aa-4316-baaf-43ad00cc1819
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4241631113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.4241631113
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.1553001745
Short name T580
Test name
Test status
Simulation time 103134906 ps
CPU time 0.94 seconds
Started Jul 23 07:06:17 PM PDT 24
Finished Jul 23 07:06:20 PM PDT 24
Peak memory 207184 kb
Host smart-2e9253cc-fb1a-417e-9e80-7e0025d13143
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553001745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.1553001745
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.2929519413
Short name T33
Test name
Test status
Simulation time 614789014 ps
CPU time 10.13 seconds
Started Jul 23 07:06:13 PM PDT 24
Finished Jul 23 07:06:24 PM PDT 24
Peak memory 216428 kb
Host smart-65128a9b-38b4-4b51-a480-317d6d305e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929519413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.2929519413
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.3798351313
Short name T733
Test name
Test status
Simulation time 4876091361 ps
CPU time 3.28 seconds
Started Jul 23 07:06:12 PM PDT 24
Finished Jul 23 07:06:16 PM PDT 24
Peak memory 216344 kb
Host smart-161f1c41-dd02-44c2-93d0-5a181d938eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798351313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.3798351313
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.654758508
Short name T325
Test name
Test status
Simulation time 104121745 ps
CPU time 0.98 seconds
Started Jul 23 07:06:13 PM PDT 24
Finished Jul 23 07:06:15 PM PDT 24
Peak memory 207156 kb
Host smart-60e624af-b8ab-4bb3-ad4f-3c49e4cd9ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654758508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.654758508
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.2043074669
Short name T354
Test name
Test status
Simulation time 94498645 ps
CPU time 0.82 seconds
Started Jul 23 07:06:17 PM PDT 24
Finished Jul 23 07:06:20 PM PDT 24
Peak memory 206080 kb
Host smart-cdf527c5-cf28-43eb-8c87-b758086496f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043074669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.2043074669
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.3463390199
Short name T597
Test name
Test status
Simulation time 12231252614 ps
CPU time 11.37 seconds
Started Jul 23 07:06:14 PM PDT 24
Finished Jul 23 07:06:27 PM PDT 24
Peak memory 224692 kb
Host smart-95d83fff-caf7-400f-8fcd-a1f5cb7964cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463390199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.3463390199
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.2665368205
Short name T479
Test name
Test status
Simulation time 2719313295 ps
CPU time 5.82 seconds
Started Jul 23 07:06:20 PM PDT 24
Finished Jul 23 07:06:27 PM PDT 24
Peak memory 224752 kb
Host smart-f972bbe1-e3ca-422f-8229-46eb8846e918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665368205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.2665368205
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.1927497109
Short name T947
Test name
Test status
Simulation time 63421803 ps
CPU time 0.74 seconds
Started Jul 23 07:06:17 PM PDT 24
Finished Jul 23 07:06:19 PM PDT 24
Peak memory 206752 kb
Host smart-ff5ae13d-018c-4d94-8532-4425133c8160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927497109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.1927497109
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.169725435
Short name T192
Test name
Test status
Simulation time 38094395019 ps
CPU time 155.32 seconds
Started Jul 23 07:06:17 PM PDT 24
Finished Jul 23 07:08:54 PM PDT 24
Peak memory 273412 kb
Host smart-fc9cb5fd-0956-4a4c-aa11-1a96f51c645d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169725435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.169725435
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.1119515934
Short name T198
Test name
Test status
Simulation time 48060082209 ps
CPU time 235.28 seconds
Started Jul 23 07:06:20 PM PDT 24
Finished Jul 23 07:10:16 PM PDT 24
Peak memory 257616 kb
Host smart-bff1d14f-6548-44b1-929c-81c9de3e54f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119515934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.1119515934
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.372227167
Short name T630
Test name
Test status
Simulation time 9571095190 ps
CPU time 134.13 seconds
Started Jul 23 07:06:18 PM PDT 24
Finished Jul 23 07:08:34 PM PDT 24
Peak memory 254308 kb
Host smart-5d2ad919-a9f8-4e34-8289-3a88bd5f2ab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372227167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idle
.372227167
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.293251671
Short name T623
Test name
Test status
Simulation time 3857121118 ps
CPU time 51.58 seconds
Started Jul 23 07:06:18 PM PDT 24
Finished Jul 23 07:07:12 PM PDT 24
Peak memory 232984 kb
Host smart-908a034f-58f4-4e83-a866-d617d83ddf48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293251671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.293251671
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.3996605344
Short name T950
Test name
Test status
Simulation time 166570840169 ps
CPU time 281.38 seconds
Started Jul 23 07:06:15 PM PDT 24
Finished Jul 23 07:10:58 PM PDT 24
Peak memory 273904 kb
Host smart-71d979c6-bbe1-4949-979d-c09f51144dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996605344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmd
s.3996605344
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_intercept.1544984798
Short name T674
Test name
Test status
Simulation time 121853297 ps
CPU time 2.46 seconds
Started Jul 23 07:06:18 PM PDT 24
Finished Jul 23 07:06:22 PM PDT 24
Peak memory 232604 kb
Host smart-a3674680-ac4f-41f4-9392-068b90b4ed51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544984798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.1544984798
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.1188116582
Short name T743
Test name
Test status
Simulation time 21192010778 ps
CPU time 13.35 seconds
Started Jul 23 07:06:16 PM PDT 24
Finished Jul 23 07:06:31 PM PDT 24
Peak memory 232904 kb
Host smart-817ae48f-14e5-427c-b9c9-c3656e1e6c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188116582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.1188116582
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.2655564118
Short name T375
Test name
Test status
Simulation time 700423067 ps
CPU time 4.34 seconds
Started Jul 23 07:06:16 PM PDT 24
Finished Jul 23 07:06:22 PM PDT 24
Peak memory 232800 kb
Host smart-e64bc4d4-1b34-40a6-86d3-ab23e07cd6a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655564118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.2655564118
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.1495291669
Short name T54
Test name
Test status
Simulation time 2886635059 ps
CPU time 6.26 seconds
Started Jul 23 07:06:20 PM PDT 24
Finished Jul 23 07:06:27 PM PDT 24
Peak memory 232936 kb
Host smart-65a37850-fd7e-4771-b2ac-435d1eb0f2d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495291669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.1495291669
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.2146769374
Short name T391
Test name
Test status
Simulation time 386593627 ps
CPU time 6.05 seconds
Started Jul 23 07:06:20 PM PDT 24
Finished Jul 23 07:06:27 PM PDT 24
Peak memory 220528 kb
Host smart-560f2108-59f3-41e5-8791-0c49293874c8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2146769374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.2146769374
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.2927378784
Short name T791
Test name
Test status
Simulation time 1269774325 ps
CPU time 6.7 seconds
Started Jul 23 07:06:19 PM PDT 24
Finished Jul 23 07:06:27 PM PDT 24
Peak memory 217828 kb
Host smart-c64ab3a9-bc1f-4fea-b0a1-0e2060c2e5dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927378784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.2927378784
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.3362148744
Short name T72
Test name
Test status
Simulation time 1345666547 ps
CPU time 2.82 seconds
Started Jul 23 07:06:12 PM PDT 24
Finished Jul 23 07:06:15 PM PDT 24
Peak memory 216388 kb
Host smart-52c6c0b4-fb70-4952-93a3-d6d2330b7755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362148744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.3362148744
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.2871930565
Short name T45
Test name
Test status
Simulation time 285944667 ps
CPU time 2.28 seconds
Started Jul 23 07:06:16 PM PDT 24
Finished Jul 23 07:06:20 PM PDT 24
Peak memory 216508 kb
Host smart-e18f20e8-0dab-4931-b1f0-e84f0b46c76b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871930565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.2871930565
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.3129890067
Short name T536
Test name
Test status
Simulation time 155262597 ps
CPU time 0.91 seconds
Started Jul 23 07:06:18 PM PDT 24
Finished Jul 23 07:06:21 PM PDT 24
Peak memory 206512 kb
Host smart-f0697903-098f-4914-a3b4-c9e9ca2ae7c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129890067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.3129890067
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.3225103072
Short name T1009
Test name
Test status
Simulation time 3672428004 ps
CPU time 6.89 seconds
Started Jul 23 07:06:17 PM PDT 24
Finished Jul 23 07:06:26 PM PDT 24
Peak memory 232896 kb
Host smart-7899cf06-771b-47d6-b252-59ba32c3b8aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225103072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.3225103072
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.101321194
Short name T782
Test name
Test status
Simulation time 23867793 ps
CPU time 0.74 seconds
Started Jul 23 07:06:26 PM PDT 24
Finished Jul 23 07:06:28 PM PDT 24
Peak memory 205588 kb
Host smart-87ff8e38-94b4-4f43-a3d5-150b9459dd63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101321194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.101321194
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.3635803002
Short name T707
Test name
Test status
Simulation time 201687192 ps
CPU time 2.49 seconds
Started Jul 23 07:06:24 PM PDT 24
Finished Jul 23 07:06:27 PM PDT 24
Peak memory 232552 kb
Host smart-5f36cd3f-ec35-4463-b434-fe9318326dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635803002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.3635803002
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.2177215788
Short name T677
Test name
Test status
Simulation time 12716531 ps
CPU time 0.74 seconds
Started Jul 23 07:06:20 PM PDT 24
Finished Jul 23 07:06:22 PM PDT 24
Peak memory 205628 kb
Host smart-aec2bf46-b223-4c63-b3e0-01317a51cae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177215788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.2177215788
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.2950417554
Short name T438
Test name
Test status
Simulation time 96635849010 ps
CPU time 49.24 seconds
Started Jul 23 07:06:27 PM PDT 24
Finished Jul 23 07:07:18 PM PDT 24
Peak memory 240712 kb
Host smart-9f9a3a47-88c4-4ebe-8f79-4c3b27531e84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950417554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.2950417554
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.4232360854
Short name T169
Test name
Test status
Simulation time 165790950202 ps
CPU time 486.99 seconds
Started Jul 23 07:06:25 PM PDT 24
Finished Jul 23 07:14:33 PM PDT 24
Peak memory 256352 kb
Host smart-bda0d29a-a54c-41dd-80cb-135fee483f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232360854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.4232360854
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.2899605304
Short name T808
Test name
Test status
Simulation time 17364323762 ps
CPU time 74.66 seconds
Started Jul 23 07:06:24 PM PDT 24
Finished Jul 23 07:07:40 PM PDT 24
Peak memory 249388 kb
Host smart-5c5ea3d2-ffd1-4535-8b5a-d753a4a03640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899605304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.2899605304
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.3767829495
Short name T971
Test name
Test status
Simulation time 125759034 ps
CPU time 3.11 seconds
Started Jul 23 07:06:24 PM PDT 24
Finished Jul 23 07:06:29 PM PDT 24
Peak memory 224692 kb
Host smart-b22755a1-d17c-4423-b45e-c90463158c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767829495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.3767829495
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.2455159394
Short name T591
Test name
Test status
Simulation time 10494783115 ps
CPU time 19.57 seconds
Started Jul 23 07:06:25 PM PDT 24
Finished Jul 23 07:06:47 PM PDT 24
Peak memory 224624 kb
Host smart-d968a333-193b-47ad-b3c4-7a06e2ce8117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455159394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmd
s.2455159394
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_intercept.2489547550
Short name T412
Test name
Test status
Simulation time 4488646896 ps
CPU time 20.75 seconds
Started Jul 23 07:06:23 PM PDT 24
Finished Jul 23 07:06:44 PM PDT 24
Peak memory 224760 kb
Host smart-2d758cd9-6017-4e2d-85b0-4875c8b2f40c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489547550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.2489547550
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.768109870
Short name T468
Test name
Test status
Simulation time 817291721 ps
CPU time 7.16 seconds
Started Jul 23 07:06:24 PM PDT 24
Finished Jul 23 07:06:32 PM PDT 24
Peak memory 236584 kb
Host smart-33fdb5ca-f81f-4993-972c-5424eef381f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768109870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.768109870
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.3359275439
Short name T815
Test name
Test status
Simulation time 15869505329 ps
CPU time 7.27 seconds
Started Jul 23 07:06:26 PM PDT 24
Finished Jul 23 07:06:35 PM PDT 24
Peak memory 232996 kb
Host smart-387272d8-60b6-4b61-812b-3b965cbac56d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359275439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.3359275439
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.2435818875
Short name T237
Test name
Test status
Simulation time 247040336 ps
CPU time 7.09 seconds
Started Jul 23 07:06:25 PM PDT 24
Finished Jul 23 07:06:33 PM PDT 24
Peak memory 232904 kb
Host smart-21351402-1396-4c2b-9743-73e0ae3bc88e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435818875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.2435818875
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.3285120347
Short name T716
Test name
Test status
Simulation time 357972725 ps
CPU time 3.87 seconds
Started Jul 23 07:06:25 PM PDT 24
Finished Jul 23 07:06:30 PM PDT 24
Peak memory 223344 kb
Host smart-fa2229e0-dbdf-4605-9f4a-044cf06a6b46
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3285120347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.3285120347
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.1514444601
Short name T1006
Test name
Test status
Simulation time 4333269505 ps
CPU time 11.21 seconds
Started Jul 23 07:06:24 PM PDT 24
Finished Jul 23 07:06:36 PM PDT 24
Peak memory 216664 kb
Host smart-acf394ba-52b0-4798-bc35-6c675479b852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514444601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.1514444601
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.1002846526
Short name T528
Test name
Test status
Simulation time 3611673060 ps
CPU time 3.22 seconds
Started Jul 23 07:06:18 PM PDT 24
Finished Jul 23 07:06:23 PM PDT 24
Peak memory 216468 kb
Host smart-01b591be-0a2e-4ddd-8fef-0f112da2b71e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002846526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.1002846526
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.2166152020
Short name T341
Test name
Test status
Simulation time 46340258 ps
CPU time 0.87 seconds
Started Jul 23 07:06:25 PM PDT 24
Finished Jul 23 07:06:26 PM PDT 24
Peak memory 207156 kb
Host smart-7f36b2d5-10ba-403f-851d-099b1b39a7e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166152020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.2166152020
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.975390378
Short name T346
Test name
Test status
Simulation time 83207723 ps
CPU time 0.99 seconds
Started Jul 23 07:06:17 PM PDT 24
Finished Jul 23 07:06:20 PM PDT 24
Peak memory 206436 kb
Host smart-e1a1ece0-e773-48d5-b567-25f26dd9fd9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975390378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.975390378
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.611312304
Short name T913
Test name
Test status
Simulation time 12690851898 ps
CPU time 13.71 seconds
Started Jul 23 07:06:26 PM PDT 24
Finished Jul 23 07:06:41 PM PDT 24
Peak memory 224732 kb
Host smart-c8e976d0-7605-43a3-a2ef-8af3dd022d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611312304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.611312304
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.1721797917
Short name T356
Test name
Test status
Simulation time 11860456 ps
CPU time 0.74 seconds
Started Jul 23 07:06:27 PM PDT 24
Finished Jul 23 07:06:29 PM PDT 24
Peak memory 205612 kb
Host smart-f5cd29c1-aec5-4fa0-80b0-7a66fb4d40a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721797917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
1721797917
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.1865349373
Short name T349
Test name
Test status
Simulation time 34028622 ps
CPU time 2.52 seconds
Started Jul 23 07:06:31 PM PDT 24
Finished Jul 23 07:06:35 PM PDT 24
Peak memory 232840 kb
Host smart-53d8fbf7-947c-40e7-9e16-8de69566f21b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865349373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.1865349373
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.3677488986
Short name T32
Test name
Test status
Simulation time 18591478 ps
CPU time 0.76 seconds
Started Jul 23 07:06:26 PM PDT 24
Finished Jul 23 07:06:28 PM PDT 24
Peak memory 206040 kb
Host smart-4f727f74-d627-4ceb-8346-d420948759fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677488986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.3677488986
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.4119949078
Short name T239
Test name
Test status
Simulation time 43986884325 ps
CPU time 104.31 seconds
Started Jul 23 07:06:31 PM PDT 24
Finished Jul 23 07:08:16 PM PDT 24
Peak memory 241124 kb
Host smart-d7198bb4-c946-4ff2-aad5-15356330a23e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119949078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.4119949078
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.1779640793
Short name T248
Test name
Test status
Simulation time 16862037034 ps
CPU time 87.25 seconds
Started Jul 23 07:06:31 PM PDT 24
Finished Jul 23 07:08:00 PM PDT 24
Peak memory 249364 kb
Host smart-901cd906-4756-4ceb-bf39-9dc22e292c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779640793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.1779640793
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.1024519689
Short name T697
Test name
Test status
Simulation time 2570085395 ps
CPU time 10.92 seconds
Started Jul 23 07:06:27 PM PDT 24
Finished Jul 23 07:06:39 PM PDT 24
Peak memory 232956 kb
Host smart-5e1229eb-b5bd-401b-8967-eca06c3131d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024519689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.1024519689
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_intercept.1717433072
Short name T173
Test name
Test status
Simulation time 1119276984 ps
CPU time 11.28 seconds
Started Jul 23 07:06:32 PM PDT 24
Finished Jul 23 07:06:44 PM PDT 24
Peak memory 232812 kb
Host smart-0c3fa89e-4d70-46a4-bd50-ac6b27779f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717433072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.1717433072
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.595003336
Short name T546
Test name
Test status
Simulation time 554415036 ps
CPU time 3.58 seconds
Started Jul 23 07:06:28 PM PDT 24
Finished Jul 23 07:06:33 PM PDT 24
Peak memory 232784 kb
Host smart-ee839a31-1f5e-4eb4-857a-0ba33167a057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595003336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.595003336
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.2742832189
Short name T268
Test name
Test status
Simulation time 12325985325 ps
CPU time 19.46 seconds
Started Jul 23 07:06:28 PM PDT 24
Finished Jul 23 07:06:49 PM PDT 24
Peak memory 240936 kb
Host smart-3a5aeed7-eefe-4155-b1f9-2fa507e1b6af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742832189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.2742832189
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.372329049
Short name T562
Test name
Test status
Simulation time 282205482 ps
CPU time 2.47 seconds
Started Jul 23 07:06:28 PM PDT 24
Finished Jul 23 07:06:31 PM PDT 24
Peak memory 232644 kb
Host smart-e8ac6fec-0f18-4dea-a12a-d866fa2ef81a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372329049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.372329049
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.1102837914
Short name T533
Test name
Test status
Simulation time 127014015 ps
CPU time 3.47 seconds
Started Jul 23 07:06:32 PM PDT 24
Finished Jul 23 07:06:37 PM PDT 24
Peak memory 223188 kb
Host smart-0b475fb3-a05a-4c21-b38d-30017c597883
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1102837914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.1102837914
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.3818693324
Short name T148
Test name
Test status
Simulation time 10898160536 ps
CPU time 190.91 seconds
Started Jul 23 07:06:28 PM PDT 24
Finished Jul 23 07:09:40 PM PDT 24
Peak memory 282204 kb
Host smart-4c044397-a2e3-44a0-877c-2d3aafb1749b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818693324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.3818693324
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.2117745347
Short name T672
Test name
Test status
Simulation time 3754775475 ps
CPU time 26.07 seconds
Started Jul 23 07:06:26 PM PDT 24
Finished Jul 23 07:06:54 PM PDT 24
Peak memory 216516 kb
Host smart-20ea1d1b-7dc4-4009-86dc-f23b03618a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117745347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.2117745347
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.903500289
Short name T34
Test name
Test status
Simulation time 618040748 ps
CPU time 3.38 seconds
Started Jul 23 07:06:26 PM PDT 24
Finished Jul 23 07:06:31 PM PDT 24
Peak memory 216400 kb
Host smart-53996dc5-a5dd-4216-8a8e-390524dde7f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903500289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.903500289
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.2474013477
Short name T319
Test name
Test status
Simulation time 29654588 ps
CPU time 1.58 seconds
Started Jul 23 07:06:31 PM PDT 24
Finished Jul 23 07:06:33 PM PDT 24
Peak memory 216428 kb
Host smart-fd8890a5-15d6-431d-9454-85453cd4f2aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474013477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.2474013477
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.1762414850
Short name T919
Test name
Test status
Simulation time 15667160 ps
CPU time 0.74 seconds
Started Jul 23 07:06:24 PM PDT 24
Finished Jul 23 07:06:25 PM PDT 24
Peak memory 206200 kb
Host smart-cc8cba3b-106a-45e7-9dbf-c2820fb4bbba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762414850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.1762414850
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.43392498
Short name T638
Test name
Test status
Simulation time 1740738440 ps
CPU time 3.87 seconds
Started Jul 23 07:06:30 PM PDT 24
Finished Jul 23 07:06:35 PM PDT 24
Peak memory 224608 kb
Host smart-dee1aac4-5644-4440-95ca-2f808b522d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43392498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.43392498
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.3423403259
Short name T753
Test name
Test status
Simulation time 38061093 ps
CPU time 0.72 seconds
Started Jul 23 07:06:32 PM PDT 24
Finished Jul 23 07:06:34 PM PDT 24
Peak memory 205500 kb
Host smart-1f3312af-fbba-4391-8899-086fc990c319
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423403259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
3423403259
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.1508825728
Short name T460
Test name
Test status
Simulation time 205596131 ps
CPU time 2.21 seconds
Started Jul 23 07:06:32 PM PDT 24
Finished Jul 23 07:06:35 PM PDT 24
Peak memory 224576 kb
Host smart-e025b227-3b12-4d24-ad56-ea60860d3e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508825728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.1508825728
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.308472480
Short name T634
Test name
Test status
Simulation time 269317331 ps
CPU time 0.81 seconds
Started Jul 23 07:06:30 PM PDT 24
Finished Jul 23 07:06:32 PM PDT 24
Peak memory 207040 kb
Host smart-2b7424d3-52f1-46e4-8385-28fab37ce90b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308472480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.308472480
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.894049408
Short name T825
Test name
Test status
Simulation time 62478741241 ps
CPU time 83.9 seconds
Started Jul 23 07:06:33 PM PDT 24
Finished Jul 23 07:07:58 PM PDT 24
Peak memory 249372 kb
Host smart-23228fbf-f2ad-4dc3-8604-cbeac066fbe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894049408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.894049408
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.1020396829
Short name T517
Test name
Test status
Simulation time 22526860076 ps
CPU time 42.06 seconds
Started Jul 23 07:06:34 PM PDT 24
Finished Jul 23 07:07:17 PM PDT 24
Peak memory 249336 kb
Host smart-ca4de701-7d7d-44ee-b7b0-4f8320e00247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020396829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.1020396829
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.666170821
Short name T851
Test name
Test status
Simulation time 1994265760 ps
CPU time 47.68 seconds
Started Jul 23 07:06:33 PM PDT 24
Finished Jul 23 07:07:22 PM PDT 24
Peak memory 265676 kb
Host smart-94930b3e-7c8f-4b3a-87bf-7f0a97783421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666170821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmds
.666170821
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/18.spi_device_intercept.1836269671
Short name T51
Test name
Test status
Simulation time 256350742 ps
CPU time 5.59 seconds
Started Jul 23 07:06:35 PM PDT 24
Finished Jul 23 07:06:41 PM PDT 24
Peak memory 232824 kb
Host smart-82409cf9-32e4-47e3-a492-3a6882e6854a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836269671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.1836269671
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.3510808547
Short name T431
Test name
Test status
Simulation time 218191354 ps
CPU time 7.01 seconds
Started Jul 23 07:06:31 PM PDT 24
Finished Jul 23 07:06:40 PM PDT 24
Peak memory 232912 kb
Host smart-53647965-c710-43c4-bb51-f664c7bb5fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510808547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.3510808547
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.3327323198
Short name T491
Test name
Test status
Simulation time 279287308 ps
CPU time 6.4 seconds
Started Jul 23 07:06:32 PM PDT 24
Finished Jul 23 07:06:40 PM PDT 24
Peak memory 240828 kb
Host smart-e35800d3-1a70-4f8d-b3e3-3077e646c261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327323198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.3327323198
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.1643411490
Short name T405
Test name
Test status
Simulation time 2764645215 ps
CPU time 9.47 seconds
Started Jul 23 07:06:28 PM PDT 24
Finished Jul 23 07:06:39 PM PDT 24
Peak memory 232876 kb
Host smart-75b80bc0-b74a-4a11-b701-9d301d514ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643411490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.1643411490
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.2499968411
Short name T882
Test name
Test status
Simulation time 388084903 ps
CPU time 5.46 seconds
Started Jul 23 07:06:31 PM PDT 24
Finished Jul 23 07:06:38 PM PDT 24
Peak memory 219564 kb
Host smart-8b7e2815-7960-46e3-ac66-9c71620adea5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2499968411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.2499968411
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.1725462228
Short name T16
Test name
Test status
Simulation time 186937111008 ps
CPU time 380.53 seconds
Started Jul 23 07:06:31 PM PDT 24
Finished Jul 23 07:12:53 PM PDT 24
Peak memory 252500 kb
Host smart-26a5d19c-6527-448b-ae16-a8ec0cb8c3fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725462228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.1725462228
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.2078375933
Short name T282
Test name
Test status
Simulation time 2221716430 ps
CPU time 5.5 seconds
Started Jul 23 07:06:30 PM PDT 24
Finished Jul 23 07:06:36 PM PDT 24
Peak memory 219428 kb
Host smart-cf70732e-0164-414d-afe9-0e342132c78e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078375933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.2078375933
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.941993175
Short name T680
Test name
Test status
Simulation time 14073171201 ps
CPU time 9.24 seconds
Started Jul 23 07:06:29 PM PDT 24
Finished Jul 23 07:06:40 PM PDT 24
Peak memory 216388 kb
Host smart-c0383c1e-02ba-4faf-a0b2-28b594e90e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941993175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.941993175
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.3018040549
Short name T485
Test name
Test status
Simulation time 44068554 ps
CPU time 0.87 seconds
Started Jul 23 07:06:28 PM PDT 24
Finished Jul 23 07:06:30 PM PDT 24
Peak memory 206772 kb
Host smart-85871ba4-1890-4bf5-bd5e-b98cb4c26ff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018040549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.3018040549
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.2078109684
Short name T361
Test name
Test status
Simulation time 40445271 ps
CPU time 0.7 seconds
Started Jul 23 07:06:27 PM PDT 24
Finished Jul 23 07:06:29 PM PDT 24
Peak memory 205732 kb
Host smart-877dba4a-6783-4202-a375-fc5b7c052f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078109684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.2078109684
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.1965398960
Short name T79
Test name
Test status
Simulation time 899741692 ps
CPU time 6.61 seconds
Started Jul 23 07:06:33 PM PDT 24
Finished Jul 23 07:06:41 PM PDT 24
Peak memory 232892 kb
Host smart-959e1513-0934-4366-b52f-84f5ccaf1f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965398960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.1965398960
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.4056654714
Short name T705
Test name
Test status
Simulation time 27796153 ps
CPU time 0.73 seconds
Started Jul 23 07:06:41 PM PDT 24
Finished Jul 23 07:06:43 PM PDT 24
Peak memory 205940 kb
Host smart-7510970e-445b-4567-b2c6-f8417a2a7bf9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056654714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
4056654714
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.542083122
Short name T443
Test name
Test status
Simulation time 118184866 ps
CPU time 3.1 seconds
Started Jul 23 07:06:37 PM PDT 24
Finished Jul 23 07:06:41 PM PDT 24
Peak memory 224664 kb
Host smart-4f297ca7-5640-4d0b-8918-9718a1eee5c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542083122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.542083122
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.3944137578
Short name T310
Test name
Test status
Simulation time 22541471 ps
CPU time 0.79 seconds
Started Jul 23 07:06:38 PM PDT 24
Finished Jul 23 07:06:39 PM PDT 24
Peak memory 206744 kb
Host smart-2eb5dfd3-3e49-430a-9c6c-02f55aa6dddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944137578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.3944137578
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.3220648646
Short name T179
Test name
Test status
Simulation time 59358002257 ps
CPU time 446.23 seconds
Started Jul 23 07:06:39 PM PDT 24
Finished Jul 23 07:14:06 PM PDT 24
Peak memory 273852 kb
Host smart-dc66f36e-afc7-4961-a6da-17de45c5331c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220648646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.3220648646
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.1524905761
Short name T432
Test name
Test status
Simulation time 36827052616 ps
CPU time 34.96 seconds
Started Jul 23 07:06:38 PM PDT 24
Finished Jul 23 07:07:14 PM PDT 24
Peak memory 217656 kb
Host smart-740dfdfb-143c-439b-a7a7-3f03486bbb03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524905761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.1524905761
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.2753119046
Short name T44
Test name
Test status
Simulation time 9787911542 ps
CPU time 121.36 seconds
Started Jul 23 07:06:40 PM PDT 24
Finished Jul 23 07:08:42 PM PDT 24
Peak memory 249384 kb
Host smart-82364945-7fb8-4b6d-b761-eaf45fd1637f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753119046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.2753119046
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.818877713
Short name T273
Test name
Test status
Simulation time 4984478062 ps
CPU time 13.47 seconds
Started Jul 23 07:06:42 PM PDT 24
Finished Jul 23 07:06:56 PM PDT 24
Peak memory 233968 kb
Host smart-8075da4f-4e24-46d5-bc7c-a8d2e55302a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818877713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.818877713
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.4101522651
Short name T648
Test name
Test status
Simulation time 152102572617 ps
CPU time 251.35 seconds
Started Jul 23 07:06:43 PM PDT 24
Finished Jul 23 07:10:56 PM PDT 24
Peak memory 265572 kb
Host smart-50b38419-8342-4ee2-aadb-5fd5dd8c5381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101522651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmd
s.4101522651
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_intercept.1959151756
Short name T793
Test name
Test status
Simulation time 3834327882 ps
CPU time 10.7 seconds
Started Jul 23 07:06:41 PM PDT 24
Finished Jul 23 07:06:53 PM PDT 24
Peak memory 232896 kb
Host smart-99003d11-ec72-4928-8879-71c0b11af19c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959151756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.1959151756
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.1949498606
Short name T56
Test name
Test status
Simulation time 295619755 ps
CPU time 7.23 seconds
Started Jul 23 07:06:44 PM PDT 24
Finished Jul 23 07:06:52 PM PDT 24
Peak memory 232884 kb
Host smart-0c51fbda-7190-4937-ae46-e708922dbc2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949498606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.1949498606
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.3516749439
Short name T904
Test name
Test status
Simulation time 8529156821 ps
CPU time 24.1 seconds
Started Jul 23 07:06:40 PM PDT 24
Finished Jul 23 07:07:05 PM PDT 24
Peak memory 241080 kb
Host smart-dc0693a4-df9b-4b9b-9273-74a34f0b3851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516749439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.3516749439
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.1259258829
Short name T995
Test name
Test status
Simulation time 31498572125 ps
CPU time 22.45 seconds
Started Jul 23 07:06:39 PM PDT 24
Finished Jul 23 07:07:02 PM PDT 24
Peak memory 239196 kb
Host smart-a1e15e59-a11f-4580-8d09-241bb5c83607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259258829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.1259258829
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.1767568441
Short name T708
Test name
Test status
Simulation time 5943715176 ps
CPU time 13.98 seconds
Started Jul 23 07:06:38 PM PDT 24
Finished Jul 23 07:06:53 PM PDT 24
Peak memory 222268 kb
Host smart-d530e3ed-9698-424a-8763-55831a4e5a65
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1767568441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.1767568441
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.195207450
Short name T901
Test name
Test status
Simulation time 347221877 ps
CPU time 1.09 seconds
Started Jul 23 07:06:43 PM PDT 24
Finished Jul 23 07:06:45 PM PDT 24
Peak memory 207220 kb
Host smart-8d22dd15-01dd-46bb-b3bc-3b503059ff5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195207450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stres
s_all.195207450
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.2077896612
Short name T547
Test name
Test status
Simulation time 3472190981 ps
CPU time 6.87 seconds
Started Jul 23 07:06:39 PM PDT 24
Finished Jul 23 07:06:47 PM PDT 24
Peak memory 216520 kb
Host smart-b0642389-b50b-43e0-89e1-a21f71cccfbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077896612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.2077896612
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.2020220470
Short name T335
Test name
Test status
Simulation time 1819822110 ps
CPU time 7.91 seconds
Started Jul 23 07:06:41 PM PDT 24
Finished Jul 23 07:06:50 PM PDT 24
Peak memory 216472 kb
Host smart-85267015-24a3-44e4-b6d8-d20e0c65b952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020220470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.2020220470
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.1045907569
Short name T751
Test name
Test status
Simulation time 292962036 ps
CPU time 3.38 seconds
Started Jul 23 07:06:38 PM PDT 24
Finished Jul 23 07:06:43 PM PDT 24
Peak memory 216364 kb
Host smart-df8bdb60-b31f-4b63-a41a-8b46e08a1f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045907569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.1045907569
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.829938818
Short name T837
Test name
Test status
Simulation time 269637276 ps
CPU time 0.83 seconds
Started Jul 23 07:06:40 PM PDT 24
Finished Jul 23 07:06:42 PM PDT 24
Peak memory 206104 kb
Host smart-56520aea-187d-4408-ad3c-55d180c5342d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829938818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.829938818
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.684798409
Short name T600
Test name
Test status
Simulation time 725237185 ps
CPU time 5.09 seconds
Started Jul 23 07:06:38 PM PDT 24
Finished Jul 23 07:06:44 PM PDT 24
Peak memory 232932 kb
Host smart-bb2a974f-cddf-4b11-9a93-163f8c7f5b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684798409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.684798409
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.276544923
Short name T327
Test name
Test status
Simulation time 16115708 ps
CPU time 0.79 seconds
Started Jul 23 07:05:13 PM PDT 24
Finished Jul 23 07:05:16 PM PDT 24
Peak memory 205616 kb
Host smart-1a155b39-fcdf-4e82-901c-372d470bfc5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276544923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.276544923
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.1245395092
Short name T496
Test name
Test status
Simulation time 19697797263 ps
CPU time 16.81 seconds
Started Jul 23 07:05:15 PM PDT 24
Finished Jul 23 07:05:35 PM PDT 24
Peak memory 223628 kb
Host smart-a2611419-344d-42c8-8068-34bb94ce1c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245395092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.1245395092
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.2509432562
Short name T448
Test name
Test status
Simulation time 37360148 ps
CPU time 0.78 seconds
Started Jul 23 07:05:10 PM PDT 24
Finished Jul 23 07:05:11 PM PDT 24
Peak memory 207036 kb
Host smart-626c466e-c10f-45d8-a2c6-65c30b19b46a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509432562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.2509432562
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.3947564011
Short name T804
Test name
Test status
Simulation time 51608380 ps
CPU time 0.74 seconds
Started Jul 23 07:05:10 PM PDT 24
Finished Jul 23 07:05:12 PM PDT 24
Peak memory 215912 kb
Host smart-40f25f19-9b0a-4590-ad59-8b7df1b3c82c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947564011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.3947564011
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.3813586793
Short name T170
Test name
Test status
Simulation time 32099275198 ps
CPU time 355.11 seconds
Started Jul 23 07:05:14 PM PDT 24
Finished Jul 23 07:11:11 PM PDT 24
Peak memory 265664 kb
Host smart-cd966fbe-810b-4743-885f-3d5f488cf2d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813586793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.3813586793
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.2198473009
Short name T180
Test name
Test status
Simulation time 29658207313 ps
CPU time 57.75 seconds
Started Jul 23 07:05:13 PM PDT 24
Finished Jul 23 07:06:13 PM PDT 24
Peak memory 264036 kb
Host smart-e3a83976-c1e0-4a4a-81f6-2811343a900f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198473009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.2198473009
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.1236387160
Short name T718
Test name
Test status
Simulation time 682591647 ps
CPU time 4.44 seconds
Started Jul 23 07:05:10 PM PDT 24
Finished Jul 23 07:05:15 PM PDT 24
Peak memory 241004 kb
Host smart-1d9df448-54a6-41f0-b5ca-3510c5816a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236387160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.1236387160
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.3030932945
Short name T966
Test name
Test status
Simulation time 9092272084 ps
CPU time 32.42 seconds
Started Jul 23 07:05:09 PM PDT 24
Finished Jul 23 07:05:42 PM PDT 24
Peak memory 234524 kb
Host smart-df3d995b-9dc9-453e-a106-98af1c747a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030932945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds
.3030932945
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_intercept.2264912051
Short name T382
Test name
Test status
Simulation time 255546137 ps
CPU time 2.87 seconds
Started Jul 23 07:05:09 PM PDT 24
Finished Jul 23 07:05:13 PM PDT 24
Peak memory 224696 kb
Host smart-edc74b73-7580-4b21-bef7-02a6475572ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264912051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.2264912051
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.2326427392
Short name T75
Test name
Test status
Simulation time 6235311120 ps
CPU time 42.12 seconds
Started Jul 23 07:05:15 PM PDT 24
Finished Jul 23 07:06:00 PM PDT 24
Peak memory 232712 kb
Host smart-db7b92ce-96b8-4754-8e78-0015c5f1926c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326427392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.2326427392
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.1532401599
Short name T969
Test name
Test status
Simulation time 579113311 ps
CPU time 2.49 seconds
Started Jul 23 07:05:09 PM PDT 24
Finished Jul 23 07:05:13 PM PDT 24
Peak memory 232540 kb
Host smart-58a761f4-f975-49c1-818f-f1b8bb34dbd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532401599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.1532401599
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.3077689319
Short name T1008
Test name
Test status
Simulation time 9882610269 ps
CPU time 13.07 seconds
Started Jul 23 07:05:07 PM PDT 24
Finished Jul 23 07:05:21 PM PDT 24
Peak memory 232948 kb
Host smart-a273f378-1fe2-4531-9fbd-188e0714c381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077689319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.3077689319
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.2774250996
Short name T847
Test name
Test status
Simulation time 2223946414 ps
CPU time 5.04 seconds
Started Jul 23 07:05:09 PM PDT 24
Finished Jul 23 07:05:15 PM PDT 24
Peak memory 222908 kb
Host smart-ecd94001-3be6-45ec-a7f9-7800f5d35fb1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2774250996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.2774250996
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.4266760449
Short name T747
Test name
Test status
Simulation time 19317306277 ps
CPU time 27.02 seconds
Started Jul 23 07:05:08 PM PDT 24
Finished Jul 23 07:05:36 PM PDT 24
Peak memory 216536 kb
Host smart-895fb5be-5b97-4beb-a988-1b28aadca371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266760449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.4266760449
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.2243680432
Short name T864
Test name
Test status
Simulation time 8319335282 ps
CPU time 8.74 seconds
Started Jul 23 07:05:15 PM PDT 24
Finished Jul 23 07:05:27 PM PDT 24
Peak memory 215160 kb
Host smart-7dbf2b09-bc84-4cb5-b06e-6eec3344e71c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243680432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.2243680432
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.3490900423
Short name T317
Test name
Test status
Simulation time 149690507 ps
CPU time 1.99 seconds
Started Jul 23 07:05:11 PM PDT 24
Finished Jul 23 07:05:14 PM PDT 24
Peak memory 216472 kb
Host smart-6a419151-90a5-4544-9a51-f461e0aca273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490900423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.3490900423
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.2992845463
Short name T433
Test name
Test status
Simulation time 70286812 ps
CPU time 0.96 seconds
Started Jul 23 07:05:09 PM PDT 24
Finished Jul 23 07:05:11 PM PDT 24
Peak memory 206480 kb
Host smart-0ef6bebd-7868-449f-859c-4a46d0e2e34e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992845463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.2992845463
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.1440090056
Short name T156
Test name
Test status
Simulation time 3356622051 ps
CPU time 6.81 seconds
Started Jul 23 07:05:08 PM PDT 24
Finished Jul 23 07:05:16 PM PDT 24
Peak memory 224728 kb
Host smart-074ecdae-ad15-4bf8-b583-4390127c1a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440090056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.1440090056
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.339224362
Short name T353
Test name
Test status
Simulation time 13134799 ps
CPU time 0.69 seconds
Started Jul 23 07:06:48 PM PDT 24
Finished Jul 23 07:06:50 PM PDT 24
Peak memory 204776 kb
Host smart-adfdb0dd-5767-4e31-b166-e9334c65c1e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339224362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.339224362
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.3877825335
Short name T208
Test name
Test status
Simulation time 286145712 ps
CPU time 6.04 seconds
Started Jul 23 07:06:43 PM PDT 24
Finished Jul 23 07:06:50 PM PDT 24
Peak memory 224708 kb
Host smart-f1fc6062-af4e-41a1-8bd8-a95fbae36453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877825335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.3877825335
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.825114672
Short name T910
Test name
Test status
Simulation time 20705302 ps
CPU time 0.8 seconds
Started Jul 23 07:06:42 PM PDT 24
Finished Jul 23 07:06:43 PM PDT 24
Peak memory 207016 kb
Host smart-94b2fe72-3259-439c-b1e7-714a2c67a659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825114672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.825114672
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.3810296748
Short name T771
Test name
Test status
Simulation time 9611936484 ps
CPU time 60.29 seconds
Started Jul 23 07:06:46 PM PDT 24
Finished Jul 23 07:07:48 PM PDT 24
Peak memory 249148 kb
Host smart-2f77d819-271b-4827-842e-395fedc1a874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810296748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.3810296748
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.3864935500
Short name T444
Test name
Test status
Simulation time 86093377563 ps
CPU time 162.19 seconds
Started Jul 23 07:06:45 PM PDT 24
Finished Jul 23 07:09:29 PM PDT 24
Peak memory 249340 kb
Host smart-333feb53-c236-42d4-829a-f66abe7ce065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864935500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.3864935500
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.49804786
Short name T972
Test name
Test status
Simulation time 89328986311 ps
CPU time 180.2 seconds
Started Jul 23 07:06:43 PM PDT 24
Finished Jul 23 07:09:44 PM PDT 24
Peak memory 224044 kb
Host smart-e896ca1b-d40c-4c97-8ff8-d86198c00ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49804786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idle.49804786
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_intercept.4032921192
Short name T961
Test name
Test status
Simulation time 7416827286 ps
CPU time 18.58 seconds
Started Jul 23 07:06:45 PM PDT 24
Finished Jul 23 07:07:06 PM PDT 24
Peak memory 224760 kb
Host smart-efd4d5ad-5ac9-4127-8ff6-e428141c79ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032921192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.4032921192
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.3949889647
Short name T552
Test name
Test status
Simulation time 238479062004 ps
CPU time 136.63 seconds
Started Jul 23 07:06:44 PM PDT 24
Finished Jul 23 07:09:02 PM PDT 24
Peak memory 249220 kb
Host smart-76088cc1-59b1-49d8-80cb-bce847c3ea4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949889647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.3949889647
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.2373398574
Short name T455
Test name
Test status
Simulation time 43326288263 ps
CPU time 11.17 seconds
Started Jul 23 07:06:40 PM PDT 24
Finished Jul 23 07:06:53 PM PDT 24
Peak memory 232920 kb
Host smart-f82827a2-f17e-4178-9a5e-0515ccd27ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373398574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.2373398574
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.4032072449
Short name T457
Test name
Test status
Simulation time 1052274360 ps
CPU time 4.87 seconds
Started Jul 23 07:06:40 PM PDT 24
Finished Jul 23 07:06:46 PM PDT 24
Peak memory 224752 kb
Host smart-4692d117-1441-471a-8a35-9cc0f2286fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032072449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.4032072449
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.1390819296
Short name T760
Test name
Test status
Simulation time 668748735 ps
CPU time 8.4 seconds
Started Jul 23 07:06:43 PM PDT 24
Finished Jul 23 07:06:53 PM PDT 24
Peak memory 223432 kb
Host smart-ba42a5d5-476c-4be9-8382-29e50e0d74e1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1390819296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.1390819296
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.3578964182
Short name T497
Test name
Test status
Simulation time 46608147 ps
CPU time 1 seconds
Started Jul 23 07:06:46 PM PDT 24
Finished Jul 23 07:06:49 PM PDT 24
Peak memory 206820 kb
Host smart-1b8c4f27-261c-4505-8a8f-cff3a607b55b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578964182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.3578964182
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.4147259927
Short name T398
Test name
Test status
Simulation time 1165866635 ps
CPU time 3.67 seconds
Started Jul 23 07:06:39 PM PDT 24
Finished Jul 23 07:06:44 PM PDT 24
Peak memory 216380 kb
Host smart-94d0e18b-3725-44cf-80a1-be4ded6932a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147259927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.4147259927
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.973296755
Short name T703
Test name
Test status
Simulation time 198509407 ps
CPU time 1.8 seconds
Started Jul 23 07:06:40 PM PDT 24
Finished Jul 23 07:06:43 PM PDT 24
Peak memory 216204 kb
Host smart-6d1b2fae-ea99-4503-bcc1-6a8375a0a85e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973296755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.973296755
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.1074764961
Short name T289
Test name
Test status
Simulation time 68781217 ps
CPU time 0.98 seconds
Started Jul 23 07:06:40 PM PDT 24
Finished Jul 23 07:06:42 PM PDT 24
Peak memory 207312 kb
Host smart-7014970b-a615-4477-bd45-0fcf00a9e3ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074764961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.1074764961
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.489682831
Short name T914
Test name
Test status
Simulation time 23050553 ps
CPU time 0.67 seconds
Started Jul 23 07:06:37 PM PDT 24
Finished Jul 23 07:06:38 PM PDT 24
Peak memory 205680 kb
Host smart-2cc25a7e-ac7e-4852-8240-aa11a222c480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489682831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.489682831
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.3442133441
Short name T553
Test name
Test status
Simulation time 12996280513 ps
CPU time 7.7 seconds
Started Jul 23 07:06:45 PM PDT 24
Finished Jul 23 07:06:54 PM PDT 24
Peak memory 224616 kb
Host smart-645b4c8a-dcc3-4c44-a4b9-2e399e9e00df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442133441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.3442133441
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.1076685
Short name T454
Test name
Test status
Simulation time 17366894 ps
CPU time 0.79 seconds
Started Jul 23 07:06:45 PM PDT 24
Finished Jul 23 07:06:48 PM PDT 24
Peak memory 205524 kb
Host smart-cc47f3e1-1256-415f-b6e1-6b2678c65820
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.1076685
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.3745151656
Short name T492
Test name
Test status
Simulation time 342710883 ps
CPU time 5.67 seconds
Started Jul 23 07:06:45 PM PDT 24
Finished Jul 23 07:06:53 PM PDT 24
Peak memory 232888 kb
Host smart-d02149f0-f850-4710-954d-b537440be9b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745151656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.3745151656
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.695245192
Short name T664
Test name
Test status
Simulation time 253395660 ps
CPU time 0.77 seconds
Started Jul 23 07:06:44 PM PDT 24
Finished Jul 23 07:06:47 PM PDT 24
Peak memory 205728 kb
Host smart-15f057be-34c1-45db-8f59-b88b87715899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695245192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.695245192
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.3578816167
Short name T181
Test name
Test status
Simulation time 204211918662 ps
CPU time 219.35 seconds
Started Jul 23 07:06:44 PM PDT 24
Finished Jul 23 07:10:25 PM PDT 24
Peak memory 250880 kb
Host smart-e078156b-5a0f-4823-9b1b-9bedab3c658d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578816167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.3578816167
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.968766938
Short name T213
Test name
Test status
Simulation time 37446420790 ps
CPU time 77.63 seconds
Started Jul 23 07:06:46 PM PDT 24
Finished Jul 23 07:08:06 PM PDT 24
Peak memory 237948 kb
Host smart-1a5214c6-8637-4d94-9a52-d0050c639399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968766938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.968766938
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.52005628
Short name T848
Test name
Test status
Simulation time 23468010442 ps
CPU time 106.86 seconds
Started Jul 23 07:06:45 PM PDT 24
Finished Jul 23 07:08:34 PM PDT 24
Peak memory 250424 kb
Host smart-18c75807-a9fb-477b-9172-95f7b15e53f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52005628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idle.52005628
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.2607734393
Short name T759
Test name
Test status
Simulation time 203784264 ps
CPU time 6.29 seconds
Started Jul 23 07:06:51 PM PDT 24
Finished Jul 23 07:06:59 PM PDT 24
Peak memory 232692 kb
Host smart-46ccca9d-2681-4b59-a96b-6ce001e0bba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607734393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.2607734393
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.3299195290
Short name T627
Test name
Test status
Simulation time 4181403195 ps
CPU time 16.08 seconds
Started Jul 23 07:06:48 PM PDT 24
Finished Jul 23 07:07:05 PM PDT 24
Peak memory 235720 kb
Host smart-d211f4ce-e9ab-4726-9044-e240a5dd7ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299195290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmd
s.3299195290
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_intercept.2432224052
Short name T241
Test name
Test status
Simulation time 396342449 ps
CPU time 3.71 seconds
Started Jul 23 07:06:45 PM PDT 24
Finished Jul 23 07:06:51 PM PDT 24
Peak memory 233032 kb
Host smart-ced38de7-a025-4a44-a7ab-ce55f1ffbe30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432224052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.2432224052
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.2163335020
Short name T606
Test name
Test status
Simulation time 17084831797 ps
CPU time 41.55 seconds
Started Jul 23 07:06:45 PM PDT 24
Finished Jul 23 07:07:28 PM PDT 24
Peak memory 224764 kb
Host smart-85f8ab2a-2348-4821-9dfa-4db8a5594f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163335020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.2163335020
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.2017000816
Short name T641
Test name
Test status
Simulation time 89081262801 ps
CPU time 35.5 seconds
Started Jul 23 07:06:50 PM PDT 24
Finished Jul 23 07:07:28 PM PDT 24
Peak memory 248404 kb
Host smart-292492bb-0b10-429b-a489-e1e994a0b054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017000816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.2017000816
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.1180280563
Short name T858
Test name
Test status
Simulation time 709951646 ps
CPU time 2.99 seconds
Started Jul 23 07:06:46 PM PDT 24
Finished Jul 23 07:06:51 PM PDT 24
Peak memory 224696 kb
Host smart-c1d6c045-a806-40c7-a2ef-c1f12a8ce143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180280563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.1180280563
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.1995286098
Short name T314
Test name
Test status
Simulation time 420520335 ps
CPU time 4.45 seconds
Started Jul 23 07:06:46 PM PDT 24
Finished Jul 23 07:06:52 PM PDT 24
Peak memory 219948 kb
Host smart-367cf57d-0cfe-4462-9bed-b102d69264fe
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1995286098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.1995286098
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.3321262905
Short name T400
Test name
Test status
Simulation time 7493761595 ps
CPU time 37.75 seconds
Started Jul 23 07:06:44 PM PDT 24
Finished Jul 23 07:07:24 PM PDT 24
Peak memory 216472 kb
Host smart-4d3b4241-5250-47e2-a5d7-78492448fb2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321262905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.3321262905
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.427168255
Short name T567
Test name
Test status
Simulation time 15921213683 ps
CPU time 10.23 seconds
Started Jul 23 07:06:46 PM PDT 24
Finished Jul 23 07:06:58 PM PDT 24
Peak memory 216532 kb
Host smart-426fa8e7-8070-4876-bf5d-87f582fa85b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427168255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.427168255
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.2132469688
Short name T675
Test name
Test status
Simulation time 703917583 ps
CPU time 3.62 seconds
Started Jul 23 07:06:51 PM PDT 24
Finished Jul 23 07:06:56 PM PDT 24
Peak memory 216252 kb
Host smart-7d81e01d-e213-4d0a-a49a-aecf86f86946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132469688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.2132469688
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.3014571243
Short name T660
Test name
Test status
Simulation time 141209929 ps
CPU time 0.92 seconds
Started Jul 23 07:06:46 PM PDT 24
Finished Jul 23 07:06:49 PM PDT 24
Peak memory 207144 kb
Host smart-a81ceb86-8251-4800-bf10-c5eeb387d5b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014571243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.3014571243
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.358982999
Short name T654
Test name
Test status
Simulation time 23048237122 ps
CPU time 31.01 seconds
Started Jul 23 07:06:48 PM PDT 24
Finished Jul 23 07:07:20 PM PDT 24
Peak memory 249260 kb
Host smart-6b50eec9-8881-48da-95a0-7e94eb757948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358982999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.358982999
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.3301541646
Short name T393
Test name
Test status
Simulation time 91541011 ps
CPU time 0.7 seconds
Started Jul 23 07:06:49 PM PDT 24
Finished Jul 23 07:06:51 PM PDT 24
Peak memory 205912 kb
Host smart-e2d29ca2-9be2-433f-a8ce-ef2018e57d0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301541646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
3301541646
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.3646107286
Short name T402
Test name
Test status
Simulation time 379573733 ps
CPU time 2.45 seconds
Started Jul 23 07:06:44 PM PDT 24
Finished Jul 23 07:06:49 PM PDT 24
Peak memory 224628 kb
Host smart-11b9bd09-d6a2-4a28-a456-ef808462e605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646107286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.3646107286
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.3038102071
Short name T666
Test name
Test status
Simulation time 55058093 ps
CPU time 0.75 seconds
Started Jul 23 07:06:44 PM PDT 24
Finished Jul 23 07:06:47 PM PDT 24
Peak memory 207172 kb
Host smart-6a3570e7-cb7e-4767-b670-95e6e18a01d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038102071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.3038102071
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.2401853767
Short name T835
Test name
Test status
Simulation time 2777500202 ps
CPU time 18.96 seconds
Started Jul 23 07:06:48 PM PDT 24
Finished Jul 23 07:07:09 PM PDT 24
Peak memory 232956 kb
Host smart-b79802b0-1d7e-4f8a-b4f3-56ec67188bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401853767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.2401853767
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.3126280292
Short name T605
Test name
Test status
Simulation time 13517835812 ps
CPU time 82.94 seconds
Started Jul 23 07:06:52 PM PDT 24
Finished Jul 23 07:08:16 PM PDT 24
Peak memory 255392 kb
Host smart-f8d69e68-a9fe-427d-b9ac-f33158758305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126280292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.3126280292
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.746052313
Short name T585
Test name
Test status
Simulation time 191897454047 ps
CPU time 331.93 seconds
Started Jul 23 07:06:50 PM PDT 24
Finished Jul 23 07:12:23 PM PDT 24
Peak memory 249372 kb
Host smart-80769a48-7600-4675-96e2-0cc9f07d1626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746052313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idle
.746052313
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.3386522092
Short name T890
Test name
Test status
Simulation time 418369916 ps
CPU time 6.44 seconds
Started Jul 23 07:06:45 PM PDT 24
Finished Jul 23 07:06:53 PM PDT 24
Peak memory 224536 kb
Host smart-e9a5b9bb-cc99-4944-af61-a19231e67ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386522092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.3386522092
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.467289601
Short name T984
Test name
Test status
Simulation time 11156546488 ps
CPU time 37.91 seconds
Started Jul 23 07:06:48 PM PDT 24
Finished Jul 23 07:07:28 PM PDT 24
Peak memory 251056 kb
Host smart-3e00e3a9-da4e-4fb9-a94e-7025ae4f0554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467289601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmds
.467289601
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_intercept.262295204
Short name T706
Test name
Test status
Simulation time 2026275277 ps
CPU time 9.14 seconds
Started Jul 23 07:06:44 PM PDT 24
Finished Jul 23 07:06:55 PM PDT 24
Peak memory 232816 kb
Host smart-45919370-e790-46c9-8c44-37f525d9d214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262295204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.262295204
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.2961026798
Short name T538
Test name
Test status
Simulation time 5164116351 ps
CPU time 44.98 seconds
Started Jul 23 07:06:45 PM PDT 24
Finished Jul 23 07:07:32 PM PDT 24
Peak memory 249292 kb
Host smart-030322e9-47f9-4c85-8934-acdb2c170bc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961026798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.2961026798
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.824622870
Short name T1010
Test name
Test status
Simulation time 3618045754 ps
CPU time 7.36 seconds
Started Jul 23 07:06:44 PM PDT 24
Finished Jul 23 07:06:53 PM PDT 24
Peak memory 232936 kb
Host smart-f0964e4b-fc8b-409e-ba39-a20af39100ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824622870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swap
.824622870
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.2540252446
Short name T57
Test name
Test status
Simulation time 189835180 ps
CPU time 3.32 seconds
Started Jul 23 07:06:51 PM PDT 24
Finished Jul 23 07:06:56 PM PDT 24
Peak memory 224668 kb
Host smart-b2f9a270-b42b-4b9e-913f-d42530b0dfd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540252446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.2540252446
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.285080208
Short name T323
Test name
Test status
Simulation time 255832428 ps
CPU time 4.04 seconds
Started Jul 23 07:06:48 PM PDT 24
Finished Jul 23 07:06:54 PM PDT 24
Peak memory 223392 kb
Host smart-2a203b70-f8a1-4fc1-978b-803091c75d45
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=285080208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dire
ct.285080208
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.3097999387
Short name T991
Test name
Test status
Simulation time 22275269546 ps
CPU time 26.59 seconds
Started Jul 23 07:06:49 PM PDT 24
Finished Jul 23 07:07:18 PM PDT 24
Peak memory 233040 kb
Host smart-54fa0491-a4cd-4d51-8b7b-700069a68ad9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097999387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.3097999387
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.3249163926
Short name T956
Test name
Test status
Simulation time 18296511893 ps
CPU time 26.55 seconds
Started Jul 23 07:06:44 PM PDT 24
Finished Jul 23 07:07:12 PM PDT 24
Peak memory 216424 kb
Host smart-8ad999e6-cdd9-4745-957e-e1a2127a6afa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249163926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.3249163926
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.770728079
Short name T645
Test name
Test status
Simulation time 3877692935 ps
CPU time 9.23 seconds
Started Jul 23 07:06:46 PM PDT 24
Finished Jul 23 07:06:57 PM PDT 24
Peak memory 216512 kb
Host smart-6b5f7e21-c406-43aa-b3b7-f935c1c19a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770728079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.770728079
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.2919939144
Short name T962
Test name
Test status
Simulation time 11106784 ps
CPU time 0.68 seconds
Started Jul 23 07:06:45 PM PDT 24
Finished Jul 23 07:06:48 PM PDT 24
Peak memory 205760 kb
Host smart-bb9e8710-4ced-4e0f-993d-d1521cd6c2ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919939144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.2919939144
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.3443661765
Short name T298
Test name
Test status
Simulation time 343622014 ps
CPU time 0.84 seconds
Started Jul 23 07:06:46 PM PDT 24
Finished Jul 23 07:06:49 PM PDT 24
Peak memory 205808 kb
Host smart-18086d61-6daa-4a5f-aba4-3d64a5f47c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443661765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.3443661765
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.978370774
Short name T1001
Test name
Test status
Simulation time 7112295321 ps
CPU time 8.22 seconds
Started Jul 23 07:06:43 PM PDT 24
Finished Jul 23 07:06:52 PM PDT 24
Peak memory 236468 kb
Host smart-a010af01-1c97-497b-ab80-82970cd5188e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978370774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.978370774
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.1474615413
Short name T957
Test name
Test status
Simulation time 20829415 ps
CPU time 0.72 seconds
Started Jul 23 07:06:55 PM PDT 24
Finished Jul 23 07:06:56 PM PDT 24
Peak memory 205588 kb
Host smart-0ddc91a8-9995-4415-90ea-4094432eb42e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474615413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
1474615413
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.425650705
Short name T602
Test name
Test status
Simulation time 738952090 ps
CPU time 11.1 seconds
Started Jul 23 07:06:55 PM PDT 24
Finished Jul 23 07:07:07 PM PDT 24
Peak memory 224716 kb
Host smart-2286fb11-ce37-4cb8-9a2b-3cbd91eea643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425650705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.425650705
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.2920039237
Short name T721
Test name
Test status
Simulation time 70990453 ps
CPU time 0.74 seconds
Started Jul 23 07:06:48 PM PDT 24
Finished Jul 23 07:06:50 PM PDT 24
Peak memory 207052 kb
Host smart-59b2e39f-5a69-45d2-aa56-4544aa1ca831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920039237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.2920039237
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.1308119068
Short name T988
Test name
Test status
Simulation time 139528412 ps
CPU time 4.74 seconds
Started Jul 23 07:06:55 PM PDT 24
Finished Jul 23 07:07:01 PM PDT 24
Peak memory 234700 kb
Host smart-4292068c-9181-4fa0-a757-b008948d32ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308119068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.1308119068
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.3537360233
Short name T6
Test name
Test status
Simulation time 118111442240 ps
CPU time 78.72 seconds
Started Jul 23 07:06:49 PM PDT 24
Finished Jul 23 07:08:10 PM PDT 24
Peak memory 255456 kb
Host smart-fe786054-344d-4dae-9d06-030d14a59de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537360233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.3537360233
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.4210241754
Short name T713
Test name
Test status
Simulation time 29214853496 ps
CPU time 70.92 seconds
Started Jul 23 07:06:54 PM PDT 24
Finished Jul 23 07:08:06 PM PDT 24
Peak memory 249232 kb
Host smart-a200506d-89b4-418b-9f3d-0e615dd62977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210241754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.4210241754
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.3248140542
Short name T271
Test name
Test status
Simulation time 1460332192 ps
CPU time 9.79 seconds
Started Jul 23 07:06:52 PM PDT 24
Finished Jul 23 07:07:03 PM PDT 24
Peak memory 232912 kb
Host smart-ac5f7565-5a80-4646-8845-39e25a9737ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248140542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.3248140542
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.1615764165
Short name T345
Test name
Test status
Simulation time 59627465 ps
CPU time 0.74 seconds
Started Jul 23 07:06:50 PM PDT 24
Finished Jul 23 07:06:52 PM PDT 24
Peak memory 215908 kb
Host smart-02e6c236-421d-4aaf-ae6d-10a43f6334ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615764165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmd
s.1615764165
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_intercept.165430366
Short name T876
Test name
Test status
Simulation time 306243783 ps
CPU time 2.33 seconds
Started Jul 23 07:06:50 PM PDT 24
Finished Jul 23 07:06:54 PM PDT 24
Peak memory 224696 kb
Host smart-bb3c3ee1-4a11-44d0-863c-49ec782afaa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165430366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.165430366
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.3351574335
Short name T195
Test name
Test status
Simulation time 4305006090 ps
CPU time 11.81 seconds
Started Jul 23 07:06:50 PM PDT 24
Finished Jul 23 07:07:04 PM PDT 24
Peak memory 248820 kb
Host smart-915e781b-7871-4bc9-b8cc-86e6382620c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351574335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.3351574335
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.2909856812
Short name T151
Test name
Test status
Simulation time 73982551 ps
CPU time 2.71 seconds
Started Jul 23 07:06:50 PM PDT 24
Finished Jul 23 07:06:54 PM PDT 24
Peak memory 232884 kb
Host smart-b896fafe-0d4f-4646-a0d0-8fbe9fc87be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909856812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.2909856812
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.3016229267
Short name T906
Test name
Test status
Simulation time 1168617156 ps
CPU time 6.45 seconds
Started Jul 23 07:06:55 PM PDT 24
Finished Jul 23 07:07:02 PM PDT 24
Peak memory 224712 kb
Host smart-f85baeea-1ebe-4faf-bbef-020a4ca277c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016229267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.3016229267
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.2439863324
Short name T131
Test name
Test status
Simulation time 7319356852 ps
CPU time 9.81 seconds
Started Jul 23 07:06:54 PM PDT 24
Finished Jul 23 07:07:05 PM PDT 24
Peak memory 223376 kb
Host smart-555ff073-19e3-4d17-bf27-26321494c97f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2439863324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.2439863324
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.3194123941
Short name T284
Test name
Test status
Simulation time 2006355726 ps
CPU time 19.16 seconds
Started Jul 23 07:06:51 PM PDT 24
Finished Jul 23 07:07:12 PM PDT 24
Peak memory 216460 kb
Host smart-cee1217e-f1c8-4208-a233-0befab1223fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194123941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.3194123941
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.257010282
Short name T404
Test name
Test status
Simulation time 23332862828 ps
CPU time 16.39 seconds
Started Jul 23 07:06:50 PM PDT 24
Finished Jul 23 07:07:08 PM PDT 24
Peak memory 216448 kb
Host smart-4dc83753-25a6-4089-911b-179ab8a81bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257010282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.257010282
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.4039216734
Short name T783
Test name
Test status
Simulation time 454306892 ps
CPU time 2.95 seconds
Started Jul 23 07:06:47 PM PDT 24
Finished Jul 23 07:06:52 PM PDT 24
Peak memory 216428 kb
Host smart-d50636bf-57a4-40a9-9aa1-26b20ec35c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039216734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.4039216734
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.1942093558
Short name T574
Test name
Test status
Simulation time 67499642 ps
CPU time 0.83 seconds
Started Jul 23 07:06:48 PM PDT 24
Finished Jul 23 07:06:50 PM PDT 24
Peak memory 205976 kb
Host smart-0e73a595-c8f0-4fec-9062-521850fa20b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942093558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.1942093558
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.3079220359
Short name T502
Test name
Test status
Simulation time 1222824150 ps
CPU time 4.67 seconds
Started Jul 23 07:06:50 PM PDT 24
Finished Jul 23 07:06:57 PM PDT 24
Peak memory 232888 kb
Host smart-5152860b-d298-4449-bbe8-65e702b199c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079220359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.3079220359
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.3322650940
Short name T501
Test name
Test status
Simulation time 13884587 ps
CPU time 0.77 seconds
Started Jul 23 07:06:59 PM PDT 24
Finished Jul 23 07:07:01 PM PDT 24
Peak memory 205924 kb
Host smart-f156d3c9-26bf-447c-b95a-aa922a6605e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322650940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
3322650940
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.1983206887
Short name T575
Test name
Test status
Simulation time 234699270 ps
CPU time 2.8 seconds
Started Jul 23 07:06:53 PM PDT 24
Finished Jul 23 07:06:56 PM PDT 24
Peak memory 232880 kb
Host smart-878828d7-17df-4928-bc36-08b37ee7f443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983206887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.1983206887
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.1488344099
Short name T556
Test name
Test status
Simulation time 36891455 ps
CPU time 0.77 seconds
Started Jul 23 07:06:55 PM PDT 24
Finished Jul 23 07:06:56 PM PDT 24
Peak memory 206744 kb
Host smart-03101781-50b6-4c37-a7b6-659d5ed290fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488344099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.1488344099
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.2309296616
Short name T870
Test name
Test status
Simulation time 37086106584 ps
CPU time 252.97 seconds
Started Jul 23 07:06:59 PM PDT 24
Finished Jul 23 07:11:13 PM PDT 24
Peak memory 257532 kb
Host smart-607d2bac-4d27-4f1e-a576-7018df4b43dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309296616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.2309296616
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.2112989750
Short name T403
Test name
Test status
Simulation time 2119210642 ps
CPU time 20.64 seconds
Started Jul 23 07:06:59 PM PDT 24
Finished Jul 23 07:07:21 PM PDT 24
Peak memory 217860 kb
Host smart-547bcb8d-8aa5-4547-93b5-81bbacecc366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112989750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.2112989750
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.3058589306
Short name T925
Test name
Test status
Simulation time 5572526457 ps
CPU time 42.65 seconds
Started Jul 23 07:07:02 PM PDT 24
Finished Jul 23 07:07:47 PM PDT 24
Peak memory 224692 kb
Host smart-83bb7a9f-bcf0-47bc-a8bf-63674b1fa7e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058589306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.3058589306
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.3424962688
Short name T275
Test name
Test status
Simulation time 3146334112 ps
CPU time 48.33 seconds
Started Jul 23 07:07:01 PM PDT 24
Finished Jul 23 07:07:51 PM PDT 24
Peak memory 232936 kb
Host smart-0a85d359-da81-4576-8a42-6a1bf80fdf61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424962688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.3424962688
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_intercept.3187993569
Short name T895
Test name
Test status
Simulation time 3949502830 ps
CPU time 13.38 seconds
Started Jul 23 07:06:54 PM PDT 24
Finished Jul 23 07:07:09 PM PDT 24
Peak memory 224748 kb
Host smart-362712b8-e842-41ba-9726-a8c7bed3ce23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187993569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.3187993569
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.96857400
Short name T778
Test name
Test status
Simulation time 3566589903 ps
CPU time 40.11 seconds
Started Jul 23 07:06:57 PM PDT 24
Finished Jul 23 07:07:38 PM PDT 24
Peak memory 233000 kb
Host smart-676e8c52-b87b-4bdf-b1c8-a5513cc85330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96857400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.96857400
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.1542051432
Short name T681
Test name
Test status
Simulation time 584320664 ps
CPU time 3.17 seconds
Started Jul 23 07:06:55 PM PDT 24
Finished Jul 23 07:06:59 PM PDT 24
Peak memory 224608 kb
Host smart-eae2966c-ece8-4b45-a51f-295b3b371d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542051432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.1542051432
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.2947946312
Short name T245
Test name
Test status
Simulation time 5510272995 ps
CPU time 15.01 seconds
Started Jul 23 07:06:56 PM PDT 24
Finished Jul 23 07:07:12 PM PDT 24
Peak memory 237792 kb
Host smart-f6c1f544-4641-4f8f-98db-e04af2c64a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947946312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.2947946312
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.3091808285
Short name T426
Test name
Test status
Simulation time 230859890 ps
CPU time 4.45 seconds
Started Jul 23 07:07:01 PM PDT 24
Finished Jul 23 07:07:08 PM PDT 24
Peak memory 220480 kb
Host smart-861c713b-6b00-49ee-b1a4-e6eb2e98c004
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3091808285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.3091808285
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.226157127
Short name T266
Test name
Test status
Simulation time 47359828416 ps
CPU time 412.92 seconds
Started Jul 23 07:06:59 PM PDT 24
Finished Jul 23 07:13:54 PM PDT 24
Peak memory 270084 kb
Host smart-20e04078-cc5a-4e5c-acb8-14e77c93e130
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226157127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stres
s_all.226157127
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.2671998475
Short name T625
Test name
Test status
Simulation time 982136497 ps
CPU time 7.4 seconds
Started Jul 23 07:06:54 PM PDT 24
Finished Jul 23 07:07:02 PM PDT 24
Peak memory 216392 kb
Host smart-a1f1d554-38c4-4d54-bd06-2a22c90169f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671998475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.2671998475
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.1183462152
Short name T799
Test name
Test status
Simulation time 9182261389 ps
CPU time 7.26 seconds
Started Jul 23 07:06:55 PM PDT 24
Finished Jul 23 07:07:04 PM PDT 24
Peak memory 216452 kb
Host smart-90368cad-a839-43e1-8bad-99be578c54cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183462152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.1183462152
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.842009895
Short name T488
Test name
Test status
Simulation time 30228483 ps
CPU time 1.15 seconds
Started Jul 23 07:06:53 PM PDT 24
Finished Jul 23 07:06:55 PM PDT 24
Peak memory 216108 kb
Host smart-cb5e0d0c-5746-47c2-b0cc-2fe20ba13e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842009895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.842009895
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.1935711072
Short name T326
Test name
Test status
Simulation time 292874068 ps
CPU time 0.88 seconds
Started Jul 23 07:06:55 PM PDT 24
Finished Jul 23 07:06:57 PM PDT 24
Peak memory 206300 kb
Host smart-dc220b3b-50b7-47eb-9403-f111e3e6614f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935711072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.1935711072
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.1232583708
Short name T878
Test name
Test status
Simulation time 3374744681 ps
CPU time 7.23 seconds
Started Jul 23 07:06:54 PM PDT 24
Finished Jul 23 07:07:02 PM PDT 24
Peak memory 232924 kb
Host smart-5e27aeb1-047e-4663-8d4e-b3d7854ff034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232583708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.1232583708
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.2378252898
Short name T23
Test name
Test status
Simulation time 22534766 ps
CPU time 0.73 seconds
Started Jul 23 07:07:04 PM PDT 24
Finished Jul 23 07:07:07 PM PDT 24
Peak memory 205556 kb
Host smart-e2bf2d28-e0e0-4ef6-a81e-6899b4cf893b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378252898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
2378252898
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.3917677699
Short name T487
Test name
Test status
Simulation time 132175543 ps
CPU time 2.3 seconds
Started Jul 23 07:06:59 PM PDT 24
Finished Jul 23 07:07:02 PM PDT 24
Peak memory 232504 kb
Host smart-c46136be-9e84-4098-bb7c-2895c0dfd307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917677699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.3917677699
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.2577950083
Short name T731
Test name
Test status
Simulation time 14789858 ps
CPU time 0.72 seconds
Started Jul 23 07:07:00 PM PDT 24
Finished Jul 23 07:07:02 PM PDT 24
Peak memory 206036 kb
Host smart-29564d7d-9444-428e-a2d5-5eefadf84044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577950083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.2577950083
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.2313512526
Short name T690
Test name
Test status
Simulation time 11020438151 ps
CPU time 91.89 seconds
Started Jul 23 07:07:04 PM PDT 24
Finished Jul 23 07:08:38 PM PDT 24
Peak memory 237192 kb
Host smart-1957b347-473f-4be5-a78e-0dca55b3eb75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313512526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.2313512526
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.2585112178
Short name T122
Test name
Test status
Simulation time 3268568952 ps
CPU time 83.99 seconds
Started Jul 23 07:07:04 PM PDT 24
Finished Jul 23 07:08:30 PM PDT 24
Peak memory 263544 kb
Host smart-a7207814-24ce-4ddd-ac71-6f4c8b424d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585112178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.2585112178
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.27885761
Short name T235
Test name
Test status
Simulation time 32689367215 ps
CPU time 217.03 seconds
Started Jul 23 07:07:05 PM PDT 24
Finished Jul 23 07:10:44 PM PDT 24
Peak memory 255428 kb
Host smart-bc6c8545-ae6e-4ec0-811d-d40edcef84b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27885761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idle.27885761
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.1548833762
Short name T343
Test name
Test status
Simulation time 328526236 ps
CPU time 7.52 seconds
Started Jul 23 07:07:02 PM PDT 24
Finished Jul 23 07:07:11 PM PDT 24
Peak memory 234464 kb
Host smart-2d02d971-74fb-42f8-9948-561ead8b3da0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548833762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.1548833762
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.3984589372
Short name T531
Test name
Test status
Simulation time 30421389 ps
CPU time 0.72 seconds
Started Jul 23 07:07:04 PM PDT 24
Finished Jul 23 07:07:07 PM PDT 24
Peak memory 215908 kb
Host smart-8817fa07-5e3f-4171-8be1-3d62b1ee0e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984589372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmd
s.3984589372
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_intercept.4239352050
Short name T651
Test name
Test status
Simulation time 1791528789 ps
CPU time 11 seconds
Started Jul 23 07:06:57 PM PDT 24
Finished Jul 23 07:07:09 PM PDT 24
Peak memory 224740 kb
Host smart-a1020d90-cb28-4dc5-ad1c-df74164a3ec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239352050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.4239352050
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.2598217168
Short name T786
Test name
Test status
Simulation time 802053739 ps
CPU time 14.31 seconds
Started Jul 23 07:06:59 PM PDT 24
Finished Jul 23 07:07:14 PM PDT 24
Peak memory 232912 kb
Host smart-9beb12e6-cf59-420e-98fb-942e93dac2c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598217168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.2598217168
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.374823041
Short name T960
Test name
Test status
Simulation time 883044725 ps
CPU time 9.33 seconds
Started Jul 23 07:06:59 PM PDT 24
Finished Jul 23 07:07:10 PM PDT 24
Peak memory 224584 kb
Host smart-e791c89b-3e7c-405b-84b2-91e87e4e9fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374823041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swap
.374823041
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.1889349280
Short name T520
Test name
Test status
Simulation time 8473741084 ps
CPU time 9 seconds
Started Jul 23 07:06:59 PM PDT 24
Finished Jul 23 07:07:09 PM PDT 24
Peak memory 233156 kb
Host smart-78fd08a5-418b-49e2-a6a1-ca30d5592f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889349280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.1889349280
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.39739527
Short name T657
Test name
Test status
Simulation time 310313289 ps
CPU time 5.8 seconds
Started Jul 23 07:07:05 PM PDT 24
Finished Jul 23 07:07:13 PM PDT 24
Peak memory 223384 kb
Host smart-97f2c574-1e82-413d-9405-22fdb48c54af
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=39739527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_direc
t.39739527
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.4128978109
Short name T954
Test name
Test status
Simulation time 4418982515 ps
CPU time 20.63 seconds
Started Jul 23 07:06:59 PM PDT 24
Finished Jul 23 07:07:21 PM PDT 24
Peak memory 216400 kb
Host smart-40ecc2d9-be67-47b0-b74c-fd2a6685e201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128978109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.4128978109
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.1488508630
Short name T892
Test name
Test status
Simulation time 6401767059 ps
CPU time 17.31 seconds
Started Jul 23 07:06:59 PM PDT 24
Finished Jul 23 07:07:18 PM PDT 24
Peak memory 216496 kb
Host smart-6c1876be-a9a0-46e7-8b3e-02d907012a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488508630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.1488508630
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.1158252749
Short name T582
Test name
Test status
Simulation time 64298681 ps
CPU time 2.87 seconds
Started Jul 23 07:07:01 PM PDT 24
Finished Jul 23 07:07:06 PM PDT 24
Peak memory 216488 kb
Host smart-20a60a3b-1373-4c05-9426-6b27c67f5441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158252749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.1158252749
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.2645467405
Short name T370
Test name
Test status
Simulation time 87663138 ps
CPU time 0.77 seconds
Started Jul 23 07:07:00 PM PDT 24
Finished Jul 23 07:07:02 PM PDT 24
Peak memory 206132 kb
Host smart-300b420a-1af5-42dc-bb04-26645025f8a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645467405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.2645467405
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.301497157
Short name T120
Test name
Test status
Simulation time 217083980 ps
CPU time 5.9 seconds
Started Jul 23 07:07:00 PM PDT 24
Finished Jul 23 07:07:07 PM PDT 24
Peak memory 232896 kb
Host smart-5369b1d1-e7a4-4a40-b596-17ced67e5503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301497157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.301497157
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.1795893347
Short name T712
Test name
Test status
Simulation time 19457500 ps
CPU time 0.71 seconds
Started Jul 23 07:07:11 PM PDT 24
Finished Jul 23 07:07:14 PM PDT 24
Peak memory 205016 kb
Host smart-3c0bb653-98e8-432a-ad53-1782656386a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795893347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
1795893347
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.4246071382
Short name T711
Test name
Test status
Simulation time 549122257 ps
CPU time 6.59 seconds
Started Jul 23 07:07:05 PM PDT 24
Finished Jul 23 07:07:14 PM PDT 24
Peak memory 232796 kb
Host smart-3ecc89da-e57d-4744-9b0b-32d0c3fd7326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246071382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.4246071382
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.947763437
Short name T826
Test name
Test status
Simulation time 13366957 ps
CPU time 0.77 seconds
Started Jul 23 07:07:06 PM PDT 24
Finished Jul 23 07:07:08 PM PDT 24
Peak memory 207052 kb
Host smart-2d3ef9e4-4178-45e0-b44b-092909cbc356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947763437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.947763437
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.2733004432
Short name T197
Test name
Test status
Simulation time 6109050058 ps
CPU time 79.48 seconds
Started Jul 23 07:07:06 PM PDT 24
Finished Jul 23 07:08:28 PM PDT 24
Peak memory 254344 kb
Host smart-5ce52d60-e688-4acc-8b40-47e5d5291de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733004432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.2733004432
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.1846364799
Short name T210
Test name
Test status
Simulation time 16037728708 ps
CPU time 97.43 seconds
Started Jul 23 07:07:10 PM PDT 24
Finished Jul 23 07:08:49 PM PDT 24
Peak memory 251508 kb
Host smart-964aeb6f-ec06-47e8-9aae-1d81ee31938c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846364799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.1846364799
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.3524219955
Short name T504
Test name
Test status
Simulation time 322146094 ps
CPU time 6.1 seconds
Started Jul 23 07:07:02 PM PDT 24
Finished Jul 23 07:07:10 PM PDT 24
Peak memory 224672 kb
Host smart-1a591194-b628-4ba4-823b-46c9e3e4aae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524219955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.3524219955
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.4234355235
Short name T877
Test name
Test status
Simulation time 66129219476 ps
CPU time 111.34 seconds
Started Jul 23 07:07:05 PM PDT 24
Finished Jul 23 07:08:58 PM PDT 24
Peak memory 254880 kb
Host smart-222c5631-2b09-4f96-a02d-2947e8883091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234355235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmd
s.4234355235
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_intercept.2497879835
Short name T100
Test name
Test status
Simulation time 98963053 ps
CPU time 3.29 seconds
Started Jul 23 07:07:03 PM PDT 24
Finished Jul 23 07:07:09 PM PDT 24
Peak memory 228456 kb
Host smart-b7cd208a-d5ca-4f71-8537-fbf6c650a23d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497879835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.2497879835
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.4093973410
Short name T550
Test name
Test status
Simulation time 6744446142 ps
CPU time 59.73 seconds
Started Jul 23 07:07:04 PM PDT 24
Finished Jul 23 07:08:06 PM PDT 24
Peak memory 233024 kb
Host smart-cce84c69-1873-4d4a-825b-42a6b22167bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093973410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.4093973410
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.930047118
Short name T668
Test name
Test status
Simulation time 323780351 ps
CPU time 4.67 seconds
Started Jul 23 07:07:07 PM PDT 24
Finished Jul 23 07:07:13 PM PDT 24
Peak memory 232852 kb
Host smart-6264cde6-b30b-40db-9a22-473ef4d6024d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930047118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swap
.930047118
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.1694604168
Short name T934
Test name
Test status
Simulation time 227637965 ps
CPU time 2.51 seconds
Started Jul 23 07:07:04 PM PDT 24
Finished Jul 23 07:07:09 PM PDT 24
Peak memory 224624 kb
Host smart-24f78dc1-94fd-48e2-9e88-4a3ac4775675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694604168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.1694604168
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.2066937148
Short name T765
Test name
Test status
Simulation time 156373305 ps
CPU time 4.38 seconds
Started Jul 23 07:07:05 PM PDT 24
Finished Jul 23 07:07:12 PM PDT 24
Peak memory 223244 kb
Host smart-a1fac65f-851e-442a-a09a-7cee81ffa4e6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2066937148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.2066937148
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.1787387751
Short name T963
Test name
Test status
Simulation time 16710737652 ps
CPU time 76.85 seconds
Started Jul 23 07:07:09 PM PDT 24
Finished Jul 23 07:08:27 PM PDT 24
Peak memory 249496 kb
Host smart-67783d66-4ed2-4c43-a5b6-81058e7f7740
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787387751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.1787387751
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.3038456629
Short name T281
Test name
Test status
Simulation time 29887794603 ps
CPU time 32.85 seconds
Started Jul 23 07:07:03 PM PDT 24
Finished Jul 23 07:07:38 PM PDT 24
Peak memory 216552 kb
Host smart-e1c8ff7e-2708-4a7e-9a1a-eb29586edc1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038456629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.3038456629
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.1684012556
Short name T342
Test name
Test status
Simulation time 36523464 ps
CPU time 0.73 seconds
Started Jul 23 07:07:04 PM PDT 24
Finished Jul 23 07:07:08 PM PDT 24
Peak memory 205836 kb
Host smart-772f7866-88dc-4e14-8189-01ec87011a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684012556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.1684012556
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.1995135033
Short name T726
Test name
Test status
Simulation time 360829888 ps
CPU time 1 seconds
Started Jul 23 07:07:08 PM PDT 24
Finished Jul 23 07:07:10 PM PDT 24
Peak memory 206836 kb
Host smart-1dbc526c-da50-4677-a3e1-7405a3c7dc0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995135033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.1995135033
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.624416973
Short name T364
Test name
Test status
Simulation time 176273390 ps
CPU time 0.88 seconds
Started Jul 23 07:07:03 PM PDT 24
Finished Jul 23 07:07:06 PM PDT 24
Peak memory 206132 kb
Host smart-119a6ee8-cd2f-41cc-a6f2-01b85661ace1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624416973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.624416973
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.4264410574
Short name T205
Test name
Test status
Simulation time 117248528539 ps
CPU time 16.71 seconds
Started Jul 23 07:07:04 PM PDT 24
Finished Jul 23 07:07:23 PM PDT 24
Peak memory 224792 kb
Host smart-520fb6ca-e457-44d4-9559-ddcd08dc150b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264410574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.4264410574
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.1796330562
Short name T118
Test name
Test status
Simulation time 12061536 ps
CPU time 0.68 seconds
Started Jul 23 07:07:09 PM PDT 24
Finished Jul 23 07:07:11 PM PDT 24
Peak memory 205584 kb
Host smart-7c61287d-f457-422b-8186-5b0964288607
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796330562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
1796330562
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.383877554
Short name T490
Test name
Test status
Simulation time 84533781 ps
CPU time 3.73 seconds
Started Jul 23 07:07:10 PM PDT 24
Finished Jul 23 07:07:16 PM PDT 24
Peak memory 232888 kb
Host smart-fe092a23-cc4c-46ba-b1f9-a0af12df34b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383877554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.383877554
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.3586739041
Short name T294
Test name
Test status
Simulation time 53473257 ps
CPU time 0.79 seconds
Started Jul 23 07:07:09 PM PDT 24
Finished Jul 23 07:07:10 PM PDT 24
Peak memory 207048 kb
Host smart-ccd36632-7dbb-44c4-b644-a95a0b7df40e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586739041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.3586739041
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.2309422369
Short name T11
Test name
Test status
Simulation time 384744620 ps
CPU time 3.27 seconds
Started Jul 23 07:07:10 PM PDT 24
Finished Jul 23 07:07:16 PM PDT 24
Peak memory 232904 kb
Host smart-0c69e7cf-d79e-4b99-9eca-1bcf9c05e353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309422369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.2309422369
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.1286700392
Short name T794
Test name
Test status
Simulation time 30671903930 ps
CPU time 178.93 seconds
Started Jul 23 07:07:10 PM PDT 24
Finished Jul 23 07:10:11 PM PDT 24
Peak memory 255320 kb
Host smart-58f146a9-4592-48f4-ab29-ec3a4763d3f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286700392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.1286700392
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.18420021
Short name T276
Test name
Test status
Simulation time 5290742774 ps
CPU time 22.47 seconds
Started Jul 23 07:07:10 PM PDT 24
Finished Jul 23 07:07:34 PM PDT 24
Peak memory 235036 kb
Host smart-b03a0032-b7c7-4c1d-a202-d6dc264b0d99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18420021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.18420021
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.3885515535
Short name T251
Test name
Test status
Simulation time 21748411491 ps
CPU time 38.89 seconds
Started Jul 23 07:07:10 PM PDT 24
Finished Jul 23 07:07:50 PM PDT 24
Peak memory 253020 kb
Host smart-e84011c6-ed36-4f53-89e5-61a12727e60e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885515535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmd
s.3885515535
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_intercept.1689870189
Short name T76
Test name
Test status
Simulation time 5709144675 ps
CPU time 19.77 seconds
Started Jul 23 07:07:10 PM PDT 24
Finished Jul 23 07:07:32 PM PDT 24
Peak memory 224704 kb
Host smart-9f70a282-bb70-463e-916a-b6eb59ab6135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689870189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.1689870189
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.3356310713
Short name T700
Test name
Test status
Simulation time 41401321475 ps
CPU time 99.31 seconds
Started Jul 23 07:07:10 PM PDT 24
Finished Jul 23 07:08:52 PM PDT 24
Peak memory 232800 kb
Host smart-4c229b48-9e7f-4301-92a4-228f2dfb249f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356310713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.3356310713
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.575222647
Short name T579
Test name
Test status
Simulation time 554888225 ps
CPU time 2.77 seconds
Started Jul 23 07:07:11 PM PDT 24
Finished Jul 23 07:07:16 PM PDT 24
Peak memory 232888 kb
Host smart-1c748fcc-6b8b-48a2-9f49-f790061d4a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575222647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swap
.575222647
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.3901410810
Short name T977
Test name
Test status
Simulation time 12407353601 ps
CPU time 15.28 seconds
Started Jul 23 07:07:13 PM PDT 24
Finished Jul 23 07:07:30 PM PDT 24
Peak memory 240252 kb
Host smart-6c09661a-2336-4e7c-b0fa-84be86920a61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901410810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.3901410810
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.2138263433
Short name T358
Test name
Test status
Simulation time 966016060 ps
CPU time 9.18 seconds
Started Jul 23 07:07:11 PM PDT 24
Finished Jul 23 07:07:22 PM PDT 24
Peak memory 221808 kb
Host smart-0c3ba210-5fd8-455a-87b5-9920de1b038e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2138263433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.2138263433
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.2144242870
Short name T572
Test name
Test status
Simulation time 9440384805 ps
CPU time 23.95 seconds
Started Jul 23 07:07:09 PM PDT 24
Finished Jul 23 07:07:34 PM PDT 24
Peak memory 216580 kb
Host smart-d60d2582-857e-4f6c-94e2-ac3e0ac9dfaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144242870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.2144242870
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.2670795031
Short name T334
Test name
Test status
Simulation time 41291881 ps
CPU time 0.7 seconds
Started Jul 23 07:07:10 PM PDT 24
Finished Jul 23 07:07:13 PM PDT 24
Peak memory 205816 kb
Host smart-5bc113db-554c-494e-a2d2-4fa4156dce04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670795031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.2670795031
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.558653503
Short name T952
Test name
Test status
Simulation time 165116968 ps
CPU time 1.7 seconds
Started Jul 23 07:07:11 PM PDT 24
Finished Jul 23 07:07:15 PM PDT 24
Peak memory 216640 kb
Host smart-eb28ea63-7855-4369-886a-a7af6a6898e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558653503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.558653503
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.797824507
Short name T486
Test name
Test status
Simulation time 15194982 ps
CPU time 0.73 seconds
Started Jul 23 07:07:10 PM PDT 24
Finished Jul 23 07:07:13 PM PDT 24
Peak memory 206076 kb
Host smart-3f86b4fc-bf48-48db-bd07-76ab54dfb00d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797824507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.797824507
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.1031822441
Short name T694
Test name
Test status
Simulation time 16280755750 ps
CPU time 14.34 seconds
Started Jul 23 07:07:09 PM PDT 24
Finished Jul 23 07:07:25 PM PDT 24
Peak memory 224740 kb
Host smart-55f42149-3dbe-4958-89a8-a6d65e7d0892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031822441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.1031822441
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.1310333971
Short name T583
Test name
Test status
Simulation time 33928363 ps
CPU time 0.69 seconds
Started Jul 23 07:07:14 PM PDT 24
Finished Jul 23 07:07:16 PM PDT 24
Peak memory 204904 kb
Host smart-fb914ceb-bfe8-40c9-b04a-fec944b2a463
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310333971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
1310333971
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.1558501361
Short name T407
Test name
Test status
Simulation time 13563229802 ps
CPU time 31.96 seconds
Started Jul 23 07:07:14 PM PDT 24
Finished Jul 23 07:07:47 PM PDT 24
Peak memory 232928 kb
Host smart-bb876b5f-168f-4b09-b48c-4c671d589737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558501361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.1558501361
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.2997844461
Short name T471
Test name
Test status
Simulation time 15101137 ps
CPU time 0.74 seconds
Started Jul 23 07:07:10 PM PDT 24
Finished Jul 23 07:07:12 PM PDT 24
Peak memory 205708 kb
Host smart-cca225d0-9d25-4bac-afaa-e5901ae02e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997844461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.2997844461
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.3219614642
Short name T47
Test name
Test status
Simulation time 814501364 ps
CPU time 10.6 seconds
Started Jul 23 07:07:13 PM PDT 24
Finished Jul 23 07:07:25 PM PDT 24
Peak memory 221540 kb
Host smart-4b570938-bf56-458c-bebd-a4a0be6d0aa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219614642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.3219614642
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.3901315648
Short name T568
Test name
Test status
Simulation time 53987269750 ps
CPU time 85.68 seconds
Started Jul 23 07:07:16 PM PDT 24
Finished Jul 23 07:08:42 PM PDT 24
Peak memory 249500 kb
Host smart-061573a2-fff7-4adf-b735-d40cbde86f52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901315648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.3901315648
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.2440655902
Short name T756
Test name
Test status
Simulation time 17328456465 ps
CPU time 155.7 seconds
Started Jul 23 07:07:14 PM PDT 24
Finished Jul 23 07:09:51 PM PDT 24
Peak memory 255668 kb
Host smart-3902109e-dea8-480b-8e2f-d31414c3057c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440655902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.2440655902
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.4292288699
Short name T566
Test name
Test status
Simulation time 263983910 ps
CPU time 3.49 seconds
Started Jul 23 07:07:17 PM PDT 24
Finished Jul 23 07:07:22 PM PDT 24
Peak memory 224668 kb
Host smart-e304f7c1-8adb-4e3e-a73c-3dcccb2d3402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292288699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.4292288699
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.2895033270
Short name T380
Test name
Test status
Simulation time 35581931706 ps
CPU time 61.66 seconds
Started Jul 23 07:07:15 PM PDT 24
Finished Jul 23 07:08:17 PM PDT 24
Peak memory 238508 kb
Host smart-2e937e02-3752-4e3d-9969-61d2dec1f4fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895033270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmd
s.2895033270
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.2872138096
Short name T569
Test name
Test status
Simulation time 9224154218 ps
CPU time 19.99 seconds
Started Jul 23 07:07:14 PM PDT 24
Finished Jul 23 07:07:35 PM PDT 24
Peak memory 232836 kb
Host smart-077c6780-0f03-43b1-836b-ecc4cdc3b7aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872138096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.2872138096
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.2788291698
Short name T537
Test name
Test status
Simulation time 457116530 ps
CPU time 10.81 seconds
Started Jul 23 07:07:17 PM PDT 24
Finished Jul 23 07:07:28 PM PDT 24
Peak memory 224668 kb
Host smart-83001e7a-ca71-439b-a6e4-28c29666477b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788291698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.2788291698
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.3231749785
Short name T689
Test name
Test status
Simulation time 393885277 ps
CPU time 2.27 seconds
Started Jul 23 07:07:17 PM PDT 24
Finished Jul 23 07:07:21 PM PDT 24
Peak memory 223976 kb
Host smart-3036ef24-dfe5-4baa-a320-eb8a23dee5c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231749785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.3231749785
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.396382394
Short name T329
Test name
Test status
Simulation time 2676811363 ps
CPU time 4.84 seconds
Started Jul 23 07:07:14 PM PDT 24
Finished Jul 23 07:07:20 PM PDT 24
Peak memory 232984 kb
Host smart-6ae47604-9ff2-4b9d-b356-284a3030064d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396382394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.396382394
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.1901370596
Short name T417
Test name
Test status
Simulation time 566133166 ps
CPU time 3.87 seconds
Started Jul 23 07:07:15 PM PDT 24
Finished Jul 23 07:07:20 PM PDT 24
Peak memory 219180 kb
Host smart-f24f16b9-03c1-473b-9f04-4ba473ec60e0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1901370596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.1901370596
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.2084997026
Short name T819
Test name
Test status
Simulation time 19010189287 ps
CPU time 161.13 seconds
Started Jul 23 07:07:12 PM PDT 24
Finished Jul 23 07:09:55 PM PDT 24
Peak memory 256964 kb
Host smart-96e9eb4f-be5f-45b9-a759-5e26f305504d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084997026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.2084997026
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.2769938726
Short name T673
Test name
Test status
Simulation time 3324782421 ps
CPU time 23.2 seconds
Started Jul 23 07:07:16 PM PDT 24
Finished Jul 23 07:07:41 PM PDT 24
Peak memory 216816 kb
Host smart-fa24159c-6d49-435a-91ed-b49cae71becd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769938726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.2769938726
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.1109645624
Short name T888
Test name
Test status
Simulation time 771163137 ps
CPU time 5.18 seconds
Started Jul 23 07:07:15 PM PDT 24
Finished Jul 23 07:07:22 PM PDT 24
Peak memory 216456 kb
Host smart-84338d24-08ce-47d8-bb5f-850dc94af1bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109645624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.1109645624
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.4119308708
Short name T318
Test name
Test status
Simulation time 106441836 ps
CPU time 1.05 seconds
Started Jul 23 07:07:15 PM PDT 24
Finished Jul 23 07:07:17 PM PDT 24
Peak memory 207228 kb
Host smart-27829764-9c27-48e0-85f1-3f0ba6184c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119308708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.4119308708
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.3657135114
Short name T302
Test name
Test status
Simulation time 38209706 ps
CPU time 0.78 seconds
Started Jul 23 07:07:16 PM PDT 24
Finished Jul 23 07:07:18 PM PDT 24
Peak memory 206068 kb
Host smart-c654ee76-7a36-4385-810c-ddd17b19df1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657135114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.3657135114
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.2514718134
Short name T246
Test name
Test status
Simulation time 1812379640 ps
CPU time 5.67 seconds
Started Jul 23 07:07:13 PM PDT 24
Finished Jul 23 07:07:20 PM PDT 24
Peak memory 224636 kb
Host smart-39cd0ab6-4451-4601-9b36-e77830fec57e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514718134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.2514718134
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.789585821
Short name T113
Test name
Test status
Simulation time 10510519 ps
CPU time 0.7 seconds
Started Jul 23 07:07:21 PM PDT 24
Finished Jul 23 07:07:23 PM PDT 24
Peak memory 205620 kb
Host smart-9533cd80-d7be-4838-83a9-3bb702b7d42c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789585821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.789585821
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.1608692322
Short name T704
Test name
Test status
Simulation time 98690107 ps
CPU time 1.95 seconds
Started Jul 23 07:07:21 PM PDT 24
Finished Jul 23 07:07:24 PM PDT 24
Peak memory 224096 kb
Host smart-90b6bbf2-1ea8-4a3c-be5a-cdb51efddd15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608692322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.1608692322
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.942609714
Short name T719
Test name
Test status
Simulation time 62584209 ps
CPU time 0.75 seconds
Started Jul 23 07:07:17 PM PDT 24
Finished Jul 23 07:07:19 PM PDT 24
Peak memory 206700 kb
Host smart-8d15c1d4-ebd4-41ca-9cc3-b60907d93c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942609714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.942609714
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.3354098911
Short name T229
Test name
Test status
Simulation time 56328095586 ps
CPU time 213.01 seconds
Started Jul 23 07:07:20 PM PDT 24
Finished Jul 23 07:10:55 PM PDT 24
Peak memory 260796 kb
Host smart-21897502-7f44-42f5-ba5c-b531093414ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354098911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.3354098911
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.3509679807
Short name T470
Test name
Test status
Simulation time 1609987883 ps
CPU time 27.59 seconds
Started Jul 23 07:07:20 PM PDT 24
Finished Jul 23 07:07:49 PM PDT 24
Peak memory 222288 kb
Host smart-8bca7182-3cb1-4ea7-ad23-ca558cb6e3e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509679807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.3509679807
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.3513816416
Short name T225
Test name
Test status
Simulation time 4149257779 ps
CPU time 51.13 seconds
Started Jul 23 07:07:19 PM PDT 24
Finished Jul 23 07:08:11 PM PDT 24
Peak memory 249368 kb
Host smart-87b3c068-8d92-4787-b177-1d85caa5fac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513816416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.3513816416
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.498908953
Short name T661
Test name
Test status
Simulation time 1865536910 ps
CPU time 15.31 seconds
Started Jul 23 07:07:19 PM PDT 24
Finished Jul 23 07:07:35 PM PDT 24
Peak memory 240956 kb
Host smart-7a4ac23d-6e1c-4084-be47-fcc31cda750d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498908953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.498908953
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.3847715161
Short name T36
Test name
Test status
Simulation time 30075508966 ps
CPU time 118.43 seconds
Started Jul 23 07:07:19 PM PDT 24
Finished Jul 23 07:09:18 PM PDT 24
Peak memory 249356 kb
Host smart-bb4a8c21-5c34-48fb-8201-d74fbcdd3def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847715161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmd
s.3847715161
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_intercept.3537986264
Short name T201
Test name
Test status
Simulation time 64921430 ps
CPU time 3.22 seconds
Started Jul 23 07:07:19 PM PDT 24
Finished Jul 23 07:07:23 PM PDT 24
Peak memory 232888 kb
Host smart-8260262b-f8cb-422a-9f2c-153901606faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537986264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.3537986264
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.1336891871
Short name T189
Test name
Test status
Simulation time 8399689603 ps
CPU time 35.43 seconds
Started Jul 23 07:07:19 PM PDT 24
Finished Jul 23 07:07:56 PM PDT 24
Peak memory 249304 kb
Host smart-f88f20dd-869c-46e8-af11-5b7e298b536b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336891871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.1336891871
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.3328434171
Short name T987
Test name
Test status
Simulation time 1146563198 ps
CPU time 9.96 seconds
Started Jul 23 07:07:21 PM PDT 24
Finished Jul 23 07:07:32 PM PDT 24
Peak memory 224656 kb
Host smart-d91f9a3c-caf1-4181-839b-c00d0e2bda16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328434171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.3328434171
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.2021142755
Short name T212
Test name
Test status
Simulation time 2207886061 ps
CPU time 3.19 seconds
Started Jul 23 07:07:19 PM PDT 24
Finished Jul 23 07:07:23 PM PDT 24
Peak memory 232972 kb
Host smart-90088108-315a-4bb2-9b4e-6ee4643adb72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021142755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.2021142755
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.512069908
Short name T55
Test name
Test status
Simulation time 540069337 ps
CPU time 6.99 seconds
Started Jul 23 07:07:20 PM PDT 24
Finished Jul 23 07:07:28 PM PDT 24
Peak memory 219976 kb
Host smart-4c7a63ff-3b8c-475d-bff1-a12e27c5eec5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=512069908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dire
ct.512069908
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.829619112
Short name T143
Test name
Test status
Simulation time 162220821 ps
CPU time 1.18 seconds
Started Jul 23 07:07:18 PM PDT 24
Finished Jul 23 07:07:20 PM PDT 24
Peak memory 207312 kb
Host smart-11355ca1-e07b-402f-a34c-f3fe7e05d0a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829619112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stres
s_all.829619112
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.87362600
Short name T686
Test name
Test status
Simulation time 5831919684 ps
CPU time 28.04 seconds
Started Jul 23 07:07:22 PM PDT 24
Finished Jul 23 07:07:51 PM PDT 24
Peak memory 216476 kb
Host smart-39bb7ea9-71ac-46fa-b458-d15d74c004a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87362600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.87362600
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.2048786051
Short name T399
Test name
Test status
Simulation time 1040104717 ps
CPU time 7.09 seconds
Started Jul 23 07:07:19 PM PDT 24
Finished Jul 23 07:07:27 PM PDT 24
Peak memory 216356 kb
Host smart-1d74a4fe-eee4-4959-b4a2-6ca6e02ff7a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048786051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.2048786051
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.2105694437
Short name T740
Test name
Test status
Simulation time 91747404 ps
CPU time 1.12 seconds
Started Jul 23 07:07:21 PM PDT 24
Finished Jul 23 07:07:23 PM PDT 24
Peak memory 207988 kb
Host smart-968170e6-3783-4f1b-92f3-ec50521af5fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105694437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.2105694437
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.3870819487
Short name T297
Test name
Test status
Simulation time 41790351 ps
CPU time 0.71 seconds
Started Jul 23 07:07:20 PM PDT 24
Finished Jul 23 07:07:22 PM PDT 24
Peak memory 205752 kb
Host smart-194c9254-b877-4654-867e-b0f9494230ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870819487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.3870819487
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.3188471961
Short name T744
Test name
Test status
Simulation time 10890018069 ps
CPU time 12.27 seconds
Started Jul 23 07:07:22 PM PDT 24
Finished Jul 23 07:07:35 PM PDT 24
Peak memory 224712 kb
Host smart-d6fbb0c6-05bb-4643-a37e-936d549258a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188471961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.3188471961
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.1226631093
Short name T116
Test name
Test status
Simulation time 10754293 ps
CPU time 0.71 seconds
Started Jul 23 07:05:15 PM PDT 24
Finished Jul 23 07:05:19 PM PDT 24
Peak memory 205872 kb
Host smart-bca7cf68-ef34-4f57-aaf7-cad461a7a169
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226631093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.1
226631093
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.1199171345
Short name T589
Test name
Test status
Simulation time 445222219 ps
CPU time 4.22 seconds
Started Jul 23 07:05:15 PM PDT 24
Finished Jul 23 07:05:22 PM PDT 24
Peak memory 232880 kb
Host smart-9c871218-27f9-4e28-83e2-0f0d66e781a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199171345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.1199171345
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.2171693725
Short name T300
Test name
Test status
Simulation time 74722051 ps
CPU time 0.77 seconds
Started Jul 23 07:05:16 PM PDT 24
Finished Jul 23 07:05:20 PM PDT 24
Peak memory 207052 kb
Host smart-fcde91ad-68e0-4bfd-8e92-714a0fd0a124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171693725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.2171693725
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.1783458882
Short name T260
Test name
Test status
Simulation time 15375190179 ps
CPU time 101.72 seconds
Started Jul 23 07:05:15 PM PDT 24
Finished Jul 23 07:06:59 PM PDT 24
Peak memory 284052 kb
Host smart-65ff43d9-eedc-41cd-b5c7-46cb89b6edd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783458882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.1783458882
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.1299006468
Short name T290
Test name
Test status
Simulation time 9670759401 ps
CPU time 46.51 seconds
Started Jul 23 07:05:12 PM PDT 24
Finished Jul 23 07:05:59 PM PDT 24
Peak memory 238224 kb
Host smart-071d484a-e342-4698-b585-18f096d34733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299006468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.1299006468
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.1635438916
Short name T149
Test name
Test status
Simulation time 1917543376 ps
CPU time 27.55 seconds
Started Jul 23 07:05:15 PM PDT 24
Finished Jul 23 07:05:45 PM PDT 24
Peak memory 241048 kb
Host smart-93c352fb-ce17-442f-b33e-048cafc8f34b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635438916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.1635438916
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.2762529083
Short name T84
Test name
Test status
Simulation time 834533851 ps
CPU time 9.03 seconds
Started Jul 23 07:05:13 PM PDT 24
Finished Jul 23 07:05:23 PM PDT 24
Peak memory 235644 kb
Host smart-df78ac06-5991-4e37-ba28-6112653cf04f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762529083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.2762529083
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.1699896389
Short name T175
Test name
Test status
Simulation time 57008594939 ps
CPU time 201.57 seconds
Started Jul 23 07:05:18 PM PDT 24
Finished Jul 23 07:08:43 PM PDT 24
Peak memory 250580 kb
Host smart-bccbade9-1709-41a6-988d-49d4ca6835a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699896389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds
.1699896389
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_intercept.2557966723
Short name T478
Test name
Test status
Simulation time 18547433547 ps
CPU time 33.26 seconds
Started Jul 23 07:05:16 PM PDT 24
Finished Jul 23 07:05:52 PM PDT 24
Peak memory 224612 kb
Host smart-a0d64c35-5a1e-4ffb-ac33-1f32ea4e73bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557966723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.2557966723
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.1183991813
Short name T534
Test name
Test status
Simulation time 1255602834 ps
CPU time 6.27 seconds
Started Jul 23 07:05:15 PM PDT 24
Finished Jul 23 07:05:24 PM PDT 24
Peak memory 224708 kb
Host smart-bf01467b-8f28-42cc-b085-79f99fa292d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183991813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.1183991813
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.4123088763
Short name T586
Test name
Test status
Simulation time 737393751 ps
CPU time 4.52 seconds
Started Jul 23 07:05:13 PM PDT 24
Finished Jul 23 07:05:18 PM PDT 24
Peak memory 232848 kb
Host smart-0db95f19-5a3b-4881-9fb9-63e5ce4fab7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123088763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.4123088763
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.2091302213
Short name T214
Test name
Test status
Simulation time 670476042 ps
CPU time 2.96 seconds
Started Jul 23 07:05:15 PM PDT 24
Finished Jul 23 07:05:20 PM PDT 24
Peak memory 232924 kb
Host smart-5ab1f7cd-4832-4e39-8fb3-ec143514fbbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091302213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.2091302213
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.1136537953
Short name T798
Test name
Test status
Simulation time 752122745 ps
CPU time 8.92 seconds
Started Jul 23 07:05:14 PM PDT 24
Finished Jul 23 07:05:26 PM PDT 24
Peak memory 222832 kb
Host smart-8d0df6c2-f33a-46fe-b711-320182909e56
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1136537953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.1136537953
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.726744882
Short name T64
Test name
Test status
Simulation time 65854104 ps
CPU time 0.98 seconds
Started Jul 23 07:05:15 PM PDT 24
Finished Jul 23 07:05:19 PM PDT 24
Peak memory 236388 kb
Host smart-a6f8eebe-4966-424f-9b7c-629720f8346f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726744882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.726744882
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.1730917751
Short name T1002
Test name
Test status
Simulation time 100220968 ps
CPU time 1 seconds
Started Jul 23 07:05:14 PM PDT 24
Finished Jul 23 07:05:18 PM PDT 24
Peak memory 207156 kb
Host smart-9d6008a0-190f-4fa6-98d3-90c8c02f1d83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730917751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.1730917751
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.2702538038
Short name T832
Test name
Test status
Simulation time 5879655733 ps
CPU time 16 seconds
Started Jul 23 07:05:14 PM PDT 24
Finished Jul 23 07:05:31 PM PDT 24
Peak memory 216424 kb
Host smart-125c1b29-e113-4e0b-9f33-010832d94fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702538038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.2702538038
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.1379287496
Short name T924
Test name
Test status
Simulation time 750803175 ps
CPU time 4.92 seconds
Started Jul 23 07:05:17 PM PDT 24
Finished Jul 23 07:05:25 PM PDT 24
Peak memory 216380 kb
Host smart-53bbf0c2-cac3-4209-aad9-aab6949519d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379287496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.1379287496
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.1021353591
Short name T285
Test name
Test status
Simulation time 39611119 ps
CPU time 0.98 seconds
Started Jul 23 07:05:13 PM PDT 24
Finished Jul 23 07:05:15 PM PDT 24
Peak memory 207472 kb
Host smart-7e679f37-7961-48f8-87af-a156db394e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021353591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.1021353591
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.999203125
Short name T516
Test name
Test status
Simulation time 280605560 ps
CPU time 0.95 seconds
Started Jul 23 07:05:14 PM PDT 24
Finished Jul 23 07:05:16 PM PDT 24
Peak memory 206604 kb
Host smart-8b906a51-ac15-403f-a94d-22508e953d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999203125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.999203125
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.2824415619
Short name T1005
Test name
Test status
Simulation time 236993464 ps
CPU time 2.82 seconds
Started Jul 23 07:05:17 PM PDT 24
Finished Jul 23 07:05:23 PM PDT 24
Peak memory 232788 kb
Host smart-a8cb5216-56aa-479f-b0d8-c2fbc6b7d452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824415619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.2824415619
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.341342161
Short name T395
Test name
Test status
Simulation time 21335362 ps
CPU time 0.73 seconds
Started Jul 23 07:07:24 PM PDT 24
Finished Jul 23 07:07:26 PM PDT 24
Peak memory 206012 kb
Host smart-bb526e47-5b19-4fa0-bf11-dbe50390915f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341342161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.341342161
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.2805879235
Short name T714
Test name
Test status
Simulation time 366632431 ps
CPU time 2.44 seconds
Started Jul 23 07:07:23 PM PDT 24
Finished Jul 23 07:07:26 PM PDT 24
Peak memory 224708 kb
Host smart-6ee79af2-cdc4-40aa-a9a9-e3479d0f7e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805879235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.2805879235
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.526946902
Short name T306
Test name
Test status
Simulation time 14023035 ps
CPU time 0.77 seconds
Started Jul 23 07:07:19 PM PDT 24
Finished Jul 23 07:07:21 PM PDT 24
Peak memory 206536 kb
Host smart-cc8e6a46-6d8a-493f-8c3b-e52b38a7835a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526946902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.526946902
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.775990654
Short name T840
Test name
Test status
Simulation time 6323929759 ps
CPU time 63.89 seconds
Started Jul 23 07:07:25 PM PDT 24
Finished Jul 23 07:08:31 PM PDT 24
Peak memory 251196 kb
Host smart-519cab17-3df7-4615-9c4f-50a7fec056dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775990654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.775990654
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.366564237
Short name T464
Test name
Test status
Simulation time 26387306172 ps
CPU time 69.45 seconds
Started Jul 23 07:07:24 PM PDT 24
Finished Jul 23 07:08:35 PM PDT 24
Peak memory 240308 kb
Host smart-3a419299-e23c-4d71-89b3-93bc73ab5aa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366564237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.366564237
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.724652178
Short name T220
Test name
Test status
Simulation time 15313299763 ps
CPU time 58.23 seconds
Started Jul 23 07:07:26 PM PDT 24
Finished Jul 23 07:08:26 PM PDT 24
Peak memory 224800 kb
Host smart-c139c4e6-75c1-47d7-b045-38adcf8f8998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724652178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idle
.724652178
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.2761461294
Short name T941
Test name
Test status
Simulation time 19859038 ps
CPU time 0.73 seconds
Started Jul 23 07:07:23 PM PDT 24
Finished Jul 23 07:07:26 PM PDT 24
Peak memory 215928 kb
Host smart-afaa0010-b64f-4710-948a-f23ee8617ccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761461294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmd
s.2761461294
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/30.spi_device_intercept.1593983378
Short name T411
Test name
Test status
Simulation time 1141351305 ps
CPU time 7.53 seconds
Started Jul 23 07:07:25 PM PDT 24
Finished Jul 23 07:07:34 PM PDT 24
Peak memory 232972 kb
Host smart-d5a3efc7-a694-49d8-84b6-a94187b8a0b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593983378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.1593983378
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.3441666768
Short name T178
Test name
Test status
Simulation time 6540031905 ps
CPU time 14.48 seconds
Started Jul 23 07:07:25 PM PDT 24
Finished Jul 23 07:07:42 PM PDT 24
Peak memory 232940 kb
Host smart-49d322f8-729e-45ee-890c-364f4cef648b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441666768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.3441666768
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.2929437447
Short name T665
Test name
Test status
Simulation time 698664824 ps
CPU time 3.44 seconds
Started Jul 23 07:07:20 PM PDT 24
Finished Jul 23 07:07:24 PM PDT 24
Peak memory 224676 kb
Host smart-ecc0c047-521f-42ed-9131-3e5a736c043e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929437447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.2929437447
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.3179238792
Short name T874
Test name
Test status
Simulation time 362544170 ps
CPU time 6.92 seconds
Started Jul 23 07:07:21 PM PDT 24
Finished Jul 23 07:07:29 PM PDT 24
Peak memory 224688 kb
Host smart-0e78da45-376c-4b22-9b06-2cc50f2bad60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179238792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.3179238792
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.1757991101
Short name T857
Test name
Test status
Simulation time 408377422 ps
CPU time 5.66 seconds
Started Jul 23 07:07:22 PM PDT 24
Finished Jul 23 07:07:29 PM PDT 24
Peak memory 223348 kb
Host smart-6df03d5e-5ae6-4e79-b3a9-b3385b8b6175
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1757991101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.1757991101
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.1111513933
Short name T355
Test name
Test status
Simulation time 45773365 ps
CPU time 0.94 seconds
Started Jul 23 07:07:24 PM PDT 24
Finished Jul 23 07:07:27 PM PDT 24
Peak memory 207652 kb
Host smart-959fe92f-b8c6-4df4-8b58-6c808622d335
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111513933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.1111513933
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.202765305
Short name T850
Test name
Test status
Simulation time 12662525445 ps
CPU time 30.5 seconds
Started Jul 23 07:07:19 PM PDT 24
Finished Jul 23 07:07:50 PM PDT 24
Peak memory 216472 kb
Host smart-89924eb1-5220-4444-96e1-e38908bc573c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202765305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.202765305
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.539896370
Short name T333
Test name
Test status
Simulation time 945151223 ps
CPU time 4.82 seconds
Started Jul 23 07:07:21 PM PDT 24
Finished Jul 23 07:07:27 PM PDT 24
Peak memory 216460 kb
Host smart-36c4d23e-7570-43e2-bc27-bfaec34bd394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539896370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.539896370
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.717921259
Short name T529
Test name
Test status
Simulation time 131945309 ps
CPU time 1.57 seconds
Started Jul 23 07:07:18 PM PDT 24
Finished Jul 23 07:07:21 PM PDT 24
Peak memory 216464 kb
Host smart-8f801c20-cd05-4c1d-bc34-5000ce6b3d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717921259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.717921259
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.2244316746
Short name T678
Test name
Test status
Simulation time 223774595 ps
CPU time 0.85 seconds
Started Jul 23 07:07:20 PM PDT 24
Finished Jul 23 07:07:22 PM PDT 24
Peak memory 207132 kb
Host smart-fcfee91b-ddc5-48c8-ac3c-ad3384bdf14d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244316746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.2244316746
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.1137214910
Short name T736
Test name
Test status
Simulation time 478466377 ps
CPU time 5.59 seconds
Started Jul 23 07:07:24 PM PDT 24
Finished Jul 23 07:07:32 PM PDT 24
Peak memory 232932 kb
Host smart-c7ba5fd7-62d8-4b3c-a571-fb06e384a941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137214910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.1137214910
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.1653287353
Short name T842
Test name
Test status
Simulation time 14268216 ps
CPU time 0.73 seconds
Started Jul 23 07:07:32 PM PDT 24
Finished Jul 23 07:07:34 PM PDT 24
Peak memory 205624 kb
Host smart-71946c30-ded5-4fde-9b83-f14fa6171790
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653287353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
1653287353
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.1230360772
Short name T812
Test name
Test status
Simulation time 984738803 ps
CPU time 7.08 seconds
Started Jul 23 07:07:25 PM PDT 24
Finished Jul 23 07:07:34 PM PDT 24
Peak memory 232812 kb
Host smart-cec9533b-1c14-449f-bad1-5f079bde5f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230360772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.1230360772
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.4010141517
Short name T365
Test name
Test status
Simulation time 16859282 ps
CPU time 0.74 seconds
Started Jul 23 07:07:23 PM PDT 24
Finished Jul 23 07:07:25 PM PDT 24
Peak memory 205712 kb
Host smart-1bc7ba25-82d6-4acc-b614-643d7090a3ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010141517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.4010141517
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.3443348499
Short name T166
Test name
Test status
Simulation time 13276112002 ps
CPU time 50.31 seconds
Started Jul 23 07:07:31 PM PDT 24
Finished Jul 23 07:08:23 PM PDT 24
Peak memory 241148 kb
Host smart-61dfd59e-3c5f-4055-8699-e67c030a0098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443348499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.3443348499
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.1547394280
Short name T114
Test name
Test status
Simulation time 6983637073 ps
CPU time 51.12 seconds
Started Jul 23 07:07:30 PM PDT 24
Finished Jul 23 07:08:23 PM PDT 24
Peak memory 241400 kb
Host smart-1538ed2b-6c21-4b80-94b2-5d9183af0734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547394280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.1547394280
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.1518232002
Short name T983
Test name
Test status
Simulation time 69553813112 ps
CPU time 137.31 seconds
Started Jul 23 07:07:34 PM PDT 24
Finished Jul 23 07:09:52 PM PDT 24
Peak memory 253104 kb
Host smart-5d723294-0a7d-4e9e-adef-c35e32d11c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518232002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.1518232002
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.3699973966
Short name T729
Test name
Test status
Simulation time 427506589 ps
CPU time 5.35 seconds
Started Jul 23 07:07:27 PM PDT 24
Finished Jul 23 07:07:34 PM PDT 24
Peak memory 232928 kb
Host smart-f0a511ce-dc2a-49a1-86c2-e35cd0e6a2c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699973966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.3699973966
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.2562296147
Short name T795
Test name
Test status
Simulation time 12487923909 ps
CPU time 99.86 seconds
Started Jul 23 07:07:23 PM PDT 24
Finished Jul 23 07:09:04 PM PDT 24
Peak memory 266260 kb
Host smart-474fdce8-b323-4086-9817-f057ee3d9568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562296147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmd
s.2562296147
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/31.spi_device_intercept.2438221839
Short name T196
Test name
Test status
Simulation time 137395998 ps
CPU time 3.06 seconds
Started Jul 23 07:07:26 PM PDT 24
Finished Jul 23 07:07:31 PM PDT 24
Peak memory 232944 kb
Host smart-66274405-e49f-44c1-931b-00e6b5b2f899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438221839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.2438221839
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.859738796
Short name T223
Test name
Test status
Simulation time 870927633 ps
CPU time 19.83 seconds
Started Jul 23 07:07:24 PM PDT 24
Finished Jul 23 07:07:46 PM PDT 24
Peak memory 236388 kb
Host smart-33f72d78-704a-457a-8b1b-9f291cfcbba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859738796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.859738796
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.662044479
Short name T263
Test name
Test status
Simulation time 3783569745 ps
CPU time 13.2 seconds
Started Jul 23 07:07:25 PM PDT 24
Finished Jul 23 07:07:40 PM PDT 24
Peak memory 233192 kb
Host smart-6588f968-31b0-4dd8-be22-e558ddd5fb9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662044479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swap
.662044479
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.3739506698
Short name T184
Test name
Test status
Simulation time 5951098308 ps
CPU time 14.63 seconds
Started Jul 23 07:07:24 PM PDT 24
Finished Jul 23 07:07:40 PM PDT 24
Peak memory 232888 kb
Host smart-95f97868-aa33-42b1-ba5d-208e023af626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739506698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.3739506698
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.1932875428
Short name T526
Test name
Test status
Simulation time 544740327 ps
CPU time 3.91 seconds
Started Jul 23 07:07:28 PM PDT 24
Finished Jul 23 07:07:33 PM PDT 24
Peak memory 220372 kb
Host smart-170cab4d-d030-42aa-855a-349887c4b59b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1932875428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.1932875428
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.2858608784
Short name T990
Test name
Test status
Simulation time 130405144 ps
CPU time 1.02 seconds
Started Jul 23 07:07:31 PM PDT 24
Finished Jul 23 07:07:34 PM PDT 24
Peak memory 207724 kb
Host smart-f3bd6d06-2cf2-4787-8f1d-3667eedf346b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858608784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.2858608784
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.2379444668
Short name T652
Test name
Test status
Simulation time 10186550441 ps
CPU time 30.32 seconds
Started Jul 23 07:07:27 PM PDT 24
Finished Jul 23 07:07:59 PM PDT 24
Peak memory 216460 kb
Host smart-aa526e2e-1725-4fb1-9d17-9147a3133215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379444668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.2379444668
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.791583740
Short name T377
Test name
Test status
Simulation time 20543286 ps
CPU time 0.72 seconds
Started Jul 23 07:07:27 PM PDT 24
Finished Jul 23 07:07:29 PM PDT 24
Peak memory 205880 kb
Host smart-8fea3546-d42c-4b5e-b045-5b5b86866e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791583740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.791583740
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.1628332012
Short name T10
Test name
Test status
Simulation time 15822023 ps
CPU time 0.69 seconds
Started Jul 23 07:07:24 PM PDT 24
Finished Jul 23 07:07:26 PM PDT 24
Peak memory 205776 kb
Host smart-a8600ba3-33cd-407f-a377-882d5708ff17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628332012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.1628332012
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.1462854225
Short name T691
Test name
Test status
Simulation time 115726565 ps
CPU time 0.88 seconds
Started Jul 23 07:07:28 PM PDT 24
Finished Jul 23 07:07:30 PM PDT 24
Peak memory 206116 kb
Host smart-81d5d3b1-eb94-41ea-b97e-1920420ca39c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462854225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.1462854225
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.1586542334
Short name T637
Test name
Test status
Simulation time 644927779 ps
CPU time 3.92 seconds
Started Jul 23 07:07:24 PM PDT 24
Finished Jul 23 07:07:30 PM PDT 24
Peak memory 224688 kb
Host smart-841e26a7-9cd6-4362-8d32-71a3a5c5d6cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586542334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.1586542334
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.2963388159
Short name T831
Test name
Test status
Simulation time 45275854 ps
CPU time 0.73 seconds
Started Jul 23 07:07:29 PM PDT 24
Finished Jul 23 07:07:31 PM PDT 24
Peak memory 205464 kb
Host smart-0edc3002-1aba-4605-8835-007e16aba364
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963388159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
2963388159
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.74348468
Short name T929
Test name
Test status
Simulation time 253379938 ps
CPU time 2.89 seconds
Started Jul 23 07:07:29 PM PDT 24
Finished Jul 23 07:07:34 PM PDT 24
Peak memory 232912 kb
Host smart-58fef871-bc0d-40a3-a9e5-adaace524d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74348468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.74348468
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.559218700
Short name T746
Test name
Test status
Simulation time 64889171 ps
CPU time 0.79 seconds
Started Jul 23 07:07:32 PM PDT 24
Finished Jul 23 07:07:34 PM PDT 24
Peak memory 207068 kb
Host smart-c9b9669a-4199-4379-8099-b524012e974f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559218700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.559218700
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.961141128
Short name T679
Test name
Test status
Simulation time 36428556381 ps
CPU time 116.96 seconds
Started Jul 23 07:07:31 PM PDT 24
Finished Jul 23 07:09:30 PM PDT 24
Peak memory 256244 kb
Host smart-f4ef4b67-8bf5-4c31-a38b-6be368d3f65a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961141128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.961141128
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.1566156253
Short name T463
Test name
Test status
Simulation time 6469082533 ps
CPU time 27.63 seconds
Started Jul 23 07:07:30 PM PDT 24
Finished Jul 23 07:07:59 PM PDT 24
Peak memory 217848 kb
Host smart-49c366b1-841b-4808-93f1-8ac5ffde7be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566156253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.1566156253
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.885056690
Short name T119
Test name
Test status
Simulation time 18711277309 ps
CPU time 179.66 seconds
Started Jul 23 07:07:31 PM PDT 24
Finished Jul 23 07:10:32 PM PDT 24
Peak memory 257556 kb
Host smart-d8f6f3a5-555f-4cc9-aa21-c46edcd93eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885056690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idle
.885056690
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.2717643464
Short name T352
Test name
Test status
Simulation time 76584796 ps
CPU time 2.47 seconds
Started Jul 23 07:07:29 PM PDT 24
Finished Jul 23 07:07:32 PM PDT 24
Peak memory 224720 kb
Host smart-4d8e8493-8ee6-40a0-b625-5e954abdaf02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717643464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.2717643464
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.1950748433
Short name T868
Test name
Test status
Simulation time 8253122691 ps
CPU time 60.89 seconds
Started Jul 23 07:07:32 PM PDT 24
Finished Jul 23 07:08:34 PM PDT 24
Peak memory 237004 kb
Host smart-fe885282-0372-412a-816b-ad7b8f57b17d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950748433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmd
s.1950748433
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_intercept.3417341935
Short name T207
Test name
Test status
Simulation time 1757262069 ps
CPU time 16.25 seconds
Started Jul 23 07:07:30 PM PDT 24
Finished Jul 23 07:07:47 PM PDT 24
Peak memory 232840 kb
Host smart-c8f259e6-8a37-45ce-bb0f-9784f49f1b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417341935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.3417341935
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.1303122833
Short name T224
Test name
Test status
Simulation time 1581564040 ps
CPU time 7.47 seconds
Started Jul 23 07:07:33 PM PDT 24
Finished Jul 23 07:07:41 PM PDT 24
Peak memory 232884 kb
Host smart-358a6bbd-fa9d-46fc-8743-19c5c72b3a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303122833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.1303122833
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.1399758718
Short name T948
Test name
Test status
Simulation time 776847206 ps
CPU time 7.91 seconds
Started Jul 23 07:07:32 PM PDT 24
Finished Jul 23 07:07:41 PM PDT 24
Peak memory 232860 kb
Host smart-5d1d7c32-59fc-4cbd-843a-30f0bd30a621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399758718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.1399758718
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.2997102490
Short name T383
Test name
Test status
Simulation time 1029558944 ps
CPU time 5.18 seconds
Started Jul 23 07:07:30 PM PDT 24
Finished Jul 23 07:07:37 PM PDT 24
Peak memory 232856 kb
Host smart-8e2e0d7d-9c48-4583-aa01-cc50e594f6a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997102490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.2997102490
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.52826803
Short name T757
Test name
Test status
Simulation time 512595554 ps
CPU time 4.81 seconds
Started Jul 23 07:07:32 PM PDT 24
Finished Jul 23 07:07:38 PM PDT 24
Peak memory 219660 kb
Host smart-e2bd3589-97e9-4f68-be11-7af150c5ab77
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=52826803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_direc
t.52826803
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.3581795700
Short name T519
Test name
Test status
Simulation time 46174677 ps
CPU time 1 seconds
Started Jul 23 07:07:30 PM PDT 24
Finished Jul 23 07:07:32 PM PDT 24
Peak memory 207944 kb
Host smart-5426b690-e760-4474-878a-5172b4642ee2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581795700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.3581795700
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.3089940525
Short name T885
Test name
Test status
Simulation time 5190815398 ps
CPU time 10.89 seconds
Started Jul 23 07:07:30 PM PDT 24
Finished Jul 23 07:07:42 PM PDT 24
Peak memory 216460 kb
Host smart-535f9d48-3c04-4ef2-b5f2-01766c493fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089940525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.3089940525
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.174211740
Short name T855
Test name
Test status
Simulation time 607711274 ps
CPU time 1.3 seconds
Started Jul 23 07:07:30 PM PDT 24
Finished Jul 23 07:07:33 PM PDT 24
Peak memory 207156 kb
Host smart-c55045cc-5835-4e89-ac1d-3c02755bde32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174211740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.174211740
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.2185423359
Short name T46
Test name
Test status
Simulation time 104624163 ps
CPU time 1.53 seconds
Started Jul 23 07:07:29 PM PDT 24
Finished Jul 23 07:07:32 PM PDT 24
Peak memory 216412 kb
Host smart-c1155f1b-eb8c-438d-9d38-d09cb5ad95ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185423359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.2185423359
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.2777207577
Short name T784
Test name
Test status
Simulation time 58805700 ps
CPU time 0.79 seconds
Started Jul 23 07:07:29 PM PDT 24
Finished Jul 23 07:07:31 PM PDT 24
Peak memory 206072 kb
Host smart-e4837bcb-4ee7-46c6-83a9-eeef3c1747bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777207577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.2777207577
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.158710521
Short name T524
Test name
Test status
Simulation time 292175763 ps
CPU time 4.27 seconds
Started Jul 23 07:07:30 PM PDT 24
Finished Jul 23 07:07:36 PM PDT 24
Peak memory 232848 kb
Host smart-8713be0b-1f20-44de-b7fd-f9b7fcb40ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158710521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.158710521
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.3397541450
Short name T561
Test name
Test status
Simulation time 11062762 ps
CPU time 0.7 seconds
Started Jul 23 07:07:39 PM PDT 24
Finished Jul 23 07:07:41 PM PDT 24
Peak memory 205588 kb
Host smart-9ca01e80-3625-460a-81ab-2189ade87098
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397541450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
3397541450
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.1754275960
Short name T834
Test name
Test status
Simulation time 85003166 ps
CPU time 2.89 seconds
Started Jul 23 07:07:40 PM PDT 24
Finished Jul 23 07:07:44 PM PDT 24
Peak memory 232820 kb
Host smart-b1ab45bb-4471-43b0-a678-3a2cd3e09abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754275960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.1754275960
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.1872399957
Short name T456
Test name
Test status
Simulation time 82646397 ps
CPU time 0.76 seconds
Started Jul 23 07:07:32 PM PDT 24
Finished Jul 23 07:07:34 PM PDT 24
Peak memory 205672 kb
Host smart-7972f9cb-d436-4bc0-98b3-418ad1fc4212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872399957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.1872399957
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.4159713074
Short name T805
Test name
Test status
Simulation time 9232955075 ps
CPU time 65.45 seconds
Started Jul 23 07:07:38 PM PDT 24
Finished Jul 23 07:08:44 PM PDT 24
Peak memory 255176 kb
Host smart-648c8423-75c1-4807-af0b-9ed6dff5d069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159713074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.4159713074
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.1108453763
Short name T923
Test name
Test status
Simulation time 14568756260 ps
CPU time 66.64 seconds
Started Jul 23 07:07:38 PM PDT 24
Finished Jul 23 07:08:45 PM PDT 24
Peak memory 240824 kb
Host smart-e6158f72-7fb6-4222-9501-82e40bef2781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108453763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.1108453763
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.2846977344
Short name T259
Test name
Test status
Simulation time 7940024972 ps
CPU time 126.62 seconds
Started Jul 23 07:07:38 PM PDT 24
Finished Jul 23 07:09:46 PM PDT 24
Peak memory 253404 kb
Host smart-b7e327dd-26f6-40dc-a969-f98f54a4e131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846977344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.2846977344
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.2131482074
Short name T863
Test name
Test status
Simulation time 6524460325 ps
CPU time 9.7 seconds
Started Jul 23 07:07:37 PM PDT 24
Finished Jul 23 07:07:48 PM PDT 24
Peak memory 232964 kb
Host smart-e15f0d84-d637-4162-a046-88236fc01b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131482074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.2131482074
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.2428241399
Short name T578
Test name
Test status
Simulation time 29380790231 ps
CPU time 64.97 seconds
Started Jul 23 07:07:39 PM PDT 24
Finished Jul 23 07:08:46 PM PDT 24
Peak memory 252592 kb
Host smart-8a7dd5d5-a42d-48e9-a60b-ef28300a7bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428241399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmd
s.2428241399
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_intercept.1348123923
Short name T779
Test name
Test status
Simulation time 474608678 ps
CPU time 7.24 seconds
Started Jul 23 07:07:38 PM PDT 24
Finished Jul 23 07:07:47 PM PDT 24
Peak memory 232904 kb
Host smart-f65d2b2d-a301-49c9-8919-3d07e64ed68d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348123923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.1348123923
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.1281502803
Short name T728
Test name
Test status
Simulation time 7997200846 ps
CPU time 28.8 seconds
Started Jul 23 07:07:40 PM PDT 24
Finished Jul 23 07:08:10 PM PDT 24
Peak memory 232956 kb
Host smart-54277cbd-dc2b-4770-a11e-29db01dee9ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281502803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.1281502803
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.164452638
Short name T243
Test name
Test status
Simulation time 1778638704 ps
CPU time 7.68 seconds
Started Jul 23 07:07:36 PM PDT 24
Finished Jul 23 07:07:44 PM PDT 24
Peak memory 224664 kb
Host smart-fa8a15d3-e800-49e0-aede-683db3a59c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164452638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swap
.164452638
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.3086921523
Short name T824
Test name
Test status
Simulation time 3935667860 ps
CPU time 4.39 seconds
Started Jul 23 07:07:39 PM PDT 24
Finished Jul 23 07:07:45 PM PDT 24
Peak memory 232904 kb
Host smart-24b7de17-f184-40c3-8087-ab172585781a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086921523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.3086921523
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.261880143
Short name T436
Test name
Test status
Simulation time 557882100 ps
CPU time 4.45 seconds
Started Jul 23 07:07:40 PM PDT 24
Finished Jul 23 07:07:46 PM PDT 24
Peak memory 223328 kb
Host smart-8fb42d71-edaf-42c8-a729-fcfc789cbfaf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=261880143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dire
ct.261880143
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.2796752095
Short name T559
Test name
Test status
Simulation time 58162892 ps
CPU time 1.07 seconds
Started Jul 23 07:07:36 PM PDT 24
Finished Jul 23 07:07:38 PM PDT 24
Peak memory 207120 kb
Host smart-f880beee-7c49-4c53-8854-cd60158863ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796752095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.2796752095
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.1732693190
Short name T351
Test name
Test status
Simulation time 76848825 ps
CPU time 0.77 seconds
Started Jul 23 07:07:39 PM PDT 24
Finished Jul 23 07:07:41 PM PDT 24
Peak memory 206048 kb
Host smart-547a29ad-24bf-4983-846e-4b494a50d4f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732693190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.1732693190
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.3969992141
Short name T563
Test name
Test status
Simulation time 2871678657 ps
CPU time 5.23 seconds
Started Jul 23 07:07:41 PM PDT 24
Finished Jul 23 07:07:47 PM PDT 24
Peak memory 216468 kb
Host smart-4230a9e1-dd9c-42a9-9565-147c30231864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969992141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.3969992141
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.1912773520
Short name T803
Test name
Test status
Simulation time 48725544 ps
CPU time 1.23 seconds
Started Jul 23 07:07:39 PM PDT 24
Finished Jul 23 07:07:41 PM PDT 24
Peak memory 216400 kb
Host smart-b53032df-c1d9-439d-9c29-a9d28cc7f2a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912773520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.1912773520
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.21129457
Short name T955
Test name
Test status
Simulation time 14692795 ps
CPU time 0.71 seconds
Started Jul 23 07:07:38 PM PDT 24
Finished Jul 23 07:07:40 PM PDT 24
Peak memory 206068 kb
Host smart-8ef73bee-95ab-4975-854d-c1728d7103b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21129457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.21129457
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.2240723302
Short name T26
Test name
Test status
Simulation time 15872974004 ps
CPU time 14.91 seconds
Started Jul 23 07:07:39 PM PDT 24
Finished Jul 23 07:07:56 PM PDT 24
Peak memory 224696 kb
Host smart-48c484ef-e862-4fb7-a8d6-c462f670bffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240723302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.2240723302
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.101588897
Short name T829
Test name
Test status
Simulation time 39826529 ps
CPU time 0.73 seconds
Started Jul 23 07:07:44 PM PDT 24
Finished Jul 23 07:07:46 PM PDT 24
Peak memory 205032 kb
Host smart-346447e9-5395-4d60-b4d4-a6ff7a713224
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101588897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.101588897
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.594443
Short name T993
Test name
Test status
Simulation time 2051281273 ps
CPU time 3.95 seconds
Started Jul 23 07:07:40 PM PDT 24
Finished Jul 23 07:07:45 PM PDT 24
Peak memory 232880 kb
Host smart-78af224e-72c3-4522-b12a-79951b81dbd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.594443
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.3510011594
Short name T821
Test name
Test status
Simulation time 28238752 ps
CPU time 0.74 seconds
Started Jul 23 07:07:41 PM PDT 24
Finished Jul 23 07:07:42 PM PDT 24
Peak memory 206728 kb
Host smart-4a358039-ca90-47d0-b293-aa571d3dcc41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510011594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.3510011594
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.1019734554
Short name T594
Test name
Test status
Simulation time 30567993627 ps
CPU time 82.78 seconds
Started Jul 23 07:07:42 PM PDT 24
Finished Jul 23 07:09:05 PM PDT 24
Peak memory 265756 kb
Host smart-06f62f99-c76c-40e4-9dc2-aa523ab7f7ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019734554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.1019734554
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.672264731
Short name T938
Test name
Test status
Simulation time 36427607492 ps
CPU time 356.78 seconds
Started Jul 23 07:07:46 PM PDT 24
Finished Jul 23 07:13:45 PM PDT 24
Peak memory 259976 kb
Host smart-d9675911-a050-4f0c-ba60-3ecaf541b0de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672264731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.672264731
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.2066410797
Short name T967
Test name
Test status
Simulation time 14446955836 ps
CPU time 54.95 seconds
Started Jul 23 07:07:44 PM PDT 24
Finished Jul 23 07:08:41 PM PDT 24
Peak memory 249404 kb
Host smart-aa90febb-01ed-4626-991d-e88d99b97457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066410797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.2066410797
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.2991875205
Short name T272
Test name
Test status
Simulation time 1233706481 ps
CPU time 12.55 seconds
Started Jul 23 07:07:45 PM PDT 24
Finished Jul 23 07:07:59 PM PDT 24
Peak memory 234768 kb
Host smart-e216dd8b-c9ff-43c4-9042-3831c2bdd4d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991875205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.2991875205
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.31956408
Short name T635
Test name
Test status
Simulation time 3657279412 ps
CPU time 11.71 seconds
Started Jul 23 07:07:42 PM PDT 24
Finished Jul 23 07:07:55 PM PDT 24
Peak memory 235508 kb
Host smart-30d9d07a-c836-42a7-b8ef-b2dcdc43a7a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31956408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmds.31956408
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/34.spi_device_intercept.1372056833
Short name T939
Test name
Test status
Simulation time 7285693575 ps
CPU time 21.32 seconds
Started Jul 23 07:07:39 PM PDT 24
Finished Jul 23 07:08:02 PM PDT 24
Peak memory 232944 kb
Host smart-ee8c05d6-c827-4d8f-8442-0597abe47cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372056833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.1372056833
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.1142712194
Short name T339
Test name
Test status
Simulation time 13125175489 ps
CPU time 71.94 seconds
Started Jul 23 07:07:40 PM PDT 24
Finished Jul 23 07:08:53 PM PDT 24
Peak memory 240652 kb
Host smart-9e9506d4-41c8-40a4-8525-88319ec2d92a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142712194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.1142712194
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.1662693961
Short name T781
Test name
Test status
Simulation time 59007379 ps
CPU time 2.69 seconds
Started Jul 23 07:07:40 PM PDT 24
Finished Jul 23 07:07:44 PM PDT 24
Peak memory 232816 kb
Host smart-9862db22-1c86-4620-bd49-1bb6c3dfd44e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662693961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.1662693961
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.1560407985
Short name T50
Test name
Test status
Simulation time 488325131 ps
CPU time 4.09 seconds
Started Jul 23 07:07:39 PM PDT 24
Finished Jul 23 07:07:44 PM PDT 24
Peak memory 219096 kb
Host smart-cc8c5e29-a109-42ea-ab6f-42ea117b6066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560407985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.1560407985
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.2867792921
Short name T642
Test name
Test status
Simulation time 261994735 ps
CPU time 3.19 seconds
Started Jul 23 07:07:42 PM PDT 24
Finished Jul 23 07:07:46 PM PDT 24
Peak memory 223328 kb
Host smart-1a7891cb-fb8a-4558-9efd-ed8f4f9dacf0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2867792921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.2867792921
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.2204034430
Short name T258
Test name
Test status
Simulation time 224701478316 ps
CPU time 505.33 seconds
Started Jul 23 07:07:41 PM PDT 24
Finished Jul 23 07:16:07 PM PDT 24
Peak memory 250080 kb
Host smart-2fb7c844-cc06-4d55-bc7d-19313b9007bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204034430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.2204034430
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.2023330385
Short name T670
Test name
Test status
Simulation time 4270146413 ps
CPU time 8.03 seconds
Started Jul 23 07:07:38 PM PDT 24
Finished Jul 23 07:07:47 PM PDT 24
Peak memory 216520 kb
Host smart-f4467261-10bc-4d57-9c2a-5c3f7c18d928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023330385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.2023330385
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.2021897251
Short name T440
Test name
Test status
Simulation time 4745757385 ps
CPU time 12.14 seconds
Started Jul 23 07:07:39 PM PDT 24
Finished Jul 23 07:07:52 PM PDT 24
Peak memory 216496 kb
Host smart-109a4101-b303-47b3-ab2a-91bdda5195f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021897251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.2021897251
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.323033488
Short name T409
Test name
Test status
Simulation time 449869685 ps
CPU time 2.1 seconds
Started Jul 23 07:07:37 PM PDT 24
Finished Jul 23 07:07:40 PM PDT 24
Peak memory 216532 kb
Host smart-068c1518-1436-4929-8f6f-c9c8422e5024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323033488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.323033488
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.210463931
Short name T980
Test name
Test status
Simulation time 304497044 ps
CPU time 0.82 seconds
Started Jul 23 07:07:38 PM PDT 24
Finished Jul 23 07:07:39 PM PDT 24
Peak memory 206096 kb
Host smart-7684f143-f57e-4f1f-8d9d-e0671323eb95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210463931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.210463931
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.564109822
Short name T558
Test name
Test status
Simulation time 80882517 ps
CPU time 3 seconds
Started Jul 23 07:07:39 PM PDT 24
Finished Jul 23 07:07:43 PM PDT 24
Peak memory 232884 kb
Host smart-e6356d67-253a-41e7-97ab-c7938c834306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564109822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.564109822
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.696778064
Short name T992
Test name
Test status
Simulation time 15283095 ps
CPU time 0.7 seconds
Started Jul 23 07:07:45 PM PDT 24
Finished Jul 23 07:07:48 PM PDT 24
Peak memory 205748 kb
Host smart-f4949cb3-6e45-46b5-a197-e93aaa39b2a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696778064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.696778064
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.3189767356
Short name T770
Test name
Test status
Simulation time 319694380 ps
CPU time 4.85 seconds
Started Jul 23 07:07:44 PM PDT 24
Finished Jul 23 07:07:51 PM PDT 24
Peak memory 224516 kb
Host smart-0bb2ec18-d1bf-42cf-a462-caa1ddb9622f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189767356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.3189767356
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.3738030054
Short name T425
Test name
Test status
Simulation time 65394888 ps
CPU time 0.8 seconds
Started Jul 23 07:07:43 PM PDT 24
Finished Jul 23 07:07:45 PM PDT 24
Peak memory 206756 kb
Host smart-53436abc-25f6-4042-9a8e-8502cb08304d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738030054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.3738030054
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.2304506938
Short name T640
Test name
Test status
Simulation time 61655114511 ps
CPU time 251.51 seconds
Started Jul 23 07:07:48 PM PDT 24
Finished Jul 23 07:12:01 PM PDT 24
Peak memory 257048 kb
Host smart-271ce76d-fbe4-4ff5-8b8d-f1158704b41d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304506938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.2304506938
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.4037665141
Short name T560
Test name
Test status
Simulation time 15412529013 ps
CPU time 111.4 seconds
Started Jul 23 07:07:43 PM PDT 24
Finished Jul 23 07:09:36 PM PDT 24
Peak memory 238716 kb
Host smart-764e3e26-2ed0-46eb-b3f9-618c18681b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037665141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.4037665141
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.3726004921
Short name T976
Test name
Test status
Simulation time 383727577 ps
CPU time 12.85 seconds
Started Jul 23 07:07:43 PM PDT 24
Finished Jul 23 07:07:58 PM PDT 24
Peak memory 232848 kb
Host smart-c260645c-4a08-4aad-8026-5cf87682e48a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726004921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.3726004921
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.3408932948
Short name T581
Test name
Test status
Simulation time 26926181962 ps
CPU time 68.27 seconds
Started Jul 23 07:07:44 PM PDT 24
Finished Jul 23 07:08:54 PM PDT 24
Peak memory 240508 kb
Host smart-b2b2700a-57da-4b8b-bb8d-6e709938b661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408932948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmd
s.3408932948
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_intercept.3516639251
Short name T424
Test name
Test status
Simulation time 6411804557 ps
CPU time 13.22 seconds
Started Jul 23 07:07:45 PM PDT 24
Finished Jul 23 07:08:00 PM PDT 24
Peak memory 232860 kb
Host smart-4368e5d8-b0de-4076-ac7e-e1429132de6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516639251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.3516639251
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.775220093
Short name T692
Test name
Test status
Simulation time 5633625593 ps
CPU time 14.98 seconds
Started Jul 23 07:07:43 PM PDT 24
Finished Jul 23 07:07:59 PM PDT 24
Peak memory 224760 kb
Host smart-f54db710-cea2-49d8-9a17-3fca1e4e991c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775220093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.775220093
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.1413137275
Short name T386
Test name
Test status
Simulation time 4331441923 ps
CPU time 5.91 seconds
Started Jul 23 07:07:45 PM PDT 24
Finished Jul 23 07:07:53 PM PDT 24
Peak memory 232888 kb
Host smart-0a72fe78-7fd2-42b4-bcf2-ef491351a116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413137275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.1413137275
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.3321814913
Short name T921
Test name
Test status
Simulation time 2883503167 ps
CPU time 5.55 seconds
Started Jul 23 07:07:45 PM PDT 24
Finished Jul 23 07:07:53 PM PDT 24
Peak memory 232920 kb
Host smart-ff1ad21a-f8d1-48e6-a869-1f403b230a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321814913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.3321814913
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.777325260
Short name T908
Test name
Test status
Simulation time 2796016993 ps
CPU time 11.83 seconds
Started Jul 23 07:07:42 PM PDT 24
Finished Jul 23 07:07:55 PM PDT 24
Peak memory 222148 kb
Host smart-b577eea6-51eb-4fd3-ab16-63f3afdf6fe0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=777325260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dire
ct.777325260
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.1355461709
Short name T710
Test name
Test status
Simulation time 11142885830 ps
CPU time 26.67 seconds
Started Jul 23 07:07:43 PM PDT 24
Finished Jul 23 07:08:11 PM PDT 24
Peak memory 236940 kb
Host smart-b7eb037a-5f97-4500-8fd2-1bbf912839ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355461709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.1355461709
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.2391181862
Short name T727
Test name
Test status
Simulation time 5946803427 ps
CPU time 14.96 seconds
Started Jul 23 07:07:42 PM PDT 24
Finished Jul 23 07:07:58 PM PDT 24
Peak memory 216448 kb
Host smart-c3c07098-c9f3-470c-a2e9-3a385f52edfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391181862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.2391181862
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.3767877867
Short name T476
Test name
Test status
Simulation time 3231817250 ps
CPU time 6.02 seconds
Started Jul 23 07:07:45 PM PDT 24
Finished Jul 23 07:07:53 PM PDT 24
Peak memory 216496 kb
Host smart-d7d7c75b-07be-4638-bf4f-cc6ec939ec83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767877867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.3767877867
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.2866063249
Short name T291
Test name
Test status
Simulation time 361537745 ps
CPU time 4.86 seconds
Started Jul 23 07:07:44 PM PDT 24
Finished Jul 23 07:07:50 PM PDT 24
Peak memory 216428 kb
Host smart-833f299c-3625-459b-ae7c-c976687bcede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866063249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.2866063249
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.2071844212
Short name T311
Test name
Test status
Simulation time 33101680 ps
CPU time 0.84 seconds
Started Jul 23 07:07:44 PM PDT 24
Finished Jul 23 07:07:47 PM PDT 24
Peak memory 206100 kb
Host smart-586b81b3-e5cd-4623-b2eb-6b274bf4572d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071844212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.2071844212
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.1898348747
Short name T336
Test name
Test status
Simulation time 417838104 ps
CPU time 3.77 seconds
Started Jul 23 07:07:43 PM PDT 24
Finished Jul 23 07:07:49 PM PDT 24
Peak memory 224672 kb
Host smart-63be809e-a85a-4f99-9853-eaca87aa34a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898348747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.1898348747
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.538267348
Short name T656
Test name
Test status
Simulation time 70130387 ps
CPU time 0.73 seconds
Started Jul 23 07:07:52 PM PDT 24
Finished Jul 23 07:07:54 PM PDT 24
Peak memory 205004 kb
Host smart-bad11638-4055-46f4-8dd0-552bb3806661
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538267348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.538267348
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.4250415217
Short name T687
Test name
Test status
Simulation time 1825056392 ps
CPU time 5.61 seconds
Started Jul 23 07:07:49 PM PDT 24
Finished Jul 23 07:07:57 PM PDT 24
Peak memory 232872 kb
Host smart-f9a4f8eb-6c08-4b24-b56b-ce0abd8fd607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250415217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.4250415217
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.3079720860
Short name T943
Test name
Test status
Simulation time 36702924 ps
CPU time 0.73 seconds
Started Jul 23 07:07:42 PM PDT 24
Finished Jul 23 07:07:44 PM PDT 24
Peak memory 207056 kb
Host smart-269bcf22-bcf1-4bbd-b65a-2db53bc0ebbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079720860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.3079720860
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.797479992
Short name T702
Test name
Test status
Simulation time 17689945052 ps
CPU time 44.59 seconds
Started Jul 23 07:07:50 PM PDT 24
Finished Jul 23 07:08:36 PM PDT 24
Peak memory 250828 kb
Host smart-e38ac74d-ca16-4a5f-9411-57ac4a39b6cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797479992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.797479992
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.1183610620
Short name T621
Test name
Test status
Simulation time 10174555102 ps
CPU time 60.39 seconds
Started Jul 23 07:07:50 PM PDT 24
Finished Jul 23 07:08:52 PM PDT 24
Peak memory 257548 kb
Host smart-9a7e167c-237d-49c0-8caf-be758f74cca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183610620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.1183610620
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.434892119
Short name T593
Test name
Test status
Simulation time 1234314341 ps
CPU time 7.05 seconds
Started Jul 23 07:07:50 PM PDT 24
Finished Jul 23 07:07:59 PM PDT 24
Peak memory 241088 kb
Host smart-8209c7d1-b1b4-43fa-8591-2e3951209609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434892119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.434892119
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.2970440509
Short name T986
Test name
Test status
Simulation time 4479064830 ps
CPU time 36.09 seconds
Started Jul 23 07:07:50 PM PDT 24
Finished Jul 23 07:08:27 PM PDT 24
Peak memory 265376 kb
Host smart-639efc1c-d615-4931-8abc-5afd5ff7bf09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970440509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmd
s.2970440509
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_intercept.2739705158
Short name T78
Test name
Test status
Simulation time 705510996 ps
CPU time 8.94 seconds
Started Jul 23 07:07:48 PM PDT 24
Finished Jul 23 07:07:58 PM PDT 24
Peak memory 232884 kb
Host smart-18574efc-5b05-4404-b70c-7277b65f20dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739705158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.2739705158
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.891337594
Short name T176
Test name
Test status
Simulation time 36711430462 ps
CPU time 39.61 seconds
Started Jul 23 07:07:47 PM PDT 24
Finished Jul 23 07:08:28 PM PDT 24
Peak memory 232904 kb
Host smart-f9cf150b-a289-43e5-a12d-5dfe9f583db6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891337594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.891337594
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.2866898388
Short name T188
Test name
Test status
Simulation time 5156390170 ps
CPU time 12.11 seconds
Started Jul 23 07:07:50 PM PDT 24
Finished Jul 23 07:08:04 PM PDT 24
Peak memory 249044 kb
Host smart-10a5ab2b-144d-4159-b384-fbbb75c151b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866898388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.2866898388
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.3703623934
Short name T996
Test name
Test status
Simulation time 19568284923 ps
CPU time 9.03 seconds
Started Jul 23 07:07:50 PM PDT 24
Finished Jul 23 07:08:01 PM PDT 24
Peak memory 240824 kb
Host smart-cf37ba18-8036-42a5-96a5-cbca9af1e2d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703623934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.3703623934
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.3837436866
Short name T328
Test name
Test status
Simulation time 1071330410 ps
CPU time 7.78 seconds
Started Jul 23 07:07:49 PM PDT 24
Finished Jul 23 07:07:59 PM PDT 24
Peak memory 220704 kb
Host smart-1261df24-8293-4d85-9d74-19d0d779d566
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3837436866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.3837436866
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.2386322815
Short name T22
Test name
Test status
Simulation time 43744616 ps
CPU time 0.9 seconds
Started Jul 23 07:07:49 PM PDT 24
Finished Jul 23 07:07:52 PM PDT 24
Peak memory 205832 kb
Host smart-e7002643-5583-4e1c-9801-f124be03d85a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386322815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.2386322815
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.1529789912
Short name T435
Test name
Test status
Simulation time 12104125227 ps
CPU time 25.69 seconds
Started Jul 23 07:07:48 PM PDT 24
Finished Jul 23 07:08:15 PM PDT 24
Peak memory 220816 kb
Host smart-3e7ef9db-68df-4632-9a75-144a6afbf52c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529789912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.1529789912
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.2935618717
Short name T508
Test name
Test status
Simulation time 8526789694 ps
CPU time 9.58 seconds
Started Jul 23 07:07:44 PM PDT 24
Finished Jul 23 07:07:56 PM PDT 24
Peak memory 216384 kb
Host smart-2d91ecbe-2569-4a87-86a4-36f362abb504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935618717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.2935618717
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.2964553360
Short name T777
Test name
Test status
Simulation time 1285781603 ps
CPU time 4.51 seconds
Started Jul 23 07:07:51 PM PDT 24
Finished Jul 23 07:07:57 PM PDT 24
Peak memory 216472 kb
Host smart-8e91c7e7-6ffe-48a4-be5b-51f849eabf77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964553360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.2964553360
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.2802569245
Short name T894
Test name
Test status
Simulation time 13887423 ps
CPU time 0.71 seconds
Started Jul 23 07:07:49 PM PDT 24
Finished Jul 23 07:07:51 PM PDT 24
Peak memory 206064 kb
Host smart-6accbea2-eb49-416c-849b-f694560c9a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802569245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.2802569245
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.404049644
Short name T525
Test name
Test status
Simulation time 28494736696 ps
CPU time 12.46 seconds
Started Jul 23 07:07:48 PM PDT 24
Finished Jul 23 07:08:02 PM PDT 24
Peak memory 224620 kb
Host smart-a203a710-98a8-4a26-a1c3-ea725ff485ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404049644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.404049644
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.3137063667
Short name T58
Test name
Test status
Simulation time 11931519 ps
CPU time 0.74 seconds
Started Jul 23 07:07:57 PM PDT 24
Finished Jul 23 07:07:59 PM PDT 24
Peak memory 204992 kb
Host smart-44c020d8-ed30-40bf-b5a2-bd026833db37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137063667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
3137063667
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.2873698933
Short name T618
Test name
Test status
Simulation time 76475603 ps
CPU time 2.21 seconds
Started Jul 23 07:07:49 PM PDT 24
Finished Jul 23 07:07:53 PM PDT 24
Peak memory 224304 kb
Host smart-604df35b-3411-4e6e-8eaa-9ca8f027b375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873698933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.2873698933
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.1225508628
Short name T52
Test name
Test status
Simulation time 54809629 ps
CPU time 0.77 seconds
Started Jul 23 07:07:49 PM PDT 24
Finished Jul 23 07:07:52 PM PDT 24
Peak memory 207040 kb
Host smart-d1b704f5-c19c-4c2c-95c3-9904b8e8d602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225508628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.1225508628
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.1004107321
Short name T548
Test name
Test status
Simulation time 2288551520 ps
CPU time 16.56 seconds
Started Jul 23 07:07:58 PM PDT 24
Finished Jul 23 07:08:15 PM PDT 24
Peak memory 224672 kb
Host smart-e969513d-d245-4a39-837a-4c8b9e3f0f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004107321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.1004107321
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.786823540
Short name T415
Test name
Test status
Simulation time 959808817 ps
CPU time 9.06 seconds
Started Jul 23 07:07:54 PM PDT 24
Finished Jul 23 07:08:04 PM PDT 24
Peak memory 217844 kb
Host smart-13155503-dc88-49a2-896e-9b18f8d18f23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786823540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.786823540
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.1196341619
Short name T613
Test name
Test status
Simulation time 67895799983 ps
CPU time 60.12 seconds
Started Jul 23 07:07:54 PM PDT 24
Finished Jul 23 07:08:56 PM PDT 24
Peak memory 241168 kb
Host smart-66e5a2c4-4881-49d5-9069-d332536fb09c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196341619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.1196341619
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.2920388824
Short name T2
Test name
Test status
Simulation time 8494207068 ps
CPU time 51.87 seconds
Started Jul 23 07:07:54 PM PDT 24
Finished Jul 23 07:08:47 PM PDT 24
Peak memory 249340 kb
Host smart-6375287e-1638-405f-b2e6-d651ce02f325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920388824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.2920388824
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.1140791133
Short name T1011
Test name
Test status
Simulation time 54156056926 ps
CPU time 361.9 seconds
Started Jul 23 07:07:54 PM PDT 24
Finished Jul 23 07:13:57 PM PDT 24
Peak memory 257304 kb
Host smart-823ab9ee-da09-48a4-b2a5-8e71c4621a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140791133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmd
s.1140791133
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_intercept.840924873
Short name T374
Test name
Test status
Simulation time 428429188 ps
CPU time 5.75 seconds
Started Jul 23 07:07:48 PM PDT 24
Finished Jul 23 07:07:56 PM PDT 24
Peak memory 224628 kb
Host smart-e55773a3-f6f8-49a1-9ef3-1514a7ab0965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840924873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.840924873
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.374508335
Short name T849
Test name
Test status
Simulation time 1524511846 ps
CPU time 19.39 seconds
Started Jul 23 07:07:50 PM PDT 24
Finished Jul 23 07:08:11 PM PDT 24
Peak memory 233044 kb
Host smart-8d476a28-5743-4936-8482-5898741ffcce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374508335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.374508335
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.2200801966
Short name T510
Test name
Test status
Simulation time 657361497 ps
CPU time 2.97 seconds
Started Jul 23 07:07:53 PM PDT 24
Finished Jul 23 07:07:56 PM PDT 24
Peak memory 224716 kb
Host smart-2d242245-510b-4788-99a3-3c7f7b1437fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200801966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.2200801966
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.4292681489
Short name T200
Test name
Test status
Simulation time 106629697 ps
CPU time 2.2 seconds
Started Jul 23 07:07:47 PM PDT 24
Finished Jul 23 07:07:50 PM PDT 24
Peak memory 224632 kb
Host smart-e70d8975-a3e4-4feb-a4e8-deded6dab775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292681489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.4292681489
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.4033772565
Short name T801
Test name
Test status
Simulation time 295182662 ps
CPU time 3.71 seconds
Started Jul 23 07:07:56 PM PDT 24
Finished Jul 23 07:08:01 PM PDT 24
Peak memory 223184 kb
Host smart-b1137cff-90eb-4d4d-b7d0-f84a1b58a556
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4033772565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.4033772565
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.2169136516
Short name T936
Test name
Test status
Simulation time 87640269377 ps
CPU time 102.44 seconds
Started Jul 23 07:07:54 PM PDT 24
Finished Jul 23 07:09:38 PM PDT 24
Peak memory 249456 kb
Host smart-ed429d4a-313e-483a-a285-c0ee20985d64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169136516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.2169136516
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.251188836
Short name T359
Test name
Test status
Simulation time 4642954683 ps
CPU time 29.51 seconds
Started Jul 23 07:07:49 PM PDT 24
Finished Jul 23 07:08:20 PM PDT 24
Peak memory 216508 kb
Host smart-0f6f5685-1a1a-4091-9a6f-294f29fb7295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251188836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.251188836
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.2875888007
Short name T363
Test name
Test status
Simulation time 894257289 ps
CPU time 4.85 seconds
Started Jul 23 07:07:51 PM PDT 24
Finished Jul 23 07:07:57 PM PDT 24
Peak memory 216428 kb
Host smart-0e59fdcc-a262-4e35-8f05-102bef3e26a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875888007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.2875888007
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.3600975523
Short name T514
Test name
Test status
Simulation time 176656678 ps
CPU time 1.88 seconds
Started Jul 23 07:07:49 PM PDT 24
Finished Jul 23 07:07:53 PM PDT 24
Peak memory 216432 kb
Host smart-2adf77e1-a1ef-4fa6-8d7a-73cb658f9e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600975523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.3600975523
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.1717388607
Short name T25
Test name
Test status
Simulation time 212368581 ps
CPU time 0.9 seconds
Started Jul 23 07:07:54 PM PDT 24
Finished Jul 23 07:07:56 PM PDT 24
Peak memory 206120 kb
Host smart-4ac27ba6-1fb6-47e2-81a6-21f1894ec742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717388607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.1717388607
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.2496540680
Short name T758
Test name
Test status
Simulation time 8610836764 ps
CPU time 5.35 seconds
Started Jul 23 07:07:51 PM PDT 24
Finished Jul 23 07:07:57 PM PDT 24
Peak memory 224796 kb
Host smart-0ccf84ea-9bae-4b74-83be-d5632414ad92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496540680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.2496540680
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.571546748
Short name T428
Test name
Test status
Simulation time 31417401 ps
CPU time 0.77 seconds
Started Jul 23 07:08:02 PM PDT 24
Finished Jul 23 07:08:05 PM PDT 24
Peak memory 205948 kb
Host smart-92e0cbb2-5ef2-440a-83f4-49c3c2dd15b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571546748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.571546748
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.1860016197
Short name T763
Test name
Test status
Simulation time 69565058 ps
CPU time 2.98 seconds
Started Jul 23 07:07:54 PM PDT 24
Finished Jul 23 07:07:57 PM PDT 24
Peak memory 232868 kb
Host smart-94ce5c37-9a6b-46ad-a810-f71ee60f0616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860016197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.1860016197
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.1934769027
Short name T978
Test name
Test status
Simulation time 14908678 ps
CPU time 0.79 seconds
Started Jul 23 07:07:56 PM PDT 24
Finished Jul 23 07:07:58 PM PDT 24
Peak memory 205732 kb
Host smart-bad1f6f6-612e-4055-ab81-53d62bf6d37a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934769027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.1934769027
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.1091052094
Short name T649
Test name
Test status
Simulation time 34543599 ps
CPU time 0.73 seconds
Started Jul 23 07:07:54 PM PDT 24
Finished Jul 23 07:07:56 PM PDT 24
Peak memory 215996 kb
Host smart-557812d3-3849-4186-ad6b-4f4e2c8838ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091052094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.1091052094
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.1269132421
Short name T29
Test name
Test status
Simulation time 72414659565 ps
CPU time 238.59 seconds
Started Jul 23 07:07:55 PM PDT 24
Finished Jul 23 07:11:54 PM PDT 24
Peak memory 268556 kb
Host smart-36598254-1f12-4b98-b18f-a66b78e11e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269132421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.1269132421
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.2175799629
Short name T288
Test name
Test status
Simulation time 1375694395 ps
CPU time 19.98 seconds
Started Jul 23 07:08:15 PM PDT 24
Finished Jul 23 07:08:37 PM PDT 24
Peak memory 217616 kb
Host smart-7ca4b7dc-3d46-4d54-8911-c95b8310da97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175799629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.2175799629
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.3745882163
Short name T472
Test name
Test status
Simulation time 8267040696 ps
CPU time 11.11 seconds
Started Jul 23 07:07:57 PM PDT 24
Finished Jul 23 07:08:09 PM PDT 24
Peak memory 232920 kb
Host smart-bad66a05-c8a4-4265-9687-02d0e28b8361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745882163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.3745882163
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.1246731867
Short name T722
Test name
Test status
Simulation time 19537690292 ps
CPU time 170.62 seconds
Started Jul 23 07:07:58 PM PDT 24
Finished Jul 23 07:10:49 PM PDT 24
Peak memory 257544 kb
Host smart-a1a34ebe-0be5-48d0-88e8-a866d33405dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246731867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmd
s.1246731867
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_intercept.614623120
Short name T774
Test name
Test status
Simulation time 224759492 ps
CPU time 2.91 seconds
Started Jul 23 07:07:56 PM PDT 24
Finished Jul 23 07:08:00 PM PDT 24
Peak memory 232912 kb
Host smart-6ce8abe2-97e0-4cf3-a300-34a5f5d31855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614623120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.614623120
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.2928158404
Short name T394
Test name
Test status
Simulation time 669899268 ps
CPU time 10.65 seconds
Started Jul 23 07:07:55 PM PDT 24
Finished Jul 23 07:08:07 PM PDT 24
Peak memory 223724 kb
Host smart-adb0dc45-b8ee-4542-af2d-a06d9cb084a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928158404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.2928158404
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.3843348518
Short name T209
Test name
Test status
Simulation time 40124355 ps
CPU time 1.99 seconds
Started Jul 23 07:07:59 PM PDT 24
Finished Jul 23 07:08:02 PM PDT 24
Peak memory 224656 kb
Host smart-cae1489c-38c9-406b-8c06-502ccf8b2432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843348518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.3843348518
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.3784164217
Short name T452
Test name
Test status
Simulation time 16990818179 ps
CPU time 15.02 seconds
Started Jul 23 07:07:57 PM PDT 24
Finished Jul 23 07:08:13 PM PDT 24
Peak memory 224700 kb
Host smart-af3486e9-5d20-40ff-a5c4-7bc090a4961a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784164217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.3784164217
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.766910043
Short name T1003
Test name
Test status
Simulation time 2375584969 ps
CPU time 7.67 seconds
Started Jul 23 07:07:54 PM PDT 24
Finished Jul 23 07:08:03 PM PDT 24
Peak memory 223744 kb
Host smart-022dd9ae-c391-4ca5-aa4b-dd7ead532a48
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=766910043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dire
ct.766910043
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.2977828389
Short name T601
Test name
Test status
Simulation time 35910055 ps
CPU time 1 seconds
Started Jul 23 07:08:02 PM PDT 24
Finished Jul 23 07:08:05 PM PDT 24
Peak memory 206908 kb
Host smart-16a993f3-67d6-4ad9-9158-79034594a89e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977828389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.2977828389
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.337121050
Short name T998
Test name
Test status
Simulation time 3463484791 ps
CPU time 19.13 seconds
Started Jul 23 07:07:55 PM PDT 24
Finished Jul 23 07:08:16 PM PDT 24
Peak memory 216520 kb
Host smart-66ce9071-e4c7-4468-85f8-b1fa3d9483bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337121050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.337121050
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.3943165798
Short name T447
Test name
Test status
Simulation time 4850612119 ps
CPU time 15.87 seconds
Started Jul 23 07:07:55 PM PDT 24
Finished Jul 23 07:08:13 PM PDT 24
Peak memory 216640 kb
Host smart-e579f142-beff-428d-9769-776cba5c9abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943165798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.3943165798
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.2000408211
Short name T527
Test name
Test status
Simulation time 24405886 ps
CPU time 1.02 seconds
Started Jul 23 07:07:55 PM PDT 24
Finished Jul 23 07:07:57 PM PDT 24
Peak memory 207344 kb
Host smart-bbd51dbd-9320-4099-b91d-9c66741ae499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000408211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.2000408211
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.3738643866
Short name T521
Test name
Test status
Simulation time 55111903 ps
CPU time 0.72 seconds
Started Jul 23 07:07:58 PM PDT 24
Finished Jul 23 07:07:59 PM PDT 24
Peak memory 206028 kb
Host smart-62cda560-eb58-46d1-9403-cc8cb3c98ebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738643866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.3738643866
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.2924536489
Short name T916
Test name
Test status
Simulation time 1355913403 ps
CPU time 11.04 seconds
Started Jul 23 07:07:55 PM PDT 24
Finished Jul 23 07:08:08 PM PDT 24
Peak memory 240740 kb
Host smart-bff4efa5-54a6-460d-a893-ab632108f67a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924536489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.2924536489
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.113990671
Short name T481
Test name
Test status
Simulation time 14693981 ps
CPU time 0.78 seconds
Started Jul 23 07:08:02 PM PDT 24
Finished Jul 23 07:08:05 PM PDT 24
Peak memory 205024 kb
Host smart-fd381605-e26f-429e-99b8-f531d7d92287
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113990671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.113990671
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.2747730294
Short name T907
Test name
Test status
Simulation time 625191020 ps
CPU time 4.2 seconds
Started Jul 23 07:08:02 PM PDT 24
Finished Jul 23 07:08:08 PM PDT 24
Peak memory 232840 kb
Host smart-7b25b2d9-d0ba-470e-8f1f-4fa0d3b23be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747730294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.2747730294
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.3431148982
Short name T688
Test name
Test status
Simulation time 23390058 ps
CPU time 0.79 seconds
Started Jul 23 07:08:01 PM PDT 24
Finished Jul 23 07:08:04 PM PDT 24
Peak memory 206744 kb
Host smart-533a15a6-5faa-49fe-abf3-7889bcbea9b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431148982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.3431148982
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.2607301153
Short name T513
Test name
Test status
Simulation time 2881636750 ps
CPU time 25.59 seconds
Started Jul 23 07:08:00 PM PDT 24
Finished Jul 23 07:08:27 PM PDT 24
Peak memory 232940 kb
Host smart-2a899419-453e-4787-8df9-364b752e6135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607301153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.2607301153
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.387209267
Short name T1000
Test name
Test status
Simulation time 12020475196 ps
CPU time 109.58 seconds
Started Jul 23 07:07:59 PM PDT 24
Finished Jul 23 07:09:50 PM PDT 24
Peak memory 250492 kb
Host smart-f3afd0a4-5d6e-40b4-be0e-f5713a81cd74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387209267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.387209267
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.4246300597
Short name T194
Test name
Test status
Simulation time 6299260900 ps
CPU time 15.12 seconds
Started Jul 23 07:08:14 PM PDT 24
Finished Jul 23 07:08:31 PM PDT 24
Peak memory 232932 kb
Host smart-e70148f2-538a-4b4d-9dd7-18e730397fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246300597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.4246300597
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.2762671755
Short name T599
Test name
Test status
Simulation time 178273277 ps
CPU time 2.84 seconds
Started Jul 23 07:08:03 PM PDT 24
Finished Jul 23 07:08:07 PM PDT 24
Peak memory 232824 kb
Host smart-271c1563-3a69-4129-981d-95fc5515e143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762671755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.2762671755
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.1649755223
Short name T437
Test name
Test status
Simulation time 1428522464 ps
CPU time 16.21 seconds
Started Jul 23 07:08:02 PM PDT 24
Finished Jul 23 07:08:20 PM PDT 24
Peak memory 224720 kb
Host smart-2dd6df31-806a-4576-86e4-ba9c3ebdbf8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649755223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmd
s.1649755223
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/39.spi_device_intercept.275696110
Short name T247
Test name
Test status
Simulation time 6416448340 ps
CPU time 11.08 seconds
Started Jul 23 07:08:00 PM PDT 24
Finished Jul 23 07:08:13 PM PDT 24
Peak memory 229728 kb
Host smart-e4c70346-2e58-4c23-819a-badd20e8bc0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275696110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.275696110
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.960095327
Short name T584
Test name
Test status
Simulation time 10139871707 ps
CPU time 7.43 seconds
Started Jul 23 07:08:01 PM PDT 24
Finished Jul 23 07:08:10 PM PDT 24
Peak memory 224724 kb
Host smart-be08644d-25b9-4ca1-b17a-f5f1fc9e377e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960095327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.960095327
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.3757960894
Short name T226
Test name
Test status
Simulation time 2505741641 ps
CPU time 3.34 seconds
Started Jul 23 07:08:02 PM PDT 24
Finished Jul 23 07:08:07 PM PDT 24
Peak memory 224716 kb
Host smart-4275a5b0-e0ad-45b9-bf6d-1526ec82206f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757960894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.3757960894
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.4111563528
Short name T218
Test name
Test status
Simulation time 11826686992 ps
CPU time 9.23 seconds
Started Jul 23 07:08:00 PM PDT 24
Finished Jul 23 07:08:10 PM PDT 24
Peak memory 224784 kb
Host smart-d6d6afe9-804e-4ed4-a111-4ac58c684ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111563528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.4111563528
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.348926557
Short name T944
Test name
Test status
Simulation time 1290181643 ps
CPU time 15.08 seconds
Started Jul 23 07:08:01 PM PDT 24
Finished Jul 23 07:08:17 PM PDT 24
Peak memory 219244 kb
Host smart-9fc7c99f-3c74-46d2-a1e4-5b3896ef3f2b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=348926557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dire
ct.348926557
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.2134802303
Short name T838
Test name
Test status
Simulation time 89599295022 ps
CPU time 788.9 seconds
Started Jul 23 07:08:02 PM PDT 24
Finished Jul 23 07:21:13 PM PDT 24
Peak memory 273384 kb
Host smart-176c0c9d-d134-41bf-ba1f-a8578ad49cb8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134802303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.2134802303
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.1941018206
Short name T484
Test name
Test status
Simulation time 1665253736 ps
CPU time 19.87 seconds
Started Jul 23 07:08:01 PM PDT 24
Finished Jul 23 07:08:23 PM PDT 24
Peak memory 216540 kb
Host smart-8454b8c3-37ec-4066-841e-a5b23f6e7c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941018206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.1941018206
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.1339239317
Short name T893
Test name
Test status
Simulation time 12461623733 ps
CPU time 6.33 seconds
Started Jul 23 07:08:01 PM PDT 24
Finished Jul 23 07:08:09 PM PDT 24
Peak memory 216492 kb
Host smart-d345ee60-76a0-4473-a549-6483593df6c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339239317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.1339239317
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.780665891
Short name T619
Test name
Test status
Simulation time 50559362 ps
CPU time 1.12 seconds
Started Jul 23 07:08:00 PM PDT 24
Finished Jul 23 07:08:03 PM PDT 24
Peak memory 207668 kb
Host smart-9f0ee164-ab03-48c3-b646-d2781a27cd26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780665891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.780665891
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.2643411247
Short name T927
Test name
Test status
Simulation time 65836959 ps
CPU time 0.93 seconds
Started Jul 23 07:08:00 PM PDT 24
Finished Jul 23 07:08:02 PM PDT 24
Peak memory 206136 kb
Host smart-e870639d-96a4-4c54-8a1e-3abe0d2daefa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643411247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.2643411247
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.3175263427
Short name T872
Test name
Test status
Simulation time 3386296099 ps
CPU time 7.31 seconds
Started Jul 23 07:07:59 PM PDT 24
Finished Jul 23 07:08:08 PM PDT 24
Peak memory 232956 kb
Host smart-6319ccbd-cc8d-4672-9ed5-41955d11669c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175263427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.3175263427
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.3465683139
Short name T970
Test name
Test status
Simulation time 13203238 ps
CPU time 0.72 seconds
Started Jul 23 07:05:22 PM PDT 24
Finished Jul 23 07:05:24 PM PDT 24
Peak memory 205036 kb
Host smart-e3289b9b-088e-419c-ad23-09105849a45f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465683139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.3
465683139
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.1510544053
Short name T465
Test name
Test status
Simulation time 362130606 ps
CPU time 3.88 seconds
Started Jul 23 07:05:19 PM PDT 24
Finished Jul 23 07:05:25 PM PDT 24
Peak memory 232848 kb
Host smart-aa14d7ed-92ee-4d59-af39-4baf6434037b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510544053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.1510544053
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.1639016099
Short name T669
Test name
Test status
Simulation time 16203190 ps
CPU time 0.77 seconds
Started Jul 23 07:05:18 PM PDT 24
Finished Jul 23 07:05:21 PM PDT 24
Peak memory 205916 kb
Host smart-69489735-cbf9-4556-b796-539ec6ec4cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639016099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.1639016099
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.1142114192
Short name T854
Test name
Test status
Simulation time 84089410617 ps
CPU time 456.76 seconds
Started Jul 23 07:05:21 PM PDT 24
Finished Jul 23 07:13:00 PM PDT 24
Peak memory 257512 kb
Host smart-dff8afaa-9e85-4adc-9174-63b1a6e01433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142114192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.1142114192
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.672647783
Short name T769
Test name
Test status
Simulation time 6072902410 ps
CPU time 106.92 seconds
Started Jul 23 07:05:18 PM PDT 24
Finished Jul 23 07:07:08 PM PDT 24
Peak memory 254752 kb
Host smart-38349f43-918e-4a07-89d9-2860b6eb3a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672647783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.672647783
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.1612123976
Short name T287
Test name
Test status
Simulation time 7456152747 ps
CPU time 37.96 seconds
Started Jul 23 07:05:20 PM PDT 24
Finished Jul 23 07:06:00 PM PDT 24
Peak memory 249100 kb
Host smart-b191cae4-8861-48ac-83a8-11a2b9c8b881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612123976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.1612123976
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.518133995
Short name T379
Test name
Test status
Simulation time 5367772661 ps
CPU time 10.48 seconds
Started Jul 23 07:05:19 PM PDT 24
Finished Jul 23 07:05:32 PM PDT 24
Peak memory 249348 kb
Host smart-3bcfc6ee-179b-4ad7-b740-e95fb5a5afd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518133995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.518133995
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_intercept.820215080
Short name T683
Test name
Test status
Simulation time 5879202617 ps
CPU time 23.23 seconds
Started Jul 23 07:05:12 PM PDT 24
Finished Jul 23 07:05:37 PM PDT 24
Peak memory 232916 kb
Host smart-9306122d-677f-4a99-8430-0aad0db1ffe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820215080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.820215080
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.1273274569
Short name T810
Test name
Test status
Simulation time 15221840338 ps
CPU time 39.76 seconds
Started Jul 23 07:05:15 PM PDT 24
Finished Jul 23 07:05:57 PM PDT 24
Peak memory 232956 kb
Host smart-bd0bfe81-6d04-4a86-8765-48928b1b2718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273274569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.1273274569
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.3302528693
Short name T231
Test name
Test status
Simulation time 16971199255 ps
CPU time 12.69 seconds
Started Jul 23 07:05:14 PM PDT 24
Finished Jul 23 07:05:29 PM PDT 24
Peak memory 235692 kb
Host smart-74098342-f7da-4384-af9d-e774fe2e7ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302528693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.3302528693
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.2944472821
Short name T897
Test name
Test status
Simulation time 20175688499 ps
CPU time 27.2 seconds
Started Jul 23 07:05:16 PM PDT 24
Finished Jul 23 07:05:46 PM PDT 24
Peak memory 239844 kb
Host smart-7af29b85-ed6e-46aa-8106-87c841965e73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944472821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.2944472821
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.846842215
Short name T5
Test name
Test status
Simulation time 8855219695 ps
CPU time 6.87 seconds
Started Jul 23 07:05:21 PM PDT 24
Finished Jul 23 07:05:30 PM PDT 24
Peak memory 223504 kb
Host smart-6f4512e4-9b08-48b1-b078-9ec3a120b9f7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=846842215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_direc
t.846842215
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.242458231
Short name T67
Test name
Test status
Simulation time 229491409 ps
CPU time 1.04 seconds
Started Jul 23 07:05:19 PM PDT 24
Finished Jul 23 07:05:22 PM PDT 24
Peak memory 235824 kb
Host smart-782c33ab-c55c-4f43-9223-8496a72f6ea4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242458231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.242458231
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.19838079
Short name T577
Test name
Test status
Simulation time 248105720150 ps
CPU time 570.75 seconds
Started Jul 23 07:05:19 PM PDT 24
Finished Jul 23 07:14:52 PM PDT 24
Peak memory 273980 kb
Host smart-bf4725b2-4730-4041-816a-ba7b0682a824
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19838079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stress_
all.19838079
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.1309590447
Short name T973
Test name
Test status
Simulation time 5318918722 ps
CPU time 28.05 seconds
Started Jul 23 07:05:15 PM PDT 24
Finished Jul 23 07:05:46 PM PDT 24
Peak memory 216668 kb
Host smart-4ee2a25d-a4e8-4fee-82db-96b3d316b2a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309590447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.1309590447
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.75250536
Short name T909
Test name
Test status
Simulation time 2033682405 ps
CPU time 2.39 seconds
Started Jul 23 07:05:14 PM PDT 24
Finished Jul 23 07:05:19 PM PDT 24
Peak memory 216172 kb
Host smart-aafa7c7d-54d0-4c1c-834a-863ca4be5b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75250536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.75250536
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.3649007169
Short name T899
Test name
Test status
Simulation time 183888279 ps
CPU time 0.9 seconds
Started Jul 23 07:05:14 PM PDT 24
Finished Jul 23 07:05:18 PM PDT 24
Peak memory 207392 kb
Host smart-c83e3f59-52a1-4c22-8c9b-b2dffc4826dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649007169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.3649007169
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.1612271049
Short name T419
Test name
Test status
Simulation time 17193792 ps
CPU time 0.74 seconds
Started Jul 23 07:05:16 PM PDT 24
Finished Jul 23 07:05:20 PM PDT 24
Peak memory 206112 kb
Host smart-3d46b14f-2bc7-467e-9902-4f6e9bc8fe17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612271049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.1612271049
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.3628375278
Short name T676
Test name
Test status
Simulation time 19509641580 ps
CPU time 29.56 seconds
Started Jul 23 07:05:15 PM PDT 24
Finished Jul 23 07:05:48 PM PDT 24
Peak memory 235052 kb
Host smart-27eb90d6-6def-4505-8cf8-c30f5674a7cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628375278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.3628375278
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.2531362280
Short name T632
Test name
Test status
Simulation time 18363955 ps
CPU time 0.71 seconds
Started Jul 23 07:08:15 PM PDT 24
Finished Jul 23 07:08:17 PM PDT 24
Peak memory 205560 kb
Host smart-44172e24-a7a3-4741-ab18-9c0682fef15d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531362280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
2531362280
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.991246190
Short name T309
Test name
Test status
Simulation time 1332122201 ps
CPU time 6.76 seconds
Started Jul 23 07:08:14 PM PDT 24
Finished Jul 23 07:08:23 PM PDT 24
Peak memory 224680 kb
Host smart-21b13cec-951f-4fbe-a0b0-6469c5758dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991246190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.991246190
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.2808022060
Short name T773
Test name
Test status
Simulation time 33901718 ps
CPU time 0.79 seconds
Started Jul 23 07:08:02 PM PDT 24
Finished Jul 23 07:08:05 PM PDT 24
Peak memory 207052 kb
Host smart-9fd73707-f02f-43f3-a7a2-32ac4048ecf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808022060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.2808022060
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.1442750090
Short name T117
Test name
Test status
Simulation time 27904978016 ps
CPU time 58.51 seconds
Started Jul 23 07:08:00 PM PDT 24
Finished Jul 23 07:09:00 PM PDT 24
Peak memory 249472 kb
Host smart-5c5a16bd-d8b5-4e52-98b5-0752cd4ce7d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442750090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.1442750090
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.2045779468
Short name T715
Test name
Test status
Simulation time 5708152620 ps
CPU time 42.17 seconds
Started Jul 23 07:08:14 PM PDT 24
Finished Jul 23 07:08:57 PM PDT 24
Peak memory 250676 kb
Host smart-bf30165c-b4a9-4bcd-be45-2bec5c0252e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045779468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.2045779468
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.3446695382
Short name T439
Test name
Test status
Simulation time 3505963239 ps
CPU time 29.04 seconds
Started Jul 23 07:08:00 PM PDT 24
Finished Jul 23 07:08:31 PM PDT 24
Peak memory 224640 kb
Host smart-7e40890e-e9dc-4367-b05d-0ad953247a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446695382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.3446695382
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.3502995294
Short name T554
Test name
Test status
Simulation time 1952416073 ps
CPU time 19.04 seconds
Started Jul 23 07:08:15 PM PDT 24
Finished Jul 23 07:08:36 PM PDT 24
Peak memory 224680 kb
Host smart-8c44c563-150e-49c4-84e6-7adb9b194b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502995294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.3502995294
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.2056184512
Short name T308
Test name
Test status
Simulation time 12867790 ps
CPU time 0.75 seconds
Started Jul 23 07:08:01 PM PDT 24
Finished Jul 23 07:08:03 PM PDT 24
Peak memory 215868 kb
Host smart-a4463ee8-7a48-4d75-9166-cccf2f7c6b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056184512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmd
s.2056184512
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_intercept.3279652733
Short name T509
Test name
Test status
Simulation time 291921266 ps
CPU time 3.9 seconds
Started Jul 23 07:08:00 PM PDT 24
Finished Jul 23 07:08:05 PM PDT 24
Peak memory 224708 kb
Host smart-e4c5b227-367c-49ef-b949-246a062091bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279652733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.3279652733
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.1171051948
Short name T150
Test name
Test status
Simulation time 114620106 ps
CPU time 2.13 seconds
Started Jul 23 07:08:03 PM PDT 24
Finished Jul 23 07:08:07 PM PDT 24
Peak memory 224132 kb
Host smart-d06ac830-5bc3-47be-b127-f4061f4d298a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171051948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.1171051948
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.3310196823
Short name T446
Test name
Test status
Simulation time 2510379871 ps
CPU time 4.21 seconds
Started Jul 23 07:08:02 PM PDT 24
Finished Jul 23 07:08:08 PM PDT 24
Peak memory 224672 kb
Host smart-ca947938-d623-49f5-93ef-1802313101af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310196823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.3310196823
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.1298645861
Short name T865
Test name
Test status
Simulation time 68965634344 ps
CPU time 12.24 seconds
Started Jul 23 07:07:58 PM PDT 24
Finished Jul 23 07:08:11 PM PDT 24
Peak memory 224648 kb
Host smart-2fdd7ca5-4d01-460f-937c-8d2799c210d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298645861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.1298645861
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.715175262
Short name T985
Test name
Test status
Simulation time 5148558162 ps
CPU time 10.07 seconds
Started Jul 23 07:08:02 PM PDT 24
Finished Jul 23 07:08:14 PM PDT 24
Peak memory 220108 kb
Host smart-d8d4c55b-7f08-45ff-97d5-efed66bd39a8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=715175262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dire
ct.715175262
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.2197382887
Short name T541
Test name
Test status
Simulation time 10684829546 ps
CPU time 57.81 seconds
Started Jul 23 07:08:00 PM PDT 24
Finished Jul 23 07:08:59 PM PDT 24
Peak memory 248856 kb
Host smart-23f9c686-d16f-480f-8b8d-e22b3fba5707
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197382887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.2197382887
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.1983551862
Short name T530
Test name
Test status
Simulation time 21636493737 ps
CPU time 25.75 seconds
Started Jul 23 07:08:14 PM PDT 24
Finished Jul 23 07:08:42 PM PDT 24
Peak memory 216800 kb
Host smart-8f50be65-9711-4b36-a904-44308e650f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983551862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.1983551862
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.1821473156
Short name T301
Test name
Test status
Simulation time 1210422524 ps
CPU time 4.26 seconds
Started Jul 23 07:08:01 PM PDT 24
Finished Jul 23 07:08:08 PM PDT 24
Peak memory 216384 kb
Host smart-55f06403-ed78-4bcf-9433-33422858b528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821473156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.1821473156
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.1749007260
Short name T388
Test name
Test status
Simulation time 173485091 ps
CPU time 2.19 seconds
Started Jul 23 07:08:01 PM PDT 24
Finished Jul 23 07:08:05 PM PDT 24
Peak memory 216444 kb
Host smart-3472f140-6a84-4beb-994e-a60b0997bfaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749007260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.1749007260
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.1490012299
Short name T911
Test name
Test status
Simulation time 231564380 ps
CPU time 0.91 seconds
Started Jul 23 07:08:14 PM PDT 24
Finished Jul 23 07:08:17 PM PDT 24
Peak memory 206108 kb
Host smart-72ee72be-c5b7-4551-8aba-7705476c4480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490012299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.1490012299
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.1729452214
Short name T755
Test name
Test status
Simulation time 412339284 ps
CPU time 5.42 seconds
Started Jul 23 07:08:02 PM PDT 24
Finished Jul 23 07:08:10 PM PDT 24
Peak memory 232876 kb
Host smart-f571ee9f-5e64-4289-836d-ba250f9d386f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729452214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.1729452214
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.4294269316
Short name T458
Test name
Test status
Simulation time 13559926 ps
CPU time 0.7 seconds
Started Jul 23 07:08:04 PM PDT 24
Finished Jul 23 07:08:06 PM PDT 24
Peak memory 205032 kb
Host smart-57240dba-5d66-49aa-9c3d-7d4effd3cd56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294269316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
4294269316
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.1569592340
Short name T742
Test name
Test status
Simulation time 70374511 ps
CPU time 2.64 seconds
Started Jul 23 07:08:03 PM PDT 24
Finished Jul 23 07:08:08 PM PDT 24
Peak memory 232864 kb
Host smart-8ca95f00-4da1-4cbf-813e-dd3cd527870e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569592340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.1569592340
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.2888500150
Short name T305
Test name
Test status
Simulation time 58172214 ps
CPU time 0.77 seconds
Started Jul 23 07:08:02 PM PDT 24
Finished Jul 23 07:08:05 PM PDT 24
Peak memory 206964 kb
Host smart-791ed6a8-893f-4a00-aa7f-98b3eecd0f2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888500150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.2888500150
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.1034659060
Short name T789
Test name
Test status
Simulation time 567487759 ps
CPU time 5.84 seconds
Started Jul 23 07:08:05 PM PDT 24
Finished Jul 23 07:08:12 PM PDT 24
Peak memory 235588 kb
Host smart-0c9301b3-acb2-451a-ae22-54ffada143d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034659060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.1034659060
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.1021490142
Short name T418
Test name
Test status
Simulation time 52835617975 ps
CPU time 234.4 seconds
Started Jul 23 07:08:05 PM PDT 24
Finished Jul 23 07:12:01 PM PDT 24
Peak memory 257764 kb
Host smart-da0755c0-da57-45de-adac-56ccfcc72d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021490142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.1021490142
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.1864153874
Short name T43
Test name
Test status
Simulation time 15887708291 ps
CPU time 174.41 seconds
Started Jul 23 07:08:06 PM PDT 24
Finished Jul 23 07:11:01 PM PDT 24
Peak memory 265276 kb
Host smart-f4a7e493-f517-4a25-8ecc-580963e82f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864153874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.1864153874
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.1390860599
Short name T762
Test name
Test status
Simulation time 1954591495 ps
CPU time 7 seconds
Started Jul 23 07:08:04 PM PDT 24
Finished Jul 23 07:08:13 PM PDT 24
Peak memory 224604 kb
Host smart-9cbf9250-b347-4dc8-a114-85c028ba7a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390860599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.1390860599
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.2014510880
Short name T262
Test name
Test status
Simulation time 6661080560 ps
CPU time 34.17 seconds
Started Jul 23 07:08:04 PM PDT 24
Finished Jul 23 07:08:40 PM PDT 24
Peak memory 239040 kb
Host smart-f8990e94-4ef3-401d-927a-fc2baa936cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014510880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmd
s.2014510880
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.4066934206
Short name T322
Test name
Test status
Simulation time 188586233 ps
CPU time 2.09 seconds
Started Jul 23 07:08:03 PM PDT 24
Finished Jul 23 07:08:07 PM PDT 24
Peak memory 224032 kb
Host smart-69561d26-7e44-4f4e-bafa-fe633b43feb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066934206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.4066934206
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.2988797595
Short name T844
Test name
Test status
Simulation time 60340141676 ps
CPU time 125.77 seconds
Started Jul 23 07:08:04 PM PDT 24
Finished Jul 23 07:10:12 PM PDT 24
Peak memory 249356 kb
Host smart-a6a480a1-2b2d-4892-ade6-6924a3f6732d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988797595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.2988797595
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.2643534563
Short name T373
Test name
Test status
Simulation time 60104998342 ps
CPU time 23.58 seconds
Started Jul 23 07:08:07 PM PDT 24
Finished Jul 23 07:08:31 PM PDT 24
Peak memory 232968 kb
Host smart-5afe731c-d545-4522-a02a-28e70e8de0ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643534563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.2643534563
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.2241377352
Short name T886
Test name
Test status
Simulation time 4047557370 ps
CPU time 12.91 seconds
Started Jul 23 07:08:06 PM PDT 24
Finished Jul 23 07:08:20 PM PDT 24
Peak memory 224720 kb
Host smart-95b87661-3f8a-44b6-a1d2-7bb9424213ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241377352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.2241377352
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.3405901413
Short name T347
Test name
Test status
Simulation time 4035172680 ps
CPU time 7.2 seconds
Started Jul 23 07:08:06 PM PDT 24
Finished Jul 23 07:08:14 PM PDT 24
Peak memory 224440 kb
Host smart-8c33a89c-e18d-4523-8fe6-086a52fdb08d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3405901413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.3405901413
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.966502881
Short name T255
Test name
Test status
Simulation time 14421401289 ps
CPU time 93.43 seconds
Started Jul 23 07:08:05 PM PDT 24
Finished Jul 23 07:09:40 PM PDT 24
Peak memory 248824 kb
Host smart-38145a97-c488-45da-aa81-a8de468d44a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966502881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stres
s_all.966502881
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.377223964
Short name T1007
Test name
Test status
Simulation time 9612319692 ps
CPU time 23.34 seconds
Started Jul 23 07:08:03 PM PDT 24
Finished Jul 23 07:08:28 PM PDT 24
Peak memory 220796 kb
Host smart-9aaaca32-6305-49ee-af05-e71300912009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377223964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.377223964
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.3445731387
Short name T828
Test name
Test status
Simulation time 135166141 ps
CPU time 0.68 seconds
Started Jul 23 07:08:05 PM PDT 24
Finished Jul 23 07:08:07 PM PDT 24
Peak memory 205840 kb
Host smart-940c8ee8-9fd2-42e3-98a8-1686e6101861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445731387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.3445731387
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.3864578625
Short name T477
Test name
Test status
Simulation time 1636935907 ps
CPU time 1.8 seconds
Started Jul 23 07:08:04 PM PDT 24
Finished Jul 23 07:08:08 PM PDT 24
Peak memory 216452 kb
Host smart-b605f5d8-2399-4bdd-87f6-ed8ea1046d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864578625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.3864578625
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.2716359465
Short name T396
Test name
Test status
Simulation time 48233424 ps
CPU time 0.81 seconds
Started Jul 23 07:08:05 PM PDT 24
Finished Jul 23 07:08:07 PM PDT 24
Peak memory 206136 kb
Host smart-150b3c7c-b251-4431-9eaf-8ca99ef26c75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716359465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.2716359465
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.1402373693
Short name T871
Test name
Test status
Simulation time 876179120 ps
CPU time 6.21 seconds
Started Jul 23 07:08:07 PM PDT 24
Finished Jul 23 07:08:14 PM PDT 24
Peak memory 232808 kb
Host smart-9dfb9085-c00b-4120-b8bd-ff16aa00c153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402373693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.1402373693
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.1417892074
Short name T776
Test name
Test status
Simulation time 34281499 ps
CPU time 0.75 seconds
Started Jul 23 07:08:09 PM PDT 24
Finished Jul 23 07:08:11 PM PDT 24
Peak memory 205616 kb
Host smart-fafe1fa8-2088-4b83-8132-f0625ad3572e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417892074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
1417892074
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.1351875073
Short name T236
Test name
Test status
Simulation time 196809080 ps
CPU time 3.4 seconds
Started Jul 23 07:08:13 PM PDT 24
Finished Jul 23 07:08:17 PM PDT 24
Peak memory 232888 kb
Host smart-fda70c48-47fa-4409-ae08-6a63c52d1be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351875073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.1351875073
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.3955841205
Short name T332
Test name
Test status
Simulation time 13892332 ps
CPU time 0.74 seconds
Started Jul 23 07:08:03 PM PDT 24
Finished Jul 23 07:08:05 PM PDT 24
Peak memory 206668 kb
Host smart-f49904d9-e358-4baf-973e-0f8eb0f74f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955841205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.3955841205
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.2320508433
Short name T903
Test name
Test status
Simulation time 2139404065 ps
CPU time 6.76 seconds
Started Jul 23 07:08:12 PM PDT 24
Finished Jul 23 07:08:19 PM PDT 24
Peak memory 241080 kb
Host smart-8d29331a-843e-4a62-86e3-b26c570c96b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320508433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.2320508433
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.1818875042
Short name T856
Test name
Test status
Simulation time 9017771294 ps
CPU time 91.05 seconds
Started Jul 23 07:08:14 PM PDT 24
Finished Jul 23 07:09:47 PM PDT 24
Peak memory 257532 kb
Host smart-bae6d648-d7a8-443b-9f32-2d0815102f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818875042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.1818875042
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.687971688
Short name T902
Test name
Test status
Simulation time 482651339 ps
CPU time 5.34 seconds
Started Jul 23 07:08:09 PM PDT 24
Finished Jul 23 07:08:16 PM PDT 24
Peak memory 224632 kb
Host smart-d94cdd6a-c24b-4f7a-8126-832399319a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687971688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.687971688
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.3018577403
Short name T253
Test name
Test status
Simulation time 176125513923 ps
CPU time 304.51 seconds
Started Jul 23 07:08:10 PM PDT 24
Finished Jul 23 07:13:15 PM PDT 24
Peak memory 256392 kb
Host smart-f3ecdfa8-5a0e-42c3-86fd-cb758f2ebdf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018577403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmd
s.3018577403
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_intercept.1715125208
Short name T965
Test name
Test status
Simulation time 86117571 ps
CPU time 1.98 seconds
Started Jul 23 07:08:13 PM PDT 24
Finished Jul 23 07:08:16 PM PDT 24
Peak memory 224704 kb
Host smart-8b9b329f-22dc-4af9-a1c6-4c06088211fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715125208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.1715125208
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.1494177390
Short name T565
Test name
Test status
Simulation time 2152379747 ps
CPU time 12.97 seconds
Started Jul 23 07:08:11 PM PDT 24
Finished Jul 23 07:08:25 PM PDT 24
Peak memory 239732 kb
Host smart-2daf422d-6ba9-4e28-aae3-e2bc67a7adcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494177390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.1494177390
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.596367534
Short name T699
Test name
Test status
Simulation time 349792823 ps
CPU time 3.16 seconds
Started Jul 23 07:08:09 PM PDT 24
Finished Jul 23 07:08:13 PM PDT 24
Peak memory 232756 kb
Host smart-b2df3fca-4c5b-4f9e-9200-90d6af2c3691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596367534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swap
.596367534
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.3210675758
Short name T999
Test name
Test status
Simulation time 9611956937 ps
CPU time 27.88 seconds
Started Jul 23 07:08:09 PM PDT 24
Finished Jul 23 07:08:38 PM PDT 24
Peak memory 232976 kb
Host smart-2ec18a53-e8f4-4331-9c0d-22c887adc4b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210675758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.3210675758
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.4063846081
Short name T132
Test name
Test status
Simulation time 152704175 ps
CPU time 3.48 seconds
Started Jul 23 07:08:10 PM PDT 24
Finished Jul 23 07:08:15 PM PDT 24
Peak memory 220444 kb
Host smart-d05e6711-b272-47fa-b65e-ba4f2f83c936
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4063846081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.4063846081
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.2263168839
Short name T249
Test name
Test status
Simulation time 26516930157 ps
CPU time 216.59 seconds
Started Jul 23 07:08:09 PM PDT 24
Finished Jul 23 07:11:47 PM PDT 24
Peak memory 272396 kb
Host smart-e5a5a370-c19b-459e-b249-a901cddf92eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263168839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.2263168839
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.2330706486
Short name T867
Test name
Test status
Simulation time 5498451704 ps
CPU time 17.29 seconds
Started Jul 23 07:08:07 PM PDT 24
Finished Jul 23 07:08:25 PM PDT 24
Peak memory 216648 kb
Host smart-5b428d83-5978-499f-9d1d-38c72aeda755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330706486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.2330706486
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.4203859774
Short name T430
Test name
Test status
Simulation time 2902137168 ps
CPU time 9.02 seconds
Started Jul 23 07:08:03 PM PDT 24
Finished Jul 23 07:08:14 PM PDT 24
Peak memory 216440 kb
Host smart-9a899c47-d479-4104-8ae3-b171fa016a55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203859774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.4203859774
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.2134502670
Short name T338
Test name
Test status
Simulation time 255783937 ps
CPU time 5.4 seconds
Started Jul 23 07:08:11 PM PDT 24
Finished Jul 23 07:08:18 PM PDT 24
Peak memory 216476 kb
Host smart-90b17199-258c-4219-97cb-d405c2127cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134502670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.2134502670
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.3440438974
Short name T603
Test name
Test status
Simulation time 11791929 ps
CPU time 0.71 seconds
Started Jul 23 07:08:09 PM PDT 24
Finished Jul 23 07:08:12 PM PDT 24
Peak memory 205744 kb
Host smart-0f7c6e05-11a7-4039-99e5-95e9e5c52da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440438974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.3440438974
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.1874591291
Short name T7
Test name
Test status
Simulation time 5794640655 ps
CPU time 19.71 seconds
Started Jul 23 07:08:11 PM PDT 24
Finished Jul 23 07:08:31 PM PDT 24
Peak memory 240848 kb
Host smart-3461b97e-c336-451d-9282-34dd39d29af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874591291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.1874591291
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.3780542858
Short name T875
Test name
Test status
Simulation time 26145419 ps
CPU time 0.74 seconds
Started Jul 23 07:08:14 PM PDT 24
Finished Jul 23 07:08:17 PM PDT 24
Peak memory 205512 kb
Host smart-d5f163f3-861e-4ab0-a38c-956b0bab7f8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780542858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
3780542858
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.2940324590
Short name T532
Test name
Test status
Simulation time 3051960744 ps
CPU time 21.86 seconds
Started Jul 23 07:08:08 PM PDT 24
Finished Jul 23 07:08:30 PM PDT 24
Peak memory 232964 kb
Host smart-5591fb5a-b13d-4b7f-a45a-7cb6d24a4e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940324590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.2940324590
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.1676615272
Short name T304
Test name
Test status
Simulation time 70744064 ps
CPU time 0.77 seconds
Started Jul 23 07:08:09 PM PDT 24
Finished Jul 23 07:08:10 PM PDT 24
Peak memory 206744 kb
Host smart-e546efb4-8de2-4b96-9fc2-288211f1a5fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676615272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.1676615272
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.2442106771
Short name T121
Test name
Test status
Simulation time 33630801825 ps
CPU time 325.33 seconds
Started Jul 23 07:08:18 PM PDT 24
Finished Jul 23 07:13:44 PM PDT 24
Peak memory 257604 kb
Host smart-4ebacaed-12d3-46cd-8da9-b533f90c6c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442106771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.2442106771
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.1488433480
Short name T134
Test name
Test status
Simulation time 385178453 ps
CPU time 3.79 seconds
Started Jul 23 07:08:14 PM PDT 24
Finished Jul 23 07:08:19 PM PDT 24
Peak memory 224572 kb
Host smart-7db69acd-62ff-45c1-9cd1-bf17e4e9c97c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488433480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.1488433480
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.962457640
Short name T650
Test name
Test status
Simulation time 1555821099 ps
CPU time 14.57 seconds
Started Jul 23 07:08:15 PM PDT 24
Finished Jul 23 07:08:31 PM PDT 24
Peak memory 241020 kb
Host smart-cc2522d7-2a34-4d39-ae68-966c27047769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962457640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmds
.962457640
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_intercept.3991528368
Short name T522
Test name
Test status
Simulation time 41803748 ps
CPU time 2.17 seconds
Started Jul 23 07:08:10 PM PDT 24
Finished Jul 23 07:08:13 PM PDT 24
Peak memory 224612 kb
Host smart-4d5c67e7-9ab9-4645-bf94-4c5da822314e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991528368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.3991528368
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.787663172
Short name T698
Test name
Test status
Simulation time 100256525 ps
CPU time 2.13 seconds
Started Jul 23 07:08:14 PM PDT 24
Finished Jul 23 07:08:17 PM PDT 24
Peak memory 224252 kb
Host smart-9fae120c-f34b-4430-a1d5-934c3e98f42f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787663172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.787663172
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.3602006293
Short name T190
Test name
Test status
Simulation time 3931703182 ps
CPU time 10.05 seconds
Started Jul 23 07:08:13 PM PDT 24
Finished Jul 23 07:08:23 PM PDT 24
Peak memory 224764 kb
Host smart-53551283-605f-4404-b3f9-621d62dcb2ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602006293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.3602006293
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.624250838
Short name T211
Test name
Test status
Simulation time 3363103236 ps
CPU time 11.72 seconds
Started Jul 23 07:08:08 PM PDT 24
Finished Jul 23 07:08:21 PM PDT 24
Peak memory 232984 kb
Host smart-a57c9466-a1e6-46fc-826c-c9e3989a522a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624250838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.624250838
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.1976988253
Short name T38
Test name
Test status
Simulation time 1088018592 ps
CPU time 12.02 seconds
Started Jul 23 07:08:15 PM PDT 24
Finished Jul 23 07:08:28 PM PDT 24
Peak memory 223280 kb
Host smart-06801ecb-e8ab-4c7a-b036-831ee55370cc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1976988253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.1976988253
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.261267607
Short name T19
Test name
Test status
Simulation time 9757013157 ps
CPU time 141.8 seconds
Started Jul 23 07:08:15 PM PDT 24
Finished Jul 23 07:10:38 PM PDT 24
Peak memory 257564 kb
Host smart-5730596b-6116-4097-ad61-e696bc60c55e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261267607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stres
s_all.261267607
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.2467494559
Short name T573
Test name
Test status
Simulation time 983065062 ps
CPU time 5.01 seconds
Started Jul 23 07:08:08 PM PDT 24
Finished Jul 23 07:08:14 PM PDT 24
Peak memory 216468 kb
Host smart-aecfef00-3ad9-44c1-855f-c99bf6f09ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467494559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.2467494559
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.2492234421
Short name T295
Test name
Test status
Simulation time 11930740 ps
CPU time 0.78 seconds
Started Jul 23 07:08:10 PM PDT 24
Finished Jul 23 07:08:12 PM PDT 24
Peak memory 205840 kb
Host smart-9fca64a6-6ed6-437f-9b2d-9c7c6a06150f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492234421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.2492234421
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.18779445
Short name T337
Test name
Test status
Simulation time 68559478 ps
CPU time 1.24 seconds
Started Jul 23 07:08:14 PM PDT 24
Finished Jul 23 07:08:16 PM PDT 24
Peak memory 208144 kb
Host smart-eb49d04d-3902-4f32-aefd-2d47ba2ceed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18779445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.18779445
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.2769799775
Short name T357
Test name
Test status
Simulation time 72731272 ps
CPU time 0.93 seconds
Started Jul 23 07:08:11 PM PDT 24
Finished Jul 23 07:08:13 PM PDT 24
Peak memory 205516 kb
Host smart-97a328d8-f8d6-48ff-85cc-a398214f8518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769799775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.2769799775
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.1785933153
Short name T360
Test name
Test status
Simulation time 3796260216 ps
CPU time 9.46 seconds
Started Jul 23 07:08:14 PM PDT 24
Finished Jul 23 07:08:24 PM PDT 24
Peak memory 235852 kb
Host smart-d439fcfb-58ef-48ab-8a9c-7c03eecec618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785933153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.1785933153
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.4169835601
Short name T764
Test name
Test status
Simulation time 123243394 ps
CPU time 0.71 seconds
Started Jul 23 07:08:23 PM PDT 24
Finished Jul 23 07:08:25 PM PDT 24
Peak memory 205016 kb
Host smart-b2cac91e-f825-4a64-a263-955739b8c1dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169835601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
4169835601
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.970736256
Short name T750
Test name
Test status
Simulation time 186473737 ps
CPU time 4.75 seconds
Started Jul 23 07:08:15 PM PDT 24
Finished Jul 23 07:08:21 PM PDT 24
Peak memory 224700 kb
Host smart-205defa1-c640-43a7-8bfb-2cb5cef541cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970736256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.970736256
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.4207406578
Short name T614
Test name
Test status
Simulation time 19820787 ps
CPU time 0.77 seconds
Started Jul 23 07:08:16 PM PDT 24
Finished Jul 23 07:08:18 PM PDT 24
Peak memory 205664 kb
Host smart-0e8b1638-fe07-4bc7-b478-4bff1cb1ca26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207406578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.4207406578
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.2907894117
Short name T1004
Test name
Test status
Simulation time 19157574268 ps
CPU time 66.66 seconds
Started Jul 23 07:08:23 PM PDT 24
Finished Jul 23 07:09:31 PM PDT 24
Peak memory 253408 kb
Host smart-7986e8d3-7f52-4ac7-9bb0-a73c2fe57f95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907894117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.2907894117
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.2629573805
Short name T932
Test name
Test status
Simulation time 13517846357 ps
CPU time 38.89 seconds
Started Jul 23 07:08:20 PM PDT 24
Finished Jul 23 07:09:01 PM PDT 24
Peak memory 249320 kb
Host smart-3d565224-325e-48e5-abb9-8979cacc5bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629573805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.2629573805
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.1108750480
Short name T473
Test name
Test status
Simulation time 2147028257 ps
CPU time 49.84 seconds
Started Jul 23 07:08:20 PM PDT 24
Finished Jul 23 07:09:12 PM PDT 24
Peak memory 256200 kb
Host smart-391a106f-52f3-4429-9271-ce9fa4c41e19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108750480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.1108750480
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.1436536813
Short name T414
Test name
Test status
Simulation time 421626509 ps
CPU time 7.77 seconds
Started Jul 23 07:08:22 PM PDT 24
Finished Jul 23 07:08:31 PM PDT 24
Peak memory 232892 kb
Host smart-b44af12f-5294-4dc3-ae9e-bb24bf538b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436536813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.1436536813
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.1758291379
Short name T869
Test name
Test status
Simulation time 79192720939 ps
CPU time 77.98 seconds
Started Jul 23 07:08:24 PM PDT 24
Finished Jul 23 07:09:44 PM PDT 24
Peak memory 241260 kb
Host smart-6ed88b85-1fe7-4218-bcea-6990841f0c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758291379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmd
s.1758291379
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_intercept.2047775500
Short name T216
Test name
Test status
Simulation time 1694565307 ps
CPU time 6.05 seconds
Started Jul 23 07:08:14 PM PDT 24
Finished Jul 23 07:08:22 PM PDT 24
Peak memory 232924 kb
Host smart-c92864b3-cc04-4f2b-a075-b43173994371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047775500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.2047775500
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.2252388678
Short name T796
Test name
Test status
Simulation time 589747088 ps
CPU time 6.17 seconds
Started Jul 23 07:08:15 PM PDT 24
Finished Jul 23 07:08:23 PM PDT 24
Peak memory 240816 kb
Host smart-9bc8ee0b-c0a5-4b2f-848d-e31f215323a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252388678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.2252388678
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.1731481291
Short name T653
Test name
Test status
Simulation time 10065173598 ps
CPU time 31.43 seconds
Started Jul 23 07:08:14 PM PDT 24
Finished Jul 23 07:08:47 PM PDT 24
Peak memory 233036 kb
Host smart-7738cfba-2398-4a34-9d09-62674b4c78bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731481291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.1731481291
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.298618466
Short name T238
Test name
Test status
Simulation time 331302292 ps
CPU time 4.73 seconds
Started Jul 23 07:08:14 PM PDT 24
Finished Jul 23 07:08:21 PM PDT 24
Peak memory 224700 kb
Host smart-35f450b2-57a1-438c-ae40-b1165bc658d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298618466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.298618466
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.2121794460
Short name T462
Test name
Test status
Simulation time 2304410480 ps
CPU time 21.47 seconds
Started Jul 23 07:08:21 PM PDT 24
Finished Jul 23 07:08:44 PM PDT 24
Peak memory 220300 kb
Host smart-09e737cf-87d4-4435-8491-dfd27208193f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2121794460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.2121794460
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.1026178129
Short name T123
Test name
Test status
Simulation time 12807552246 ps
CPU time 202.37 seconds
Started Jul 23 07:08:20 PM PDT 24
Finished Jul 23 07:11:43 PM PDT 24
Peak memory 265912 kb
Host smart-f2e9228b-fdac-4860-9792-55a2257a7d67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026178129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.1026178129
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.1824220944
Short name T283
Test name
Test status
Simulation time 954134801 ps
CPU time 5.57 seconds
Started Jul 23 07:08:15 PM PDT 24
Finished Jul 23 07:08:23 PM PDT 24
Peak memory 219420 kb
Host smart-48296188-d979-482b-b298-aa4f82fe5d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824220944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.1824220944
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.1917948183
Short name T369
Test name
Test status
Simulation time 2047155686 ps
CPU time 3.92 seconds
Started Jul 23 07:08:16 PM PDT 24
Finished Jul 23 07:08:21 PM PDT 24
Peak memory 216424 kb
Host smart-ac7feb56-d34c-49fe-be1d-595667c81055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917948183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.1917948183
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.2636125251
Short name T787
Test name
Test status
Simulation time 38571752 ps
CPU time 1.75 seconds
Started Jul 23 07:08:14 PM PDT 24
Finished Jul 23 07:08:18 PM PDT 24
Peak memory 216440 kb
Host smart-af20450d-9340-42c4-a58c-e0f86ff90a2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636125251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.2636125251
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.1025006518
Short name T598
Test name
Test status
Simulation time 18887975 ps
CPU time 0.75 seconds
Started Jul 23 07:08:15 PM PDT 24
Finished Jul 23 07:08:18 PM PDT 24
Peak memory 206124 kb
Host smart-9fde1ddc-a5e7-4a66-9d8d-46e3a42389f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025006518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.1025006518
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.288143154
Short name T543
Test name
Test status
Simulation time 1833942009 ps
CPU time 8.1 seconds
Started Jul 23 07:08:17 PM PDT 24
Finished Jul 23 07:08:26 PM PDT 24
Peak memory 232844 kb
Host smart-aed2ea2d-146d-4068-8dd8-161d1145c97b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288143154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.288143154
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.989987028
Short name T806
Test name
Test status
Simulation time 14213810 ps
CPU time 0.78 seconds
Started Jul 23 07:08:22 PM PDT 24
Finished Jul 23 07:08:24 PM PDT 24
Peak memory 205052 kb
Host smart-14c31a9d-9546-4143-bb50-bbcd05f285d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989987028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.989987028
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.3412896117
Short name T215
Test name
Test status
Simulation time 276637525 ps
CPU time 2.12 seconds
Started Jul 23 07:08:20 PM PDT 24
Finished Jul 23 07:08:23 PM PDT 24
Peak memory 224564 kb
Host smart-afefc5f0-c286-41f2-90bc-9c930951cff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412896117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.3412896117
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.2519676742
Short name T612
Test name
Test status
Simulation time 18648365 ps
CPU time 0.76 seconds
Started Jul 23 07:08:19 PM PDT 24
Finished Jul 23 07:08:21 PM PDT 24
Peak memory 207244 kb
Host smart-9f5ef670-3beb-4aa3-87f4-aead8b543ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519676742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.2519676742
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.212513330
Short name T915
Test name
Test status
Simulation time 41164674671 ps
CPU time 153.87 seconds
Started Jul 23 07:08:20 PM PDT 24
Finished Jul 23 07:10:56 PM PDT 24
Peak memory 256280 kb
Host smart-5dfc952b-5a4d-4bdc-a94c-ec099faf82e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212513330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.212513330
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.1680382741
Short name T227
Test name
Test status
Simulation time 25038700835 ps
CPU time 232.36 seconds
Started Jul 23 07:08:20 PM PDT 24
Finished Jul 23 07:12:14 PM PDT 24
Peak memory 249468 kb
Host smart-7376ed78-260f-4e66-a247-8138f1ed5b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680382741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.1680382741
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.905347062
Short name T115
Test name
Test status
Simulation time 465451608 ps
CPU time 11.61 seconds
Started Jul 23 07:08:20 PM PDT 24
Finished Jul 23 07:08:34 PM PDT 24
Peak memory 239068 kb
Host smart-eb34c1a7-731b-4978-beb3-5f4728cbd240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905347062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.905347062
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.2712888413
Short name T499
Test name
Test status
Simulation time 96001660397 ps
CPU time 169.08 seconds
Started Jul 23 07:08:25 PM PDT 24
Finished Jul 23 07:11:15 PM PDT 24
Peak memory 252236 kb
Host smart-11d4a203-4584-4db1-8441-bcec6735b98e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712888413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmd
s.2712888413
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_intercept.3656509957
Short name T861
Test name
Test status
Simulation time 767373090 ps
CPU time 5.2 seconds
Started Jul 23 07:08:22 PM PDT 24
Finished Jul 23 07:08:28 PM PDT 24
Peak memory 232848 kb
Host smart-b99efa94-0798-435d-8313-1ddef454077b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656509957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.3656509957
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.3856226504
Short name T474
Test name
Test status
Simulation time 557540414 ps
CPU time 7.94 seconds
Started Jul 23 07:08:24 PM PDT 24
Finished Jul 23 07:08:34 PM PDT 24
Peak memory 232884 kb
Host smart-ee9eb978-0e7f-42bc-9569-131f4a13d1e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856226504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.3856226504
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.3954368039
Short name T926
Test name
Test status
Simulation time 10210373771 ps
CPU time 10.03 seconds
Started Jul 23 07:08:24 PM PDT 24
Finished Jul 23 07:08:36 PM PDT 24
Peak memory 232992 kb
Host smart-a1642ff7-d123-484f-a99e-85bc031a7235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954368039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.3954368039
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.3360548363
Short name T469
Test name
Test status
Simulation time 18670018292 ps
CPU time 11.97 seconds
Started Jul 23 07:08:20 PM PDT 24
Finished Jul 23 07:08:34 PM PDT 24
Peak memory 224676 kb
Host smart-e36706a4-92c9-44e8-8505-2380611e7201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360548363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.3360548363
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.3026697054
Short name T133
Test name
Test status
Simulation time 6377128420 ps
CPU time 9.34 seconds
Started Jul 23 07:08:22 PM PDT 24
Finished Jul 23 07:08:32 PM PDT 24
Peak memory 223356 kb
Host smart-6b62338e-e575-46bf-8509-73e47373382b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3026697054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.3026697054
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.138896994
Short name T14
Test name
Test status
Simulation time 56335653 ps
CPU time 1.07 seconds
Started Jul 23 07:08:24 PM PDT 24
Finished Jul 23 07:08:26 PM PDT 24
Peak memory 207856 kb
Host smart-b03fcc7b-30ab-4da5-bb38-0f171940d992
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138896994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stres
s_all.138896994
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.3179404960
Short name T671
Test name
Test status
Simulation time 1250447282 ps
CPU time 2.63 seconds
Started Jul 23 07:08:22 PM PDT 24
Finished Jul 23 07:08:26 PM PDT 24
Peak memory 216428 kb
Host smart-ca2781a3-a016-4bd5-bc77-4234d6bbc49c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179404960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.3179404960
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.3142446367
Short name T449
Test name
Test status
Simulation time 5462128149 ps
CPU time 14.99 seconds
Started Jul 23 07:08:20 PM PDT 24
Finished Jul 23 07:08:36 PM PDT 24
Peak memory 216416 kb
Host smart-efaf3d5f-5ec8-471d-8179-eb8fa0acd1bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142446367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.3142446367
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.106751233
Short name T853
Test name
Test status
Simulation time 24444741 ps
CPU time 0.93 seconds
Started Jul 23 07:08:22 PM PDT 24
Finished Jul 23 07:08:24 PM PDT 24
Peak memory 207104 kb
Host smart-95661a6e-93e6-48a9-9f38-4caa475ad8a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106751233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.106751233
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.3264764545
Short name T735
Test name
Test status
Simulation time 317287872 ps
CPU time 1.06 seconds
Started Jul 23 07:08:23 PM PDT 24
Finished Jul 23 07:08:26 PM PDT 24
Peak memory 207156 kb
Host smart-352a8963-028b-48b1-bb3b-9d994849e7e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264764545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.3264764545
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.1212278617
Short name T836
Test name
Test status
Simulation time 2235512468 ps
CPU time 5.54 seconds
Started Jul 23 07:08:20 PM PDT 24
Finished Jul 23 07:08:27 PM PDT 24
Peak memory 232892 kb
Host smart-caac06d8-ed76-4ea3-92df-03a6abec0133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212278617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.1212278617
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.483801159
Short name T505
Test name
Test status
Simulation time 17494398 ps
CPU time 0.74 seconds
Started Jul 23 07:08:25 PM PDT 24
Finished Jul 23 07:08:27 PM PDT 24
Peak memory 205528 kb
Host smart-3770a68b-195b-4d37-85b9-0f938afbdc31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483801159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.483801159
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.3941766979
Short name T244
Test name
Test status
Simulation time 4420278430 ps
CPU time 10.88 seconds
Started Jul 23 07:08:27 PM PDT 24
Finished Jul 23 07:08:40 PM PDT 24
Peak memory 232888 kb
Host smart-c3b23343-52fd-4048-857c-c14745802213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941766979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.3941766979
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.3910832504
Short name T833
Test name
Test status
Simulation time 169012446 ps
CPU time 0.73 seconds
Started Jul 23 07:08:26 PM PDT 24
Finished Jul 23 07:08:28 PM PDT 24
Peak memory 205572 kb
Host smart-5e09a014-ddc5-4c88-ab10-41f3621c9acd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910832504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.3910832504
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.2041149122
Short name T191
Test name
Test status
Simulation time 134053900707 ps
CPU time 259.76 seconds
Started Jul 23 07:08:25 PM PDT 24
Finished Jul 23 07:12:46 PM PDT 24
Peak memory 255668 kb
Host smart-10ebc2c4-eb40-4070-91a7-e2982d4a3637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041149122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.2041149122
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.3253874012
Short name T167
Test name
Test status
Simulation time 61475645532 ps
CPU time 142.68 seconds
Started Jul 23 07:08:25 PM PDT 24
Finished Jul 23 07:10:49 PM PDT 24
Peak memory 257572 kb
Host smart-31eb5a11-be5e-4bb7-94d6-187134d3a3f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253874012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.3253874012
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.540475321
Short name T199
Test name
Test status
Simulation time 5709759399 ps
CPU time 79.68 seconds
Started Jul 23 07:08:25 PM PDT 24
Finished Jul 23 07:09:46 PM PDT 24
Peak memory 241176 kb
Host smart-073d68a8-612b-4d78-9afb-cdc7c317e420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540475321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idle
.540475321
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.3358949726
Short name T390
Test name
Test status
Simulation time 6997633682 ps
CPU time 30.37 seconds
Started Jul 23 07:08:27 PM PDT 24
Finished Jul 23 07:08:59 PM PDT 24
Peak memory 232892 kb
Host smart-eb447de9-3fe5-4dc5-a32d-42b67d6199f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358949726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.3358949726
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.3028470607
Short name T172
Test name
Test status
Simulation time 559387279510 ps
CPU time 310.71 seconds
Started Jul 23 07:08:28 PM PDT 24
Finished Jul 23 07:13:40 PM PDT 24
Peak memory 265556 kb
Host smart-3a4a7c45-e3a2-46a9-ac28-d4f6d20652ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028470607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmd
s.3028470607
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.3940153289
Short name T221
Test name
Test status
Simulation time 596460900 ps
CPU time 4.42 seconds
Started Jul 23 07:08:26 PM PDT 24
Finished Jul 23 07:08:32 PM PDT 24
Peak memory 219972 kb
Host smart-a8ce20c1-50f4-4493-a5fa-f49a3c11d54b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940153289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.3940153289
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.1185623166
Short name T873
Test name
Test status
Simulation time 5373928337 ps
CPU time 47.31 seconds
Started Jul 23 07:08:29 PM PDT 24
Finished Jul 23 07:09:17 PM PDT 24
Peak memory 224724 kb
Host smart-61b89fbb-21cd-4b8e-ad72-1d253e169eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185623166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.1185623166
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.510761248
Short name T1
Test name
Test status
Simulation time 2459230461 ps
CPU time 5.9 seconds
Started Jul 23 07:08:27 PM PDT 24
Finished Jul 23 07:08:35 PM PDT 24
Peak memory 232940 kb
Host smart-fcf37efd-223a-4882-ba56-697288ff13f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510761248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swap
.510761248
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.538924008
Short name T887
Test name
Test status
Simulation time 67189386 ps
CPU time 2.42 seconds
Started Jul 23 07:08:28 PM PDT 24
Finished Jul 23 07:08:32 PM PDT 24
Peak memory 232520 kb
Host smart-ffb650bb-970c-4c64-85f6-65bf5b356974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538924008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.538924008
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.2632412444
Short name T482
Test name
Test status
Simulation time 2398988049 ps
CPU time 5.74 seconds
Started Jul 23 07:08:26 PM PDT 24
Finished Jul 23 07:08:33 PM PDT 24
Peak memory 220484 kb
Host smart-4f57c099-9408-4643-b9ac-8ec6afbe9704
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2632412444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.2632412444
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.3139960775
Short name T278
Test name
Test status
Simulation time 93567656177 ps
CPU time 211.07 seconds
Started Jul 23 07:08:27 PM PDT 24
Finished Jul 23 07:11:59 PM PDT 24
Peak memory 249832 kb
Host smart-111b3196-9320-481b-8deb-1e61a39e0eea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139960775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.3139960775
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.3382686464
Short name T549
Test name
Test status
Simulation time 526120054 ps
CPU time 7.54 seconds
Started Jul 23 07:08:27 PM PDT 24
Finished Jul 23 07:08:37 PM PDT 24
Peak memory 216672 kb
Host smart-28836cfd-b148-43e5-bddf-b3af51c7f945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382686464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.3382686464
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.3017106064
Short name T483
Test name
Test status
Simulation time 20142119572 ps
CPU time 15.6 seconds
Started Jul 23 07:08:25 PM PDT 24
Finished Jul 23 07:08:42 PM PDT 24
Peak memory 216496 kb
Host smart-16ad0216-6964-4642-a0b9-7fb72dc8327c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017106064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.3017106064
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.2476121865
Short name T620
Test name
Test status
Simulation time 67937845 ps
CPU time 1.94 seconds
Started Jul 23 07:08:26 PM PDT 24
Finished Jul 23 07:08:30 PM PDT 24
Peak memory 216452 kb
Host smart-18bdd38e-c7ee-4cd9-a7c1-473b0c0695e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476121865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.2476121865
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.727277369
Short name T866
Test name
Test status
Simulation time 15766289 ps
CPU time 0.73 seconds
Started Jul 23 07:08:27 PM PDT 24
Finished Jul 23 07:08:29 PM PDT 24
Peak memory 206460 kb
Host smart-75a2e4b1-d780-4cd9-b5b2-21a39989a505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727277369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.727277369
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.478282004
Short name T183
Test name
Test status
Simulation time 7056127413 ps
CPU time 12.21 seconds
Started Jul 23 07:08:28 PM PDT 24
Finished Jul 23 07:08:41 PM PDT 24
Peak memory 232864 kb
Host smart-05083609-72a8-4a0b-8080-b59cc2cb3d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478282004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.478282004
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.3954535434
Short name T859
Test name
Test status
Simulation time 26994318 ps
CPU time 0.75 seconds
Started Jul 23 07:08:32 PM PDT 24
Finished Jul 23 07:08:34 PM PDT 24
Peak memory 205032 kb
Host smart-8d7720bc-b5e8-4154-bd2f-8bb2b8498833
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954535434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
3954535434
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.3050242236
Short name T441
Test name
Test status
Simulation time 55469733 ps
CPU time 3.03 seconds
Started Jul 23 07:08:33 PM PDT 24
Finished Jul 23 07:08:38 PM PDT 24
Peak memory 232844 kb
Host smart-80b0e8d7-0e0b-492a-97ed-1e9cc7e27fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050242236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.3050242236
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.3637517865
Short name T408
Test name
Test status
Simulation time 29557567 ps
CPU time 0.79 seconds
Started Jul 23 07:08:27 PM PDT 24
Finished Jul 23 07:08:29 PM PDT 24
Peak memory 206740 kb
Host smart-617f4630-b5e5-43a6-bf4a-685d28ddca65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637517865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.3637517865
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.1706680636
Short name T662
Test name
Test status
Simulation time 123653545876 ps
CPU time 213.78 seconds
Started Jul 23 07:08:34 PM PDT 24
Finished Jul 23 07:12:09 PM PDT 24
Peak memory 254248 kb
Host smart-5ed04967-eef4-4f90-90dd-d54607f9852a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706680636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.1706680636
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.505369508
Short name T49
Test name
Test status
Simulation time 22298339709 ps
CPU time 207.07 seconds
Started Jul 23 07:08:32 PM PDT 24
Finished Jul 23 07:12:00 PM PDT 24
Peak memory 251168 kb
Host smart-611d6596-dbb8-440c-bd04-c750c0cfd9ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505369508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idle
.505369508
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.3470833284
Short name T695
Test name
Test status
Simulation time 864758702 ps
CPU time 6.6 seconds
Started Jul 23 07:08:35 PM PDT 24
Finished Jul 23 07:08:43 PM PDT 24
Peak memory 233368 kb
Host smart-93e20639-833b-4624-9380-ea3abca1a6e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470833284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.3470833284
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.3735562348
Short name T185
Test name
Test status
Simulation time 53548686498 ps
CPU time 66.79 seconds
Started Jul 23 07:08:31 PM PDT 24
Finished Jul 23 07:09:38 PM PDT 24
Peak memory 264656 kb
Host smart-750ed391-d2eb-45dd-95fb-f60c00c686e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735562348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmd
s.3735562348
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_intercept.93494659
Short name T748
Test name
Test status
Simulation time 305413259 ps
CPU time 2.69 seconds
Started Jul 23 07:08:26 PM PDT 24
Finished Jul 23 07:08:30 PM PDT 24
Peak memory 232836 kb
Host smart-3319b354-975c-4408-8a2a-d65538add9d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93494659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.93494659
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.313868738
Short name T814
Test name
Test status
Simulation time 11713559966 ps
CPU time 39.41 seconds
Started Jul 23 07:08:32 PM PDT 24
Finished Jul 23 07:09:12 PM PDT 24
Peak memory 232940 kb
Host smart-6d920adc-b75b-4e0a-8beb-bbbea9dac4e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313868738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.313868738
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.2818694731
Short name T595
Test name
Test status
Simulation time 34772417414 ps
CPU time 22.51 seconds
Started Jul 23 07:08:26 PM PDT 24
Finished Jul 23 07:08:51 PM PDT 24
Peak memory 232872 kb
Host smart-a4e136ab-edcd-4417-8926-de045c0115dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818694731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.2818694731
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.2618908946
Short name T741
Test name
Test status
Simulation time 984579017 ps
CPU time 5.3 seconds
Started Jul 23 07:08:29 PM PDT 24
Finished Jul 23 07:08:35 PM PDT 24
Peak memory 224736 kb
Host smart-c3269668-835e-40a0-a396-32f3d493d3a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618908946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.2618908946
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.372832665
Short name T427
Test name
Test status
Simulation time 1945952346 ps
CPU time 15.87 seconds
Started Jul 23 07:08:32 PM PDT 24
Finished Jul 23 07:08:49 PM PDT 24
Peak memory 220248 kb
Host smart-ae5d694f-ba3a-4a57-8e6b-cfaa17b6196a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=372832665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dire
ct.372832665
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.638226691
Short name T17
Test name
Test status
Simulation time 111219839151 ps
CPU time 201.01 seconds
Started Jul 23 07:08:30 PM PDT 24
Finished Jul 23 07:11:52 PM PDT 24
Peak memory 252388 kb
Host smart-935ab263-ddf0-4772-8b57-00dd1ddc4e6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638226691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stres
s_all.638226691
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.65321105
Short name T280
Test name
Test status
Simulation time 3325984814 ps
CPU time 24.9 seconds
Started Jul 23 07:08:28 PM PDT 24
Finished Jul 23 07:08:54 PM PDT 24
Peak memory 216544 kb
Host smart-5ba01eb3-4237-41bf-adf2-c3c69a5c30b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65321105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.65321105
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.2964979689
Short name T371
Test name
Test status
Simulation time 15488753022 ps
CPU time 11.03 seconds
Started Jul 23 07:08:27 PM PDT 24
Finished Jul 23 07:08:40 PM PDT 24
Peak memory 216480 kb
Host smart-b28c20aa-15fa-4e05-a207-66a249e58e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964979689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.2964979689
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.611210481
Short name T292
Test name
Test status
Simulation time 225834358 ps
CPU time 5.12 seconds
Started Jul 23 07:08:25 PM PDT 24
Finished Jul 23 07:08:32 PM PDT 24
Peak memory 216484 kb
Host smart-9cc7d64d-9883-498b-bcc3-89a7775c6789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611210481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.611210481
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.1403398766
Short name T450
Test name
Test status
Simulation time 75220469 ps
CPU time 0.77 seconds
Started Jul 23 07:08:27 PM PDT 24
Finished Jul 23 07:08:29 PM PDT 24
Peak memory 206120 kb
Host smart-6dc09b02-8773-4d08-872e-e72059d59f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403398766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.1403398766
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.2316236248
Short name T8
Test name
Test status
Simulation time 5457424658 ps
CPU time 6.09 seconds
Started Jul 23 07:08:34 PM PDT 24
Finished Jul 23 07:08:42 PM PDT 24
Peak memory 224728 kb
Host smart-a9d78314-e5ad-4f22-af5b-3b660ca8e382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316236248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.2316236248
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.1619100121
Short name T445
Test name
Test status
Simulation time 16424303 ps
CPU time 0.7 seconds
Started Jul 23 07:08:39 PM PDT 24
Finished Jul 23 07:08:41 PM PDT 24
Peak memory 204996 kb
Host smart-a51d2158-825f-4d24-929b-c03ff3307df8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619100121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
1619100121
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.4207383859
Short name T881
Test name
Test status
Simulation time 12007495531 ps
CPU time 15.52 seconds
Started Jul 23 07:08:29 PM PDT 24
Finished Jul 23 07:08:46 PM PDT 24
Peak memory 232820 kb
Host smart-eea7734f-36b2-4e25-a915-2117f9fa62cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207383859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.4207383859
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.797860830
Short name T387
Test name
Test status
Simulation time 33786632 ps
CPU time 0.81 seconds
Started Jul 23 07:08:34 PM PDT 24
Finished Jul 23 07:08:36 PM PDT 24
Peak memory 206700 kb
Host smart-253192d7-3476-4f52-ab79-e4a476dcf410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797860830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.797860830
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.909761010
Short name T797
Test name
Test status
Simulation time 20748504 ps
CPU time 0.77 seconds
Started Jul 23 07:08:32 PM PDT 24
Finished Jul 23 07:08:34 PM PDT 24
Peak memory 215924 kb
Host smart-f76e3aa0-9aa7-422c-86ae-3adcb112fbc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909761010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.909761010
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.3336137299
Short name T860
Test name
Test status
Simulation time 52023466726 ps
CPU time 85.27 seconds
Started Jul 23 07:08:33 PM PDT 24
Finished Jul 23 07:09:59 PM PDT 24
Peak memory 256044 kb
Host smart-b02858fe-a65a-4be9-90b8-07f84eb6a722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336137299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.3336137299
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.1276931450
Short name T725
Test name
Test status
Simulation time 106107559412 ps
CPU time 294.03 seconds
Started Jul 23 07:08:32 PM PDT 24
Finished Jul 23 07:13:28 PM PDT 24
Peak memory 254768 kb
Host smart-2cdd5ecc-34cb-4c1a-86cd-8fb48621f853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276931450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.1276931450
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.3358764835
Short name T818
Test name
Test status
Simulation time 3659249852 ps
CPU time 16.94 seconds
Started Jul 23 07:08:32 PM PDT 24
Finished Jul 23 07:08:49 PM PDT 24
Peak memory 232936 kb
Host smart-4ffed106-41aa-4402-9ed9-070c20d73485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358764835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.3358764835
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.3048662577
Short name T997
Test name
Test status
Simulation time 1277048035 ps
CPU time 14.75 seconds
Started Jul 23 07:08:31 PM PDT 24
Finished Jul 23 07:08:46 PM PDT 24
Peak memory 236712 kb
Host smart-568e7d5c-f38c-4477-a664-428f51b8369d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048662577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmd
s.3048662577
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_intercept.2596939751
Short name T709
Test name
Test status
Simulation time 68274365 ps
CPU time 2.6 seconds
Started Jul 23 07:08:34 PM PDT 24
Finished Jul 23 07:08:38 PM PDT 24
Peak memory 224668 kb
Host smart-77a73a07-755d-4216-850e-80eab5cf1268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596939751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.2596939751
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.1379934494
Short name T544
Test name
Test status
Simulation time 4932448082 ps
CPU time 24.66 seconds
Started Jul 23 07:08:30 PM PDT 24
Finished Jul 23 07:08:55 PM PDT 24
Peak memory 224768 kb
Host smart-35cf0167-6a44-4ab4-999f-67167c1d6cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379934494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.1379934494
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.4076714099
Short name T228
Test name
Test status
Simulation time 246585617 ps
CPU time 2.34 seconds
Started Jul 23 07:08:35 PM PDT 24
Finished Jul 23 07:08:38 PM PDT 24
Peak memory 232804 kb
Host smart-f1c4d544-07ec-4593-8b6f-ef0da943d219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076714099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.4076714099
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.613432156
Short name T608
Test name
Test status
Simulation time 1712854017 ps
CPU time 12.98 seconds
Started Jul 23 07:08:33 PM PDT 24
Finished Jul 23 07:08:47 PM PDT 24
Peak memory 232928 kb
Host smart-829ecb68-95c5-404f-a80e-312e7fa5f8eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613432156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.613432156
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.3876254479
Short name T590
Test name
Test status
Simulation time 1174765809 ps
CPU time 11.6 seconds
Started Jul 23 07:08:31 PM PDT 24
Finished Jul 23 07:08:44 PM PDT 24
Peak memory 222864 kb
Host smart-9ce0ea29-a0c5-4cb4-aae4-694029a3be7b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3876254479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.3876254479
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.3173834244
Short name T147
Test name
Test status
Simulation time 2144220820 ps
CPU time 52.11 seconds
Started Jul 23 07:08:37 PM PDT 24
Finished Jul 23 07:09:30 PM PDT 24
Peak memory 256100 kb
Host smart-97a5b362-829c-4d76-88e8-9a2a24f94fb2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173834244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.3173834244
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.2855814323
Short name T286
Test name
Test status
Simulation time 113477266073 ps
CPU time 42.36 seconds
Started Jul 23 07:08:34 PM PDT 24
Finished Jul 23 07:09:17 PM PDT 24
Peak memory 216476 kb
Host smart-94519433-d777-4164-960f-9ce8db358776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855814323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.2855814323
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.2388532055
Short name T682
Test name
Test status
Simulation time 3159997674 ps
CPU time 11.67 seconds
Started Jul 23 07:08:32 PM PDT 24
Finished Jul 23 07:08:44 PM PDT 24
Peak memory 216520 kb
Host smart-5402315e-623b-4619-ac8d-8222dc36312c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388532055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.2388532055
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.3464009007
Short name T511
Test name
Test status
Simulation time 189179832 ps
CPU time 2.82 seconds
Started Jul 23 07:08:30 PM PDT 24
Finished Jul 23 07:08:33 PM PDT 24
Peak memory 216472 kb
Host smart-d1b1f656-230e-4ec7-b8a8-ff0b1689e7af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464009007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.3464009007
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.3033635225
Short name T570
Test name
Test status
Simulation time 169373766 ps
CPU time 0.93 seconds
Started Jul 23 07:08:33 PM PDT 24
Finished Jul 23 07:08:35 PM PDT 24
Peak memory 207140 kb
Host smart-b82af13c-8253-4cf3-81d3-72fdfc31476d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033635225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.3033635225
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.789755587
Short name T542
Test name
Test status
Simulation time 76095927 ps
CPU time 2.75 seconds
Started Jul 23 07:08:33 PM PDT 24
Finished Jul 23 07:08:37 PM PDT 24
Peak memory 232852 kb
Host smart-a8d038e8-f8dc-46df-802f-f742ffa22f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789755587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.789755587
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.1913788061
Short name T822
Test name
Test status
Simulation time 19808475 ps
CPU time 0.72 seconds
Started Jul 23 07:08:38 PM PDT 24
Finished Jul 23 07:08:40 PM PDT 24
Peak memory 205588 kb
Host smart-5fc2f21d-a9d1-4706-aa11-eadf5821d7ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913788061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
1913788061
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.3236688950
Short name T639
Test name
Test status
Simulation time 114528913 ps
CPU time 3.35 seconds
Started Jul 23 07:08:38 PM PDT 24
Finished Jul 23 07:08:43 PM PDT 24
Peak memory 232884 kb
Host smart-46937e49-9f26-4336-8a28-ad4a0a47e5b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236688950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.3236688950
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.3573044854
Short name T628
Test name
Test status
Simulation time 71113582 ps
CPU time 0.77 seconds
Started Jul 23 07:08:35 PM PDT 24
Finished Jul 23 07:08:37 PM PDT 24
Peak memory 207048 kb
Host smart-90f0e857-3d88-4cdb-8d40-2bca94471a86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573044854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.3573044854
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.922676911
Short name T264
Test name
Test status
Simulation time 84268395910 ps
CPU time 81.26 seconds
Started Jul 23 07:08:35 PM PDT 24
Finished Jul 23 07:09:58 PM PDT 24
Peak memory 251356 kb
Host smart-092cbec8-4f4d-4408-9c30-9e03e3967d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922676911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.922676911
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.1142523984
Short name T493
Test name
Test status
Simulation time 11645273350 ps
CPU time 101.74 seconds
Started Jul 23 07:08:37 PM PDT 24
Finished Jul 23 07:10:20 PM PDT 24
Peak memory 257160 kb
Host smart-57de51ef-deb2-4cbf-9cd4-86121e6f40f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142523984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.1142523984
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.1267346417
Short name T754
Test name
Test status
Simulation time 58400248049 ps
CPU time 247.96 seconds
Started Jul 23 07:08:36 PM PDT 24
Finished Jul 23 07:12:45 PM PDT 24
Peak memory 266484 kb
Host smart-8f12fcb6-5206-498b-aa54-78c70c7abec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267346417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.1267346417
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.3717329632
Short name T940
Test name
Test status
Simulation time 790027936 ps
CPU time 7.41 seconds
Started Jul 23 07:08:36 PM PDT 24
Finished Jul 23 07:08:45 PM PDT 24
Peak memory 232796 kb
Host smart-9ca20d69-95f9-4f6d-b313-85a5b1b4d0df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717329632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.3717329632
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.1239910672
Short name T489
Test name
Test status
Simulation time 116962096 ps
CPU time 0.77 seconds
Started Jul 23 07:08:38 PM PDT 24
Finished Jul 23 07:08:40 PM PDT 24
Peak memory 216156 kb
Host smart-434ef7d0-9e78-4275-b36f-7dcf04cb49be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239910672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmd
s.1239910672
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_intercept.3967004295
Short name T636
Test name
Test status
Simulation time 120059255 ps
CPU time 2.2 seconds
Started Jul 23 07:08:39 PM PDT 24
Finished Jul 23 07:08:43 PM PDT 24
Peak memory 232544 kb
Host smart-197a8ace-f03f-4c29-bce5-5c33209f3f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967004295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.3967004295
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.2875057037
Short name T685
Test name
Test status
Simulation time 13787012985 ps
CPU time 115.19 seconds
Started Jul 23 07:08:38 PM PDT 24
Finished Jul 23 07:10:34 PM PDT 24
Peak memory 240764 kb
Host smart-fd92a75c-ebbf-45d1-8804-4e1b067fa0f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875057037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.2875057037
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.1989618125
Short name T39
Test name
Test status
Simulation time 38905722656 ps
CPU time 12.87 seconds
Started Jul 23 07:08:39 PM PDT 24
Finished Jul 23 07:08:53 PM PDT 24
Peak memory 237780 kb
Host smart-6e1198db-0a4b-44d8-a085-cc98287b079a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989618125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.1989618125
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.2661290423
Short name T596
Test name
Test status
Simulation time 439581233 ps
CPU time 2.36 seconds
Started Jul 23 07:08:37 PM PDT 24
Finished Jul 23 07:08:40 PM PDT 24
Peak memory 224696 kb
Host smart-077958fd-0d57-439f-a968-c3db3c6aeacf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661290423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.2661290423
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.4286658039
Short name T732
Test name
Test status
Simulation time 3448177854 ps
CPU time 4.46 seconds
Started Jul 23 07:08:38 PM PDT 24
Finished Jul 23 07:08:44 PM PDT 24
Peak memory 223036 kb
Host smart-671149fa-89e0-4fc2-94e3-33aa36e47d84
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4286658039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.4286658039
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.1627511670
Short name T775
Test name
Test status
Simulation time 302639685792 ps
CPU time 642.83 seconds
Started Jul 23 07:08:40 PM PDT 24
Finished Jul 23 07:19:24 PM PDT 24
Peak memory 289176 kb
Host smart-8f11a85c-44d7-4528-a907-c03d2c6b6d66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627511670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.1627511670
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.1463628758
Short name T406
Test name
Test status
Simulation time 3689847523 ps
CPU time 12.42 seconds
Started Jul 23 07:08:37 PM PDT 24
Finished Jul 23 07:08:51 PM PDT 24
Peak memory 216448 kb
Host smart-b266d1c9-a3fa-406c-b43e-78c62cdd3692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463628758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.1463628758
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.1862710841
Short name T320
Test name
Test status
Simulation time 1556519505 ps
CPU time 3.06 seconds
Started Jul 23 07:08:40 PM PDT 24
Finished Jul 23 07:08:44 PM PDT 24
Peak memory 216452 kb
Host smart-c2688bb2-0145-4f55-9594-7a6824c70881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862710841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.1862710841
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.1123967706
Short name T331
Test name
Test status
Simulation time 189475818 ps
CPU time 0.88 seconds
Started Jul 23 07:08:37 PM PDT 24
Finished Jul 23 07:08:39 PM PDT 24
Peak memory 206772 kb
Host smart-48823ced-4c09-4f6f-9ba9-87cdbc0de3be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123967706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.1123967706
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.2896160663
Short name T823
Test name
Test status
Simulation time 13556774 ps
CPU time 0.69 seconds
Started Jul 23 07:08:36 PM PDT 24
Finished Jul 23 07:08:38 PM PDT 24
Peak memory 205828 kb
Host smart-70211878-dd7b-42ee-9621-9440f2fefa90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896160663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.2896160663
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.1191464630
Short name T13
Test name
Test status
Simulation time 1350077632 ps
CPU time 8.95 seconds
Started Jul 23 07:08:34 PM PDT 24
Finished Jul 23 07:08:44 PM PDT 24
Peak memory 240552 kb
Host smart-9ea462f4-13f3-4c0f-8a37-520ede72f98e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191464630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.1191464630
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.979995838
Short name T616
Test name
Test status
Simulation time 12849399 ps
CPU time 0.71 seconds
Started Jul 23 07:05:35 PM PDT 24
Finished Jul 23 07:05:37 PM PDT 24
Peak memory 205596 kb
Host smart-4c667abd-bcdb-4fe4-8c41-a17ab46f9cd8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979995838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.979995838
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.3685441806
Short name T587
Test name
Test status
Simulation time 946785856 ps
CPU time 11.52 seconds
Started Jul 23 07:05:21 PM PDT 24
Finished Jul 23 07:05:34 PM PDT 24
Peak memory 232872 kb
Host smart-640acc67-8bf4-4fca-95e3-6928795cc5e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685441806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.3685441806
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.2918244527
Short name T296
Test name
Test status
Simulation time 17882759 ps
CPU time 0.78 seconds
Started Jul 23 07:05:19 PM PDT 24
Finished Jul 23 07:05:22 PM PDT 24
Peak memory 206740 kb
Host smart-7ff80ac6-2ec9-4a96-a13d-a9e651b499f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918244527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.2918244527
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.1224402303
Short name T964
Test name
Test status
Simulation time 28680215382 ps
CPU time 58.33 seconds
Started Jul 23 07:05:24 PM PDT 24
Finished Jul 23 07:06:23 PM PDT 24
Peak memory 251660 kb
Host smart-5c142eb4-cf43-4408-b14f-4db9bfa16dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224402303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.1224402303
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.130561094
Short name T846
Test name
Test status
Simulation time 5188729466 ps
CPU time 75.76 seconds
Started Jul 23 07:05:26 PM PDT 24
Finished Jul 23 07:06:43 PM PDT 24
Peak memory 249392 kb
Host smart-a28ea632-39e5-4bd5-a45f-74cba6808b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130561094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.130561094
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.285147591
Short name T230
Test name
Test status
Simulation time 100237437581 ps
CPU time 242.3 seconds
Started Jul 23 07:05:36 PM PDT 24
Finished Jul 23 07:09:39 PM PDT 24
Peak memory 255268 kb
Host smart-c52c3f3e-6de4-45e9-ab41-aef971a021e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285147591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle.
285147591
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.2971928976
Short name T730
Test name
Test status
Simulation time 1352972485 ps
CPU time 5.65 seconds
Started Jul 23 07:05:22 PM PDT 24
Finished Jul 23 07:05:29 PM PDT 24
Peak memory 241056 kb
Host smart-77a75ce0-6a2c-46ed-a989-af5eba88df33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971928976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.2971928976
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.4239530265
Short name T935
Test name
Test status
Simulation time 119202833155 ps
CPU time 235.83 seconds
Started Jul 23 07:05:20 PM PDT 24
Finished Jul 23 07:09:18 PM PDT 24
Peak memory 265644 kb
Host smart-4b887d09-10ba-45ec-b5cd-9b235c5e1bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239530265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds
.4239530265
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_intercept.3183024270
Short name T384
Test name
Test status
Simulation time 649573532 ps
CPU time 5.37 seconds
Started Jul 23 07:05:18 PM PDT 24
Finished Jul 23 07:05:26 PM PDT 24
Peak memory 224648 kb
Host smart-49f5c1a8-7c0e-4fe5-bb8e-a5e9356d6141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183024270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.3183024270
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.1370113451
Short name T658
Test name
Test status
Simulation time 4141684907 ps
CPU time 22.21 seconds
Started Jul 23 07:05:18 PM PDT 24
Finished Jul 23 07:05:43 PM PDT 24
Peak memory 235056 kb
Host smart-4c4fe655-b81d-4ea2-b7d8-661dc20815cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370113451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.1370113451
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.2054479020
Short name T506
Test name
Test status
Simulation time 102955155 ps
CPU time 2.92 seconds
Started Jul 23 07:05:20 PM PDT 24
Finished Jul 23 07:05:25 PM PDT 24
Peak memory 232792 kb
Host smart-36bd17cf-ddd8-449e-bf54-a2c0e3364418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054479020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.2054479020
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.1023311532
Short name T953
Test name
Test status
Simulation time 607706899 ps
CPU time 4.03 seconds
Started Jul 23 07:05:21 PM PDT 24
Finished Jul 23 07:05:27 PM PDT 24
Peak memory 232896 kb
Host smart-44613e65-8084-4668-9d66-ce1b78dd4761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023311532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.1023311532
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.3454195965
Short name T130
Test name
Test status
Simulation time 1123154168 ps
CPU time 9.42 seconds
Started Jul 23 07:05:21 PM PDT 24
Finished Jul 23 07:05:32 PM PDT 24
Peak memory 223080 kb
Host smart-31fea8bb-0ef9-40cc-ab90-3205660dac8d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3454195965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.3454195965
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.990731435
Short name T968
Test name
Test status
Simulation time 6306138054 ps
CPU time 40.36 seconds
Started Jul 23 07:05:25 PM PDT 24
Finished Jul 23 07:06:06 PM PDT 24
Peak memory 249696 kb
Host smart-bcf6a9fb-6f4a-45d7-9e52-cbd4a584bf4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990731435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stress
_all.990731435
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.3570086420
Short name T368
Test name
Test status
Simulation time 9254190749 ps
CPU time 25.2 seconds
Started Jul 23 07:05:18 PM PDT 24
Finished Jul 23 07:05:46 PM PDT 24
Peak memory 216532 kb
Host smart-3813bf92-1490-4671-9503-bedb523fbff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570086420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.3570086420
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.1703750964
Short name T930
Test name
Test status
Simulation time 31738890298 ps
CPU time 19.6 seconds
Started Jul 23 07:05:20 PM PDT 24
Finished Jul 23 07:05:42 PM PDT 24
Peak memory 216564 kb
Host smart-8a959e1c-e9ea-444b-8089-1e14d72298a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703750964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.1703750964
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.3659141665
Short name T931
Test name
Test status
Simulation time 61565716 ps
CPU time 1.1 seconds
Started Jul 23 07:05:19 PM PDT 24
Finished Jul 23 07:05:23 PM PDT 24
Peak memory 207856 kb
Host smart-2583db49-e63a-4b0d-9c21-7a81799996c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659141665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.3659141665
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.2129991132
Short name T313
Test name
Test status
Simulation time 84284481 ps
CPU time 0.74 seconds
Started Jul 23 07:05:21 PM PDT 24
Finished Jul 23 07:05:24 PM PDT 24
Peak memory 206116 kb
Host smart-1e24841d-c4c2-4e20-8677-6629710c5c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129991132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.2129991132
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.1699919203
Short name T809
Test name
Test status
Simulation time 1522882506 ps
CPU time 10 seconds
Started Jul 23 07:05:18 PM PDT 24
Finished Jul 23 07:05:31 PM PDT 24
Peak memory 241048 kb
Host smart-9710b83a-1031-48df-a5fa-377ef2ccbe19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699919203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.1699919203
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.1603603525
Short name T545
Test name
Test status
Simulation time 14055656 ps
CPU time 0.7 seconds
Started Jul 23 07:05:36 PM PDT 24
Finished Jul 23 07:05:38 PM PDT 24
Peak memory 205576 kb
Host smart-53bcdb65-0bdc-4511-b943-58b271301721
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603603525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.1
603603525
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.857170768
Short name T592
Test name
Test status
Simulation time 475080680 ps
CPU time 2.27 seconds
Started Jul 23 07:05:36 PM PDT 24
Finished Jul 23 07:05:39 PM PDT 24
Peak memory 224580 kb
Host smart-8ac7c1c9-230b-4e2a-aeed-b88cd6fa8ed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857170768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.857170768
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.3435207244
Short name T655
Test name
Test status
Simulation time 19602742 ps
CPU time 0.79 seconds
Started Jul 23 07:05:24 PM PDT 24
Finished Jul 23 07:05:25 PM PDT 24
Peak memory 206728 kb
Host smart-738d8f9a-b8ce-4254-8609-bbd75f26840b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435207244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.3435207244
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.116830210
Short name T193
Test name
Test status
Simulation time 226212422890 ps
CPU time 376.32 seconds
Started Jul 23 07:05:28 PM PDT 24
Finished Jul 23 07:11:45 PM PDT 24
Peak memory 254392 kb
Host smart-cb1d2441-ef52-4808-af61-c5d632b4e502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116830210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.116830210
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.796515781
Short name T515
Test name
Test status
Simulation time 38224394447 ps
CPU time 79.51 seconds
Started Jul 23 07:05:25 PM PDT 24
Finished Jul 23 07:06:46 PM PDT 24
Peak memory 237196 kb
Host smart-e67aa432-62ce-4aef-a0bb-d4233c4a3201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796515781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.796515781
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.2211877722
Short name T827
Test name
Test status
Simulation time 2769121847 ps
CPU time 20.67 seconds
Started Jul 23 07:05:25 PM PDT 24
Finished Jul 23 07:05:47 PM PDT 24
Peak memory 224020 kb
Host smart-21250738-2c6b-4869-8a90-eaf0be2cc9c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211877722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.2211877722
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.2349509069
Short name T466
Test name
Test status
Simulation time 1634365673 ps
CPU time 9.14 seconds
Started Jul 23 07:05:24 PM PDT 24
Finished Jul 23 07:05:34 PM PDT 24
Peak memory 232880 kb
Host smart-8de5ec19-ae1f-4bbc-adb5-e9f426f0c59e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349509069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.2349509069
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.88168553
Short name T629
Test name
Test status
Simulation time 43854874371 ps
CPU time 147.26 seconds
Started Jul 23 07:05:36 PM PDT 24
Finished Jul 23 07:08:04 PM PDT 24
Peak memory 249320 kb
Host smart-be6ba7e6-ff3f-4ae7-b344-9c3ae93cd4b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88168553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds.88168553
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/6.spi_device_intercept.2661511117
Short name T420
Test name
Test status
Simulation time 164171282 ps
CPU time 2.38 seconds
Started Jul 23 07:05:25 PM PDT 24
Finished Jul 23 07:05:29 PM PDT 24
Peak memory 224688 kb
Host smart-f45381cf-2857-4c21-a783-d754d9b9a0dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661511117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.2661511117
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.308056281
Short name T381
Test name
Test status
Simulation time 674941480 ps
CPU time 9.39 seconds
Started Jul 23 07:05:23 PM PDT 24
Finished Jul 23 07:05:33 PM PDT 24
Peak memory 232912 kb
Host smart-10995537-5c6a-435c-92b4-096e8efe2b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308056281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.308056281
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.475783609
Short name T385
Test name
Test status
Simulation time 36826393969 ps
CPU time 26.56 seconds
Started Jul 23 07:05:25 PM PDT 24
Finished Jul 23 07:05:53 PM PDT 24
Peak memory 232908 kb
Host smart-3ee6db8a-0d9b-4ef0-a0d2-e16729fd158c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475783609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap.
475783609
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.3712019684
Short name T202
Test name
Test status
Simulation time 313902985 ps
CPU time 4.37 seconds
Started Jul 23 07:05:27 PM PDT 24
Finished Jul 23 07:05:32 PM PDT 24
Peak memory 224628 kb
Host smart-22027b25-a356-490d-aeb1-8a09d88eb6ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712019684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.3712019684
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.912140333
Short name T898
Test name
Test status
Simulation time 237382086 ps
CPU time 5.06 seconds
Started Jul 23 07:05:29 PM PDT 24
Finished Jul 23 07:05:35 PM PDT 24
Peak memory 222776 kb
Host smart-da4e94a7-c2a4-47ab-bab3-5df19700cd7e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=912140333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_direc
t.912140333
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.3301558128
Short name T667
Test name
Test status
Simulation time 92441100 ps
CPU time 0.99 seconds
Started Jul 23 07:05:25 PM PDT 24
Finished Jul 23 07:05:27 PM PDT 24
Peak memory 207084 kb
Host smart-13acd6df-68ff-4c05-b87c-4a8404e9bc7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301558128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.3301558128
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.683271652
Short name T410
Test name
Test status
Simulation time 918951047 ps
CPU time 5.52 seconds
Started Jul 23 07:05:27 PM PDT 24
Finished Jul 23 07:05:34 PM PDT 24
Peak memory 216428 kb
Host smart-ec887115-e91e-452a-a4a9-f9bf206d7e19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683271652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.683271652
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.2985041022
Short name T626
Test name
Test status
Simulation time 86838695047 ps
CPU time 16.11 seconds
Started Jul 23 07:05:25 PM PDT 24
Finished Jul 23 07:05:42 PM PDT 24
Peak memory 216584 kb
Host smart-b0e08f3c-e180-42e2-8d59-b86b1b8d9753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985041022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.2985041022
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.2597982881
Short name T340
Test name
Test status
Simulation time 23392839 ps
CPU time 1.3 seconds
Started Jul 23 07:05:25 PM PDT 24
Finished Jul 23 07:05:28 PM PDT 24
Peak memory 216372 kb
Host smart-a32d5b53-7e20-468b-b0c9-63db120e8de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597982881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.2597982881
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.2538510970
Short name T434
Test name
Test status
Simulation time 49858637 ps
CPU time 0.88 seconds
Started Jul 23 07:05:24 PM PDT 24
Finished Jul 23 07:05:26 PM PDT 24
Peak memory 207140 kb
Host smart-9cd2368b-2363-497e-9bbd-f15254a7eb9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538510970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.2538510970
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.3805029364
Short name T204
Test name
Test status
Simulation time 14693352685 ps
CPU time 22.56 seconds
Started Jul 23 07:05:36 PM PDT 24
Finished Jul 23 07:05:59 PM PDT 24
Peak memory 241108 kb
Host smart-3aba0372-490c-409f-8c4f-27ae06eaed78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805029364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.3805029364
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.3610262293
Short name T324
Test name
Test status
Simulation time 12950246 ps
CPU time 0.72 seconds
Started Jul 23 07:05:31 PM PDT 24
Finished Jul 23 07:05:32 PM PDT 24
Peak memory 205040 kb
Host smart-9c62f65e-e280-4505-bc4c-e8761d6d2062
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610262293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.3
610262293
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.987801544
Short name T880
Test name
Test status
Simulation time 2003200526 ps
CPU time 11.86 seconds
Started Jul 23 07:05:32 PM PDT 24
Finished Jul 23 07:05:45 PM PDT 24
Peak memory 232932 kb
Host smart-1460d3a8-2e02-402a-8e81-5ce5117a04f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987801544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.987801544
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.2464736833
Short name T316
Test name
Test status
Simulation time 13861068 ps
CPU time 0.76 seconds
Started Jul 23 07:05:32 PM PDT 24
Finished Jul 23 07:05:34 PM PDT 24
Peak memory 206756 kb
Host smart-c6c2aad7-9417-4556-abad-0a7b4fbfabfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464736833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.2464736833
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.285430837
Short name T367
Test name
Test status
Simulation time 10363202252 ps
CPU time 68.21 seconds
Started Jul 23 07:05:31 PM PDT 24
Finished Jul 23 07:06:40 PM PDT 24
Peak memory 257616 kb
Host smart-c251faf2-0e4a-42d5-8fca-e8039480f8e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285430837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.285430837
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.2918651437
Short name T270
Test name
Test status
Simulation time 65591837231 ps
CPU time 169.89 seconds
Started Jul 23 07:05:33 PM PDT 24
Finished Jul 23 07:08:24 PM PDT 24
Peak memory 249420 kb
Host smart-58df9b17-0c7b-4ea8-827e-96842c1ba695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918651437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.2918651437
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.267774624
Short name T68
Test name
Test status
Simulation time 16411282001 ps
CPU time 70.57 seconds
Started Jul 23 07:05:32 PM PDT 24
Finished Jul 23 07:06:44 PM PDT 24
Peak memory 265724 kb
Host smart-c9c8cff1-f8af-4b3b-9076-f8a445ef81f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267774624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle.
267774624
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.4107240916
Short name T663
Test name
Test status
Simulation time 5408126438 ps
CPU time 24.23 seconds
Started Jul 23 07:05:33 PM PDT 24
Finished Jul 23 07:05:59 PM PDT 24
Peak memory 232856 kb
Host smart-a06fecea-1514-40f0-9083-4e9e2fba8315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107240916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.4107240916
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.2319738057
Short name T807
Test name
Test status
Simulation time 9282993991 ps
CPU time 97.88 seconds
Started Jul 23 07:05:32 PM PDT 24
Finished Jul 23 07:07:11 PM PDT 24
Peak memory 255360 kb
Host smart-fd1c4c1a-2371-4af8-b831-917d12f9fdb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319738057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds
.2319738057
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.3630777539
Short name T442
Test name
Test status
Simulation time 828777713 ps
CPU time 4.84 seconds
Started Jul 23 07:05:32 PM PDT 24
Finished Jul 23 07:05:37 PM PDT 24
Peak memory 232940 kb
Host smart-d74436e0-393b-41c1-88f9-0cb87a83bdc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630777539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.3630777539
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.2932462692
Short name T615
Test name
Test status
Simulation time 244246353 ps
CPU time 6.71 seconds
Started Jul 23 07:05:33 PM PDT 24
Finished Jul 23 07:05:41 PM PDT 24
Peak memory 241048 kb
Host smart-4de53c4c-ee1a-42e2-881c-d8c1523097b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932462692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.2932462692
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.3936203108
Short name T256
Test name
Test status
Simulation time 2624515634 ps
CPU time 5.21 seconds
Started Jul 23 07:05:33 PM PDT 24
Finished Jul 23 07:05:39 PM PDT 24
Peak memory 232932 kb
Host smart-6c3a4b7c-b3a2-4ab0-a88b-b8aa8f380390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936203108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.3936203108
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.1916602051
Short name T979
Test name
Test status
Simulation time 2742589026 ps
CPU time 7.15 seconds
Started Jul 23 07:05:33 PM PDT 24
Finished Jul 23 07:05:41 PM PDT 24
Peak memory 224696 kb
Host smart-d8ef5ffc-bd2f-4d2b-b89f-0ae86e22ed22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916602051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.1916602051
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.4034140855
Short name T315
Test name
Test status
Simulation time 1803556619 ps
CPU time 11.57 seconds
Started Jul 23 07:05:30 PM PDT 24
Finished Jul 23 07:05:42 PM PDT 24
Peak memory 223180 kb
Host smart-1fadf689-1383-4003-914f-54aa2633daef
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4034140855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.4034140855
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.3586693436
Short name T265
Test name
Test status
Simulation time 102898269397 ps
CPU time 278.2 seconds
Started Jul 23 07:05:33 PM PDT 24
Finished Jul 23 07:10:13 PM PDT 24
Peak memory 282156 kb
Host smart-0de6ccd8-6194-4fed-8438-c8f97410e7a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586693436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.3586693436
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.3046876243
Short name T981
Test name
Test status
Simulation time 6693020897 ps
CPU time 38.04 seconds
Started Jul 23 07:05:34 PM PDT 24
Finished Jul 23 07:06:13 PM PDT 24
Peak memory 216412 kb
Host smart-c36bd86d-ab9e-49fa-b210-bf5a6a5ccab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046876243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.3046876243
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.1197499376
Short name T423
Test name
Test status
Simulation time 1313983571 ps
CPU time 7.34 seconds
Started Jul 23 07:05:33 PM PDT 24
Finished Jul 23 07:05:41 PM PDT 24
Peak memory 216412 kb
Host smart-fcac12de-e8a9-4ac7-96e2-d79144ae88e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197499376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.1197499376
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.595737217
Short name T494
Test name
Test status
Simulation time 67928668 ps
CPU time 0.91 seconds
Started Jul 23 07:05:33 PM PDT 24
Finished Jul 23 07:05:36 PM PDT 24
Peak memory 207156 kb
Host smart-cd46f155-c499-4370-bc82-69691d9b10c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595737217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.595737217
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.2111018226
Short name T30
Test name
Test status
Simulation time 214496500 ps
CPU time 0.96 seconds
Started Jul 23 07:05:32 PM PDT 24
Finished Jul 23 07:05:34 PM PDT 24
Peak memory 206124 kb
Host smart-7035de4b-eede-4beb-91f6-98bd3bdefde2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111018226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.2111018226
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.3346889637
Short name T217
Test name
Test status
Simulation time 912157605 ps
CPU time 7.24 seconds
Started Jul 23 07:05:32 PM PDT 24
Finished Jul 23 07:05:40 PM PDT 24
Peak memory 240708 kb
Host smart-9d34bea7-bdd3-4b64-a8c1-b08dd6422c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346889637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.3346889637
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.1115857596
Short name T551
Test name
Test status
Simulation time 11516794 ps
CPU time 0.72 seconds
Started Jul 23 07:05:42 PM PDT 24
Finished Jul 23 07:05:44 PM PDT 24
Peak memory 205660 kb
Host smart-dfae59e1-ac90-49f9-b42a-f848c161cd76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115857596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.1
115857596
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.2718616692
Short name T975
Test name
Test status
Simulation time 81028232 ps
CPU time 3.26 seconds
Started Jul 23 07:05:37 PM PDT 24
Finished Jul 23 07:05:41 PM PDT 24
Peak memory 233004 kb
Host smart-8bdf9b8f-eed2-442c-8884-76a5b24cf01c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718616692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.2718616692
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.470707957
Short name T376
Test name
Test status
Simulation time 61200922 ps
CPU time 0.82 seconds
Started Jul 23 07:05:35 PM PDT 24
Finished Jul 23 07:05:36 PM PDT 24
Peak memory 206928 kb
Host smart-586a60bb-a868-4287-a7e8-55b4305818b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470707957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.470707957
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.1839882927
Short name T232
Test name
Test status
Simulation time 7351526167 ps
CPU time 25.49 seconds
Started Jul 23 07:05:41 PM PDT 24
Finished Jul 23 07:06:07 PM PDT 24
Peak memory 232972 kb
Host smart-3f561dee-4c6c-44b4-8ef4-06b8e1e7f2af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839882927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.1839882927
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.291603866
Short name T717
Test name
Test status
Simulation time 30511466530 ps
CPU time 266.84 seconds
Started Jul 23 07:05:42 PM PDT 24
Finished Jul 23 07:10:10 PM PDT 24
Peak memory 249392 kb
Host smart-dd4c2b2a-03d6-4961-8091-ee12ead7d3a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291603866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.291603866
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.2788422398
Short name T421
Test name
Test status
Simulation time 30022267356 ps
CPU time 202.43 seconds
Started Jul 23 07:05:41 PM PDT 24
Finished Jul 23 07:09:04 PM PDT 24
Peak memory 257592 kb
Host smart-2641d075-f976-46a9-a828-86778283f64a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788422398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.2788422398
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.2213055793
Short name T900
Test name
Test status
Simulation time 2272680201 ps
CPU time 10.73 seconds
Started Jul 23 07:05:39 PM PDT 24
Finished Jul 23 07:05:50 PM PDT 24
Peak memory 233460 kb
Host smart-608967ad-4af3-4722-9cdb-55ff6b0c0284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213055793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.2213055793
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_intercept.444908632
Short name T523
Test name
Test status
Simulation time 2150162914 ps
CPU time 5.3 seconds
Started Jul 23 07:05:40 PM PDT 24
Finished Jul 23 07:05:46 PM PDT 24
Peak memory 224744 kb
Host smart-180256ec-4ba7-4785-b753-c3b733b730a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444908632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.444908632
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.105214696
Short name T512
Test name
Test status
Simulation time 737495918 ps
CPU time 3.57 seconds
Started Jul 23 07:05:39 PM PDT 24
Finished Jul 23 07:05:44 PM PDT 24
Peak memory 224688 kb
Host smart-2ba62362-b874-4f01-b0bb-c76b463f2526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105214696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.105214696
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.2720561544
Short name T422
Test name
Test status
Simulation time 1729750929 ps
CPU time 3.85 seconds
Started Jul 23 07:05:38 PM PDT 24
Finished Jul 23 07:05:42 PM PDT 24
Peak memory 224628 kb
Host smart-6658af63-40da-4e88-9871-d846de769ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720561544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.2720561544
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.2214613450
Short name T222
Test name
Test status
Simulation time 3169071291 ps
CPU time 9.72 seconds
Started Jul 23 07:05:36 PM PDT 24
Finished Jul 23 07:05:47 PM PDT 24
Peak memory 252316 kb
Host smart-7d091abd-3019-4bc1-a13a-c5ebb3d20122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214613450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.2214613450
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.2400529774
Short name T905
Test name
Test status
Simulation time 5248927618 ps
CPU time 10.95 seconds
Started Jul 23 07:05:41 PM PDT 24
Finished Jul 23 07:05:53 PM PDT 24
Peak memory 219524 kb
Host smart-d619a05f-52c5-4ac8-8e6f-a29bef19fa80
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2400529774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.2400529774
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.4093737947
Short name T429
Test name
Test status
Simulation time 3847310524 ps
CPU time 30.92 seconds
Started Jul 23 07:05:44 PM PDT 24
Finished Jul 23 07:06:15 PM PDT 24
Peak memory 224848 kb
Host smart-39d9fc64-c67f-47fd-bb4e-f9e3ae12b693
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093737947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.4093737947
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.1450262237
Short name T24
Test name
Test status
Simulation time 2158947218 ps
CPU time 12.07 seconds
Started Jul 23 07:05:38 PM PDT 24
Finished Jul 23 07:05:51 PM PDT 24
Peak memory 216520 kb
Host smart-d1dad73a-194f-484d-9745-47535430f150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450262237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.1450262237
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.1796177870
Short name T644
Test name
Test status
Simulation time 1419576178 ps
CPU time 5.77 seconds
Started Jul 23 07:05:32 PM PDT 24
Finished Jul 23 07:05:39 PM PDT 24
Peak memory 216416 kb
Host smart-86799d32-a117-467e-a78a-92161d268550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796177870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.1796177870
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.4831033
Short name T933
Test name
Test status
Simulation time 10742721 ps
CPU time 0.68 seconds
Started Jul 23 07:05:42 PM PDT 24
Finished Jul 23 07:05:43 PM PDT 24
Peak memory 205760 kb
Host smart-8638fbaf-c97f-4fd8-95e0-d8fdc3dfea95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4831033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.4831033
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.3170365939
Short name T12
Test name
Test status
Simulation time 104340914 ps
CPU time 0.9 seconds
Started Jul 23 07:05:38 PM PDT 24
Finished Jul 23 07:05:39 PM PDT 24
Peak memory 206484 kb
Host smart-552812ab-96b5-4baa-80ff-ce51466d548f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170365939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.3170365939
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.586061213
Short name T498
Test name
Test status
Simulation time 47494083843 ps
CPU time 24.68 seconds
Started Jul 23 07:05:39 PM PDT 24
Finished Jul 23 07:06:04 PM PDT 24
Peak memory 241176 kb
Host smart-ca1a6bc1-0bc8-4779-9114-12ebe913792c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586061213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.586061213
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.2209076499
Short name T59
Test name
Test status
Simulation time 16310045 ps
CPU time 0.71 seconds
Started Jul 23 07:05:48 PM PDT 24
Finished Jul 23 07:05:50 PM PDT 24
Peak memory 205980 kb
Host smart-918a0782-315d-4fe3-8d93-2c7e77d03854
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209076499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.2
209076499
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.3238606084
Short name T461
Test name
Test status
Simulation time 162655350 ps
CPU time 2.99 seconds
Started Jul 23 07:05:49 PM PDT 24
Finished Jul 23 07:05:52 PM PDT 24
Peak memory 224612 kb
Host smart-b63fb25d-fa02-44e9-b7c6-c7faf165be94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238606084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.3238606084
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.2484534476
Short name T350
Test name
Test status
Simulation time 21494851 ps
CPU time 0.85 seconds
Started Jul 23 07:05:43 PM PDT 24
Finished Jul 23 07:05:45 PM PDT 24
Peak memory 206744 kb
Host smart-01acd289-f7d1-4c9e-93f2-3e6472c98b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484534476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.2484534476
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.652642865
Short name T891
Test name
Test status
Simulation time 85817231832 ps
CPU time 165.43 seconds
Started Jul 23 07:05:46 PM PDT 24
Finished Jul 23 07:08:32 PM PDT 24
Peak memory 249276 kb
Host smart-e8a593a2-2c89-4eb8-a648-c71ec6c65562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652642865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.652642865
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.2372739136
Short name T203
Test name
Test status
Simulation time 40259834193 ps
CPU time 184.54 seconds
Started Jul 23 07:05:47 PM PDT 24
Finished Jul 23 07:08:52 PM PDT 24
Peak memory 257544 kb
Host smart-0c53b08b-6d4a-46c8-9533-900b32a25fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372739136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.2372739136
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.3402318284
Short name T35
Test name
Test status
Simulation time 248238109324 ps
CPU time 304.84 seconds
Started Jul 23 07:05:49 PM PDT 24
Finished Jul 23 07:10:55 PM PDT 24
Peak memory 257540 kb
Host smart-23ec91f4-a942-46a9-a9ed-7b7e2b6a26fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402318284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.3402318284
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.3396010691
Short name T362
Test name
Test status
Simulation time 881086651 ps
CPU time 15.53 seconds
Started Jul 23 07:05:47 PM PDT 24
Finished Jul 23 07:06:04 PM PDT 24
Peak memory 237900 kb
Host smart-ff05cf9a-0582-494c-b947-7a8ce096334c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396010691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.3396010691
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.2011174412
Short name T883
Test name
Test status
Simulation time 5380194120 ps
CPU time 18.79 seconds
Started Jul 23 07:05:49 PM PDT 24
Finished Jul 23 07:06:09 PM PDT 24
Peak memory 238312 kb
Host smart-feae902f-65ff-45e6-8d07-1228f481ef04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011174412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds
.2011174412
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.2580874240
Short name T564
Test name
Test status
Simulation time 1656848026 ps
CPU time 4.7 seconds
Started Jul 23 07:05:48 PM PDT 24
Finished Jul 23 07:05:54 PM PDT 24
Peak memory 232840 kb
Host smart-11e29a1c-6894-4bc6-afd0-3ae2f63c2cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580874240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.2580874240
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.2924629267
Short name T303
Test name
Test status
Simulation time 308340169 ps
CPU time 2.07 seconds
Started Jul 23 07:05:46 PM PDT 24
Finished Jul 23 07:05:49 PM PDT 24
Peak memory 232512 kb
Host smart-228875bf-c9b5-4bd5-b8c0-824b395ea1d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924629267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.2924629267
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.4160374527
Short name T768
Test name
Test status
Simulation time 8074440835 ps
CPU time 25.22 seconds
Started Jul 23 07:05:44 PM PDT 24
Finished Jul 23 07:06:10 PM PDT 24
Peak memory 232940 kb
Host smart-9f5edf8e-7791-410b-8156-30db61dc5a35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160374527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.4160374527
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.3882529183
Short name T738
Test name
Test status
Simulation time 114709762 ps
CPU time 3.18 seconds
Started Jul 23 07:05:47 PM PDT 24
Finished Jul 23 07:05:51 PM PDT 24
Peak memory 232920 kb
Host smart-eecf72c0-b9fb-4ec8-9e1e-93546959ba20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882529183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.3882529183
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.4055926238
Short name T397
Test name
Test status
Simulation time 158441260 ps
CPU time 4.23 seconds
Started Jul 23 07:05:48 PM PDT 24
Finished Jul 23 07:05:53 PM PDT 24
Peak memory 223240 kb
Host smart-67126dbb-5697-43b5-ab73-3e88efc469ef
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4055926238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.4055926238
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.3726963229
Short name T500
Test name
Test status
Simulation time 14884273305 ps
CPU time 20.68 seconds
Started Jul 23 07:05:43 PM PDT 24
Finished Jul 23 07:06:04 PM PDT 24
Peak memory 216644 kb
Host smart-6a3436bc-431e-43fe-a0b7-3e9704656f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726963229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.3726963229
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.1081004586
Short name T312
Test name
Test status
Simulation time 946992769 ps
CPU time 5.97 seconds
Started Jul 23 07:05:44 PM PDT 24
Finished Jul 23 07:05:51 PM PDT 24
Peak memory 216356 kb
Host smart-16cd8e61-1d41-432b-a4a9-586b18f1aa89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081004586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.1081004586
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.3508412706
Short name T862
Test name
Test status
Simulation time 38291365 ps
CPU time 1.03 seconds
Started Jul 23 07:05:44 PM PDT 24
Finished Jul 23 07:05:46 PM PDT 24
Peak memory 207236 kb
Host smart-e30f187b-8c2b-41ae-843c-d8f02f4856ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508412706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.3508412706
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.45304213
Short name T307
Test name
Test status
Simulation time 148027549 ps
CPU time 0.78 seconds
Started Jul 23 07:05:41 PM PDT 24
Finished Jul 23 07:05:42 PM PDT 24
Peak memory 206116 kb
Host smart-8b3de61d-07ac-4d09-97d9-68d41d8ac9b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45304213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.45304213
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.2914585821
Short name T958
Test name
Test status
Simulation time 280273766 ps
CPU time 3.06 seconds
Started Jul 23 07:05:48 PM PDT 24
Finished Jul 23 07:05:51 PM PDT 24
Peak memory 224628 kb
Host smart-fa9801bc-4a07-4f1d-9f56-e48798ba34fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914585821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.2914585821
Directory /workspace/9.spi_device_upload/latest
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