Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2144901	1			T1	3316		T2	1202		T3	1
all_values[1]	2144901	1			T1	3316		T2	1202		T3	1
all_values[2]	2144901	1			T1	3316		T2	1202		T3	1
all_values[3]	2144901	1			T1	3316		T2	1202		T3	1
all_values[4]	2144901	1			T1	3316		T2	1202		T3	1
all_values[5]	2144901	1			T1	3316		T2	1202		T3	1
all_values[6]	2144901	1			T1	3316		T2	1202		T3	1
all_values[7]	2144901	1			T1	3316		T2	1202		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16874249

1

T1

26528

T2

9616

T3

8

auto[1]

284959

1

T7

103

T15

11225

T19

65

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17134363

1

T1

26528

T2

9616

T3

8

auto[1]

24845

1

T7

69

T11

269

T15

295

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2125276	1			T1	3316		T2	1202		T3	1
all_values[0]	auto[0]	auto[1]	11521	1			T7	7		T11	120		T15	3
all_values[0]	auto[1]	auto[0]	7679	1			T7	6		T15	3601		T19	7
all_values[0]	auto[1]	auto[1]	425	1			T7	4		T15	133		T20	1
all_values[1]	auto[0]	auto[0]	2064334	1			T1	3316		T2	1202		T3	1
all_values[1]	auto[0]	auto[1]	7504	1			T7	5		T11	107		T15	87
all_values[1]	auto[1]	auto[0]	72443	1			T7	7		T15	3		T19	11
all_values[1]	auto[1]	auto[1]	620	1			T7	2		T15	2		T19	1
all_values[2]	auto[0]	auto[0]	2109968	1			T1	3316		T2	1202		T3	1
all_values[2]	auto[0]	auto[1]	2662	1			T7	4		T11	42		T18	17
all_values[2]	auto[1]	auto[0]	31948	1			T7	11		T15	3689		T19	5
all_values[2]	auto[1]	auto[1]	323	1			T7	2		T15	46		T19	3
all_values[3]	auto[0]	auto[0]	2121798	1			T1	3316		T2	1202		T3	1
all_values[3]	auto[0]	auto[1]	186	1			T7	9		T15	1		T19	3
all_values[3]	auto[1]	auto[0]	22731	1			T7	5		T15	3		T19	6
all_values[3]	auto[1]	auto[1]	186	1			T7	6		T15	2		T19	6
all_values[4]	auto[0]	auto[0]	2120405	1			T1	3316		T2	1202		T3	1
all_values[4]	auto[0]	auto[1]	198	1			T7	5		T15	4		T19	4
all_values[4]	auto[1]	auto[0]	24111	1			T7	15		T15	3		T19	4
all_values[4]	auto[1]	auto[1]	187	1			T7	2		T15	1		T19	1
all_values[5]	auto[0]	auto[0]	2094731	1			T1	3316		T2	1202		T3	1
all_values[5]	auto[0]	auto[1]	153	1			T7	4		T15	4		T19	5
all_values[5]	auto[1]	auto[0]	49837	1			T7	7		T15	3729		T19	2
all_values[5]	auto[1]	auto[1]	180	1			T7	9		T15	3		T19	3
all_values[6]	auto[0]	auto[0]	2074263	1			T1	3316		T2	1202		T3	1
all_values[6]	auto[0]	auto[1]	163	1			T7	1		T15	1		T19	1
all_values[6]	auto[1]	auto[0]	70296	1			T7	12		T15	2		T19	8
all_values[6]	auto[1]	auto[1]	179	1			T7	5		T15	2		T19	2
all_values[7]	auto[0]	auto[0]	2140904	1			T1	3316		T2	1202		T3	1
all_values[7]	auto[0]	auto[1]	183	1			T7	2		T15	2		T19	1
all_values[7]	auto[1]	auto[0]	3639	1			T7	8		T15	2		T19	3
all_values[7]	auto[1]	auto[1]	175	1			T7	2		T15	4		T19	3