Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	34934	1			T3	2		T10	235		T11	97
auto[SpiFlashAddrCfg]	7865	1			T3	4		T5	5		T6	8
auto[SpiFlashAddr3b]	9164	1			T5	5		T6	6		T10	11
auto[SpiFlashAddr4b]	7602	1			T6	2		T10	14		T11	17

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34242

1

T3

6

T5

10

T6

16

auto[1]

25323

1

T10

115

T11

79

T14

28

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31382

1

T3

6

T5

5

T6

14

auto[1]

28183

1

T5

5

T6

2

T10

200

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	39578	1			T3	2		T10	247		T11	109
values[1]	1150	1			T10	4		T11	4		T15	13
values[2]	1492	1			T10	3		T11	5		T15	7
values[3]	1385	1			T6	2		T10	1		T11	9
values[4]	1482	1			T10	1		T11	3		T14	2
values[5]	1546	1			T3	4		T6	6		T10	3
values[6]	1519	1			T10	2		T11	7		T15	14
values[7]	1458	1			T5	5		T10	5		T11	7
values[8]	9955	1			T5	5		T6	8		T10	12

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32334

1

T3

6

T6

16

T10

278

auto[1]

27231

1

T5

10

T15

439

T16

280

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

56317

1

T3

6

T5

10

T6

16

write

3248

1

T10

6

T11

10

T14

4

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

19645

1

T3

6

T5

10

T6

16

valids[0x1]

39920

1

T10

233

T11

114

T14

18

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1627	1			T10	1		T11	6		T14	2
internal_process_ops[0x5a]	1602	1			T10	2		T11	3		T15	10
internal_process_ops[0x05]	20806	1			T10	199		T11	58		T14	2
internal_process_ops[0x35]	1575	1			T10	3		T11	3		T15	12
internal_process_ops[0x15]	1648	1			T10	4		T11	7		T14	4
internal_process_ops[0x03]	1053	1			T10	5		T11	2		T15	2
internal_process_ops[0x0b]	1106	1			T10	2		T11	4		T14	4
internal_process_ops[0x3b]	1083	1			T5	5		T10	2		T11	4
internal_process_ops[0x6b]	1112	1			T5	3		T6	8		T10	4
internal_process_ops[0xbb]	1115	1			T6	6		T10	4		T11	5
internal_process_ops[0xeb]	1096	1			T5	2		T6	2		T10	2

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

57887

1

T3

6

T5

10

T6

16

auto[1]

1678

1

T10

4

T11

4

T14

4

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

57238

1

T3

6

T5

10

T6

16

auto[1]

2327

1

T10

9

T11

12

T15

21

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10650

1

T3

2

T10

137

T11

47

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6696

1

T10

95

T11

45

T14

8

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2265

1

T3

4

T6

8

T10

9

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

2008

1

T10

8

T11

2

T14

4

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2659

1

T6

6

T10

5

T11

16

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2273

1

T10

6

T11

17

T14

6

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2210

1

T6

2

T10

8

T11

6

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1933

1

T10

4

T11

10

T14

6

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

99

1

T10

1

T17

2

T18

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

97

1

T10

1

T11

2

T18

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

111

1

T11

3

T37

1

T38

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

149

1

T10

1

T14

4

T18

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

121

1

T37

1

T38

1

T39

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

89

1

T38

1

T40

3

T22

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

88

1

T39

3

T22

4

T23

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

122

1

T10

1

T37

2

T20

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

107

1

T37

1

T38

2

T36

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

97

1

T11

2

T18

2

T37

4

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

75

1

T11

2

T36

2

T39

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

103

1

T36

1

T22

7

T23

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

109

1

T10

1

T11

1

T18

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

93

1

T10

1

T36

1

T20

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

87

1

T18

7

T37

1

T38

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

93

1

T18

1

T38

4

T36

1

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10191

1

T15

116

T16

85

T24

115

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6549

1

T15

157

T16

34

T24

55

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1397

1

T5

5

T15

21

T16

20

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1350

1

T15

24

T16

32

T24

16

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1778

1

T5

5

T15

35

T16

34

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1691

1

T15

24

T16

24

T24

36

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1421

1

T15

15

T16

15

T24

25

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1246

1

T15

20

T16

18

T24

28

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

103

1

T15

1

T24

1

T25

4

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

110

1

T15

5

T16

2

T24

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

89

1

T26

1

T42

3

T33

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

90

1

T15

2

T16

1

T24

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

110

1

T16

1

T24

2

T33

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

112

1

T24

3

T163

1

T76

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

105

1

T15

3

T16

2

T24

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

98

1

T15

1

T163

4

T164

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

111

1

T15

2

T16

1

T25

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

110

1

T15

4

T24

5

T165

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

56

1

T164

2

T76

2

T166

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

104

1

T15

2

T24

1

T25

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

99

1

T15

3

T16

3

T26

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

104

1

T15

1

T16

1

T24

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

100

1

T16

3

T25

4

T26

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

107

1

T15

3

T16

4

T24

1

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	4070	1			T3	2		T10	24		T11	19
auto[0]	values[0]	valids[0x1]	16302	1			T10	223		T11	90		T14	14
auto[0]	values[1]	valids[0x1]	631	1			T10	4		T11	4		T18	5
auto[0]	values[2]	valids[0x0]	595	1			T10	3		T11	1		T18	5
auto[0]	values[2]	valids[0x1]	302	1			T11	4		T18	3		T37	2
auto[0]	values[3]	valids[0x0]	527	1			T6	2		T10	1		T11	7
auto[0]	values[3]	valids[0x1]	297	1			T11	2		T18	1		T109	2
auto[0]	values[4]	valids[0x0]	531	1			T10	1		T11	3		T14	2
auto[0]	values[4]	valids[0x1]	326	1			T18	1		T38	3		T20	3
auto[0]	values[5]	valids[0x0]	585	1			T3	4		T6	6		T10	3
auto[0]	values[5]	valids[0x1]	308	1			T11	3		T38	2		T36	2
auto[0]	values[6]	valids[0x0]	597	1			T11	4		T18	5		T37	1
auto[0]	values[6]	valids[0x1]	295	1			T10	2		T11	3		T18	1
auto[0]	values[7]	valids[0x0]	609	1			T10	5		T11	6		T18	3
auto[0]	values[7]	valids[0x1]	296	1			T11	1		T18	2		T37	1
auto[0]	values[8]	valids[0x0]	3913	1			T6	8		T10	8		T11	16
auto[0]	values[8]	valids[0x1]	2150	1			T10	4		T11	7		T14	4
auto[1]	values[0]	valids[0x0]	3755	1			T15	52		T16	72		T24	54
auto[1]	values[0]	valids[0x1]	15451	1			T15	257		T16	70		T24	146
auto[1]	values[1]	valids[0x1]	519	1			T15	13		T16	10		T24	9
auto[1]	values[2]	valids[0x0]	372	1			T15	5		T16	8		T24	7
auto[1]	values[2]	valids[0x1]	223	1			T15	2		T16	1		T24	4
auto[1]	values[3]	valids[0x0]	336	1			T15	4		T16	11		T24	8
auto[1]	values[3]	valids[0x1]	225	1			T15	5		T16	7		T24	3
auto[1]	values[4]	valids[0x0]	353	1			T15	4		T16	5		T24	10
auto[1]	values[4]	valids[0x1]	272	1			T15	7		T16	9		T24	3
auto[1]	values[5]	valids[0x0]	394	1			T15	9		T16	1		T24	9
auto[1]	values[5]	valids[0x1]	259	1			T15	6		T16	10		T25	2
auto[1]	values[6]	valids[0x0]	346	1			T15	11		T16	5		T24	8
auto[1]	values[6]	valids[0x1]	281	1			T15	3		T16	10		T24	5
auto[1]	values[7]	valids[0x0]	331	1			T5	5		T15	5		T16	4
auto[1]	values[7]	valids[0x1]	222	1			T15	2		T16	5		T24	6
auto[1]	values[8]	valids[0x0]	2331	1			T5	5		T15	32		T16	38
auto[1]	values[8]	valids[0x1]	1561	1			T15	22		T16	14		T24	22