Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3555763

1

T3

6

T5

4460

T6

927

auto[1]

33443

1

T10

198

T11

53

T15

159

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1004921

1

T3

6

T5

4460

T6

927

auto[1]

2584285

1

T10

7072

T11

11322

T15

19570

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	690985	1			T3	2		T5	2018		T6	98
auto[524288:1048575]	404473	1			T10	214		T11	156		T15	128
auto[1048576:1572863]	424969	1			T5	597		T6	36		T11	1
auto[1572864:2097151]	403172	1			T6	197		T10	28		T15	913
auto[2097152:2621439]	415480	1			T6	236		T11	1570		T15	3040
auto[2621440:3145727]	385363	1			T6	213		T10	1		T11	784
auto[3145728:3670015]	450085	1			T3	4		T6	2		T11	7788
auto[3670016:4194303]	414679	1			T5	1845		T6	145		T10	4993

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2618854

1

T3

6

T5

12

T6

78

auto[1]

970352

1

T5

4448

T6

849

T10

5

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3153218

1

T3

1

T5

4460

T6

927

auto[1]

435988

1

T3

5

T10

1735

T11

1317

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	206770	1			T3	1		T5	2018		T6	98
auto[0]	auto[0]	auto[0:524287]	auto[1]	418107	1			T10	260		T11	3		T15	2801
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	118255	1			T10	3		T11	8		T15	3
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	236773	1			T10	2		T11	131		T15	46
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	120801	1			T5	597		T6	36		T11	1
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	248656	1			T15	1448		T16	808		T18	4246
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	90706	1			T6	197		T10	2		T15	7
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	255059	1			T10	1		T15	772		T16	284
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	122321	1			T6	236		T11	8		T15	1
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	242507	1			T11	1431		T15	2885		T16	207
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	105816	1			T6	213		T10	1		T11	6
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	231882	1			T11	774		T15	3699		T16	3304
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	134818	1			T6	2		T11	6		T15	5
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	235185	1			T11	6584		T16	4168		T18	257
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	95240	1			T5	1845		T6	145		T10	5
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	260817	1			T10	4936		T11	1057		T15	6748
auto[0]	auto[1]	auto[0:524287]	auto[0]	1004	1			T3	1		T10	4		T15	2
auto[0]	auto[1]	auto[0:524287]	auto[1]	59253	1			T10	1555		T16	640		T26	2751
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	739	1			T10	2		T11	2		T16	16
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	44272	1			T10	129		T25	128		T38	512
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	808	1			T16	11		T26	1		T37	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	51558	1			T16	5		T26	128		T37	2727
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	832	1			T16	8		T24	2		T26	2
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	52094	1			T15	129		T16	5		T24	256
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	510	1			T11	2		T15	1		T16	10
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	46417	1			T11	128		T15	129		T16	256
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	622	1			T15	2		T16	6		T42	13
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	44124	1			T15	257		T24	1408		T42	415
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	743	1			T3	4		T11	3		T15	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	74001	1			T11	1173		T15	513		T18	256
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	796	1			T15	1		T16	12		T24	1
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	54277	1			T15	5		T18	885		T24	1
auto[1]	auto[0]	auto[0:524287]	auto[0]	625	1			T10	2		T11	3		T16	5
auto[1]	auto[0]	auto[0:524287]	auto[1]	4807	1			T10	33		T11	8		T25	2
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	458	1			T10	2		T11	3		T15	4
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	3518	1			T10	39		T11	12		T15	75
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	343	1			T15	1		T16	16		T18	3
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2521	1			T18	14		T24	5		T26	10
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	474	1			T10	1		T15	2		T16	3
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	3472	1			T10	24		T15	2		T24	14
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	398	1			T11	1		T15	3		T16	2
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2806	1			T15	10		T18	4		T24	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	346	1			T11	1		T15	1		T16	9
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	1974	1			T11	3		T15	5		T24	6
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	422	1			T11	3		T24	1		T25	3
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	4304	1			T11	10		T24	5		T25	19
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	406	1			T10	2		T15	6		T18	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	2631	1			T10	50		T15	34		T25	15
auto[1]	auto[1]	auto[0:524287]	auto[0]	66	1			T10	1		T26	1		T38	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	353	1			T10	7		T26	7		T38	10
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	89	1			T10	1		T36	1		T39	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	369	1			T10	36		T36	16		T39	2
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	89	1			T16	6		T36	2		T20	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	193	1			T36	11		T20	6		T22	12
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	79	1			T15	1		T26	1		T38	2
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	456	1			T26	16		T38	16		T36	27
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	63	1			T15	1		T24	1		T166	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	458	1			T15	10		T24	3		T166	20
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	87	1			T15	1		T42	3		T33	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	512	1			T42	97		T33	5		T21	11
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	78	1			T11	1		T15	1		T20	3
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	534	1			T11	8		T15	2		T20	7
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	117	1			T24	1		T25	1		T38	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	395	1			T24	1		T25	2		T38	1

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	2154733	1			T3	1		T5	12		T6	78
auto[0]	auto[0]	auto[1]	968980	1			T5	4448		T6	849		T10	1
auto[0]	auto[1]	auto[0]	431349	1			T3	5		T10	1689		T11	1308
auto[0]	auto[1]	auto[1]	701	1			T10	1		T26	1		T223	1
auto[1]	auto[0]	auto[0]	28949	1			T10	150		T11	44		T15	143
auto[1]	auto[0]	auto[1]	556	1			T10	3		T16	5		T26	4
auto[1]	auto[1]	auto[0]	3823	1			T10	45		T11	9		T15	16
auto[1]	auto[1]	auto[1]	115	1			T16	1		T26	2		T42	1