Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2144901	1			T1	3316		T2	1202		T3	1
all_pins[1]	2144901	1			T1	3316		T2	1202		T3	1
all_pins[2]	2144901	1			T1	3316		T2	1202		T3	1
all_pins[3]	2144901	1			T1	3316		T2	1202		T3	1
all_pins[4]	2144901	1			T1	3316		T2	1202		T3	1
all_pins[5]	2144901	1			T1	3316		T2	1202		T3	1
all_pins[6]	2144901	1			T1	3316		T2	1202		T3	1
all_pins[7]	2144901	1			T1	3316		T2	1202		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	17085407	1			T1	26528		T2	9616		T3	8
values[0x1]	73801	1			T7	32		T15	688		T19	19
transitions[0x0=>0x1]	72611	1			T7	24		T15	684		T19	16
transitions[0x1=>0x0]	72621	1			T7	24		T15	684		T19	16

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2144432	1			T1	3316		T2	1202		T3	1
all_pins[0]	values[0x1]	469	1			T7	4		T15	154		T20	1
all_pins[0]	transitions[0x0=>0x1]	382	1			T7	4		T15	153		T20	1
all_pins[0]	transitions[0x1=>0x0]	571	1			T7	2		T15	1		T19	1
all_pins[1]	values[0x0]	2144243	1			T1	3316		T2	1202		T3	1
all_pins[1]	values[0x1]	658	1			T7	2		T15	2		T19	1
all_pins[1]	transitions[0x0=>0x1]	529	1			T7	2		T15	2		T19	1
all_pins[1]	transitions[0x1=>0x0]	205	1			T7	2		T15	53		T19	3
all_pins[2]	values[0x0]	2144567	1			T1	3316		T2	1202		T3	1
all_pins[2]	values[0x1]	334	1			T7	2		T15	53		T19	3
all_pins[2]	transitions[0x0=>0x1]	276	1			T7	1		T15	53		T19	1
all_pins[2]	transitions[0x1=>0x0]	128	1			T7	5		T15	2		T19	4
all_pins[3]	values[0x0]	2144715	1			T1	3316		T2	1202		T3	1
all_pins[3]	values[0x1]	186	1			T7	6		T15	2		T19	6
all_pins[3]	transitions[0x0=>0x1]	136	1			T7	6		T15	2		T19	6
all_pins[3]	transitions[0x1=>0x0]	137	1			T7	2		T15	1		T19	1
all_pins[4]	values[0x0]	2144714	1			T1	3316		T2	1202		T3	1
all_pins[4]	values[0x1]	187	1			T7	2		T15	1		T19	1
all_pins[4]	transitions[0x0=>0x1]	141	1			T7	1		T15	1		T19	1
all_pins[4]	transitions[0x1=>0x0]	1657	1			T7	8		T15	470		T19	3
all_pins[5]	values[0x0]	2143198	1			T1	3316		T2	1202		T3	1
all_pins[5]	values[0x1]	1703	1			T7	9		T15	470		T19	3
all_pins[5]	transitions[0x0=>0x1]	997	1			T7	5		T15	470		T19	3
all_pins[5]	transitions[0x1=>0x0]	69383	1			T7	1		T15	2		T19	2
all_pins[6]	values[0x0]	2074812	1			T1	3316		T2	1202		T3	1
all_pins[6]	values[0x1]	70089	1			T7	5		T15	2		T19	2
all_pins[6]	transitions[0x0=>0x1]	70032	1			T7	4		T19	1		T20	1
all_pins[6]	transitions[0x1=>0x0]	118	1			T7	1		T15	2		T19	2
all_pins[7]	values[0x0]	2144726	1			T1	3316		T2	1202		T3	1
all_pins[7]	values[0x1]	175	1			T7	2		T15	4		T19	3
all_pins[7]	transitions[0x0=>0x1]	118	1			T7	1		T15	3		T19	3
all_pins[7]	transitions[0x1=>0x0]	422	1			T7	3		T15	153		T20	1