Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18596

1

T3

6

T6

16

T10

163

auto[1]

13738

1

T10

115

T11

79

T14

28

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3879	1			T17	16		T18	40		T37	39
values[1]	3912	1			T3	6		T109	12		T221	4
values[2]	3614	1			T18	54		T37	25		T223	10
values[3]	4173	1			T6	16		T11	52		T14	28
values[4]	4140	1			T10	109		T11	97		T18	20
values[5]	4175	1			T10	57		T11	24		T18	20
values[6]	4540	1			T10	55		T37	62		T38	134
values[7]	3901	1			T10	57		T36	41		T40	24

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3722	1			T10	166		T11	48		T18	54
values[1]	4127	1			T38	81		T36	253		T20	42
values[2]	3958	1			T3	6		T6	16		T17	16
values[3]	3817	1			T10	55		T11	29		T18	20
values[4]	4374	1			T10	57		T18	20		T37	64
values[5]	3683	1			T11	31		T18	51		T36	123
values[6]	4245	1			T11	20		T14	28		T218	14
values[7]	4408	1			T11	45		T18	20		T37	31

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	234	1			T20	8		T210	15		T160	4
auto[0]	values[0]	values[1]	233	1			T39	7		T197	16		T69	12
auto[0]	values[0]	values[2]	290	1			T17	16		T38	7		T190	10
auto[0]	values[0]	values[3]	287	1			T178	15		T224	8		T29	10
auto[0]	values[0]	values[4]	162	1			T18	11		T37	13		T23	20
auto[0]	values[0]	values[5]	325	1			T18	11		T36	53		T178	11
auto[0]	values[0]	values[6]	344	1			T196	19		T193	8		T43	9
auto[0]	values[0]	values[7]	361	1			T38	11		T225	18		T52	14
auto[0]	values[1]	values[0]	132	1			T20	11		T151	8		T153	12
auto[0]	values[1]	values[1]	390	1			T36	125		T23	27		T195	13
auto[0]	values[1]	values[2]	268	1			T3	6		T197	16		T226	14
auto[0]	values[1]	values[3]	234	1			T109	12		T38	12		T203	8
auto[0]	values[1]	values[4]	243	1			T192	27		T69	13		T43	23
auto[0]	values[1]	values[5]	176	1			T23	10		T179	10		T71	26
auto[0]	values[1]	values[6]	446	1			T22	14		T227	4		T197	72
auto[0]	values[1]	values[7]	201	1			T221	4		T40	15		T228	8
auto[0]	values[2]	values[0]	318	1			T18	24		T39	11		T22	47
auto[0]	values[2]	values[1]	202	1			T38	11		T195	13		T208	11
auto[0]	values[2]	values[2]	209	1			T223	10		T38	39		T20	14
auto[0]	values[2]	values[3]	244	1			T203	14		T187	14		T180	14
auto[0]	values[2]	values[4]	214	1			T37	12		T36	38		T72	10
auto[0]	values[2]	values[5]	255	1			T36	11		T22	7		T29	14
auto[0]	values[2]	values[6]	163	1			T22	9		T210	10		T196	11
auto[0]	values[2]	values[7]	325	1			T18	11		T39	7		T219	2
auto[0]	values[3]	values[0]	210	1			T93	2		T210	9		T229	2
auto[0]	values[3]	values[1]	255	1			T40	10		T192	10		T179	9
auto[0]	values[3]	values[2]	497	1			T6	16		T197	10		T68	14
auto[0]	values[3]	values[3]	306	1			T36	11		T22	11		T192	41
auto[0]	values[3]	values[4]	254	1			T20	10		T40	11		T150	12
auto[0]	values[3]	values[5]	187	1			T11	20		T18	11		T54	6
auto[0]	values[3]	values[6]	241	1			T218	14		T22	10		T210	12
auto[0]	values[3]	values[7]	474	1			T11	17		T40	11		T193	50
auto[0]	values[4]	values[0]	244	1			T10	14		T11	10		T18	12
auto[0]	values[4]	values[1]	251	1			T36	10		T20	13		T39	8
auto[0]	values[4]	values[2]	224	1			T36	7		T230	10		T231	13
auto[0]	values[4]	values[3]	222	1			T11	22		T39	16		T193	9
auto[0]	values[4]	values[4]	392	1			T23	8		T232	20		T43	16
auto[0]	values[4]	values[5]	254	1			T40	11		T197	39		T233	14
auto[0]	values[4]	values[6]	308	1			T11	13		T36	11		T234	50
auto[0]	values[4]	values[7]	350	1			T235	12		T22	11		T23	6
auto[0]	values[5]	values[0]	262	1			T10	48		T40	12		T29	12
auto[0]	values[5]	values[1]	249	1			T38	13		T36	5		T20	13
auto[0]	values[5]	values[2]	341	1			T178	15		T69	23		T72	46
auto[0]	values[5]	values[3]	311	1			T18	7		T215	4		T39	15
auto[0]	values[5]	values[4]	413	1			T191	16		T20	15		T22	12
auto[0]	values[5]	values[5]	256	1			T210	12		T158	6		T192	16
auto[0]	values[5]	values[6]	361	1			T20	11		T210	13		T197	10
auto[0]	values[5]	values[7]	446	1			T11	12		T37	13		T40	14
auto[0]	values[6]	values[0]	447	1			T37	10		T39	13		T22	33
auto[0]	values[6]	values[1]	247	1			T38	8		T39	11		T29	14
auto[0]	values[6]	values[2]	256	1			T183	14		T78	32		T179	15
auto[0]	values[6]	values[3]	445	1			T10	50		T38	64		T36	15
auto[0]	values[6]	values[4]	459	1			T20	27		T22	11		T78	11
auto[0]	values[6]	values[5]	288	1			T23	12		T78	7		T72	48
auto[0]	values[6]	values[6]	255	1			T39	12		T22	24		T69	12
auto[0]	values[6]	values[7]	167	1			T22	29		T78	19		T187	14
auto[0]	values[7]	values[0]	303	1			T40	17		T22	22		T183	13
auto[0]	values[7]	values[1]	411	1			T23	8		T210	6		T192	14
auto[0]	values[7]	values[2]	228	1			T178	10		T23	18		T210	11
auto[0]	values[7]	values[3]	310	1			T23	29		T78	20		T205	18
auto[0]	values[7]	values[4]	427	1			T10	51		T129	12		T72	19
auto[0]	values[7]	values[5]	248	1			T36	28		T22	9		T161	20
auto[0]	values[7]	values[6]	296	1			T192	8		T196	5		T236	2
auto[0]	values[7]	values[7]	245	1			T237	10		T22	9		T238	20
auto[1]	values[0]	values[0]	184	1			T20	12		T210	34		T78	14
auto[1]	values[0]	values[1]	312	1			T39	13		T197	4		T69	25
auto[1]	values[0]	values[2]	259	1			T38	23		T20	22		T39	15
auto[1]	values[0]	values[3]	116	1			T178	5		T29	10		T197	10
auto[1]	values[0]	values[4]	206	1			T18	9		T37	26		T23	3
auto[1]	values[0]	values[5]	197	1			T18	9		T36	9		T178	9
auto[1]	values[0]	values[6]	176	1			T239	6		T196	21		T193	12
auto[1]	values[0]	values[7]	193	1			T38	9		T52	6		T203	12
auto[1]	values[1]	values[0]	209	1			T20	9		T128	20		T151	32
auto[1]	values[1]	values[1]	207	1			T36	4		T23	17		T195	7
auto[1]	values[1]	values[2]	259	1			T197	4		T240	113		T241	12
auto[1]	values[1]	values[3]	161	1			T38	8		T242	22		T203	12
auto[1]	values[1]	values[4]	186	1			T243	12		T192	7		T69	7
auto[1]	values[1]	values[5]	279	1			T23	10		T179	10		T244	13
auto[1]	values[1]	values[6]	324	1			T22	6		T245	4		T197	11
auto[1]	values[1]	values[7]	197	1			T40	6		T29	3		T151	4
auto[1]	values[2]	values[0]	230	1			T18	10		T39	9		T22	66
auto[1]	values[2]	values[1]	132	1			T38	11		T195	20		T246	14
auto[1]	values[2]	values[2]	133	1			T38	12		T20	6		T39	9
auto[1]	values[2]	values[3]	197	1			T203	6		T187	6		T180	6
auto[1]	values[2]	values[4]	283	1			T37	13		T36	55		T72	10
auto[1]	values[2]	values[5]	194	1			T36	9		T22	15		T29	8
auto[1]	values[2]	values[6]	180	1			T22	11		T210	10		T196	9
auto[1]	values[2]	values[7]	335	1			T18	9		T39	13		T22	22
auto[1]	values[3]	values[0]	79	1			T210	11		T67	4		T187	14
auto[1]	values[3]	values[1]	383	1			T40	11		T192	68		T179	11
auto[1]	values[3]	values[2]	247	1			T213	12		T197	10		T43	6
auto[1]	values[3]	values[3]	224	1			T36	35		T22	11		T192	17
auto[1]	values[3]	values[4]	214	1			T20	10		T40	9		T150	11
auto[1]	values[3]	values[5]	192	1			T11	11		T18	20		T244	6
auto[1]	values[3]	values[6]	234	1			T14	28		T22	31		T210	8
auto[1]	values[3]	values[7]	176	1			T11	4		T40	34		T193	8
auto[1]	values[4]	values[0]	261	1			T10	95		T11	38		T18	8
auto[1]	values[4]	values[1]	217	1			T36	64		T20	7		T39	16
auto[1]	values[4]	values[2]	232	1			T36	13		T230	10		T231	7
auto[1]	values[4]	values[3]	174	1			T11	7		T39	5		T193	43
auto[1]	values[4]	values[4]	177	1			T23	12		T43	11		T150	10
auto[1]	values[4]	values[5]	296	1			T40	66		T197	9		T151	16
auto[1]	values[4]	values[6]	192	1			T11	7		T36	9		T43	33
auto[1]	values[4]	values[7]	346	1			T22	19		T23	14		T210	7
auto[1]	values[5]	values[0]	177	1			T10	9		T40	10		T29	10
auto[1]	values[5]	values[1]	188	1			T38	7		T36	45		T20	9
auto[1]	values[5]	values[2]	124	1			T94	6		T178	5		T69	10
auto[1]	values[5]	values[3]	157	1			T18	13		T39	5		T72	35
auto[1]	values[5]	values[4]	144	1			T20	5		T22	8		T210	6
auto[1]	values[5]	values[5]	207	1			T210	8		T192	14		T195	8
auto[1]	values[5]	values[6]	275	1			T20	9		T210	69		T197	10
auto[1]	values[5]	values[7]	264	1			T11	12		T37	18		T40	6
auto[1]	values[6]	values[0]	230	1			T37	52		T39	10		T22	31
auto[1]	values[6]	values[1]	232	1			T38	31		T39	9		T29	6
auto[1]	values[6]	values[2]	161	1			T183	6		T78	55		T179	5
auto[1]	values[6]	values[3]	285	1			T10	5		T38	31		T36	5
auto[1]	values[6]	values[4]	389	1			T20	107		T22	9		T78	30
auto[1]	values[6]	values[5]	244	1			T23	8		T78	87		T72	8
auto[1]	values[6]	values[6]	251	1			T39	10		T22	7		T69	8
auto[1]	values[6]	values[7]	184	1			T22	7		T78	21		T187	30
auto[1]	values[7]	values[0]	202	1			T40	7		T22	8		T183	7
auto[1]	values[7]	values[1]	218	1			T23	12		T210	14		T192	6
auto[1]	values[7]	values[2]	230	1			T178	10		T23	2		T210	25
auto[1]	values[7]	values[3]	144	1			T23	6		T78	11		T197	26
auto[1]	values[7]	values[4]	211	1			T10	6		T72	21		T152	10
auto[1]	values[7]	values[5]	85	1			T36	13		T22	11		T193	6
auto[1]	values[7]	values[6]	199	1			T192	40		T196	15		T186	6
auto[1]	values[7]	values[7]	144	1			T22	15		T183	10		T29	11