Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	471	1			T18	1		T37	4		T38	4
auto[ReadAddrCrossIntoMailbox]	330	1			T6	4		T10	2		T38	3
auto[ReadAddrCrossOutOfMailbox]	320	1			T6	6		T10	1		T11	1
auto[ReadAddrCrossAllMailbox]	206	1			T6	6		T10	1		T18	2
auto[ReadAddrOutsideMailbox]	3794	1			T10	15		T11	24		T14	6

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2514

1

T6

8

T10

10

T11

12

auto[1]

2607

1

T6

8

T10

9

T11

13

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	812	1			T10	5		T11	2		T37	2
read_ops[0x0b]	869	1			T10	2		T11	4		T14	4
read_ops[0x3b]	851	1			T10	2		T11	4		T17	2
read_ops[0x6b]	854	1			T6	8		T10	4		T11	6
read_ops[0xbb]	892	1			T6	6		T10	4		T11	5
read_ops[0xeb]	843	1			T6	2		T10	2		T11	4

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	39	1			T38	1		T191	1		T20	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	36	1			T36	1		T191	1		T40	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	30	1			T39	2		T22	1		T78	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	30	1			T10	1		T22	1		T178	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	27	1			T20	1		T22	1		T72	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	29	1			T22	2		T192	1		T197	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T20	1		T40	1		T78	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T78	1		T197	1		T186	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	266	1			T10	2		T11	1		T37	2
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	317	1			T10	2		T11	1		T38	3
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	39	1			T37	1		T38	1		T36	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	41	1			T37	2		T191	1		T23	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	30	1			T38	1		T36	2		T178	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	26	1			T36	1		T40	1		T22	2
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	21	1			T11	1		T20	1		T22	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	24	1			T38	2		T22	1		T149	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T178	2		T193	1		T69	2
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	14	1			T18	1		T23	1		T193	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	311	1			T11	3		T14	2		T17	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	348	1			T10	2		T14	2		T17	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	50	1			T38	1		T36	2		T191	3
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	42	1			T191	3		T22	1		T29	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	21	1			T20	1		T22	2		T178	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	33	1			T36	1		T39	1		T40	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	31	1			T39	2		T22	1		T78	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	25	1			T20	1		T192	2		T197	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T36	1		T244	1		T230	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	13	1			T39	2		T210	1		T151	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	312	1			T10	2		T11	2		T17	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	306	1			T11	2		T17	1		T37	3
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	32	1			T36	1		T39	1		T22	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	36	1			T20	1		T183	1		T210	2
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	23	1			T6	2		T10	1		T38	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	27	1			T6	2		T38	1		T40	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	35	1			T6	1		T36	1		T39	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	30	1			T6	1		T183	1		T210	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	21	1			T6	1		T221	1		T38	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	15	1			T6	1		T18	1		T221	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	322	1			T10	2		T11	1		T18	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	313	1			T10	1		T11	5		T18	3
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	40	1			T191	1		T68	2		T72	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	50	1			T38	1		T36	2		T191	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	27	1			T36	1		T39	1		T23	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	25	1			T20	3		T178	1		T179	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	16	1			T6	1		T22	1		T72	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	34	1			T6	1		T10	1		T18	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T6	2		T36	1		T193	3
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	23	1			T6	2		T20	2		T22	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	346	1			T10	3		T11	2		T14	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	315	1			T11	3		T14	1		T18	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	33	1			T191	1		T39	2		T210	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	33	1			T18	1		T37	1		T191	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	28	1			T39	1		T22	1		T183	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	30	1			T20	1		T39	2		T22	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	30	1			T6	1		T18	1		T20	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	18	1			T6	1		T20	1		T40	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T221	1		T36	1		T39	2
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T10	1		T37	1		T221	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	299	1			T11	2		T18	2		T109	2
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	339	1			T10	1		T11	2		T18	1