Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	760	1			T7	21		T15	10		T19	14
all_values[1]	760	1			T7	21		T15	10		T19	14
all_values[2]	760	1			T7	21		T15	10		T19	14
all_values[3]	760	1			T7	21		T15	10		T19	14
all_values[4]	760	1			T7	21		T15	10		T19	14
all_values[5]	760	1			T7	21		T15	10		T19	14
all_values[6]	760	1			T7	21		T15	10		T19	14
all_values[7]	760	1			T7	21		T15	10		T19	14

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3233

1

T7

77

T15

42

T19

64

auto[1]

2847

1

T7

91

T15

38

T19

48

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2447

1

T7

68

T15

36

T19

52

auto[1]

3633

1

T7

100

T15

44

T19

60

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3522

1

T7

88

T15

46

T19

69

auto[1]

2558

1

T7

80

T15

34

T19

43

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	158	1			T7	2		T15	1		T19	6
all_values[0]	auto[0]	auto[0]	auto[1]	55	1			T7	2		T19	1		T28	1
all_values[0]	auto[0]	auto[1]	auto[0]	130	1			T7	3		T15	3		T19	5
all_values[0]	auto[0]	auto[1]	auto[1]	79	1			T7	1		T15	1		T20	1
all_values[0]	auto[1]	auto[0]	auto[1]	168	1			T7	6		T15	2		T19	2
all_values[0]	auto[1]	auto[1]	auto[1]	170	1			T7	7		T15	3		T20	2
all_values[1]	auto[0]	auto[0]	auto[0]	170	1			T7	7		T15	2		T19	1
all_values[1]	auto[0]	auto[0]	auto[1]	81	1			T7	2		T15	1		T19	1
all_values[1]	auto[0]	auto[1]	auto[0]	124	1			T7	4		T19	6		T27	4
all_values[1]	auto[0]	auto[1]	auto[1]	81	1			T15	1		T20	1		T27	2
all_values[1]	auto[1]	auto[0]	auto[1]	160	1			T7	5		T15	2		T19	4
all_values[1]	auto[1]	auto[1]	auto[1]	144	1			T7	3		T15	4		T19	2
all_values[2]	auto[0]	auto[0]	auto[0]	167	1			T7	3		T15	2		T19	4
all_values[2]	auto[0]	auto[0]	auto[1]	81	1			T7	1		T19	2		T21	1
all_values[2]	auto[0]	auto[1]	auto[0]	115	1			T7	7		T15	6		T19	2
all_values[2]	auto[0]	auto[1]	auto[1]	90	1			T7	1		T19	1		T20	2
all_values[2]	auto[1]	auto[0]	auto[1]	154	1			T7	6		T19	3		T20	1
all_values[2]	auto[1]	auto[1]	auto[1]	153	1			T7	3		T15	2		T19	2
all_values[3]	auto[0]	auto[0]	auto[0]	174	1			T7	1		T15	5		T19	1
all_values[3]	auto[0]	auto[0]	auto[1]	71	1			T7	3		T15	1		T19	2
all_values[3]	auto[0]	auto[1]	auto[0]	103	1			T7	3		T15	1		T19	3
all_values[3]	auto[0]	auto[1]	auto[1]	80	1			T7	3		T15	1		T19	4
all_values[3]	auto[1]	auto[0]	auto[1]	182	1			T7	6		T19	3		T20	1
all_values[3]	auto[1]	auto[1]	auto[1]	150	1			T7	5		T15	2		T19	1
all_values[4]	auto[0]	auto[0]	auto[0]	154	1			T7	2		T15	2		T19	5
all_values[4]	auto[0]	auto[0]	auto[1]	80	1			T7	1		T15	2		T19	2
all_values[4]	auto[0]	auto[1]	auto[0]	123	1			T7	7		T15	2		T19	1
all_values[4]	auto[0]	auto[1]	auto[1]	80	1			T7	2		T27	3		T29	1
all_values[4]	auto[1]	auto[0]	auto[1]	164	1			T7	4		T15	3		T19	3
all_values[4]	auto[1]	auto[1]	auto[1]	159	1			T7	5		T15	1		T19	3
all_values[5]	auto[0]	auto[0]	auto[0]	228	1			T7	3		T15	1		T19	4
all_values[5]	auto[0]	auto[1]	auto[0]	199	1			T7	5		T15	2		T19	2
all_values[5]	auto[1]	auto[0]	auto[1]	178	1			T7	4		T15	4		T19	6
all_values[5]	auto[1]	auto[1]	auto[1]	155	1			T7	9		T15	3		T19	2
all_values[6]	auto[0]	auto[0]	auto[0]	166	1			T7	5		T15	6		T19	4
all_values[6]	auto[0]	auto[0]	auto[1]	68	1			T15	1		T21	3		T27	1
all_values[6]	auto[0]	auto[1]	auto[0]	142	1			T7	4		T19	3		T20	4
all_values[6]	auto[0]	auto[1]	auto[1]	73	1			T7	2		T19	1		T21	1
all_values[6]	auto[1]	auto[0]	auto[1]	173	1			T7	2		T15	1		T19	2
all_values[6]	auto[1]	auto[1]	auto[1]	138	1			T7	8		T15	2		T19	4
all_values[7]	auto[0]	auto[0]	auto[0]	157	1			T7	8		T15	2		T19	4
all_values[7]	auto[0]	auto[0]	auto[1]	73	1			T7	1		T15	2		T19	1
all_values[7]	auto[0]	auto[1]	auto[0]	137	1			T7	4		T15	1		T19	1
all_values[7]	auto[0]	auto[1]	auto[1]	83	1			T7	1		T19	2		T20	2
all_values[7]	auto[1]	auto[0]	auto[1]	171	1			T7	3		T15	2		T19	3
all_values[7]	auto[1]	auto[1]	auto[1]	139	1			T7	4		T15	3		T19	3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal