Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1749

1

T1

10

T2

5

T4

14

auto[1]

1659

1

T1

8

T2

2

T4

11

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1824

1

T1

18

T2

7

T11

6

auto[1]

1584

1

T4

25

T11

2

T15

7

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2722

1

T1

18

T2

5

T4

25

auto[1]

686

1

T2

2

T11

3

T15

19

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	700	1			T1	3		T2	2		T4	9
valid[1]	690	1			T1	5		T2	3		T4	6
valid[2]	656	1			T1	2		T4	2		T11	2
valid[3]	643	1			T1	2		T2	1		T15	4
valid[4]	719	1			T1	6		T2	1		T4	8

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	123	1			T1	2		T2	2		T18	1
auto[0]	auto[0]	valid[0]	auto[1]	151	1			T4	3		T87	1		T306	1
auto[0]	auto[0]	valid[1]	auto[0]	118	1			T1	3		T2	1		T11	1
auto[0]	auto[0]	valid[1]	auto[1]	174	1			T4	4		T15	1		T37	1
auto[0]	auto[0]	valid[2]	auto[0]	121	1			T1	1		T15	2		T24	2
auto[0]	auto[0]	valid[2]	auto[1]	174	1			T4	2		T11	1		T15	1
auto[0]	auto[0]	valid[3]	auto[0]	108	1			T1	2		T26	1		T37	2
auto[0]	auto[0]	valid[3]	auto[1]	137	1			T15	1		T85	1		T87	2
auto[0]	auto[0]	valid[4]	auto[0]	120	1			T1	2		T15	4		T18	1
auto[0]	auto[0]	valid[4]	auto[1]	161	1			T4	5		T15	1		T37	1
auto[0]	auto[1]	valid[0]	auto[0]	104	1			T1	1		T15	4		T37	1
auto[0]	auto[1]	valid[0]	auto[1]	170	1			T4	6		T15	2		T85	1
auto[0]	auto[1]	valid[1]	auto[0]	103	1			T1	2		T2	1		T11	1
auto[0]	auto[1]	valid[1]	auto[1]	144	1			T4	2		T85	1		T126	1
auto[0]	auto[1]	valid[2]	auto[0]	93	1			T1	1		T11	1		T15	1
auto[0]	auto[1]	valid[2]	auto[1]	153	1			T15	1		T85	1		T87	2
auto[0]	auto[1]	valid[3]	auto[0]	124	1			T2	1		T15	1		T18	3
auto[0]	auto[1]	valid[3]	auto[1]	145	1			T37	1		T85	1		T87	1
auto[0]	auto[1]	valid[4]	auto[0]	124	1			T1	4		T24	3		T22	2
auto[0]	auto[1]	valid[4]	auto[1]	175	1			T4	3		T11	1		T85	1
auto[1]	auto[0]	valid[0]	auto[0]	80	1			T11	1		T15	2		T39	1
auto[1]	auto[0]	valid[1]	auto[0]	83	1			T2	1		T15	1		T37	3
auto[1]	auto[0]	valid[2]	auto[0]	60	1			T15	5		T24	2		T30	1
auto[1]	auto[0]	valid[3]	auto[0]	72	1			T76	1		T30	2		T148	1
auto[1]	auto[0]	valid[4]	auto[0]	67	1			T2	1		T15	1		T18	1
auto[1]	auto[1]	valid[0]	auto[0]	72	1			T11	1		T15	3		T18	1
auto[1]	auto[1]	valid[1]	auto[0]	68	1			T15	3		T24	2		T25	1
auto[1]	auto[1]	valid[2]	auto[0]	55	1			T15	1		T24	1		T76	1
auto[1]	auto[1]	valid[3]	auto[0]	57	1			T15	2		T37	1		T165	1
auto[1]	auto[1]	valid[4]	auto[0]	72	1			T11	1		T15	1		T24	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal