Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

44771

1

T1

238

T2

137

T11

278

auto[1]

16576

1

T4

438

T11

69

T15

101

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

45043

1

T1

166

T2

84

T4

438

auto[1]

16304

1

T1

72

T2

53

T11

99

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	31574	1			T1	123		T2	75		T4	212
others[1]	5218	1			T1	24		T2	5		T4	46
others[2]	5142	1			T1	21		T2	12		T4	37
others[3]	5910	1			T1	16		T2	13		T4	53
interest[1]	3388	1			T1	15		T2	13		T4	17
interest[4]	20663	1			T1	76		T2	46		T4	150
interest[64]	10115	1			T1	39		T2	19		T4	73

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	14657	1			T1	88		T2	45		T11	94
auto[0]	auto[0]	others[1]	2421	1			T1	15		T2	2		T11	10
auto[0]	auto[0]	others[2]	2376	1			T1	14		T2	7		T11	9
auto[0]	auto[0]	others[3]	2767	1			T1	11		T2	9		T11	17
auto[0]	auto[0]	interest[1]	1580	1			T1	11		T2	8		T11	12
auto[0]	auto[0]	interest[4]	9513	1			T1	53		T2	26		T11	66
auto[0]	auto[0]	interest[64]	4666	1			T1	27		T2	13		T11	37
auto[0]	auto[1]	others[0]	8585	1			T4	212		T11	33		T15	53
auto[0]	auto[1]	others[1]	1387	1			T4	46		T11	5		T15	9
auto[0]	auto[1]	others[2]	1377	1			T4	37		T11	5		T15	9
auto[0]	auto[1]	others[3]	1615	1			T4	53		T11	12		T15	6
auto[0]	auto[1]	interest[1]	900	1			T4	17		T11	3		T15	7
auto[0]	auto[1]	interest[4]	5748	1			T4	150		T11	24		T15	33
auto[0]	auto[1]	interest[64]	2712	1			T4	73		T11	11		T15	17
auto[1]	auto[0]	others[0]	8332	1			T1	35		T2	30		T11	52
auto[1]	auto[0]	others[1]	1410	1			T1	9		T2	3		T11	11
auto[1]	auto[0]	others[2]	1389	1			T1	7		T2	5		T11	11
auto[1]	auto[0]	others[3]	1528	1			T1	5		T2	4		T11	11
auto[1]	auto[0]	interest[1]	908	1			T1	4		T2	5		T11	4
auto[1]	auto[0]	interest[4]	5402	1			T1	23		T2	20		T11	36
auto[1]	auto[0]	interest[64]	2737	1			T1	12		T2	6		T11	10

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal