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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.04 98.38 93.99 98.62 89.36 97.19 95.45 99.26


Total test records in report: 1131
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T119 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1608432394 Jul 24 05:52:41 PM PDT 24 Jul 24 05:52:43 PM PDT 24 100581685 ps
T108 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3990127401 Jul 24 05:52:53 PM PDT 24 Jul 24 05:52:55 PM PDT 24 147814881 ps
T120 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.966870225 Jul 24 05:52:52 PM PDT 24 Jul 24 05:52:55 PM PDT 24 355158720 ps
T1032 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1056293374 Jul 24 05:52:53 PM PDT 24 Jul 24 05:52:54 PM PDT 24 18236019 ps
T145 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.767704237 Jul 24 05:52:39 PM PDT 24 Jul 24 05:53:03 PM PDT 24 997191003 ps
T1033 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.865114119 Jul 24 05:52:34 PM PDT 24 Jul 24 05:52:37 PM PDT 24 389171068 ps
T101 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.3621954510 Jul 24 05:52:35 PM PDT 24 Jul 24 05:52:40 PM PDT 24 142960048 ps
T1034 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3526397115 Jul 24 05:52:34 PM PDT 24 Jul 24 05:52:35 PM PDT 24 13171429 ps
T102 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3018817882 Jul 24 05:52:38 PM PDT 24 Jul 24 05:52:41 PM PDT 24 128594413 ps
T1035 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.1049442016 Jul 24 05:52:55 PM PDT 24 Jul 24 05:52:56 PM PDT 24 53587919 ps
T1036 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.4256943785 Jul 24 05:52:34 PM PDT 24 Jul 24 05:53:00 PM PDT 24 3090357606 ps
T1037 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.4225069413 Jul 24 05:52:57 PM PDT 24 Jul 24 05:52:58 PM PDT 24 13965455 ps
T1038 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2626007178 Jul 24 05:52:49 PM PDT 24 Jul 24 05:52:52 PM PDT 24 128713324 ps
T1039 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.3053734994 Jul 24 05:52:59 PM PDT 24 Jul 24 05:53:01 PM PDT 24 19875177 ps
T1040 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1116483596 Jul 24 05:52:57 PM PDT 24 Jul 24 05:52:57 PM PDT 24 85465095 ps
T104 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.4284616653 Jul 24 05:52:46 PM PDT 24 Jul 24 05:52:49 PM PDT 24 55070696 ps
T1041 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.3050360915 Jul 24 05:52:56 PM PDT 24 Jul 24 05:52:57 PM PDT 24 171683607 ps
T105 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.3922451748 Jul 24 05:52:55 PM PDT 24 Jul 24 05:52:59 PM PDT 24 367567322 ps
T1042 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.1427693444 Jul 24 05:52:31 PM PDT 24 Jul 24 05:53:07 PM PDT 24 7512785152 ps
T121 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2011975792 Jul 24 05:52:44 PM PDT 24 Jul 24 05:52:47 PM PDT 24 104118534 ps
T170 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.1041145337 Jul 24 05:52:45 PM PDT 24 Jul 24 05:52:51 PM PDT 24 814170601 ps
T1043 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.3969062721 Jul 24 05:52:30 PM PDT 24 Jul 24 05:52:31 PM PDT 24 15845952 ps
T1044 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.968916100 Jul 24 05:52:39 PM PDT 24 Jul 24 05:52:43 PM PDT 24 642153125 ps
T81 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.274641308 Jul 24 05:52:31 PM PDT 24 Jul 24 05:52:32 PM PDT 24 63948140 ps
T106 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.3442010851 Jul 24 05:52:33 PM PDT 24 Jul 24 05:52:37 PM PDT 24 202026460 ps
T167 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.3557120945 Jul 24 05:52:52 PM PDT 24 Jul 24 05:52:56 PM PDT 24 243278637 ps
T122 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.121992355 Jul 24 05:52:34 PM PDT 24 Jul 24 05:52:42 PM PDT 24 467762651 ps
T1045 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3530477057 Jul 24 05:53:00 PM PDT 24 Jul 24 05:53:01 PM PDT 24 13173298 ps
T1046 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3530584195 Jul 24 05:52:43 PM PDT 24 Jul 24 05:52:45 PM PDT 24 23617398 ps
T171 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2063447697 Jul 24 05:52:40 PM PDT 24 Jul 24 05:52:58 PM PDT 24 650615571 ps
T1047 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1623927789 Jul 24 05:52:32 PM PDT 24 Jul 24 05:53:09 PM PDT 24 1869818433 ps
T1048 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.2078195028 Jul 24 05:52:59 PM PDT 24 Jul 24 05:53:00 PM PDT 24 42326703 ps
T146 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.531819073 Jul 24 05:52:33 PM PDT 24 Jul 24 05:52:40 PM PDT 24 1249428322 ps
T1049 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.300137731 Jul 24 05:52:53 PM PDT 24 Jul 24 05:52:55 PM PDT 24 56863842 ps
T82 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.958937638 Jul 24 05:52:32 PM PDT 24 Jul 24 05:52:34 PM PDT 24 296804005 ps
T1050 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.4189894049 Jul 24 05:52:50 PM PDT 24 Jul 24 05:52:54 PM PDT 24 150726031 ps
T1051 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.4161698805 Jul 24 05:52:36 PM PDT 24 Jul 24 05:52:44 PM PDT 24 3787755092 ps
T1052 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1973108967 Jul 24 05:52:30 PM PDT 24 Jul 24 05:52:33 PM PDT 24 139427393 ps
T1053 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.1156002386 Jul 24 05:52:30 PM PDT 24 Jul 24 05:52:33 PM PDT 24 25507029 ps
T1054 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3844495913 Jul 24 05:52:36 PM PDT 24 Jul 24 05:52:37 PM PDT 24 39746105 ps
T147 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1065883982 Jul 24 05:52:49 PM PDT 24 Jul 24 05:52:51 PM PDT 24 127130561 ps
T162 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.2788351403 Jul 24 05:52:44 PM PDT 24 Jul 24 05:52:48 PM PDT 24 147751763 ps
T1055 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.4110773904 Jul 24 05:52:39 PM PDT 24 Jul 24 05:52:40 PM PDT 24 18605901 ps
T1056 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.1846123505 Jul 24 05:52:54 PM PDT 24 Jul 24 05:52:55 PM PDT 24 11196940 ps
T1057 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3900638497 Jul 24 05:52:55 PM PDT 24 Jul 24 05:52:57 PM PDT 24 135604240 ps
T123 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3551949309 Jul 24 05:52:44 PM PDT 24 Jul 24 05:52:46 PM PDT 24 164155351 ps
T1058 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.408748019 Jul 24 05:52:35 PM PDT 24 Jul 24 05:52:36 PM PDT 24 13802220 ps
T1059 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.205328285 Jul 24 05:52:48 PM PDT 24 Jul 24 05:52:49 PM PDT 24 58975664 ps
T83 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.1986787557 Jul 24 05:52:29 PM PDT 24 Jul 24 05:52:30 PM PDT 24 52344983 ps
T1060 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.1592888225 Jul 24 05:52:57 PM PDT 24 Jul 24 05:52:58 PM PDT 24 11827388 ps
T1061 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.1651744372 Jul 24 05:52:38 PM PDT 24 Jul 24 05:52:39 PM PDT 24 80072204 ps
T1062 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3208445837 Jul 24 05:52:43 PM PDT 24 Jul 24 05:52:47 PM PDT 24 302445320 ps
T124 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2876435726 Jul 24 05:52:33 PM PDT 24 Jul 24 05:52:36 PM PDT 24 397361121 ps
T1063 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.762104081 Jul 24 05:52:51 PM PDT 24 Jul 24 05:52:53 PM PDT 24 276858135 ps
T1064 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3501668545 Jul 24 05:52:52 PM PDT 24 Jul 24 05:52:56 PM PDT 24 341832166 ps
T176 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.2839602022 Jul 24 05:52:32 PM PDT 24 Jul 24 05:52:51 PM PDT 24 804592427 ps
T1065 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3251592030 Jul 24 05:52:39 PM PDT 24 Jul 24 05:52:41 PM PDT 24 334793344 ps
T174 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.3389616902 Jul 24 05:52:51 PM PDT 24 Jul 24 05:53:10 PM PDT 24 1904303236 ps
T1066 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.3780389519 Jul 24 05:52:50 PM PDT 24 Jul 24 05:52:51 PM PDT 24 43035104 ps
T1067 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.3301512294 Jul 24 05:52:51 PM PDT 24 Jul 24 05:52:54 PM PDT 24 50554530 ps
T1068 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.2724971025 Jul 24 05:52:36 PM PDT 24 Jul 24 05:52:38 PM PDT 24 75668411 ps
T1069 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.1901877054 Jul 24 05:52:45 PM PDT 24 Jul 24 05:52:46 PM PDT 24 14280137 ps
T1070 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1608009691 Jul 24 05:52:32 PM PDT 24 Jul 24 05:52:36 PM PDT 24 521506420 ps
T1071 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.4059083521 Jul 24 05:52:41 PM PDT 24 Jul 24 05:52:44 PM PDT 24 228240729 ps
T175 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.4268359920 Jul 24 05:52:49 PM PDT 24 Jul 24 05:53:01 PM PDT 24 227979394 ps
T1072 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2794215572 Jul 24 05:52:39 PM PDT 24 Jul 24 05:52:41 PM PDT 24 30067242 ps
T173 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.4095387612 Jul 24 05:52:40 PM PDT 24 Jul 24 05:52:53 PM PDT 24 197475805 ps
T1073 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.2899699427 Jul 24 05:52:52 PM PDT 24 Jul 24 05:52:56 PM PDT 24 87159722 ps
T169 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.705234369 Jul 24 05:52:30 PM PDT 24 Jul 24 05:52:43 PM PDT 24 363379377 ps
T1074 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.2121561481 Jul 24 05:52:36 PM PDT 24 Jul 24 05:52:45 PM PDT 24 1003321342 ps
T1075 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.4030181335 Jul 24 05:52:44 PM PDT 24 Jul 24 05:52:47 PM PDT 24 347687896 ps
T1076 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.3443554292 Jul 24 05:52:37 PM PDT 24 Jul 24 05:52:39 PM PDT 24 109993679 ps
T84 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3439867930 Jul 24 05:52:34 PM PDT 24 Jul 24 05:52:36 PM PDT 24 22416029 ps
T1077 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.299942265 Jul 24 05:52:35 PM PDT 24 Jul 24 05:52:38 PM PDT 24 1092111144 ps
T1078 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.3926418578 Jul 24 05:52:32 PM PDT 24 Jul 24 05:52:36 PM PDT 24 238432444 ps
T1079 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.1576724804 Jul 24 05:52:41 PM PDT 24 Jul 24 05:52:42 PM PDT 24 230459764 ps
T1080 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.637285516 Jul 24 05:52:47 PM PDT 24 Jul 24 05:52:49 PM PDT 24 100835980 ps
T1081 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.802118716 Jul 24 05:52:51 PM PDT 24 Jul 24 05:52:52 PM PDT 24 20714808 ps
T1082 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.376769240 Jul 24 05:53:00 PM PDT 24 Jul 24 05:53:01 PM PDT 24 18972330 ps
T1083 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.1690189625 Jul 24 05:52:56 PM PDT 24 Jul 24 05:52:57 PM PDT 24 64272979 ps
T1084 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.4034756624 Jul 24 05:52:52 PM PDT 24 Jul 24 05:52:56 PM PDT 24 108260807 ps
T1085 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.2508434975 Jul 24 05:52:38 PM PDT 24 Jul 24 05:52:39 PM PDT 24 40903095 ps
T1086 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.1402332202 Jul 24 05:53:02 PM PDT 24 Jul 24 05:53:03 PM PDT 24 46505686 ps
T1087 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1936862212 Jul 24 05:52:34 PM PDT 24 Jul 24 05:52:37 PM PDT 24 40082048 ps
T1088 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.4228324644 Jul 24 05:52:42 PM PDT 24 Jul 24 05:52:45 PM PDT 24 407579976 ps
T1089 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1048041141 Jul 24 05:52:33 PM PDT 24 Jul 24 05:52:51 PM PDT 24 2882869477 ps
T177 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.3811040256 Jul 24 05:52:51 PM PDT 24 Jul 24 05:52:59 PM PDT 24 1985552496 ps
T1090 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.3951968294 Jul 24 05:53:02 PM PDT 24 Jul 24 05:53:03 PM PDT 24 12556913 ps
T1091 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.412468041 Jul 24 05:52:50 PM PDT 24 Jul 24 05:52:52 PM PDT 24 29486747 ps
T172 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2185296786 Jul 24 05:52:35 PM PDT 24 Jul 24 05:52:48 PM PDT 24 205863741 ps
T1092 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.476912526 Jul 24 05:52:40 PM PDT 24 Jul 24 05:52:45 PM PDT 24 967540152 ps
T1093 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2535900640 Jul 24 05:52:51 PM PDT 24 Jul 24 05:52:55 PM PDT 24 118490819 ps
T168 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.2822182999 Jul 24 05:52:44 PM PDT 24 Jul 24 05:52:46 PM PDT 24 76987709 ps
T1094 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3063612092 Jul 24 05:52:33 PM PDT 24 Jul 24 05:52:34 PM PDT 24 517354576 ps
T1095 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3881744026 Jul 24 05:52:51 PM PDT 24 Jul 24 05:53:07 PM PDT 24 2145576375 ps
T1096 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.1514552145 Jul 24 05:53:02 PM PDT 24 Jul 24 05:53:03 PM PDT 24 80283122 ps
T1097 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1288546638 Jul 24 05:52:32 PM PDT 24 Jul 24 05:52:34 PM PDT 24 70221432 ps
T1098 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.2646415022 Jul 24 05:52:59 PM PDT 24 Jul 24 05:53:01 PM PDT 24 184702555 ps
T1099 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.1428367677 Jul 24 05:53:00 PM PDT 24 Jul 24 05:53:01 PM PDT 24 29571399 ps
T1100 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3707537425 Jul 24 05:52:50 PM PDT 24 Jul 24 05:52:52 PM PDT 24 25951815 ps
T1101 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.1179258586 Jul 24 05:52:44 PM PDT 24 Jul 24 05:52:49 PM PDT 24 3243905466 ps
T1102 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.1856833376 Jul 24 05:52:49 PM PDT 24 Jul 24 05:53:10 PM PDT 24 4915272761 ps
T1103 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3787959243 Jul 24 05:52:44 PM PDT 24 Jul 24 05:52:47 PM PDT 24 168744995 ps
T1104 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1856804456 Jul 24 05:52:40 PM PDT 24 Jul 24 05:52:45 PM PDT 24 235602372 ps
T1105 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2599906677 Jul 24 05:52:37 PM PDT 24 Jul 24 05:52:41 PM PDT 24 748669251 ps
T1106 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.2592530609 Jul 24 05:52:41 PM PDT 24 Jul 24 05:52:44 PM PDT 24 110880565 ps
T1107 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.80034362 Jul 24 05:52:30 PM PDT 24 Jul 24 05:52:44 PM PDT 24 864261384 ps
T1108 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.4041024241 Jul 24 05:52:34 PM PDT 24 Jul 24 05:52:50 PM PDT 24 716578935 ps
T1109 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.808852585 Jul 24 05:52:28 PM PDT 24 Jul 24 05:52:29 PM PDT 24 27683579 ps
T1110 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.231717287 Jul 24 05:52:59 PM PDT 24 Jul 24 05:53:00 PM PDT 24 38350567 ps
T1111 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.1722440279 Jul 24 05:53:01 PM PDT 24 Jul 24 05:53:02 PM PDT 24 15895865 ps
T1112 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.1458719823 Jul 24 05:52:58 PM PDT 24 Jul 24 05:52:59 PM PDT 24 21704633 ps
T1113 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2447306099 Jul 24 05:52:56 PM PDT 24 Jul 24 05:52:57 PM PDT 24 89030903 ps
T1114 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2056944837 Jul 24 05:52:34 PM PDT 24 Jul 24 05:52:39 PM PDT 24 157798538 ps
T1115 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2511478493 Jul 24 05:52:32 PM PDT 24 Jul 24 05:52:38 PM PDT 24 244819380 ps
T1116 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3024244009 Jul 24 05:52:44 PM PDT 24 Jul 24 05:52:48 PM PDT 24 2305899431 ps
T1117 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1523183087 Jul 24 05:52:49 PM PDT 24 Jul 24 05:52:51 PM PDT 24 108522376 ps
T1118 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1129328583 Jul 24 05:52:51 PM PDT 24 Jul 24 05:52:52 PM PDT 24 28725421 ps
T1119 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.2381936560 Jul 24 05:52:44 PM PDT 24 Jul 24 05:52:47 PM PDT 24 153359520 ps
T1120 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.1107687838 Jul 24 05:52:54 PM PDT 24 Jul 24 05:52:57 PM PDT 24 107324580 ps
T1121 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2822519728 Jul 24 05:52:56 PM PDT 24 Jul 24 05:52:57 PM PDT 24 20838029 ps
T1122 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1938758717 Jul 24 05:52:44 PM PDT 24 Jul 24 05:52:52 PM PDT 24 565968500 ps
T1123 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2413845365 Jul 24 05:52:39 PM PDT 24 Jul 24 05:52:40 PM PDT 24 27732022 ps
T1124 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.86202427 Jul 24 05:52:36 PM PDT 24 Jul 24 05:53:17 PM PDT 24 1818583853 ps
T1125 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1577786313 Jul 24 05:52:36 PM PDT 24 Jul 24 05:52:37 PM PDT 24 36239226 ps
T1126 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.4168094117 Jul 24 05:52:36 PM PDT 24 Jul 24 05:52:53 PM PDT 24 2314517674 ps
T1127 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.252076281 Jul 24 05:53:01 PM PDT 24 Jul 24 05:53:02 PM PDT 24 38237972 ps
T1128 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.3612611478 Jul 24 05:52:34 PM PDT 24 Jul 24 05:52:35 PM PDT 24 11977573 ps
T1129 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.399726091 Jul 24 05:52:34 PM PDT 24 Jul 24 05:52:38 PM PDT 24 191295357 ps
T1130 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.4125872007 Jul 24 05:52:33 PM PDT 24 Jul 24 05:52:34 PM PDT 24 18926931 ps
T1131 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2672797849 Jul 24 05:52:34 PM PDT 24 Jul 24 05:52:36 PM PDT 24 65441530 ps

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.2681751996
Short name T10
Test name
Test status
Simulation time 23651893918 ps
CPU time 65.43 seconds
Started Jul 24 05:56:20 PM PDT 24
Finished Jul 24 05:57:26 PM PDT 24
Peak memory 250508 kb
Host smart-f75c1277-fc89-4234-ae94-823b650c4dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681751996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.2681751996
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.761089980
Short name T15
Test name
Test status
Simulation time 5390477289 ps
CPU time 128.81 seconds
Started Jul 24 05:54:34 PM PDT 24
Finished Jul 24 05:56:43 PM PDT 24
Peak memory 273940 kb
Host smart-20d87ece-0562-49a3-bbf1-fe9147b07f94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761089980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stres
s_all.761089980
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.2415499233
Short name T22
Test name
Test status
Simulation time 164083008096 ps
CPU time 511.55 seconds
Started Jul 24 05:55:58 PM PDT 24
Finished Jul 24 06:04:29 PM PDT 24
Peak memory 298028 kb
Host smart-fb649eb9-022c-4108-81f5-2c45ce422304
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415499233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.2415499233
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.376819728
Short name T58
Test name
Test status
Simulation time 379169943 ps
CPU time 8.71 seconds
Started Jul 24 05:52:51 PM PDT 24
Finished Jul 24 05:52:59 PM PDT 24
Peak memory 215980 kb
Host smart-dfa8c7ee-48e7-4aba-b737-5d34cb6f5eb7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376819728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device
_tl_intg_err.376819728
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.3937421023
Short name T11
Test name
Test status
Simulation time 23227558957 ps
CPU time 110.31 seconds
Started Jul 24 05:55:30 PM PDT 24
Finished Jul 24 05:57:20 PM PDT 24
Peak memory 265672 kb
Host smart-12f95c83-9e05-426a-8fd5-e3670a0b154b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937421023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.3937421023
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.1337337142
Short name T61
Test name
Test status
Simulation time 15982255 ps
CPU time 0.77 seconds
Started Jul 24 05:53:53 PM PDT 24
Finished Jul 24 05:53:54 PM PDT 24
Peak memory 216208 kb
Host smart-8b1e0f00-4c4c-40ca-8e68-d946d96fcd22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337337142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.1337337142
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.3719969862
Short name T20
Test name
Test status
Simulation time 18856852595 ps
CPU time 188.69 seconds
Started Jul 24 05:54:58 PM PDT 24
Finished Jul 24 05:58:07 PM PDT 24
Peak memory 265700 kb
Host smart-f29daa64-d16e-4698-adf9-9756b4c3fe68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719969862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.3719969862
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.1409039791
Short name T23
Test name
Test status
Simulation time 139743469777 ps
CPU time 542.35 seconds
Started Jul 24 05:54:33 PM PDT 24
Finished Jul 24 06:03:36 PM PDT 24
Peak memory 257560 kb
Host smart-a84d4602-983c-4cf2-9581-af5520a85ba5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409039791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.1409039791
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.2021481715
Short name T100
Test name
Test status
Simulation time 526090784 ps
CPU time 4 seconds
Started Jul 24 05:52:42 PM PDT 24
Finished Jul 24 05:52:47 PM PDT 24
Peak memory 215720 kb
Host smart-3b3a6bbf-4598-4244-b749-392978fd79e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021481715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
2021481715
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.3313833712
Short name T152
Test name
Test status
Simulation time 87221963351 ps
CPU time 304 seconds
Started Jul 24 05:54:06 PM PDT 24
Finished Jul 24 05:59:10 PM PDT 24
Peak memory 273992 kb
Host smart-e94db93d-aab0-4da6-8aa9-4025cfa0bd45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313833712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.3313833712
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.1560871430
Short name T69
Test name
Test status
Simulation time 104251217929 ps
CPU time 263.74 seconds
Started Jul 24 05:54:11 PM PDT 24
Finished Jul 24 05:58:35 PM PDT 24
Peak memory 272852 kb
Host smart-487b1fb9-5934-4dcb-8b71-436806c97449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560871430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.1560871430
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.23642992
Short name T5
Test name
Test status
Simulation time 13458909625 ps
CPU time 34.5 seconds
Started Jul 24 05:54:35 PM PDT 24
Finished Jul 24 05:55:10 PM PDT 24
Peak memory 234564 kb
Host smart-89c9ea70-2f07-4125-891c-f71f057c1c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23642992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.23642992
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.3747296181
Short name T62
Test name
Test status
Simulation time 172013462 ps
CPU time 0.99 seconds
Started Jul 24 05:54:02 PM PDT 24
Finished Jul 24 05:54:03 PM PDT 24
Peak memory 235856 kb
Host smart-4b8f5a38-7882-46f9-a148-f8882533f93a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747296181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.3747296181
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.2825692786
Short name T36
Test name
Test status
Simulation time 14946833429 ps
CPU time 90.31 seconds
Started Jul 24 05:56:11 PM PDT 24
Finished Jul 24 05:57:41 PM PDT 24
Peak memory 270236 kb
Host smart-83a74b9e-df90-4b1f-bff5-f5d6527b8454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825692786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.2825692786
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.3586156198
Short name T78
Test name
Test status
Simulation time 242747752955 ps
CPU time 185.98 seconds
Started Jul 24 05:55:53 PM PDT 24
Finished Jul 24 05:58:59 PM PDT 24
Peak memory 265836 kb
Host smart-a8186f3c-7599-4bd2-bbdc-65bc26497b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586156198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.3586156198
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.2722170920
Short name T180
Test name
Test status
Simulation time 11258112718 ps
CPU time 65.04 seconds
Started Jul 24 05:56:39 PM PDT 24
Finished Jul 24 05:57:45 PM PDT 24
Peak memory 265736 kb
Host smart-81c9c347-619e-487c-a2b1-46918dfafdc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722170920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmd
s.2722170920
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.3913012800
Short name T113
Test name
Test status
Simulation time 36194481 ps
CPU time 2.38 seconds
Started Jul 24 05:52:29 PM PDT 24
Finished Jul 24 05:52:32 PM PDT 24
Peak memory 215568 kb
Host smart-f00ddb0c-5b89-4c47-a7ae-cf525fce17d6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913012800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.3
913012800
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.2304792801
Short name T44
Test name
Test status
Simulation time 166553317771 ps
CPU time 385.8 seconds
Started Jul 24 05:55:59 PM PDT 24
Finished Jul 24 06:02:25 PM PDT 24
Peak memory 268080 kb
Host smart-6086ca7f-1c72-4718-a5fe-8cea50c91cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304792801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.2304792801
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.1407890497
Short name T37
Test name
Test status
Simulation time 2075191303 ps
CPU time 53.54 seconds
Started Jul 24 05:55:24 PM PDT 24
Finished Jul 24 05:56:18 PM PDT 24
Peak memory 253992 kb
Host smart-e87d2414-d4b2-4cc7-aa8e-ba6ad066fcc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407890497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.1407890497
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.2903542207
Short name T407
Test name
Test status
Simulation time 101745874001 ps
CPU time 250.11 seconds
Started Jul 24 05:55:13 PM PDT 24
Finished Jul 24 05:59:23 PM PDT 24
Peak memory 255332 kb
Host smart-e6a81a20-b35d-4311-aa71-21a6141c6167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903542207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.2903542207
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.3889051657
Short name T39
Test name
Test status
Simulation time 62837794241 ps
CPU time 591.2 seconds
Started Jul 24 05:56:33 PM PDT 24
Finished Jul 24 06:06:25 PM PDT 24
Peak memory 254608 kb
Host smart-620218a9-8904-4b86-a864-488d14ccbc0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889051657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.3889051657
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.4001564456
Short name T150
Test name
Test status
Simulation time 46182220159 ps
CPU time 332.51 seconds
Started Jul 24 05:55:38 PM PDT 24
Finished Jul 24 06:01:11 PM PDT 24
Peak memory 265824 kb
Host smart-70090041-83b5-4a31-83cf-9c4f19595546
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001564456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.4001564456
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.3442010851
Short name T106
Test name
Test status
Simulation time 202026460 ps
CPU time 3.35 seconds
Started Jul 24 05:52:33 PM PDT 24
Finished Jul 24 05:52:37 PM PDT 24
Peak memory 215688 kb
Host smart-86707daf-1499-4fcb-b04f-0636168a643e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442010851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.3
442010851
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.1189990058
Short name T262
Test name
Test status
Simulation time 1841042657 ps
CPU time 35.94 seconds
Started Jul 24 05:55:09 PM PDT 24
Finished Jul 24 05:55:45 PM PDT 24
Peak memory 250516 kb
Host smart-9f8b7078-d29d-4263-b365-a1940ebac164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189990058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.1189990058
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.3506415579
Short name T196
Test name
Test status
Simulation time 5249281981 ps
CPU time 65.39 seconds
Started Jul 24 05:55:36 PM PDT 24
Finished Jul 24 05:56:41 PM PDT 24
Peak memory 249756 kb
Host smart-9fe88fa2-d6d7-4546-8af5-00cbfd7417cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506415579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmd
s.3506415579
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.1654317628
Short name T383
Test name
Test status
Simulation time 18904305 ps
CPU time 0.77 seconds
Started Jul 24 05:54:52 PM PDT 24
Finished Jul 24 05:54:52 PM PDT 24
Peak memory 205464 kb
Host smart-98e4555d-c68d-4394-8b28-65011d2056c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654317628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
1654317628
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.4095387612
Short name T173
Test name
Test status
Simulation time 197475805 ps
CPU time 12.69 seconds
Started Jul 24 05:52:40 PM PDT 24
Finished Jul 24 05:52:53 PM PDT 24
Peak memory 216032 kb
Host smart-8000b78b-020c-40dc-ae0a-453029244122
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095387612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.4095387612
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.3097690912
Short name T284
Test name
Test status
Simulation time 10745381959 ps
CPU time 47.55 seconds
Started Jul 24 05:54:50 PM PDT 24
Finished Jul 24 05:55:38 PM PDT 24
Peak memory 256000 kb
Host smart-90b4775a-24fc-4a27-af57-9c4c2556e660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097690912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.3097690912
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.4132749601
Short name T580
Test name
Test status
Simulation time 108339848024 ps
CPU time 252.62 seconds
Started Jul 24 05:54:38 PM PDT 24
Finished Jul 24 05:58:50 PM PDT 24
Peak memory 259704 kb
Host smart-da3fe69f-9e82-49f7-9739-490127ec29e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132749601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.4132749601
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.3159713828
Short name T182
Test name
Test status
Simulation time 3157299547 ps
CPU time 64.46 seconds
Started Jul 24 05:55:51 PM PDT 24
Finished Jul 24 05:56:56 PM PDT 24
Peak memory 251636 kb
Host smart-c1303c48-a5c9-43a5-a243-5d7c9a2e0f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159713828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmd
s.3159713828
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.4241437535
Short name T202
Test name
Test status
Simulation time 10412155237 ps
CPU time 139.91 seconds
Started Jul 24 05:54:23 PM PDT 24
Finished Jul 24 05:56:43 PM PDT 24
Peak memory 258156 kb
Host smart-d5fa60ee-4bb8-46fa-9d16-c7aaff6cf292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241437535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.4241437535
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.367074433
Short name T260
Test name
Test status
Simulation time 18540749563 ps
CPU time 195.94 seconds
Started Jul 24 05:53:58 PM PDT 24
Finished Jul 24 05:57:14 PM PDT 24
Peak memory 273356 kb
Host smart-6097d4c3-5b01-4dc5-8a68-8c5df4ed932c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367074433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stress
_all.367074433
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.3671418267
Short name T304
Test name
Test status
Simulation time 5095508307 ps
CPU time 47.43 seconds
Started Jul 24 05:53:56 PM PDT 24
Finished Jul 24 05:54:43 PM PDT 24
Peak memory 241224 kb
Host smart-bec61a72-b375-4371-a13f-d390b34110de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671418267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.3671418267
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.4061582372
Short name T133
Test name
Test status
Simulation time 370587299493 ps
CPU time 1019.57 seconds
Started Jul 24 05:55:41 PM PDT 24
Finished Jul 24 06:12:41 PM PDT 24
Peak memory 312272 kb
Host smart-baf643af-4180-4fa5-b6aa-6b04a1062944
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061582372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.4061582372
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.1555904217
Short name T268
Test name
Test status
Simulation time 36029828963 ps
CPU time 175.55 seconds
Started Jul 24 05:54:10 PM PDT 24
Finished Jul 24 05:57:06 PM PDT 24
Peak memory 265664 kb
Host smart-bcc8abb9-41f1-405d-ae1c-aaf28ae45cfe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555904217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.1555904217
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.767704237
Short name T145
Test name
Test status
Simulation time 997191003 ps
CPU time 23.92 seconds
Started Jul 24 05:52:39 PM PDT 24
Finished Jul 24 05:53:03 PM PDT 24
Peak memory 215440 kb
Host smart-b38df279-54b0-4fad-9686-2e7e65493a9d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767704237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device
_tl_intg_err.767704237
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.6181872
Short name T288
Test name
Test status
Simulation time 3153851313 ps
CPU time 53.11 seconds
Started Jul 24 05:53:56 PM PDT 24
Finished Jul 24 05:54:49 PM PDT 24
Peak memory 232920 kb
Host smart-ef47c80f-6be3-4fa3-ae66-5d312260e834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6181872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.6181872
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.4217403176
Short name T178
Test name
Test status
Simulation time 26629705226 ps
CPU time 122.97 seconds
Started Jul 24 05:54:10 PM PDT 24
Finished Jul 24 05:56:13 PM PDT 24
Peak memory 252648 kb
Host smart-5a691cc2-986b-4571-9d43-a1a025ceefae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217403176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds
.4217403176
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.174916999
Short name T879
Test name
Test status
Simulation time 3686751881 ps
CPU time 80.71 seconds
Started Jul 24 05:54:23 PM PDT 24
Finished Jul 24 05:55:44 PM PDT 24
Peak memory 264108 kb
Host smart-8d9346d6-40e5-4d39-9c6f-f9d2bcc7dbab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174916999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds.
174916999
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.2989981529
Short name T14
Test name
Test status
Simulation time 19227422619 ps
CPU time 12.49 seconds
Started Jul 24 05:54:15 PM PDT 24
Finished Jul 24 05:54:28 PM PDT 24
Peak memory 232976 kb
Host smart-c628d66c-27f2-4042-b6eb-211b78633a93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989981529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.2989981529
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3018817882
Short name T102
Test name
Test status
Simulation time 128594413 ps
CPU time 2.5 seconds
Started Jul 24 05:52:38 PM PDT 24
Finished Jul 24 05:52:41 PM PDT 24
Peak memory 218900 kb
Host smart-fbc2489a-9c3a-4286-bf2b-ba22fe459f7f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018817882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
3018817882
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.1041145337
Short name T170
Test name
Test status
Simulation time 814170601 ps
CPU time 6.7 seconds
Started Jul 24 05:52:45 PM PDT 24
Finished Jul 24 05:52:51 PM PDT 24
Peak memory 215832 kb
Host smart-88738c57-9e42-4da1-b522-75aa798b4b5b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041145337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.1041145337
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.3811469398
Short name T277
Test name
Test status
Simulation time 1722024166 ps
CPU time 26.11 seconds
Started Jul 24 05:54:38 PM PDT 24
Finished Jul 24 05:55:04 PM PDT 24
Peak memory 233944 kb
Host smart-f1313c6a-9407-4627-b8ba-1724efa76558
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811469398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.3811469398
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.2207897825
Short name T16
Test name
Test status
Simulation time 3831713501 ps
CPU time 69.77 seconds
Started Jul 24 05:54:36 PM PDT 24
Finished Jul 24 05:55:46 PM PDT 24
Peak memory 250672 kb
Host smart-71bda66a-88b9-4ebd-b287-f601091088ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207897825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmd
s.2207897825
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.2853315189
Short name T306
Test name
Test status
Simulation time 1161461394 ps
CPU time 6 seconds
Started Jul 24 05:54:37 PM PDT 24
Finished Jul 24 05:54:44 PM PDT 24
Peak memory 216440 kb
Host smart-fa0593fe-a9f6-491f-8bbc-9a6348f11aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853315189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.2853315189
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.3342304045
Short name T715
Test name
Test status
Simulation time 654156804 ps
CPU time 13.15 seconds
Started Jul 24 05:54:35 PM PDT 24
Finished Jul 24 05:54:48 PM PDT 24
Peak memory 239440 kb
Host smart-8c7411b8-efa8-4eed-924a-7175330f9a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342304045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.3342304045
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.274641308
Short name T81
Test name
Test status
Simulation time 63948140 ps
CPU time 0.93 seconds
Started Jul 24 05:52:31 PM PDT 24
Finished Jul 24 05:52:32 PM PDT 24
Peak memory 207012 kb
Host smart-d6918f89-1b24-4482-9150-9f0f95f64cb1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274641308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_hw_reset.274641308
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.1125334023
Short name T31
Test name
Test status
Simulation time 1821001983 ps
CPU time 31.26 seconds
Started Jul 24 05:53:56 PM PDT 24
Finished Jul 24 05:54:27 PM PDT 24
Peak memory 241104 kb
Host smart-fc9545bf-c0dc-43e3-a551-34d6ff070233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125334023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.1125334023
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.4161698805
Short name T1051
Test name
Test status
Simulation time 3787755092 ps
CPU time 8.13 seconds
Started Jul 24 05:52:36 PM PDT 24
Finished Jul 24 05:52:44 PM PDT 24
Peak memory 215548 kb
Host smart-943c88bd-1984-484e-bae3-d735e9a8b2af
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161698805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.4161698805
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1921218631
Short name T1022
Test name
Test status
Simulation time 183248930 ps
CPU time 12.31 seconds
Started Jul 24 05:52:30 PM PDT 24
Finished Jul 24 05:52:42 PM PDT 24
Peak memory 207356 kb
Host smart-1fb8e8aa-4e1a-44cc-875c-b15b970d1fd1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921218631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.1921218631
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1608009691
Short name T1070
Test name
Test status
Simulation time 521506420 ps
CPU time 3.71 seconds
Started Jul 24 05:52:32 PM PDT 24
Finished Jul 24 05:52:36 PM PDT 24
Peak memory 218456 kb
Host smart-e42417b9-1884-4657-bf77-0598318393c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608009691 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.1608009691
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.3445531076
Short name T1027
Test name
Test status
Simulation time 27830467 ps
CPU time 0.76 seconds
Started Jul 24 05:52:27 PM PDT 24
Finished Jul 24 05:52:28 PM PDT 24
Peak memory 203968 kb
Host smart-051bae2c-bfae-4f23-a04e-b8295fd9f3b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445531076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.3
445531076
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.2737670266
Short name T117
Test name
Test status
Simulation time 25944348 ps
CPU time 2.11 seconds
Started Jul 24 05:52:30 PM PDT 24
Finished Jul 24 05:52:32 PM PDT 24
Peak memory 215436 kb
Host smart-18de695d-dbbf-42ee-9495-390e0dca1272
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737670266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.2737670266
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.4009487134
Short name T1023
Test name
Test status
Simulation time 12189585 ps
CPU time 0.7 seconds
Started Jul 24 05:52:34 PM PDT 24
Finished Jul 24 05:52:35 PM PDT 24
Peak memory 203940 kb
Host smart-51104375-ab85-484b-9d01-cc45a16a5e77
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009487134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.4009487134
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.2439459915
Short name T144
Test name
Test status
Simulation time 602490571 ps
CPU time 1.92 seconds
Started Jul 24 05:52:31 PM PDT 24
Finished Jul 24 05:52:34 PM PDT 24
Peak memory 215448 kb
Host smart-7448f17c-4315-4c54-9f3c-271ed7925106
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439459915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.2439459915
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2511478493
Short name T1115
Test name
Test status
Simulation time 244819380 ps
CPU time 5.41 seconds
Started Jul 24 05:52:32 PM PDT 24
Finished Jul 24 05:52:38 PM PDT 24
Peak memory 215720 kb
Host smart-f16f1c9a-2cea-44ec-a9ee-927a60c29489
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511478493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.2
511478493
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.80034362
Short name T1107
Test name
Test status
Simulation time 864261384 ps
CPU time 13.09 seconds
Started Jul 24 05:52:30 PM PDT 24
Finished Jul 24 05:52:44 PM PDT 24
Peak memory 215544 kb
Host smart-52867484-bca3-4077-a198-94672afbf693
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80034362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_t
l_intg_err.80034362
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.4168094117
Short name T1126
Test name
Test status
Simulation time 2314517674 ps
CPU time 16.53 seconds
Started Jul 24 05:52:36 PM PDT 24
Finished Jul 24 05:52:53 PM PDT 24
Peak memory 215624 kb
Host smart-79fa7e36-5ab4-4a5b-a5d3-234f7a33bba4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168094117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.4168094117
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.1427693444
Short name T1042
Test name
Test status
Simulation time 7512785152 ps
CPU time 35.45 seconds
Started Jul 24 05:52:31 PM PDT 24
Finished Jul 24 05:53:07 PM PDT 24
Peak memory 207412 kb
Host smart-4e195115-f1f4-4054-9722-37453628fd3b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427693444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.1427693444
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.1986787557
Short name T83
Test name
Test status
Simulation time 52344983 ps
CPU time 1.01 seconds
Started Jul 24 05:52:29 PM PDT 24
Finished Jul 24 05:52:30 PM PDT 24
Peak memory 206936 kb
Host smart-d3e69723-223b-49f0-8755-d0b6485b29d7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986787557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.1986787557
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3083491935
Short name T59
Test name
Test status
Simulation time 185857901 ps
CPU time 1.79 seconds
Started Jul 24 05:52:30 PM PDT 24
Finished Jul 24 05:52:32 PM PDT 24
Peak memory 215592 kb
Host smart-de28ce00-4b4d-46ba-8b81-371421ecfbdc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083491935 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.3083491935
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.499430948
Short name T116
Test name
Test status
Simulation time 162019069 ps
CPU time 2.03 seconds
Started Jul 24 05:52:28 PM PDT 24
Finished Jul 24 05:52:30 PM PDT 24
Peak memory 215464 kb
Host smart-468c82c8-1bb9-413b-8d6e-569a7e8b735e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499430948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.499430948
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.1485831799
Short name T1011
Test name
Test status
Simulation time 62905381 ps
CPU time 0.79 seconds
Started Jul 24 05:52:36 PM PDT 24
Finished Jul 24 05:52:37 PM PDT 24
Peak memory 204312 kb
Host smart-73c072a9-e845-4b28-a2a2-67713fbff3a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485831799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.1
485831799
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.1156002386
Short name T1053
Test name
Test status
Simulation time 25507029 ps
CPU time 2.14 seconds
Started Jul 24 05:52:30 PM PDT 24
Finished Jul 24 05:52:33 PM PDT 24
Peak memory 215420 kb
Host smart-26773749-0416-4c61-8d10-c22b56dddac3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156002386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.1156002386
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.3969062721
Short name T1043
Test name
Test status
Simulation time 15845952 ps
CPU time 0.65 seconds
Started Jul 24 05:52:30 PM PDT 24
Finished Jul 24 05:52:31 PM PDT 24
Peak memory 204272 kb
Host smart-471ecfed-9899-480d-962b-068859bea987
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969062721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.3969062721
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1499884781
Short name T1024
Test name
Test status
Simulation time 238266545 ps
CPU time 3.98 seconds
Started Jul 24 05:52:36 PM PDT 24
Finished Jul 24 05:52:40 PM PDT 24
Peak memory 215480 kb
Host smart-19042de8-dd1c-46d1-a38b-4e215ea78701
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499884781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.1499884781
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.705234369
Short name T169
Test name
Test status
Simulation time 363379377 ps
CPU time 13.32 seconds
Started Jul 24 05:52:30 PM PDT 24
Finished Jul 24 05:52:43 PM PDT 24
Peak memory 215536 kb
Host smart-9ebe1254-d60d-4fbd-9b8a-1407b41a1c44
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705234369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_
tl_intg_err.705234369
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1856804456
Short name T1104
Test name
Test status
Simulation time 235602372 ps
CPU time 4.83 seconds
Started Jul 24 05:52:40 PM PDT 24
Finished Jul 24 05:52:45 PM PDT 24
Peak memory 218152 kb
Host smart-c5505a56-ea7e-4936-8dea-99eb70227d6b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856804456 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.1856804456
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3787959243
Short name T1103
Test name
Test status
Simulation time 168744995 ps
CPU time 2.74 seconds
Started Jul 24 05:52:44 PM PDT 24
Finished Jul 24 05:52:47 PM PDT 24
Peak memory 215532 kb
Host smart-eafee984-5339-4055-9c8c-09912a09b47f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787959243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
3787959243
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.1651744372
Short name T1061
Test name
Test status
Simulation time 80072204 ps
CPU time 0.74 seconds
Started Jul 24 05:52:38 PM PDT 24
Finished Jul 24 05:52:39 PM PDT 24
Peak memory 204000 kb
Host smart-0b6e61c6-6d2f-4dc6-b325-d9f5616b2f61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651744372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
1651744372
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2794215572
Short name T1072
Test name
Test status
Simulation time 30067242 ps
CPU time 1.77 seconds
Started Jul 24 05:52:39 PM PDT 24
Finished Jul 24 05:52:41 PM PDT 24
Peak memory 215528 kb
Host smart-1381cc28-a620-4121-b7ab-178879c9cba3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794215572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.2794215572
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3024244009
Short name T1116
Test name
Test status
Simulation time 2305899431 ps
CPU time 3.65 seconds
Started Jul 24 05:52:44 PM PDT 24
Finished Jul 24 05:52:48 PM PDT 24
Peak memory 217412 kb
Host smart-c6f6f363-383c-4b8a-8706-44617ab84949
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024244009 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.3024244009
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.2381936560
Short name T1119
Test name
Test status
Simulation time 153359520 ps
CPU time 2.67 seconds
Started Jul 24 05:52:44 PM PDT 24
Finished Jul 24 05:52:47 PM PDT 24
Peak memory 215428 kb
Host smart-b5cc522b-4af9-4459-a68d-556becf688a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381936560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
2381936560
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.2864079806
Short name T1029
Test name
Test status
Simulation time 44670832 ps
CPU time 0.74 seconds
Started Jul 24 05:52:44 PM PDT 24
Finished Jul 24 05:52:45 PM PDT 24
Peak memory 204272 kb
Host smart-6bd50cad-300b-490e-93a0-0d0e5c48be59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864079806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
2864079806
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.476912526
Short name T1092
Test name
Test status
Simulation time 967540152 ps
CPU time 4.54 seconds
Started Jul 24 05:52:40 PM PDT 24
Finished Jul 24 05:52:45 PM PDT 24
Peak memory 215536 kb
Host smart-639aae29-a063-4d43-b96b-8c274dc42132
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476912526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.s
pi_device_same_csr_outstanding.476912526
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3530584195
Short name T1046
Test name
Test status
Simulation time 23617398 ps
CPU time 1.55 seconds
Started Jul 24 05:52:43 PM PDT 24
Finished Jul 24 05:52:45 PM PDT 24
Peak memory 215556 kb
Host smart-fb3e0572-2ae3-44bb-bfb3-b28a4fb35808
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530584195 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.3530584195
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2011975792
Short name T121
Test name
Test status
Simulation time 104118534 ps
CPU time 2.53 seconds
Started Jul 24 05:52:44 PM PDT 24
Finished Jul 24 05:52:47 PM PDT 24
Peak memory 215544 kb
Host smart-ede7373f-52f6-46cf-bccb-e135e49d2275
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011975792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
2011975792
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.1901877054
Short name T1069
Test name
Test status
Simulation time 14280137 ps
CPU time 0.74 seconds
Started Jul 24 05:52:45 PM PDT 24
Finished Jul 24 05:52:46 PM PDT 24
Peak memory 204280 kb
Host smart-10ce128c-eb5d-4f00-8a2e-08cbe4de8414
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901877054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
1901877054
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1523183087
Short name T1117
Test name
Test status
Simulation time 108522376 ps
CPU time 1.89 seconds
Started Jul 24 05:52:49 PM PDT 24
Finished Jul 24 05:52:51 PM PDT 24
Peak memory 215492 kb
Host smart-21668216-3902-4ac4-a20a-10551b252547
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523183087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.1523183087
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.2788351403
Short name T162
Test name
Test status
Simulation time 147751763 ps
CPU time 3.77 seconds
Started Jul 24 05:52:44 PM PDT 24
Finished Jul 24 05:52:48 PM PDT 24
Peak memory 215628 kb
Host smart-a9e98597-e6d4-4baa-b0d1-57cebe3f60a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788351403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
2788351403
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.1856833376
Short name T1102
Test name
Test status
Simulation time 4915272761 ps
CPU time 20.45 seconds
Started Jul 24 05:52:49 PM PDT 24
Finished Jul 24 05:53:10 PM PDT 24
Peak memory 215664 kb
Host smart-47473e30-b218-4945-a12d-a29c133e7195
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856833376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.1856833376
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2626007178
Short name T1038
Test name
Test status
Simulation time 128713324 ps
CPU time 3.62 seconds
Started Jul 24 05:52:49 PM PDT 24
Finished Jul 24 05:52:52 PM PDT 24
Peak memory 217836 kb
Host smart-bcd9903b-d286-4cb0-90f5-91b9ff303e97
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626007178 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.2626007178
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.637285516
Short name T1080
Test name
Test status
Simulation time 100835980 ps
CPU time 1.79 seconds
Started Jul 24 05:52:47 PM PDT 24
Finished Jul 24 05:52:49 PM PDT 24
Peak memory 215452 kb
Host smart-2ad7c6b6-fa31-458c-aceb-72711cf1eec2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637285516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.637285516
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.151814263
Short name T1014
Test name
Test status
Simulation time 34567709 ps
CPU time 0.75 seconds
Started Jul 24 05:52:49 PM PDT 24
Finished Jul 24 05:52:50 PM PDT 24
Peak memory 204000 kb
Host smart-379be8e5-bad7-46e2-98c1-d4ca36fb0df2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151814263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.151814263
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1065883982
Short name T147
Test name
Test status
Simulation time 127130561 ps
CPU time 1.74 seconds
Started Jul 24 05:52:49 PM PDT 24
Finished Jul 24 05:52:51 PM PDT 24
Peak memory 215444 kb
Host smart-a5718032-4492-4d85-b3b6-4a3b3f5605d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065883982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.1065883982
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.4284616653
Short name T104
Test name
Test status
Simulation time 55070696 ps
CPU time 3.5 seconds
Started Jul 24 05:52:46 PM PDT 24
Finished Jul 24 05:52:49 PM PDT 24
Peak memory 215624 kb
Host smart-d93df4a7-a5a7-428f-ad9a-2e6ddade1890
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284616653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
4284616653
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3737985566
Short name T98
Test name
Test status
Simulation time 1218949748 ps
CPU time 18.66 seconds
Started Jul 24 05:52:49 PM PDT 24
Finished Jul 24 05:53:07 PM PDT 24
Peak memory 215512 kb
Host smart-2097068e-535e-438f-ab0c-da7a696209a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737985566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.3737985566
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3501668545
Short name T1064
Test name
Test status
Simulation time 341832166 ps
CPU time 4.12 seconds
Started Jul 24 05:52:52 PM PDT 24
Finished Jul 24 05:52:56 PM PDT 24
Peak memory 217192 kb
Host smart-38039ea4-98cd-40d0-ab49-9aed590d7595
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501668545 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.3501668545
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.2815455012
Short name T136
Test name
Test status
Simulation time 39740879 ps
CPU time 2.44 seconds
Started Jul 24 05:52:49 PM PDT 24
Finished Jul 24 05:52:51 PM PDT 24
Peak memory 215444 kb
Host smart-eaef003a-4c68-4281-945a-b68707822461
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815455012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
2815455012
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.3118232508
Short name T1018
Test name
Test status
Simulation time 13803903 ps
CPU time 0.76 seconds
Started Jul 24 05:52:45 PM PDT 24
Finished Jul 24 05:52:46 PM PDT 24
Peak memory 204036 kb
Host smart-b8357bc0-086b-4d8d-8b8e-57b767e69ea6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118232508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
3118232508
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2535900640
Short name T1093
Test name
Test status
Simulation time 118490819 ps
CPU time 4.09 seconds
Started Jul 24 05:52:51 PM PDT 24
Finished Jul 24 05:52:55 PM PDT 24
Peak memory 215556 kb
Host smart-e03d939d-81d0-434f-a7f2-7667d7db6b20
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535900640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.2535900640
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.4030181335
Short name T1075
Test name
Test status
Simulation time 347687896 ps
CPU time 2.27 seconds
Started Jul 24 05:52:44 PM PDT 24
Finished Jul 24 05:52:47 PM PDT 24
Peak memory 215632 kb
Host smart-e046fa09-03d6-4629-812e-848ada1f3fa1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030181335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
4030181335
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3990127401
Short name T108
Test name
Test status
Simulation time 147814881 ps
CPU time 1.82 seconds
Started Jul 24 05:52:53 PM PDT 24
Finished Jul 24 05:52:55 PM PDT 24
Peak memory 216564 kb
Host smart-6fb0969a-1aef-41d2-910f-82e99eac0be9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990127401 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.3990127401
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.300137731
Short name T1049
Test name
Test status
Simulation time 56863842 ps
CPU time 1.95 seconds
Started Jul 24 05:52:53 PM PDT 24
Finished Jul 24 05:52:55 PM PDT 24
Peak memory 215500 kb
Host smart-ecfd282f-deba-4736-8d86-a8fe51cdf130
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300137731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.300137731
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.3780389519
Short name T1066
Test name
Test status
Simulation time 43035104 ps
CPU time 0.69 seconds
Started Jul 24 05:52:50 PM PDT 24
Finished Jul 24 05:52:51 PM PDT 24
Peak memory 204028 kb
Host smart-b9357d1a-6474-4c00-9da5-6115a5fd0eaf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780389519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
3780389519
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.762104081
Short name T1063
Test name
Test status
Simulation time 276858135 ps
CPU time 1.84 seconds
Started Jul 24 05:52:51 PM PDT 24
Finished Jul 24 05:52:53 PM PDT 24
Peak memory 207264 kb
Host smart-99fc6461-ca17-44b8-b56c-31967e62a477
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762104081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.s
pi_device_same_csr_outstanding.762104081
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.3301512294
Short name T1067
Test name
Test status
Simulation time 50554530 ps
CPU time 3.03 seconds
Started Jul 24 05:52:51 PM PDT 24
Finished Jul 24 05:52:54 PM PDT 24
Peak memory 215592 kb
Host smart-939f9583-7976-47ed-a414-d68b78b8a94e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301512294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
3301512294
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.3389616902
Short name T174
Test name
Test status
Simulation time 1904303236 ps
CPU time 18.5 seconds
Started Jul 24 05:52:51 PM PDT 24
Finished Jul 24 05:53:10 PM PDT 24
Peak memory 216376 kb
Host smart-cadbce71-22f8-435c-baf4-6d0edff7e3af
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389616902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.3389616902
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.2899699427
Short name T1073
Test name
Test status
Simulation time 87159722 ps
CPU time 2.98 seconds
Started Jul 24 05:52:52 PM PDT 24
Finished Jul 24 05:52:56 PM PDT 24
Peak memory 217252 kb
Host smart-e5a1f2c6-f2d8-4f92-b432-aeada146e9a4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899699427 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.2899699427
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2248151116
Short name T112
Test name
Test status
Simulation time 262583364 ps
CPU time 2.13 seconds
Started Jul 24 05:52:54 PM PDT 24
Finished Jul 24 05:52:56 PM PDT 24
Peak memory 215432 kb
Host smart-b66d048c-45bf-4335-ab43-f3fe91357fd4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248151116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
2248151116
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.205328285
Short name T1059
Test name
Test status
Simulation time 58975664 ps
CPU time 0.75 seconds
Started Jul 24 05:52:48 PM PDT 24
Finished Jul 24 05:52:49 PM PDT 24
Peak memory 203992 kb
Host smart-98a70205-ebd1-4992-98ca-b08f1ee7217d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205328285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.205328285
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3707537425
Short name T1100
Test name
Test status
Simulation time 25951815 ps
CPU time 1.81 seconds
Started Jul 24 05:52:50 PM PDT 24
Finished Jul 24 05:52:52 PM PDT 24
Peak memory 216024 kb
Host smart-eaff0acb-b488-41b1-bc80-0a6995c83cb6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707537425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.3707537425
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.1041298354
Short name T95
Test name
Test status
Simulation time 82717880 ps
CPU time 2.22 seconds
Started Jul 24 05:52:51 PM PDT 24
Finished Jul 24 05:52:54 PM PDT 24
Peak memory 215680 kb
Host smart-6250c6d8-66b8-43bc-ac5d-d5955fdf8316
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041298354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
1041298354
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.4268359920
Short name T175
Test name
Test status
Simulation time 227979394 ps
CPU time 11.54 seconds
Started Jul 24 05:52:49 PM PDT 24
Finished Jul 24 05:53:01 PM PDT 24
Peak memory 215440 kb
Host smart-d8e7f268-981a-4917-bbdf-720ed067489d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268359920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.4268359920
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.4034756624
Short name T1084
Test name
Test status
Simulation time 108260807 ps
CPU time 4.02 seconds
Started Jul 24 05:52:52 PM PDT 24
Finished Jul 24 05:52:56 PM PDT 24
Peak memory 217216 kb
Host smart-c2ee3480-0ccf-484f-b27a-cab17ca04b92
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034756624 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.4034756624
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.966870225
Short name T120
Test name
Test status
Simulation time 355158720 ps
CPU time 2.52 seconds
Started Jul 24 05:52:52 PM PDT 24
Finished Jul 24 05:52:55 PM PDT 24
Peak memory 215552 kb
Host smart-8d489873-f4b2-4cfb-9874-d2d8df48c012
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966870225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.966870225
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.802118716
Short name T1081
Test name
Test status
Simulation time 20714808 ps
CPU time 0.71 seconds
Started Jul 24 05:52:51 PM PDT 24
Finished Jul 24 05:52:52 PM PDT 24
Peak memory 203996 kb
Host smart-e6e54102-c65b-4cf8-8a5a-e198a10a366f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802118716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.802118716
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.4189894049
Short name T1050
Test name
Test status
Simulation time 150726031 ps
CPU time 3.77 seconds
Started Jul 24 05:52:50 PM PDT 24
Finished Jul 24 05:52:54 PM PDT 24
Peak memory 215576 kb
Host smart-0d2e626b-692e-47b7-af42-ba1456d8803f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189894049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.4189894049
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.412468041
Short name T1091
Test name
Test status
Simulation time 29486747 ps
CPU time 2.02 seconds
Started Jul 24 05:52:50 PM PDT 24
Finished Jul 24 05:52:52 PM PDT 24
Peak memory 215576 kb
Host smart-28367af0-87ab-4737-a0be-a3b2d54e73a1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412468041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.412468041
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3881744026
Short name T1095
Test name
Test status
Simulation time 2145576375 ps
CPU time 15.23 seconds
Started Jul 24 05:52:51 PM PDT 24
Finished Jul 24 05:53:07 PM PDT 24
Peak memory 215612 kb
Host smart-49247ae1-7242-459f-be3e-d50089d2f611
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881744026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.3881744026
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.1107687838
Short name T1120
Test name
Test status
Simulation time 107324580 ps
CPU time 2.92 seconds
Started Jul 24 05:52:54 PM PDT 24
Finished Jul 24 05:52:57 PM PDT 24
Peak memory 216896 kb
Host smart-dab7da24-d663-4771-aa2c-0f665a61ef97
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107687838 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.1107687838
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3900638497
Short name T1057
Test name
Test status
Simulation time 135604240 ps
CPU time 2.12 seconds
Started Jul 24 05:52:55 PM PDT 24
Finished Jul 24 05:52:57 PM PDT 24
Peak memory 215508 kb
Host smart-b82ca42d-ce48-4cd2-918c-9b251d1dc32f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900638497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
3900638497
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1129328583
Short name T1118
Test name
Test status
Simulation time 28725421 ps
CPU time 0.69 seconds
Started Jul 24 05:52:51 PM PDT 24
Finished Jul 24 05:52:52 PM PDT 24
Peak memory 204012 kb
Host smart-ff7e0097-46e0-44e9-a2e7-17c63f791dc4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129328583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
1129328583
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2028099648
Short name T137
Test name
Test status
Simulation time 124179744 ps
CPU time 3.83 seconds
Started Jul 24 05:52:50 PM PDT 24
Finished Jul 24 05:52:54 PM PDT 24
Peak memory 215536 kb
Host smart-ad93c2bb-bcb5-4351-96cb-f75001fedc63
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028099648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.2028099648
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.3557120945
Short name T167
Test name
Test status
Simulation time 243278637 ps
CPU time 3.27 seconds
Started Jul 24 05:52:52 PM PDT 24
Finished Jul 24 05:52:56 PM PDT 24
Peak memory 215560 kb
Host smart-fd10f174-71dd-45a9-9df2-d2dbc7f5eb05
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557120945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
3557120945
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.1543403421
Short name T107
Test name
Test status
Simulation time 141616260 ps
CPU time 3.76 seconds
Started Jul 24 05:52:55 PM PDT 24
Finished Jul 24 05:52:59 PM PDT 24
Peak memory 218320 kb
Host smart-3fff23dc-56eb-47ab-b683-61a65540a775
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543403421 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.1543403421
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.2646415022
Short name T1098
Test name
Test status
Simulation time 184702555 ps
CPU time 1.36 seconds
Started Jul 24 05:52:59 PM PDT 24
Finished Jul 24 05:53:01 PM PDT 24
Peak memory 219428 kb
Host smart-369c45fd-43d1-4d89-ac22-89253652fa4f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646415022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
2646415022
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1056293374
Short name T1032
Test name
Test status
Simulation time 18236019 ps
CPU time 0.71 seconds
Started Jul 24 05:52:53 PM PDT 24
Finished Jul 24 05:52:54 PM PDT 24
Peak memory 203988 kb
Host smart-e5e7ccd2-8e04-405e-be27-dae48b8f969f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056293374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
1056293374
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.719158587
Short name T1031
Test name
Test status
Simulation time 86060660 ps
CPU time 2.75 seconds
Started Jul 24 05:52:59 PM PDT 24
Finished Jul 24 05:53:01 PM PDT 24
Peak memory 215556 kb
Host smart-6727e73b-4773-42dd-b7a8-dde59a63277a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719158587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.s
pi_device_same_csr_outstanding.719158587
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.3922451748
Short name T105
Test name
Test status
Simulation time 367567322 ps
CPU time 3.31 seconds
Started Jul 24 05:52:55 PM PDT 24
Finished Jul 24 05:52:59 PM PDT 24
Peak memory 215600 kb
Host smart-b02e3c2c-1e2b-4aa1-8ee5-50302125c791
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922451748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
3922451748
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.3811040256
Short name T177
Test name
Test status
Simulation time 1985552496 ps
CPU time 7.55 seconds
Started Jul 24 05:52:51 PM PDT 24
Finished Jul 24 05:52:59 PM PDT 24
Peak memory 215512 kb
Host smart-c528b5f5-858c-4c33-aa2a-6998677cebf1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811040256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.3811040256
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.121992355
Short name T122
Test name
Test status
Simulation time 467762651 ps
CPU time 8.36 seconds
Started Jul 24 05:52:34 PM PDT 24
Finished Jul 24 05:52:42 PM PDT 24
Peak memory 207248 kb
Host smart-219d4628-345c-4712-a812-73662e418a4a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121992355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_aliasing.121992355
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.4256943785
Short name T1036
Test name
Test status
Simulation time 3090357606 ps
CPU time 25.79 seconds
Started Jul 24 05:52:34 PM PDT 24
Finished Jul 24 05:53:00 PM PDT 24
Peak memory 215568 kb
Host smart-8fb3b5a4-2f89-4937-84f7-aaa8071a25ce
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256943785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.4256943785
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.958937638
Short name T82
Test name
Test status
Simulation time 296804005 ps
CPU time 1.36 seconds
Started Jul 24 05:52:32 PM PDT 24
Finished Jul 24 05:52:34 PM PDT 24
Peak memory 216448 kb
Host smart-c71180a2-9dc7-485f-a631-333dbba94db7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958937638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_hw_reset.958937638
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1973108967
Short name T1052
Test name
Test status
Simulation time 139427393 ps
CPU time 2.77 seconds
Started Jul 24 05:52:30 PM PDT 24
Finished Jul 24 05:52:33 PM PDT 24
Peak memory 216940 kb
Host smart-fb77648f-3f43-4661-ab85-a0f04625d120
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973108967 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.1973108967
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2876435726
Short name T124
Test name
Test status
Simulation time 397361121 ps
CPU time 3 seconds
Started Jul 24 05:52:33 PM PDT 24
Finished Jul 24 05:52:36 PM PDT 24
Peak memory 207164 kb
Host smart-a1c455b6-a7ff-48f4-9d8e-d0d06d2c4d47
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876435726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.2
876435726
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.808852585
Short name T1109
Test name
Test status
Simulation time 27683579 ps
CPU time 0.72 seconds
Started Jul 24 05:52:28 PM PDT 24
Finished Jul 24 05:52:29 PM PDT 24
Peak memory 203952 kb
Host smart-7cb9cbc8-ae87-4a34-b5cc-eb8e46b933d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808852585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.808852585
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.3200649714
Short name T114
Test name
Test status
Simulation time 50662085 ps
CPU time 2.21 seconds
Started Jul 24 05:52:30 PM PDT 24
Finished Jul 24 05:52:32 PM PDT 24
Peak memory 215468 kb
Host smart-2ea0e8d7-1c15-4ddd-bb6c-aa88ac2b179a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200649714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.3200649714
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.4125872007
Short name T1130
Test name
Test status
Simulation time 18926931 ps
CPU time 0.67 seconds
Started Jul 24 05:52:33 PM PDT 24
Finished Jul 24 05:52:34 PM PDT 24
Peak memory 204224 kb
Host smart-d8781add-61b4-491a-9ad3-154189af724c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125872007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.4125872007
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.399726091
Short name T1129
Test name
Test status
Simulation time 191295357 ps
CPU time 3.34 seconds
Started Jul 24 05:52:34 PM PDT 24
Finished Jul 24 05:52:38 PM PDT 24
Peak memory 215484 kb
Host smart-ffe7059c-f8ac-41f0-b0a4-8c3588c3701d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399726091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sp
i_device_same_csr_outstanding.399726091
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1936862212
Short name T1087
Test name
Test status
Simulation time 40082048 ps
CPU time 2.83 seconds
Started Jul 24 05:52:34 PM PDT 24
Finished Jul 24 05:52:37 PM PDT 24
Peak memory 215676 kb
Host smart-f873a9eb-a934-4586-bf66-eca773f4da73
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936862212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.1
936862212
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.531819073
Short name T146
Test name
Test status
Simulation time 1249428322 ps
CPU time 7.26 seconds
Started Jul 24 05:52:33 PM PDT 24
Finished Jul 24 05:52:40 PM PDT 24
Peak memory 215660 kb
Host smart-3ed67266-7bcb-438c-94d3-a9612cd47525
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531819073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_
tl_intg_err.531819073
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.1321225426
Short name T1026
Test name
Test status
Simulation time 16438997 ps
CPU time 0.74 seconds
Started Jul 24 05:53:02 PM PDT 24
Finished Jul 24 05:53:03 PM PDT 24
Peak memory 204004 kb
Host smart-1784952f-7dcf-4f13-beb6-219ce1236292
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321225426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
1321225426
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.376769240
Short name T1082
Test name
Test status
Simulation time 18972330 ps
CPU time 0.77 seconds
Started Jul 24 05:53:00 PM PDT 24
Finished Jul 24 05:53:01 PM PDT 24
Peak memory 203788 kb
Host smart-7a686b4b-82de-4e61-9076-746830817e9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376769240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.376769240
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.2968753364
Short name T1013
Test name
Test status
Simulation time 16597230 ps
CPU time 0.74 seconds
Started Jul 24 05:52:56 PM PDT 24
Finished Jul 24 05:52:56 PM PDT 24
Peak memory 204312 kb
Host smart-92e34406-7742-438f-a2b2-0d4556c7dc1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968753364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
2968753364
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2030135481
Short name T1019
Test name
Test status
Simulation time 72936214 ps
CPU time 0.71 seconds
Started Jul 24 05:52:56 PM PDT 24
Finished Jul 24 05:52:57 PM PDT 24
Peak memory 203952 kb
Host smart-ebc1f928-038b-4df3-afad-bb23d44b7fc2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030135481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
2030135481
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1116483596
Short name T1040
Test name
Test status
Simulation time 85465095 ps
CPU time 0.7 seconds
Started Jul 24 05:52:57 PM PDT 24
Finished Jul 24 05:52:57 PM PDT 24
Peak memory 203984 kb
Host smart-5a6d3363-bbc0-44f9-870b-dc6b1320407b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116483596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
1116483596
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.3050360915
Short name T1041
Test name
Test status
Simulation time 171683607 ps
CPU time 0.77 seconds
Started Jul 24 05:52:56 PM PDT 24
Finished Jul 24 05:52:57 PM PDT 24
Peak memory 204272 kb
Host smart-5dfe5316-9a6d-48a3-b9c6-7ee2d575a167
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050360915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
3050360915
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2822519728
Short name T1121
Test name
Test status
Simulation time 20838029 ps
CPU time 0.72 seconds
Started Jul 24 05:52:56 PM PDT 24
Finished Jul 24 05:52:57 PM PDT 24
Peak memory 204276 kb
Host smart-3f5c6bc1-d3a7-4acd-8578-b48d8a9bd936
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822519728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
2822519728
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.1690189625
Short name T1083
Test name
Test status
Simulation time 64272979 ps
CPU time 0.78 seconds
Started Jul 24 05:52:56 PM PDT 24
Finished Jul 24 05:52:57 PM PDT 24
Peak memory 204276 kb
Host smart-26430aff-9d2e-4ae4-bf0c-783cc23d6512
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690189625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
1690189625
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.1402332202
Short name T1086
Test name
Test status
Simulation time 46505686 ps
CPU time 0.77 seconds
Started Jul 24 05:53:02 PM PDT 24
Finished Jul 24 05:53:03 PM PDT 24
Peak memory 204012 kb
Host smart-91849a58-ff76-4ba2-991a-ff5b6c783348
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402332202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
1402332202
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.3951968294
Short name T1090
Test name
Test status
Simulation time 12556913 ps
CPU time 0.73 seconds
Started Jul 24 05:53:02 PM PDT 24
Finished Jul 24 05:53:03 PM PDT 24
Peak memory 204004 kb
Host smart-9f04411f-8d96-4818-9d35-3f5173cbabc1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951968294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
3951968294
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.1778859468
Short name T115
Test name
Test status
Simulation time 957920720 ps
CPU time 25.25 seconds
Started Jul 24 05:52:33 PM PDT 24
Finished Jul 24 05:52:58 PM PDT 24
Peak memory 215560 kb
Host smart-959fc08b-c5f2-4664-a890-8340b9c10145
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778859468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.1778859468
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1623927789
Short name T1047
Test name
Test status
Simulation time 1869818433 ps
CPU time 36.91 seconds
Started Jul 24 05:52:32 PM PDT 24
Finished Jul 24 05:53:09 PM PDT 24
Peak memory 207276 kb
Host smart-cbafec51-9bdd-4d17-a1b4-d39bcec14e23
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623927789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.1623927789
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3439867930
Short name T84
Test name
Test status
Simulation time 22416029 ps
CPU time 1.4 seconds
Started Jul 24 05:52:34 PM PDT 24
Finished Jul 24 05:52:36 PM PDT 24
Peak memory 207368 kb
Host smart-ce61d256-79fc-4aa7-9e81-047ec79a45a1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439867930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.3439867930
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.3926418578
Short name T1078
Test name
Test status
Simulation time 238432444 ps
CPU time 3.74 seconds
Started Jul 24 05:52:32 PM PDT 24
Finished Jul 24 05:52:36 PM PDT 24
Peak memory 218188 kb
Host smart-bbf68dcd-d5b5-47f2-ac66-b60ef450941e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926418578 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.3926418578
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.2724971025
Short name T1068
Test name
Test status
Simulation time 75668411 ps
CPU time 2.05 seconds
Started Jul 24 05:52:36 PM PDT 24
Finished Jul 24 05:52:38 PM PDT 24
Peak memory 215516 kb
Host smart-e3c97d98-1a2c-4c42-b6e2-b51bbf6dc4e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724971025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.2
724971025
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.3612611478
Short name T1128
Test name
Test status
Simulation time 11977573 ps
CPU time 0.7 seconds
Started Jul 24 05:52:34 PM PDT 24
Finished Jul 24 05:52:35 PM PDT 24
Peak memory 203988 kb
Host smart-4a19c8b2-17c2-4e43-9590-8210a5350d43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612611478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.3
612611478
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2672797849
Short name T1131
Test name
Test status
Simulation time 65441530 ps
CPU time 1.26 seconds
Started Jul 24 05:52:34 PM PDT 24
Finished Jul 24 05:52:36 PM PDT 24
Peak memory 215384 kb
Host smart-e4126f45-449e-4466-a56e-84633603fba8
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672797849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.2672797849
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.408748019
Short name T1058
Test name
Test status
Simulation time 13802220 ps
CPU time 0.67 seconds
Started Jul 24 05:52:35 PM PDT 24
Finished Jul 24 05:52:36 PM PDT 24
Peak memory 203872 kb
Host smart-f09d8073-6869-41b7-bdba-830f050fe128
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408748019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem
_walk.408748019
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.299942265
Short name T1077
Test name
Test status
Simulation time 1092111144 ps
CPU time 2.95 seconds
Started Jul 24 05:52:35 PM PDT 24
Finished Jul 24 05:52:38 PM PDT 24
Peak memory 215540 kb
Host smart-2975cded-10b0-402e-b692-234b3710fa86
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299942265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sp
i_device_same_csr_outstanding.299942265
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.1915866975
Short name T103
Test name
Test status
Simulation time 68499268 ps
CPU time 1.88 seconds
Started Jul 24 05:52:30 PM PDT 24
Finished Jul 24 05:52:32 PM PDT 24
Peak memory 215564 kb
Host smart-379d3a3b-95ff-437a-8090-150bd600acd6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915866975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.1
915866975
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1048041141
Short name T1089
Test name
Test status
Simulation time 2882869477 ps
CPU time 17.04 seconds
Started Jul 24 05:52:33 PM PDT 24
Finished Jul 24 05:52:51 PM PDT 24
Peak memory 215672 kb
Host smart-b7d8915f-a991-49fd-a14e-ede3e05d54e5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048041141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.1048041141
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2447306099
Short name T1113
Test name
Test status
Simulation time 89030903 ps
CPU time 0.75 seconds
Started Jul 24 05:52:56 PM PDT 24
Finished Jul 24 05:52:57 PM PDT 24
Peak memory 204040 kb
Host smart-f6f4d59a-fe2c-473d-b4e1-ec3835ff95bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447306099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
2447306099
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.625889236
Short name T1028
Test name
Test status
Simulation time 76588683 ps
CPU time 0.71 seconds
Started Jul 24 05:52:59 PM PDT 24
Finished Jul 24 05:52:59 PM PDT 24
Peak memory 204308 kb
Host smart-a0d3a3b2-a24e-45c7-b55c-018116d40d9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625889236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.625889236
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.1716430639
Short name T1015
Test name
Test status
Simulation time 53560831 ps
CPU time 0.8 seconds
Started Jul 24 05:53:00 PM PDT 24
Finished Jul 24 05:53:01 PM PDT 24
Peak memory 203944 kb
Host smart-1c9db5c8-33b5-4996-9f61-0155aca8d4a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716430639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
1716430639
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.1158811480
Short name T1030
Test name
Test status
Simulation time 52888095 ps
CPU time 0.77 seconds
Started Jul 24 05:52:59 PM PDT 24
Finished Jul 24 05:53:00 PM PDT 24
Peak memory 203972 kb
Host smart-0dfa0233-534d-466f-a8e8-4d3ef64f8254
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158811480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
1158811480
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.4225069413
Short name T1037
Test name
Test status
Simulation time 13965455 ps
CPU time 0.72 seconds
Started Jul 24 05:52:57 PM PDT 24
Finished Jul 24 05:52:58 PM PDT 24
Peak memory 204008 kb
Host smart-575c8b65-3df8-49f3-953d-b43902c1b79c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225069413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
4225069413
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.1846123505
Short name T1056
Test name
Test status
Simulation time 11196940 ps
CPU time 0.79 seconds
Started Jul 24 05:52:54 PM PDT 24
Finished Jul 24 05:52:55 PM PDT 24
Peak memory 204012 kb
Host smart-7d87dc79-1bd5-4822-b8f1-dd0786e6acd5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846123505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
1846123505
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.1722440279
Short name T1111
Test name
Test status
Simulation time 15895865 ps
CPU time 0.78 seconds
Started Jul 24 05:53:01 PM PDT 24
Finished Jul 24 05:53:02 PM PDT 24
Peak memory 204208 kb
Host smart-53e7fb1f-0890-462d-bae5-f3ab7642afd1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722440279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
1722440279
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.1428367677
Short name T1099
Test name
Test status
Simulation time 29571399 ps
CPU time 0.8 seconds
Started Jul 24 05:53:00 PM PDT 24
Finished Jul 24 05:53:01 PM PDT 24
Peak memory 203864 kb
Host smart-7764e7d0-6fe0-48bc-8f48-ee69ffcb092d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428367677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
1428367677
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.4197440394
Short name T1012
Test name
Test status
Simulation time 16541138 ps
CPU time 0.8 seconds
Started Jul 24 05:53:03 PM PDT 24
Finished Jul 24 05:53:04 PM PDT 24
Peak memory 204320 kb
Host smart-0ab5f8fb-f85b-492b-bd69-0b04514fa136
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197440394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
4197440394
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.2078195028
Short name T1048
Test name
Test status
Simulation time 42326703 ps
CPU time 0.69 seconds
Started Jul 24 05:52:59 PM PDT 24
Finished Jul 24 05:53:00 PM PDT 24
Peak memory 204220 kb
Host smart-5dc04ac7-d686-406a-965a-44bc8e9f48d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078195028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
2078195028
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.4041024241
Short name T1108
Test name
Test status
Simulation time 716578935 ps
CPU time 15.19 seconds
Started Jul 24 05:52:34 PM PDT 24
Finished Jul 24 05:52:50 PM PDT 24
Peak memory 207240 kb
Host smart-017961b8-e4d7-4048-8c35-2272f2c46878
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041024241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.4041024241
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.86202427
Short name T1124
Test name
Test status
Simulation time 1818583853 ps
CPU time 40.91 seconds
Started Jul 24 05:52:36 PM PDT 24
Finished Jul 24 05:53:17 PM PDT 24
Peak memory 207212 kb
Host smart-c1875248-39ee-47c2-b1e7-86478c06a71d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86202427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_
bit_bash.86202427
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3063612092
Short name T1094
Test name
Test status
Simulation time 517354576 ps
CPU time 1.21 seconds
Started Jul 24 05:52:33 PM PDT 24
Finished Jul 24 05:52:34 PM PDT 24
Peak memory 215492 kb
Host smart-d86b76ad-4591-4c5e-ab98-ac07dea5ba29
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063612092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.3063612092
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1288546638
Short name T1097
Test name
Test status
Simulation time 70221432 ps
CPU time 2.4 seconds
Started Jul 24 05:52:32 PM PDT 24
Finished Jul 24 05:52:34 PM PDT 24
Peak memory 217940 kb
Host smart-6671db4e-be24-469a-a25f-1b6e78f8cc4f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288546638 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.1288546638
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.3443554292
Short name T1076
Test name
Test status
Simulation time 109993679 ps
CPU time 1.88 seconds
Started Jul 24 05:52:37 PM PDT 24
Finished Jul 24 05:52:39 PM PDT 24
Peak memory 207224 kb
Host smart-ac142fac-30b5-4a00-a55b-29bd9511d51e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443554292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.3
443554292
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3844495913
Short name T1054
Test name
Test status
Simulation time 39746105 ps
CPU time 0.81 seconds
Started Jul 24 05:52:36 PM PDT 24
Finished Jul 24 05:52:37 PM PDT 24
Peak memory 203888 kb
Host smart-f4cbb849-9a7d-426e-8ac7-8146a98b58d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844495913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.3
844495913
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.217812858
Short name T118
Test name
Test status
Simulation time 27361305 ps
CPU time 2.46 seconds
Started Jul 24 05:52:33 PM PDT 24
Finished Jul 24 05:52:36 PM PDT 24
Peak memory 215468 kb
Host smart-637a0712-f080-4229-99d8-31b87c772fd4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217812858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_
device_mem_partial_access.217812858
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1577786313
Short name T1125
Test name
Test status
Simulation time 36239226 ps
CPU time 0.7 seconds
Started Jul 24 05:52:36 PM PDT 24
Finished Jul 24 05:52:37 PM PDT 24
Peak memory 203964 kb
Host smart-4b442fce-5764-4ff4-a661-7be0cf15e765
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577786313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.1577786313
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1636504419
Short name T1021
Test name
Test status
Simulation time 55694670 ps
CPU time 1.79 seconds
Started Jul 24 05:52:34 PM PDT 24
Finished Jul 24 05:52:36 PM PDT 24
Peak memory 207196 kb
Host smart-b3754ccb-255c-4039-984b-83bbb9c02ac3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636504419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.1636504419
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2056944837
Short name T1114
Test name
Test status
Simulation time 157798538 ps
CPU time 4.33 seconds
Started Jul 24 05:52:34 PM PDT 24
Finished Jul 24 05:52:39 PM PDT 24
Peak memory 215632 kb
Host smart-dd44d0d4-e4fa-4af8-9d5f-75a972aed94d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056944837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.2
056944837
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2185296786
Short name T172
Test name
Test status
Simulation time 205863741 ps
CPU time 12.56 seconds
Started Jul 24 05:52:35 PM PDT 24
Finished Jul 24 05:52:48 PM PDT 24
Peak memory 215496 kb
Host smart-9ed3f0e3-70bb-4d96-a2b5-62320bdd7193
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185296786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.2185296786
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.252076281
Short name T1127
Test name
Test status
Simulation time 38237972 ps
CPU time 0.71 seconds
Started Jul 24 05:53:01 PM PDT 24
Finished Jul 24 05:53:02 PM PDT 24
Peak memory 203912 kb
Host smart-9818c716-2338-4272-80fb-f846e7777713
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252076281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.252076281
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.1458719823
Short name T1112
Test name
Test status
Simulation time 21704633 ps
CPU time 0.7 seconds
Started Jul 24 05:52:58 PM PDT 24
Finished Jul 24 05:52:59 PM PDT 24
Peak memory 204296 kb
Host smart-ca748d7f-f574-465b-b78b-cff98c855864
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458719823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
1458719823
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.1049442016
Short name T1035
Test name
Test status
Simulation time 53587919 ps
CPU time 0.78 seconds
Started Jul 24 05:52:55 PM PDT 24
Finished Jul 24 05:52:56 PM PDT 24
Peak memory 204000 kb
Host smart-0f3a9e28-c8e6-482a-8169-cd602ddbb8c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049442016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
1049442016
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.1592888225
Short name T1060
Test name
Test status
Simulation time 11827388 ps
CPU time 0.68 seconds
Started Jul 24 05:52:57 PM PDT 24
Finished Jul 24 05:52:58 PM PDT 24
Peak memory 204020 kb
Host smart-927d5090-0037-467b-84d2-c763f1ffbfc2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592888225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
1592888225
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1112808452
Short name T1020
Test name
Test status
Simulation time 18661622 ps
CPU time 0.69 seconds
Started Jul 24 05:53:01 PM PDT 24
Finished Jul 24 05:53:02 PM PDT 24
Peak memory 203956 kb
Host smart-5d23b3fe-2cbe-4765-b3bb-2f3bfdba52a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112808452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
1112808452
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3530477057
Short name T1045
Test name
Test status
Simulation time 13173298 ps
CPU time 0.72 seconds
Started Jul 24 05:53:00 PM PDT 24
Finished Jul 24 05:53:01 PM PDT 24
Peak memory 203980 kb
Host smart-ea7b6cae-c57c-4afd-8ec6-1866d6d25ff9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530477057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
3530477057
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.3053734994
Short name T1039
Test name
Test status
Simulation time 19875177 ps
CPU time 0.77 seconds
Started Jul 24 05:52:59 PM PDT 24
Finished Jul 24 05:53:01 PM PDT 24
Peak memory 203908 kb
Host smart-3b015168-ed1c-4bc0-9862-b5d05c25a76e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053734994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
3053734994
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.1514552145
Short name T1096
Test name
Test status
Simulation time 80283122 ps
CPU time 0.8 seconds
Started Jul 24 05:53:02 PM PDT 24
Finished Jul 24 05:53:03 PM PDT 24
Peak memory 204008 kb
Host smart-908a79a0-87bb-489a-a944-607399e55cc1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514552145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
1514552145
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2134174912
Short name T1017
Test name
Test status
Simulation time 18324594 ps
CPU time 0.8 seconds
Started Jul 24 05:52:56 PM PDT 24
Finished Jul 24 05:52:57 PM PDT 24
Peak memory 204024 kb
Host smart-a2b0155e-bc61-4770-8ae0-f499d43cb628
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134174912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
2134174912
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.231717287
Short name T1110
Test name
Test status
Simulation time 38350567 ps
CPU time 0.82 seconds
Started Jul 24 05:52:59 PM PDT 24
Finished Jul 24 05:53:00 PM PDT 24
Peak memory 203960 kb
Host smart-6c7a6095-6f36-4aaf-93ff-2c99564eeda1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231717287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.231717287
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.4056555880
Short name T60
Test name
Test status
Simulation time 138196692 ps
CPU time 3.8 seconds
Started Jul 24 05:52:36 PM PDT 24
Finished Jul 24 05:52:40 PM PDT 24
Peak memory 217240 kb
Host smart-3a0b2ef7-46c5-4206-8f4c-c3029f2a6371
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056555880 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.4056555880
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.2508434975
Short name T1085
Test name
Test status
Simulation time 40903095 ps
CPU time 1.27 seconds
Started Jul 24 05:52:38 PM PDT 24
Finished Jul 24 05:52:39 PM PDT 24
Peak memory 207284 kb
Host smart-87228c85-d2bb-44aa-b749-4a92227f25ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508434975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.2
508434975
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3526397115
Short name T1034
Test name
Test status
Simulation time 13171429 ps
CPU time 0.71 seconds
Started Jul 24 05:52:34 PM PDT 24
Finished Jul 24 05:52:35 PM PDT 24
Peak memory 203992 kb
Host smart-ba526589-1f90-45c4-a3a4-36c860219caf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526397115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.3
526397115
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.3545825214
Short name T1025
Test name
Test status
Simulation time 108892850 ps
CPU time 2.98 seconds
Started Jul 24 05:52:35 PM PDT 24
Finished Jul 24 05:52:38 PM PDT 24
Peak memory 215508 kb
Host smart-d811aace-6ddb-41cf-b52e-312906c4c5ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545825214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.3545825214
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.748393381
Short name T96
Test name
Test status
Simulation time 158521417 ps
CPU time 2.4 seconds
Started Jul 24 05:52:39 PM PDT 24
Finished Jul 24 05:52:42 PM PDT 24
Peak memory 215744 kb
Host smart-a3aa483f-e3f6-4df2-907b-531030634dfc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748393381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.748393381
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.2121561481
Short name T1074
Test name
Test status
Simulation time 1003321342 ps
CPU time 9.02 seconds
Started Jul 24 05:52:36 PM PDT 24
Finished Jul 24 05:52:45 PM PDT 24
Peak memory 215532 kb
Host smart-cd68511a-7533-4781-b1b1-579e8cbd94ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121561481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.2121561481
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2599906677
Short name T1105
Test name
Test status
Simulation time 748669251 ps
CPU time 3.05 seconds
Started Jul 24 05:52:37 PM PDT 24
Finished Jul 24 05:52:41 PM PDT 24
Peak memory 216556 kb
Host smart-02f458f2-d3fc-491c-98f1-08fb5e6bb40f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599906677 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.2599906677
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1198202666
Short name T111
Test name
Test status
Simulation time 73080372 ps
CPU time 2.6 seconds
Started Jul 24 05:52:37 PM PDT 24
Finished Jul 24 05:52:40 PM PDT 24
Peak memory 215296 kb
Host smart-674fd740-eb3d-4bd7-a861-e9d59eb5daa4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198202666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.1
198202666
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2413845365
Short name T1123
Test name
Test status
Simulation time 27732022 ps
CPU time 0.73 seconds
Started Jul 24 05:52:39 PM PDT 24
Finished Jul 24 05:52:40 PM PDT 24
Peak memory 204320 kb
Host smart-7135fabd-13e2-4fe4-9486-60095af153e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413845365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.2
413845365
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.865114119
Short name T1033
Test name
Test status
Simulation time 389171068 ps
CPU time 2.77 seconds
Started Jul 24 05:52:34 PM PDT 24
Finished Jul 24 05:52:37 PM PDT 24
Peak memory 215580 kb
Host smart-c993978f-7ecf-42a5-b3e0-a84ddd563611
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865114119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sp
i_device_same_csr_outstanding.865114119
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.3621954510
Short name T101
Test name
Test status
Simulation time 142960048 ps
CPU time 4.44 seconds
Started Jul 24 05:52:35 PM PDT 24
Finished Jul 24 05:52:40 PM PDT 24
Peak memory 215724 kb
Host smart-6497ae96-4853-4de3-82fa-9279560a79ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621954510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.3
621954510
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.2839602022
Short name T176
Test name
Test status
Simulation time 804592427 ps
CPU time 19.54 seconds
Started Jul 24 05:52:32 PM PDT 24
Finished Jul 24 05:52:51 PM PDT 24
Peak memory 215472 kb
Host smart-0dbaaa55-da3a-4cef-8757-56b5bc81a978
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839602022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.2839602022
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3251592030
Short name T1065
Test name
Test status
Simulation time 334793344 ps
CPU time 1.9 seconds
Started Jul 24 05:52:39 PM PDT 24
Finished Jul 24 05:52:41 PM PDT 24
Peak memory 215556 kb
Host smart-dfe55b22-d0ff-4d74-a011-3a916468e021
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251592030 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.3251592030
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1608432394
Short name T119
Test name
Test status
Simulation time 100581685 ps
CPU time 1.9 seconds
Started Jul 24 05:52:41 PM PDT 24
Finished Jul 24 05:52:43 PM PDT 24
Peak memory 215536 kb
Host smart-d4ba46c2-fa24-4a17-be9a-f12b1298656f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608432394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.1
608432394
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.1576724804
Short name T1079
Test name
Test status
Simulation time 230459764 ps
CPU time 0.72 seconds
Started Jul 24 05:52:41 PM PDT 24
Finished Jul 24 05:52:42 PM PDT 24
Peak memory 204032 kb
Host smart-cbc2e2d2-735f-4048-9444-473158935e60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576724804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.1
576724804
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.4059083521
Short name T1071
Test name
Test status
Simulation time 228240729 ps
CPU time 3.18 seconds
Started Jul 24 05:52:41 PM PDT 24
Finished Jul 24 05:52:44 PM PDT 24
Peak memory 215576 kb
Host smart-ef632d91-9a62-4865-acb2-15c685b64ef0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059083521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.4059083521
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.644693711
Short name T99
Test name
Test status
Simulation time 86188354 ps
CPU time 2.33 seconds
Started Jul 24 05:52:41 PM PDT 24
Finished Jul 24 05:52:43 PM PDT 24
Peak memory 215756 kb
Host smart-c56b0afe-9983-4a8d-91dc-b65ad927fcf1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644693711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.644693711
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.3715273696
Short name T97
Test name
Test status
Simulation time 817620292 ps
CPU time 12.38 seconds
Started Jul 24 05:52:39 PM PDT 24
Finished Jul 24 05:52:51 PM PDT 24
Peak memory 215512 kb
Host smart-66f85268-338d-48f6-9e13-99c1522f6776
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715273696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.3715273696
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3208445837
Short name T1062
Test name
Test status
Simulation time 302445320 ps
CPU time 3.86 seconds
Started Jul 24 05:52:43 PM PDT 24
Finished Jul 24 05:52:47 PM PDT 24
Peak memory 218672 kb
Host smart-264d72bf-fd8a-4093-9fb5-c5e335652cfd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208445837 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.3208445837
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3551949309
Short name T123
Test name
Test status
Simulation time 164155351 ps
CPU time 1.32 seconds
Started Jul 24 05:52:44 PM PDT 24
Finished Jul 24 05:52:46 PM PDT 24
Peak memory 215612 kb
Host smart-f72caeb8-4a66-4a62-8003-30b723f105b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551949309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.3
551949309
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.2988227889
Short name T1016
Test name
Test status
Simulation time 54768528 ps
CPU time 0.78 seconds
Started Jul 24 05:52:40 PM PDT 24
Finished Jul 24 05:52:41 PM PDT 24
Peak memory 204004 kb
Host smart-82007628-28ca-4f56-8048-7a2f71b7e015
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988227889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.2
988227889
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.1003482779
Short name T143
Test name
Test status
Simulation time 543232811 ps
CPU time 3.26 seconds
Started Jul 24 05:52:42 PM PDT 24
Finished Jul 24 05:52:46 PM PDT 24
Peak memory 215480 kb
Host smart-7d37dfbb-8f2e-423a-b599-d19ab1a05cc4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003482779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.1003482779
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.1179258586
Short name T1101
Test name
Test status
Simulation time 3243905466 ps
CPU time 4.64 seconds
Started Jul 24 05:52:44 PM PDT 24
Finished Jul 24 05:52:49 PM PDT 24
Peak memory 215672 kb
Host smart-a4e996e2-119f-4d6b-a1c2-968a64696a35
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179258586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.1
179258586
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1938758717
Short name T1122
Test name
Test status
Simulation time 565968500 ps
CPU time 7.44 seconds
Started Jul 24 05:52:44 PM PDT 24
Finished Jul 24 05:52:52 PM PDT 24
Peak memory 215640 kb
Host smart-7e3662c1-845b-40fa-9abc-fe6dc176693e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938758717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.1938758717
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.968916100
Short name T1044
Test name
Test status
Simulation time 642153125 ps
CPU time 3.58 seconds
Started Jul 24 05:52:39 PM PDT 24
Finished Jul 24 05:52:43 PM PDT 24
Peak memory 216688 kb
Host smart-799a8f4c-9f27-4e81-b03f-f33ce04dc903
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968916100 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.968916100
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.2592530609
Short name T1106
Test name
Test status
Simulation time 110880565 ps
CPU time 2.54 seconds
Started Jul 24 05:52:41 PM PDT 24
Finished Jul 24 05:52:44 PM PDT 24
Peak memory 215488 kb
Host smart-81956776-c7c2-4a86-852b-dbbd19d64c0e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592530609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.2
592530609
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.4110773904
Short name T1055
Test name
Test status
Simulation time 18605901 ps
CPU time 0.92 seconds
Started Jul 24 05:52:39 PM PDT 24
Finished Jul 24 05:52:40 PM PDT 24
Peak memory 204288 kb
Host smart-a30c1d25-ed4f-4f0f-b232-6a76a2ff99a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110773904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.4
110773904
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.4228324644
Short name T1088
Test name
Test status
Simulation time 407579976 ps
CPU time 3.04 seconds
Started Jul 24 05:52:42 PM PDT 24
Finished Jul 24 05:52:45 PM PDT 24
Peak memory 215652 kb
Host smart-6d1cb19e-0491-470d-b6b0-2438708393c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228324644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.4228324644
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.2822182999
Short name T168
Test name
Test status
Simulation time 76987709 ps
CPU time 1.69 seconds
Started Jul 24 05:52:44 PM PDT 24
Finished Jul 24 05:52:46 PM PDT 24
Peak memory 215616 kb
Host smart-d9a7292e-6796-4974-8884-7d03d65e19c6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822182999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.2
822182999
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2063447697
Short name T171
Test name
Test status
Simulation time 650615571 ps
CPU time 18.03 seconds
Started Jul 24 05:52:40 PM PDT 24
Finished Jul 24 05:52:58 PM PDT 24
Peak memory 215560 kb
Host smart-dfcf5234-a04c-4054-8514-63b42ee8e917
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063447697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.2063447697
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.250285839
Short name T819
Test name
Test status
Simulation time 14823867 ps
CPU time 0.72 seconds
Started Jul 24 05:53:55 PM PDT 24
Finished Jul 24 05:53:56 PM PDT 24
Peak memory 205028 kb
Host smart-5ca354a9-027a-4e87-aad3-3a0bbbc41682
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250285839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.250285839
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.3424229763
Short name T54
Test name
Test status
Simulation time 38851490 ps
CPU time 2.36 seconds
Started Jul 24 05:54:02 PM PDT 24
Finished Jul 24 05:54:04 PM PDT 24
Peak memory 224684 kb
Host smart-5e8ea5c6-22a9-486f-b17d-75a31bec8f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424229763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.3424229763
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.4126886051
Short name T455
Test name
Test status
Simulation time 45096811 ps
CPU time 0.75 seconds
Started Jul 24 05:53:54 PM PDT 24
Finished Jul 24 05:53:55 PM PDT 24
Peak memory 206748 kb
Host smart-3befb92b-a0cd-4c41-a9b5-2784ecf7838f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126886051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.4126886051
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.4080681393
Short name T285
Test name
Test status
Simulation time 19730765077 ps
CPU time 90.62 seconds
Started Jul 24 05:54:02 PM PDT 24
Finished Jul 24 05:55:33 PM PDT 24
Peak memory 253972 kb
Host smart-24f33eac-e797-4807-b176-6e5df6971b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080681393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.4080681393
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.3599751526
Short name T282
Test name
Test status
Simulation time 12591597879 ps
CPU time 102.31 seconds
Started Jul 24 05:53:58 PM PDT 24
Finished Jul 24 05:55:40 PM PDT 24
Peak memory 257576 kb
Host smart-5acad8e2-e035-438b-9cfd-1f1a57ee4163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599751526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.3599751526
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.3705142574
Short name T402
Test name
Test status
Simulation time 5654492586 ps
CPU time 65.59 seconds
Started Jul 24 05:54:01 PM PDT 24
Finished Jul 24 05:55:07 PM PDT 24
Peak memory 264976 kb
Host smart-2fa9ab00-cc94-4bb0-bb57-c8fc928641f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705142574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.3705142574
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.3192727011
Short name T564
Test name
Test status
Simulation time 7202011640 ps
CPU time 44.32 seconds
Started Jul 24 05:53:56 PM PDT 24
Finished Jul 24 05:54:41 PM PDT 24
Peak memory 255168 kb
Host smart-c7d7a47e-9a05-44f5-a4d9-d34f6a433e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192727011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds
.3192727011
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_intercept.3538961157
Short name T894
Test name
Test status
Simulation time 211959739 ps
CPU time 3.86 seconds
Started Jul 24 05:53:51 PM PDT 24
Finished Jul 24 05:53:55 PM PDT 24
Peak memory 224660 kb
Host smart-ec375bd7-6b14-43d5-adc9-830bc96847a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538961157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.3538961157
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.1200610833
Short name T189
Test name
Test status
Simulation time 5778574925 ps
CPU time 24.76 seconds
Started Jul 24 05:53:56 PM PDT 24
Finished Jul 24 05:54:21 PM PDT 24
Peak memory 232960 kb
Host smart-d8afcfac-e371-4dd8-ad1b-03773f165e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200610833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.1200610833
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.124248102
Short name T497
Test name
Test status
Simulation time 3598865101 ps
CPU time 8.86 seconds
Started Jul 24 05:53:49 PM PDT 24
Finished Jul 24 05:53:58 PM PDT 24
Peak memory 224736 kb
Host smart-1425b83f-f0a2-4ed5-814d-2be7c447e023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124248102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap.
124248102
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.1197070172
Short name T676
Test name
Test status
Simulation time 1345053938 ps
CPU time 5.57 seconds
Started Jul 24 05:53:49 PM PDT 24
Finished Jul 24 05:53:54 PM PDT 24
Peak memory 232788 kb
Host smart-624b7901-59d1-442e-bc20-f14fe5e3cbee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197070172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.1197070172
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.234878892
Short name T853
Test name
Test status
Simulation time 974331754 ps
CPU time 6.37 seconds
Started Jul 24 05:53:55 PM PDT 24
Finished Jul 24 05:54:01 PM PDT 24
Peak memory 223252 kb
Host smart-f452ac1f-090b-4946-8dd2-708dced140b8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=234878892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_direc
t.234878892
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.2541727338
Short name T64
Test name
Test status
Simulation time 38784243 ps
CPU time 1.05 seconds
Started Jul 24 05:53:57 PM PDT 24
Finished Jul 24 05:53:58 PM PDT 24
Peak memory 236532 kb
Host smart-e818b464-c858-41b1-9069-76e03b5b43d3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541727338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.2541727338
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.4012180096
Short name T296
Test name
Test status
Simulation time 34888459366 ps
CPU time 42.42 seconds
Started Jul 24 05:53:49 PM PDT 24
Finished Jul 24 05:54:32 PM PDT 24
Peak memory 216496 kb
Host smart-58c56cfa-9839-4d93-9ac0-0705eb108b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012180096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.4012180096
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.653011583
Short name T484
Test name
Test status
Simulation time 2494385611 ps
CPU time 7.14 seconds
Started Jul 24 05:53:49 PM PDT 24
Finished Jul 24 05:53:56 PM PDT 24
Peak memory 216496 kb
Host smart-21ab1f43-da8e-4cbd-a29e-e916df3b3222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653011583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.653011583
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.4288246030
Short name T312
Test name
Test status
Simulation time 342537260 ps
CPU time 1.2 seconds
Started Jul 24 05:53:50 PM PDT 24
Finished Jul 24 05:53:51 PM PDT 24
Peak memory 208024 kb
Host smart-a3e744ab-802b-4a5d-a388-6307d0194425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288246030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.4288246030
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.591938425
Short name T900
Test name
Test status
Simulation time 44252442 ps
CPU time 0.88 seconds
Started Jul 24 05:53:56 PM PDT 24
Finished Jul 24 05:53:57 PM PDT 24
Peak memory 206124 kb
Host smart-a271bbe6-9307-4e73-89bc-d087a999c1a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591938425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.591938425
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.2894643180
Short name T215
Test name
Test status
Simulation time 640632806 ps
CPU time 3.46 seconds
Started Jul 24 05:53:57 PM PDT 24
Finished Jul 24 05:54:01 PM PDT 24
Peak memory 224720 kb
Host smart-a992b25e-3205-485e-bb63-f6e00b3c923c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894643180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.2894643180
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.729857207
Short name T552
Test name
Test status
Simulation time 23198396 ps
CPU time 0.77 seconds
Started Jul 24 05:54:02 PM PDT 24
Finished Jul 24 05:54:02 PM PDT 24
Peak memory 205028 kb
Host smart-bc0d9e46-75e1-493d-b6d9-bf64216a1502
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729857207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.729857207
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.186933524
Short name T785
Test name
Test status
Simulation time 236105693 ps
CPU time 2.21 seconds
Started Jul 24 05:53:57 PM PDT 24
Finished Jul 24 05:53:59 PM PDT 24
Peak memory 224660 kb
Host smart-6e5367c4-ea6b-419b-b2a2-0d37aac0090a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186933524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.186933524
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.4113758260
Short name T897
Test name
Test status
Simulation time 17270184 ps
CPU time 0.78 seconds
Started Jul 24 05:53:57 PM PDT 24
Finished Jul 24 05:53:58 PM PDT 24
Peak memory 206756 kb
Host smart-e1d4027a-d0a8-4a1d-ac22-8dd35172a042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113758260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.4113758260
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.3143625138
Short name T579
Test name
Test status
Simulation time 10488136465 ps
CPU time 19.43 seconds
Started Jul 24 05:53:58 PM PDT 24
Finished Jul 24 05:54:18 PM PDT 24
Peak memory 224776 kb
Host smart-79cac3bc-8a71-4284-a3ce-f9eeff8a8e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143625138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.3143625138
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.3726742060
Short name T959
Test name
Test status
Simulation time 8640124263 ps
CPU time 79.64 seconds
Started Jul 24 05:54:02 PM PDT 24
Finished Jul 24 05:55:22 PM PDT 24
Peak memory 263172 kb
Host smart-28d59049-2889-40ff-b2a5-992bbe8675e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726742060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.3726742060
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.3619770946
Short name T923
Test name
Test status
Simulation time 618294935 ps
CPU time 5.92 seconds
Started Jul 24 05:53:54 PM PDT 24
Finished Jul 24 05:54:00 PM PDT 24
Peak memory 224676 kb
Host smart-378e0418-19d0-4b51-8a58-5fc73d3deb4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619770946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.3619770946
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.1210527231
Short name T448
Test name
Test status
Simulation time 11826557760 ps
CPU time 63.64 seconds
Started Jul 24 05:53:57 PM PDT 24
Finished Jul 24 05:55:01 PM PDT 24
Peak memory 249388 kb
Host smart-dc68073e-1d94-49fc-9b41-d1412a16edbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210527231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds
.1210527231
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_intercept.1062430717
Short name T610
Test name
Test status
Simulation time 4256391876 ps
CPU time 18.17 seconds
Started Jul 24 05:53:57 PM PDT 24
Finished Jul 24 05:54:16 PM PDT 24
Peak memory 224688 kb
Host smart-d0b64f2c-798e-4ee8-b1e5-bd49fa83a975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062430717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.1062430717
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.2055951154
Short name T462
Test name
Test status
Simulation time 14239947456 ps
CPU time 135.57 seconds
Started Jul 24 05:53:58 PM PDT 24
Finished Jul 24 05:56:14 PM PDT 24
Peak memory 232592 kb
Host smart-82df971a-e496-48f8-bb66-fdbf55af3374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055951154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.2055951154
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.4020291481
Short name T836
Test name
Test status
Simulation time 16862315376 ps
CPU time 13.68 seconds
Started Jul 24 05:53:57 PM PDT 24
Finished Jul 24 05:54:11 PM PDT 24
Peak memory 232948 kb
Host smart-d1bc14d7-b6e4-41d0-aeec-3464cf54a8ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020291481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.4020291481
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.2996062698
Short name T235
Test name
Test status
Simulation time 2557695850 ps
CPU time 8.81 seconds
Started Jul 24 05:53:55 PM PDT 24
Finished Jul 24 05:54:04 PM PDT 24
Peak memory 235296 kb
Host smart-c2afef2c-f57e-430b-80f0-5f8aa3aacc37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996062698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.2996062698
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.2032228905
Short name T595
Test name
Test status
Simulation time 4016503254 ps
CPU time 10.13 seconds
Started Jul 24 05:53:56 PM PDT 24
Finished Jul 24 05:54:06 PM PDT 24
Peak memory 220888 kb
Host smart-4981e6ad-ae37-4479-a15e-1f690c6fe57c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2032228905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.2032228905
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.4135396348
Short name T66
Test name
Test status
Simulation time 440762234 ps
CPU time 1.1 seconds
Started Jul 24 05:53:59 PM PDT 24
Finished Jul 24 05:54:00 PM PDT 24
Peak memory 235880 kb
Host smart-779b19a8-7a0c-4a15-984e-d099e165855f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135396348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.4135396348
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.700547312
Short name T539
Test name
Test status
Simulation time 12295851785 ps
CPU time 10.91 seconds
Started Jul 24 05:54:01 PM PDT 24
Finished Jul 24 05:54:12 PM PDT 24
Peak memory 216496 kb
Host smart-346c22a4-df2b-4d9c-a891-43d7def300df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700547312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.700547312
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.3171606631
Short name T492
Test name
Test status
Simulation time 857505208 ps
CPU time 3.48 seconds
Started Jul 24 05:53:58 PM PDT 24
Finished Jul 24 05:54:02 PM PDT 24
Peak memory 216368 kb
Host smart-b17d923e-7be8-4191-89c1-885ffd2d090c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171606631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.3171606631
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.4189618869
Short name T722
Test name
Test status
Simulation time 82488780 ps
CPU time 3.8 seconds
Started Jul 24 05:53:56 PM PDT 24
Finished Jul 24 05:54:00 PM PDT 24
Peak memory 216432 kb
Host smart-11c24427-bce9-47e1-8ed3-886c242eb982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189618869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.4189618869
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.2149918552
Short name T991
Test name
Test status
Simulation time 113386093 ps
CPU time 0.75 seconds
Started Jul 24 05:53:55 PM PDT 24
Finished Jul 24 05:53:56 PM PDT 24
Peak memory 206108 kb
Host smart-a5ed2c72-e1d1-49ce-a3eb-5694b027014d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149918552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.2149918552
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.4123664912
Short name T639
Test name
Test status
Simulation time 118231275 ps
CPU time 2.64 seconds
Started Jul 24 05:53:57 PM PDT 24
Finished Jul 24 05:54:00 PM PDT 24
Peak memory 232876 kb
Host smart-0942cbd5-ce88-4ed9-b999-3a94511dd53f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123664912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.4123664912
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.2721882711
Short name T806
Test name
Test status
Simulation time 86579885 ps
CPU time 0.72 seconds
Started Jul 24 05:54:32 PM PDT 24
Finished Jul 24 05:54:33 PM PDT 24
Peak memory 205028 kb
Host smart-1934f99f-06c5-47eb-b9e5-e86788ca4614
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721882711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
2721882711
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.550803211
Short name T158
Test name
Test status
Simulation time 1983389893 ps
CPU time 8.42 seconds
Started Jul 24 05:54:28 PM PDT 24
Finished Jul 24 05:54:36 PM PDT 24
Peak memory 224668 kb
Host smart-42e7c0b2-1a54-4db6-a075-36f71efd1569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550803211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.550803211
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.2220524520
Short name T313
Test name
Test status
Simulation time 53381835 ps
CPU time 0.78 seconds
Started Jul 24 05:54:26 PM PDT 24
Finished Jul 24 05:54:27 PM PDT 24
Peak memory 205700 kb
Host smart-4b227759-8736-4cc2-83c5-939f8324093f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220524520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.2220524520
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.688377488
Short name T794
Test name
Test status
Simulation time 2207275304 ps
CPU time 41.45 seconds
Started Jul 24 05:54:30 PM PDT 24
Finished Jul 24 05:55:11 PM PDT 24
Peak memory 249348 kb
Host smart-6f1a0894-3550-45ca-9542-2c3d22b2d464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688377488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.688377488
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.3709094151
Short name T641
Test name
Test status
Simulation time 4728515913 ps
CPU time 25.88 seconds
Started Jul 24 05:54:28 PM PDT 24
Finished Jul 24 05:54:54 PM PDT 24
Peak memory 219424 kb
Host smart-d8794538-1c4c-4ca0-9681-7be930fff9f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709094151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.3709094151
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.1333230466
Short name T514
Test name
Test status
Simulation time 25801399405 ps
CPU time 209.7 seconds
Started Jul 24 05:54:28 PM PDT 24
Finished Jul 24 05:57:58 PM PDT 24
Peak memory 253552 kb
Host smart-4a96bee0-262d-4562-b28a-dcfe2712f1fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333230466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.1333230466
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.751092285
Short name T292
Test name
Test status
Simulation time 1873821272 ps
CPU time 10.93 seconds
Started Jul 24 05:54:27 PM PDT 24
Finished Jul 24 05:54:38 PM PDT 24
Peak memory 232952 kb
Host smart-98b5d38b-6e7d-4fc6-9bea-7068e6041da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751092285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.751092285
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.1820283422
Short name T772
Test name
Test status
Simulation time 34289706268 ps
CPU time 26.65 seconds
Started Jul 24 05:54:37 PM PDT 24
Finished Jul 24 05:55:04 PM PDT 24
Peak memory 237528 kb
Host smart-c6384ef9-f91c-4a44-a0ad-3a724d8c3f4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820283422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmd
s.1820283422
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_intercept.2386327453
Short name T647
Test name
Test status
Simulation time 10645449469 ps
CPU time 12.38 seconds
Started Jul 24 05:54:37 PM PDT 24
Finished Jul 24 05:54:49 PM PDT 24
Peak memory 232884 kb
Host smart-6bb178d0-109d-43ed-8854-2b3286419c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386327453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.2386327453
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.592326796
Short name T937
Test name
Test status
Simulation time 344614707 ps
CPU time 6.14 seconds
Started Jul 24 05:54:34 PM PDT 24
Finished Jul 24 05:54:40 PM PDT 24
Peak memory 224704 kb
Host smart-0ca22868-8d5c-4829-977a-012b249c6710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592326796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.592326796
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.209649559
Short name T608
Test name
Test status
Simulation time 4415188763 ps
CPU time 9.96 seconds
Started Jul 24 05:54:31 PM PDT 24
Finished Jul 24 05:54:41 PM PDT 24
Peak memory 240904 kb
Host smart-99360f48-f1a2-4d6a-9850-6fa2096be6fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209649559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swap
.209649559
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.4244305094
Short name T414
Test name
Test status
Simulation time 3580490099 ps
CPU time 10.19 seconds
Started Jul 24 05:54:27 PM PDT 24
Finished Jul 24 05:54:37 PM PDT 24
Peak memory 239724 kb
Host smart-606ae00b-b02b-4da4-9b5f-244a417ef2fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244305094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.4244305094
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.4283619691
Short name T989
Test name
Test status
Simulation time 1817999014 ps
CPU time 7.95 seconds
Started Jul 24 05:54:32 PM PDT 24
Finished Jul 24 05:54:40 PM PDT 24
Peak memory 224008 kb
Host smart-871951c1-7f72-4299-a9f0-795bc35f6c75
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4283619691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.4283619691
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.4240657424
Short name T995
Test name
Test status
Simulation time 12339330866 ps
CPU time 183.57 seconds
Started Jul 24 05:54:34 PM PDT 24
Finished Jul 24 05:57:38 PM PDT 24
Peak memory 253724 kb
Host smart-add110b0-075a-40fd-8bc9-4dc54a62f9d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240657424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.4240657424
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.1215801812
Short name T899
Test name
Test status
Simulation time 13417385737 ps
CPU time 37.62 seconds
Started Jul 24 05:54:27 PM PDT 24
Finished Jul 24 05:55:05 PM PDT 24
Peak memory 216388 kb
Host smart-c7ccf5af-c5fc-41f4-a518-5edb1726a155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215801812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.1215801812
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.1488238016
Short name T657
Test name
Test status
Simulation time 3671696018 ps
CPU time 8.74 seconds
Started Jul 24 05:54:28 PM PDT 24
Finished Jul 24 05:54:37 PM PDT 24
Peak memory 216472 kb
Host smart-3bb2bcb4-62cf-49d5-b1a1-1682f0c65bad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488238016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.1488238016
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.1346584239
Short name T550
Test name
Test status
Simulation time 11680263 ps
CPU time 0.71 seconds
Started Jul 24 05:54:30 PM PDT 24
Finished Jul 24 05:54:31 PM PDT 24
Peak memory 205824 kb
Host smart-b76c319d-e71e-4ee0-ad28-3e162803b72c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346584239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.1346584239
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.3551141067
Short name T974
Test name
Test status
Simulation time 129842337 ps
CPU time 0.83 seconds
Started Jul 24 05:54:33 PM PDT 24
Finished Jul 24 05:54:35 PM PDT 24
Peak memory 206100 kb
Host smart-f870adef-45a5-4c49-a08e-aff7d0bd83ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551141067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.3551141067
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.1253514710
Short name T17
Test name
Test status
Simulation time 8589039654 ps
CPU time 27.49 seconds
Started Jul 24 05:54:28 PM PDT 24
Finished Jul 24 05:54:56 PM PDT 24
Peak memory 240084 kb
Host smart-ebed33a8-3bec-4698-bdba-e83920d16fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253514710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.1253514710
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.3498123964
Short name T871
Test name
Test status
Simulation time 22958185 ps
CPU time 0.71 seconds
Started Jul 24 05:54:28 PM PDT 24
Finished Jul 24 05:54:29 PM PDT 24
Peak memory 204988 kb
Host smart-75bb7b4e-94a8-489a-80a4-41a126b16a67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498123964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
3498123964
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.2477493257
Short name T498
Test name
Test status
Simulation time 157022305 ps
CPU time 2.33 seconds
Started Jul 24 05:57:07 PM PDT 24
Finished Jul 24 05:57:10 PM PDT 24
Peak memory 224696 kb
Host smart-68c577a1-eea2-4a35-99c2-3668459531b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477493257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.2477493257
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.1636549794
Short name T766
Test name
Test status
Simulation time 14514824 ps
CPU time 0.76 seconds
Started Jul 24 05:54:29 PM PDT 24
Finished Jul 24 05:54:30 PM PDT 24
Peak memory 205712 kb
Host smart-a6f2f5a0-9757-4f03-9df1-73718cd6b978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636549794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.1636549794
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.3462863982
Short name T193
Test name
Test status
Simulation time 40224936489 ps
CPU time 279.3 seconds
Started Jul 24 05:54:31 PM PDT 24
Finished Jul 24 05:59:11 PM PDT 24
Peak memory 254120 kb
Host smart-d4fc0d6a-8f55-49d6-aa37-f2f5faa9f342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462863982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.3462863982
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.67013196
Short name T751
Test name
Test status
Simulation time 9529187739 ps
CPU time 19.59 seconds
Started Jul 24 05:54:29 PM PDT 24
Finished Jul 24 05:54:49 PM PDT 24
Peak memory 217720 kb
Host smart-e8030ec4-7d40-4005-b843-e17910dca49f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67013196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.67013196
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.1292467483
Short name T18
Test name
Test status
Simulation time 3504303942 ps
CPU time 77 seconds
Started Jul 24 05:54:34 PM PDT 24
Finished Jul 24 05:55:51 PM PDT 24
Peak memory 255960 kb
Host smart-c1461f57-404e-4744-9d1c-ae34df0e6311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292467483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.1292467483
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.3026550258
Short name T661
Test name
Test status
Simulation time 1373026543 ps
CPU time 4.47 seconds
Started Jul 24 05:54:35 PM PDT 24
Finished Jul 24 05:54:39 PM PDT 24
Peak memory 232940 kb
Host smart-01605783-1d24-433c-8b4c-a9fb5c58b68b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026550258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.3026550258
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.1687149561
Short name T861
Test name
Test status
Simulation time 13060490121 ps
CPU time 57.81 seconds
Started Jul 24 05:54:30 PM PDT 24
Finished Jul 24 05:55:28 PM PDT 24
Peak memory 252580 kb
Host smart-9cef5067-c373-4902-8f25-15ae292cf349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687149561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmd
s.1687149561
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_intercept.3336506754
Short name T807
Test name
Test status
Simulation time 518521815 ps
CPU time 3.47 seconds
Started Jul 24 05:54:33 PM PDT 24
Finished Jul 24 05:54:36 PM PDT 24
Peak memory 232936 kb
Host smart-a50b257b-de10-469c-8081-a3276a4d4fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336506754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.3336506754
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.1980283502
Short name T821
Test name
Test status
Simulation time 62729086712 ps
CPU time 162.57 seconds
Started Jul 24 05:54:28 PM PDT 24
Finished Jul 24 05:57:11 PM PDT 24
Peak memory 233164 kb
Host smart-1096fba1-fd99-458c-a3d0-85388f677126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980283502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.1980283502
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.3651833854
Short name T258
Test name
Test status
Simulation time 3636731027 ps
CPU time 7.41 seconds
Started Jul 24 05:54:28 PM PDT 24
Finished Jul 24 05:54:36 PM PDT 24
Peak memory 219976 kb
Host smart-ff397a4d-e7b1-4bd8-91f7-c67d8735cce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651833854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.3651833854
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.48392641
Short name T228
Test name
Test status
Simulation time 4285909856 ps
CPU time 14.05 seconds
Started Jul 24 05:54:29 PM PDT 24
Finished Jul 24 05:54:43 PM PDT 24
Peak memory 232888 kb
Host smart-acde86c1-09ab-4ae1-9316-e812b9c324f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48392641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.48392641
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.3655225275
Short name T337
Test name
Test status
Simulation time 7692047845 ps
CPU time 10.01 seconds
Started Jul 24 05:54:29 PM PDT 24
Finished Jul 24 05:54:39 PM PDT 24
Peak memory 223360 kb
Host smart-79aa351c-2302-465a-9735-9d26d58acdd6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3655225275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.3655225275
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.1696493261
Short name T680
Test name
Test status
Simulation time 245474846 ps
CPU time 3.09 seconds
Started Jul 24 05:54:28 PM PDT 24
Finished Jul 24 05:54:31 PM PDT 24
Peak memory 216356 kb
Host smart-4a308c00-1063-45fc-9207-8feb587e7f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696493261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.1696493261
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.2759513064
Short name T771
Test name
Test status
Simulation time 3735609755 ps
CPU time 12.64 seconds
Started Jul 24 05:54:35 PM PDT 24
Finished Jul 24 05:54:48 PM PDT 24
Peak memory 216432 kb
Host smart-84907583-2f5a-47bb-966b-0c2a98cb4d1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759513064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.2759513064
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.234991197
Short name T348
Test name
Test status
Simulation time 205715077 ps
CPU time 2.26 seconds
Started Jul 24 05:54:28 PM PDT 24
Finished Jul 24 05:54:30 PM PDT 24
Peak memory 216408 kb
Host smart-5d512bf3-5ace-4bb8-980a-1a1e3c5f5ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234991197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.234991197
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.3139991029
Short name T526
Test name
Test status
Simulation time 111240891 ps
CPU time 0.8 seconds
Started Jul 24 05:54:34 PM PDT 24
Finished Jul 24 05:54:35 PM PDT 24
Peak memory 206092 kb
Host smart-4ebb8f08-fb8f-4f95-945a-e0ab50d86120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139991029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.3139991029
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.632043468
Short name T947
Test name
Test status
Simulation time 468720898 ps
CPU time 3.33 seconds
Started Jul 24 05:54:27 PM PDT 24
Finished Jul 24 05:54:31 PM PDT 24
Peak memory 232920 kb
Host smart-94b22711-e8d3-41dc-8163-23a65a2ba774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632043468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.632043468
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.3490147588
Short name T717
Test name
Test status
Simulation time 12767012 ps
CPU time 0.74 seconds
Started Jul 24 05:54:41 PM PDT 24
Finished Jul 24 05:54:42 PM PDT 24
Peak memory 205584 kb
Host smart-97a346a4-125f-4687-a091-e39dd290fb0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490147588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
3490147588
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.3722105281
Short name T733
Test name
Test status
Simulation time 331174916 ps
CPU time 4.63 seconds
Started Jul 24 05:54:28 PM PDT 24
Finished Jul 24 05:54:33 PM PDT 24
Peak memory 224640 kb
Host smart-979564ef-07ba-490e-93c0-9fd2979731a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722105281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.3722105281
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.2707126197
Short name T321
Test name
Test status
Simulation time 15849084 ps
CPU time 0.76 seconds
Started Jul 24 05:54:29 PM PDT 24
Finished Jul 24 05:54:30 PM PDT 24
Peak memory 206712 kb
Host smart-3adc0d25-0a6f-448a-8e72-b55bd3602786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707126197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.2707126197
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.1769145764
Short name T210
Test name
Test status
Simulation time 30822766971 ps
CPU time 257.96 seconds
Started Jul 24 05:54:34 PM PDT 24
Finished Jul 24 05:58:52 PM PDT 24
Peak memory 256448 kb
Host smart-de36446c-cee8-424d-ac58-4beaf296202e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769145764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.1769145764
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.2966062314
Short name T901
Test name
Test status
Simulation time 77592376870 ps
CPU time 728.75 seconds
Started Jul 24 05:54:35 PM PDT 24
Finished Jul 24 06:06:44 PM PDT 24
Peak memory 273404 kb
Host smart-5d07910e-3b1b-489b-8568-1ccfa0356808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966062314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.2966062314
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.2502289998
Short name T135
Test name
Test status
Simulation time 40951383618 ps
CPU time 159.96 seconds
Started Jul 24 05:54:34 PM PDT 24
Finished Jul 24 05:57:15 PM PDT 24
Peak memory 268208 kb
Host smart-073eb134-a8f7-4254-86a6-86a6c0167cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502289998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.2502289998
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.2594155423
Short name T142
Test name
Test status
Simulation time 910575906 ps
CPU time 8.19 seconds
Started Jul 24 05:54:33 PM PDT 24
Finished Jul 24 05:54:42 PM PDT 24
Peak memory 224496 kb
Host smart-ff60bc46-bf78-4472-908c-b7ffe6d6c5dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594155423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.2594155423
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.2772559407
Short name T965
Test name
Test status
Simulation time 146525524290 ps
CPU time 250.28 seconds
Started Jul 24 05:54:29 PM PDT 24
Finished Jul 24 05:58:40 PM PDT 24
Peak memory 262632 kb
Host smart-4046ca19-e4ca-4f0c-ab67-7ec4f22bfea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772559407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmd
s.2772559407
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_intercept.2079165056
Short name T47
Test name
Test status
Simulation time 630498442 ps
CPU time 4.41 seconds
Started Jul 24 05:54:28 PM PDT 24
Finished Jul 24 05:54:33 PM PDT 24
Peak memory 224728 kb
Host smart-ce2a1700-4455-467e-934c-9497f7df9c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079165056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.2079165056
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.1352836137
Short name T617
Test name
Test status
Simulation time 10691241018 ps
CPU time 45.47 seconds
Started Jul 24 05:54:36 PM PDT 24
Finished Jul 24 05:55:22 PM PDT 24
Peak memory 250768 kb
Host smart-cc63593e-55ea-470e-aad4-f1204f6b4617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352836137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.1352836137
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.1458868246
Short name T470
Test name
Test status
Simulation time 1222617482 ps
CPU time 5.13 seconds
Started Jul 24 05:54:37 PM PDT 24
Finished Jul 24 05:54:42 PM PDT 24
Peak memory 232808 kb
Host smart-61c1c02a-4c8c-4f20-9af2-5da668ee218e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458868246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.1458868246
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.3326113851
Short name T435
Test name
Test status
Simulation time 679002207 ps
CPU time 4.27 seconds
Started Jul 24 05:54:29 PM PDT 24
Finished Jul 24 05:54:34 PM PDT 24
Peak memory 232904 kb
Host smart-711d79c4-f33a-42ca-a4ff-873d6141f8c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326113851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.3326113851
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.3071732225
Short name T799
Test name
Test status
Simulation time 231569703 ps
CPU time 4.75 seconds
Started Jul 24 05:54:29 PM PDT 24
Finished Jul 24 05:54:34 PM PDT 24
Peak memory 223280 kb
Host smart-410a36c7-60df-4da6-9ea6-2b2311529cd9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3071732225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.3071732225
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.3300944645
Short name T415
Test name
Test status
Simulation time 169080212 ps
CPU time 3.23 seconds
Started Jul 24 05:54:36 PM PDT 24
Finished Jul 24 05:54:40 PM PDT 24
Peak memory 218504 kb
Host smart-3fc39c4a-68f4-4f98-82bf-49517e84d456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300944645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.3300944645
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.2502437053
Short name T917
Test name
Test status
Simulation time 1962932761 ps
CPU time 5.82 seconds
Started Jul 24 05:54:32 PM PDT 24
Finished Jul 24 05:54:38 PM PDT 24
Peak memory 216376 kb
Host smart-b32ae860-52bc-4cfe-a229-dd9c00c7d276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502437053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.2502437053
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.21343494
Short name T938
Test name
Test status
Simulation time 131799511 ps
CPU time 3.7 seconds
Started Jul 24 05:54:34 PM PDT 24
Finished Jul 24 05:54:38 PM PDT 24
Peak memory 216356 kb
Host smart-347c5b55-b05b-4c65-baed-2b21d4387b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21343494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.21343494
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.1054938692
Short name T648
Test name
Test status
Simulation time 26458616 ps
CPU time 0.72 seconds
Started Jul 24 05:54:29 PM PDT 24
Finished Jul 24 05:54:30 PM PDT 24
Peak memory 206112 kb
Host smart-e18370d0-0991-48b3-9ce4-b636143e168a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054938692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.1054938692
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.2003535768
Short name T793
Test name
Test status
Simulation time 1373078442 ps
CPU time 9.52 seconds
Started Jul 24 05:54:34 PM PDT 24
Finished Jul 24 05:54:44 PM PDT 24
Peak memory 239628 kb
Host smart-cf2ce4a0-96e7-4124-8910-9ec7b6285115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003535768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.2003535768
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.1121886703
Short name T658
Test name
Test status
Simulation time 13600735 ps
CPU time 0.74 seconds
Started Jul 24 05:54:41 PM PDT 24
Finished Jul 24 05:54:42 PM PDT 24
Peak memory 205952 kb
Host smart-b3f8a665-3a20-456b-ba7a-dac077e67bf6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121886703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
1121886703
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.258449224
Short name T567
Test name
Test status
Simulation time 124695656 ps
CPU time 3.71 seconds
Started Jul 24 05:54:36 PM PDT 24
Finished Jul 24 05:54:40 PM PDT 24
Peak memory 232792 kb
Host smart-486a5087-545b-4650-97af-afccc2a87191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258449224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.258449224
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.482682398
Short name T425
Test name
Test status
Simulation time 17781318 ps
CPU time 0.81 seconds
Started Jul 24 05:54:32 PM PDT 24
Finished Jul 24 05:54:33 PM PDT 24
Peak memory 206796 kb
Host smart-530be3b8-29f5-4fd6-aa93-b564b9cb5826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482682398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.482682398
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.3011223041
Short name T52
Test name
Test status
Simulation time 2482883150 ps
CPU time 18.88 seconds
Started Jul 24 05:54:36 PM PDT 24
Finished Jul 24 05:54:55 PM PDT 24
Peak memory 224764 kb
Host smart-6aa21b23-b8e7-45cf-af6f-f3f33aff28b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011223041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.3011223041
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.816039821
Short name T939
Test name
Test status
Simulation time 1796841488 ps
CPU time 13.08 seconds
Started Jul 24 05:54:36 PM PDT 24
Finished Jul 24 05:54:49 PM PDT 24
Peak memory 224728 kb
Host smart-8af8c1f2-7e3c-4f1d-a6cd-833ef2d5ec93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816039821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.816039821
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.768788474
Short name T1000
Test name
Test status
Simulation time 10034136741 ps
CPU time 21.48 seconds
Started Jul 24 05:54:36 PM PDT 24
Finished Jul 24 05:54:57 PM PDT 24
Peak memory 224732 kb
Host smart-3a277bff-2e19-4e19-9bf9-1311963f8f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768788474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idle
.768788474
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_intercept.4000719160
Short name T445
Test name
Test status
Simulation time 1311551271 ps
CPU time 7.36 seconds
Started Jul 24 05:54:37 PM PDT 24
Finished Jul 24 05:54:45 PM PDT 24
Peak memory 224632 kb
Host smart-0fa38c95-4418-4d04-b648-1837abc191c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000719160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.4000719160
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.2644800506
Short name T251
Test name
Test status
Simulation time 2630732798 ps
CPU time 18.66 seconds
Started Jul 24 05:54:36 PM PDT 24
Finished Jul 24 05:54:55 PM PDT 24
Peak memory 239880 kb
Host smart-6fb5b380-aabd-46e0-b92a-fac7d138d77a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644800506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.2644800506
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.1008154410
Short name T542
Test name
Test status
Simulation time 1821873216 ps
CPU time 9.19 seconds
Started Jul 24 05:54:34 PM PDT 24
Finished Jul 24 05:54:43 PM PDT 24
Peak memory 224612 kb
Host smart-0815eaa3-91e3-427c-bfb7-645c31a1fd6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008154410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.1008154410
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.519818727
Short name T201
Test name
Test status
Simulation time 15446576318 ps
CPU time 11.21 seconds
Started Jul 24 05:54:41 PM PDT 24
Finished Jul 24 05:54:52 PM PDT 24
Peak memory 224720 kb
Host smart-e23281c5-9d67-419c-b05c-72ac7c6dcca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519818727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.519818727
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.704377305
Short name T436
Test name
Test status
Simulation time 4536706182 ps
CPU time 6.56 seconds
Started Jul 24 05:54:35 PM PDT 24
Finished Jul 24 05:54:42 PM PDT 24
Peak memory 219584 kb
Host smart-2a315c2f-09e3-4d12-9859-73dbe25a21d9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=704377305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dire
ct.704377305
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.921725441
Short name T740
Test name
Test status
Simulation time 1732677626 ps
CPU time 26.1 seconds
Started Jul 24 05:54:35 PM PDT 24
Finished Jul 24 05:55:01 PM PDT 24
Peak memory 216448 kb
Host smart-409a65aa-c970-4a09-874d-822f84ceecc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921725441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.921725441
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.304036883
Short name T890
Test name
Test status
Simulation time 95278369 ps
CPU time 0.9 seconds
Started Jul 24 05:54:33 PM PDT 24
Finished Jul 24 05:54:34 PM PDT 24
Peak memory 207892 kb
Host smart-7b53429e-9299-4f8a-91e8-b78f58d54ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304036883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.304036883
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.2988529399
Short name T943
Test name
Test status
Simulation time 139927081 ps
CPU time 1.05 seconds
Started Jul 24 05:54:41 PM PDT 24
Finished Jul 24 05:54:42 PM PDT 24
Peak memory 207156 kb
Host smart-b6dd7a1d-ce52-4a86-9d58-42ab6bf88da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988529399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.2988529399
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.3367892506
Short name T255
Test name
Test status
Simulation time 10202885652 ps
CPU time 18.65 seconds
Started Jul 24 05:54:35 PM PDT 24
Finished Jul 24 05:54:54 PM PDT 24
Peak memory 240100 kb
Host smart-17d58988-8b26-4a4f-bbaa-a1ff042bb5b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367892506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.3367892506
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.3343622684
Short name T994
Test name
Test status
Simulation time 54948788 ps
CPU time 0.75 seconds
Started Jul 24 05:54:38 PM PDT 24
Finished Jul 24 05:54:39 PM PDT 24
Peak memory 205884 kb
Host smart-fcbc65ad-2939-4cdf-b4f8-1efa7d7d9672
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343622684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
3343622684
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.2794232814
Short name T433
Test name
Test status
Simulation time 87612092 ps
CPU time 3.32 seconds
Started Jul 24 05:54:41 PM PDT 24
Finished Jul 24 05:54:45 PM PDT 24
Peak memory 232916 kb
Host smart-79de3563-1585-4dcc-8d77-7a6c6b42c047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794232814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.2794232814
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.1824396699
Short name T762
Test name
Test status
Simulation time 16655079 ps
CPU time 0.92 seconds
Started Jul 24 05:54:36 PM PDT 24
Finished Jul 24 05:54:37 PM PDT 24
Peak memory 206720 kb
Host smart-e5fa9307-01a5-4c57-90a2-90e130e851a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824396699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.1824396699
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.2353872801
Short name T754
Test name
Test status
Simulation time 41944146961 ps
CPU time 279.43 seconds
Started Jul 24 05:54:44 PM PDT 24
Finished Jul 24 05:59:24 PM PDT 24
Peak memory 238780 kb
Host smart-f17f3304-6d7a-4c70-a8c0-64e7f2bb876c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353872801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.2353872801
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.2987587420
Short name T254
Test name
Test status
Simulation time 18155642246 ps
CPU time 100.55 seconds
Started Jul 24 05:54:40 PM PDT 24
Finished Jul 24 05:56:20 PM PDT 24
Peak memory 254272 kb
Host smart-c727ef93-444f-4445-ba1f-a27597c7bdad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987587420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.2987587420
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.435560597
Short name T741
Test name
Test status
Simulation time 13449657536 ps
CPU time 75.85 seconds
Started Jul 24 05:54:35 PM PDT 24
Finished Jul 24 05:55:51 PM PDT 24
Peak memory 252388 kb
Host smart-663dde69-50a9-4c24-abd5-49071ba7a1e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435560597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmds
.435560597
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_intercept.3585266009
Short name T805
Test name
Test status
Simulation time 282084651 ps
CPU time 5.29 seconds
Started Jul 24 05:54:35 PM PDT 24
Finished Jul 24 05:54:40 PM PDT 24
Peak memory 224708 kb
Host smart-d59eae20-b33d-4850-878c-7cb15a9d609a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585266009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.3585266009
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.200063782
Short name T798
Test name
Test status
Simulation time 73895814 ps
CPU time 2.56 seconds
Started Jul 24 05:54:41 PM PDT 24
Finished Jul 24 05:54:44 PM PDT 24
Peak memory 232604 kb
Host smart-2926f4b9-82e6-496d-8a13-3b8c756147f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200063782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.200063782
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.1135790405
Short name T655
Test name
Test status
Simulation time 36954538 ps
CPU time 2.54 seconds
Started Jul 24 05:54:34 PM PDT 24
Finished Jul 24 05:54:37 PM PDT 24
Peak memory 232792 kb
Host smart-efc0f9fc-e332-4324-9fa2-f04ee583adee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135790405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.1135790405
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.2616355547
Short name T597
Test name
Test status
Simulation time 179828048 ps
CPU time 3.62 seconds
Started Jul 24 05:54:34 PM PDT 24
Finished Jul 24 05:54:38 PM PDT 24
Peak memory 232900 kb
Host smart-19c04d27-83a3-4c2d-8dcc-e5866940b37e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616355547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.2616355547
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.3050608967
Short name T767
Test name
Test status
Simulation time 8035395332 ps
CPU time 6.21 seconds
Started Jul 24 05:54:40 PM PDT 24
Finished Jul 24 05:54:46 PM PDT 24
Peak memory 223376 kb
Host smart-3ebc0e7c-ff4b-449f-9fc1-cb14005de55a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3050608967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.3050608967
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.1518819883
Short name T153
Test name
Test status
Simulation time 58807982978 ps
CPU time 148.36 seconds
Started Jul 24 05:54:39 PM PDT 24
Finished Jul 24 05:57:07 PM PDT 24
Peak memory 273968 kb
Host smart-88fd73f3-a1d0-47df-92c0-987e545675be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518819883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.1518819883
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.95421902
Short name T392
Test name
Test status
Simulation time 4597008184 ps
CPU time 13.46 seconds
Started Jul 24 05:54:37 PM PDT 24
Finished Jul 24 05:54:51 PM PDT 24
Peak memory 220264 kb
Host smart-ffc55907-1ec6-4360-aeff-3cbf6cec8954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95421902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.95421902
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.3627262
Short name T361
Test name
Test status
Simulation time 5340060104 ps
CPU time 4.3 seconds
Started Jul 24 05:54:41 PM PDT 24
Finished Jul 24 05:54:46 PM PDT 24
Peak memory 216468 kb
Host smart-c3bfb0c8-5447-43fc-808d-67c12c39ba97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.3627262
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.568684747
Short name T544
Test name
Test status
Simulation time 27877528 ps
CPU time 1.1 seconds
Started Jul 24 05:54:36 PM PDT 24
Finished Jul 24 05:54:37 PM PDT 24
Peak memory 207948 kb
Host smart-f82f353e-13e3-429a-b10e-ce3ea7939f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568684747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.568684747
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.3295363246
Short name T85
Test name
Test status
Simulation time 181312524 ps
CPU time 0.87 seconds
Started Jul 24 05:54:36 PM PDT 24
Finished Jul 24 05:54:37 PM PDT 24
Peak memory 206076 kb
Host smart-ff2356c2-2bfd-401a-8baf-ceb5d97f3e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295363246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.3295363246
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.585255035
Short name T205
Test name
Test status
Simulation time 2033708094 ps
CPU time 8.63 seconds
Started Jul 24 05:54:37 PM PDT 24
Finished Jul 24 05:54:46 PM PDT 24
Peak memory 224744 kb
Host smart-8418582d-4bf0-42d1-ba66-aad03ff868f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585255035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.585255035
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.1608028582
Short name T412
Test name
Test status
Simulation time 36610407 ps
CPU time 0.79 seconds
Started Jul 24 05:54:45 PM PDT 24
Finished Jul 24 05:54:46 PM PDT 24
Peak memory 204996 kb
Host smart-0905bf45-8a62-4f45-85db-a7ccf282b846
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608028582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
1608028582
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.3242437804
Short name T630
Test name
Test status
Simulation time 1626231692 ps
CPU time 6.45 seconds
Started Jul 24 05:54:45 PM PDT 24
Finished Jul 24 05:54:51 PM PDT 24
Peak memory 232820 kb
Host smart-8ceffbff-fd33-425c-9c0c-15a9d7105a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242437804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.3242437804
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.3795680207
Short name T519
Test name
Test status
Simulation time 17263705 ps
CPU time 0.75 seconds
Started Jul 24 05:54:43 PM PDT 24
Finished Jul 24 05:54:44 PM PDT 24
Peak memory 205692 kb
Host smart-f9d009ab-94ca-4da8-ae6f-c952a174dcda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795680207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.3795680207
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.695282651
Short name T257
Test name
Test status
Simulation time 199228844432 ps
CPU time 249.18 seconds
Started Jul 24 05:54:39 PM PDT 24
Finished Jul 24 05:58:48 PM PDT 24
Peak memory 251736 kb
Host smart-8508a63d-3bad-45ec-abc8-48a1635c28d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695282651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.695282651
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.3889599448
Short name T197
Test name
Test status
Simulation time 83648713067 ps
CPU time 265.48 seconds
Started Jul 24 05:54:40 PM PDT 24
Finished Jul 24 05:59:06 PM PDT 24
Peak memory 265756 kb
Host smart-b08af0f3-ed52-440e-8597-ed74755d3bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889599448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.3889599448
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.1477527361
Short name T45
Test name
Test status
Simulation time 37886693591 ps
CPU time 55.97 seconds
Started Jul 24 05:54:45 PM PDT 24
Finished Jul 24 05:55:41 PM PDT 24
Peak memory 232992 kb
Host smart-bdbd30f3-481f-4472-a6d2-21918fb20b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477527361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.1477527361
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.3691879401
Short name T125
Test name
Test status
Simulation time 1325399168 ps
CPU time 22.44 seconds
Started Jul 24 05:54:41 PM PDT 24
Finished Jul 24 05:55:04 PM PDT 24
Peak memory 232864 kb
Host smart-a5b17acf-1bed-4c3d-8bbe-dd7bafedf5c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691879401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.3691879401
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.1324656503
Short name T208
Test name
Test status
Simulation time 12920804219 ps
CPU time 113.2 seconds
Started Jul 24 05:54:43 PM PDT 24
Finished Jul 24 05:56:36 PM PDT 24
Peak memory 249340 kb
Host smart-fd39462c-6263-41a9-9e87-0d35261c8ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324656503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmd
s.1324656503
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_intercept.2525726577
Short name T770
Test name
Test status
Simulation time 204609654 ps
CPU time 2.3 seconds
Started Jul 24 05:54:40 PM PDT 24
Finished Jul 24 05:54:43 PM PDT 24
Peak memory 232484 kb
Host smart-0bffcf25-6d5f-4de9-8830-a06d51765006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525726577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.2525726577
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.4122580905
Short name T50
Test name
Test status
Simulation time 526820245 ps
CPU time 4.53 seconds
Started Jul 24 05:54:41 PM PDT 24
Finished Jul 24 05:54:46 PM PDT 24
Peak memory 232908 kb
Host smart-bfeaf8e7-cf65-438f-80e1-524eea33f26f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122580905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.4122580905
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.3400377722
Short name T547
Test name
Test status
Simulation time 1613503593 ps
CPU time 6.07 seconds
Started Jul 24 05:54:38 PM PDT 24
Finished Jul 24 05:54:44 PM PDT 24
Peak memory 224668 kb
Host smart-bf8a97ba-4f0c-44ac-b1ab-916a2cb0c820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400377722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.3400377722
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.2547038160
Short name T636
Test name
Test status
Simulation time 66311154 ps
CPU time 2.92 seconds
Started Jul 24 05:54:39 PM PDT 24
Finished Jul 24 05:54:42 PM PDT 24
Peak memory 232852 kb
Host smart-490e28bb-682c-4d45-893d-019082280467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547038160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.2547038160
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.2179524258
Short name T389
Test name
Test status
Simulation time 267321988 ps
CPU time 6.48 seconds
Started Jul 24 05:54:44 PM PDT 24
Finished Jul 24 05:54:51 PM PDT 24
Peak memory 223288 kb
Host smart-aa9c0edc-850f-4f35-804c-3aaf7c4d3fb4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2179524258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.2179524258
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.63140826
Short name T249
Test name
Test status
Simulation time 5573898708 ps
CPU time 45.84 seconds
Started Jul 24 05:54:39 PM PDT 24
Finished Jul 24 05:55:25 PM PDT 24
Peak memory 252020 kb
Host smart-86b0b9d0-632b-4d27-bb66-40d3560ec08e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63140826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stress
_all.63140826
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.777492387
Short name T586
Test name
Test status
Simulation time 8931759617 ps
CPU time 28.12 seconds
Started Jul 24 05:54:42 PM PDT 24
Finished Jul 24 05:55:10 PM PDT 24
Peak memory 216452 kb
Host smart-d3b26cab-a9a1-40ce-9678-928583caea7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777492387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.777492387
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.733591080
Short name T908
Test name
Test status
Simulation time 22006321373 ps
CPU time 11.54 seconds
Started Jul 24 05:54:40 PM PDT 24
Finished Jul 24 05:54:52 PM PDT 24
Peak memory 216596 kb
Host smart-9ddf06a1-2e2b-4294-8221-1344e63287c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733591080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.733591080
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.3380517935
Short name T721
Test name
Test status
Simulation time 171298383 ps
CPU time 2.13 seconds
Started Jul 24 05:54:40 PM PDT 24
Finished Jul 24 05:54:42 PM PDT 24
Peak memory 216376 kb
Host smart-21447f82-4ec2-4346-9852-22fa6ed7f272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380517935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.3380517935
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.2003664292
Short name T350
Test name
Test status
Simulation time 118483338 ps
CPU time 0.9 seconds
Started Jul 24 05:54:43 PM PDT 24
Finished Jul 24 05:54:44 PM PDT 24
Peak memory 206164 kb
Host smart-e16b8b3a-a228-42ef-a248-ae6cc099e72e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003664292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.2003664292
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.239977662
Short name T222
Test name
Test status
Simulation time 5626848474 ps
CPU time 12.53 seconds
Started Jul 24 05:54:39 PM PDT 24
Finished Jul 24 05:54:52 PM PDT 24
Peak memory 241108 kb
Host smart-e09666cc-845a-4113-ad81-75c865d14bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239977662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.239977662
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.1474669922
Short name T482
Test name
Test status
Simulation time 23379254 ps
CPU time 0.74 seconds
Started Jul 24 05:54:46 PM PDT 24
Finished Jul 24 05:54:47 PM PDT 24
Peak memory 205008 kb
Host smart-9f68fbf3-eb6a-4a22-b4c8-3e55d6d114a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474669922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
1474669922
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.3155516203
Short name T364
Test name
Test status
Simulation time 2303410249 ps
CPU time 7.02 seconds
Started Jul 24 05:54:47 PM PDT 24
Finished Jul 24 05:54:54 PM PDT 24
Peak memory 232944 kb
Host smart-1ae8edda-0139-4610-a50d-e0dfed961d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155516203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.3155516203
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.1493090110
Short name T333
Test name
Test status
Simulation time 25257943 ps
CPU time 0.82 seconds
Started Jul 24 05:54:46 PM PDT 24
Finished Jul 24 05:54:47 PM PDT 24
Peak memory 206768 kb
Host smart-8f76408a-f5bf-4b24-a2ed-dcd578e5ea54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493090110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.1493090110
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.113408773
Short name T240
Test name
Test status
Simulation time 3522144965 ps
CPU time 37.97 seconds
Started Jul 24 05:54:45 PM PDT 24
Finished Jul 24 05:55:24 PM PDT 24
Peak memory 253040 kb
Host smart-9a6038b2-78d8-46df-8dcb-bf38a5647c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113408773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.113408773
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.2552424657
Short name T76
Test name
Test status
Simulation time 2621679673 ps
CPU time 71.59 seconds
Started Jul 24 05:54:56 PM PDT 24
Finished Jul 24 05:56:08 PM PDT 24
Peak memory 254692 kb
Host smart-cdfb337a-c32b-487b-855c-fee106ecfff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552424657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.2552424657
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.3616475477
Short name T43
Test name
Test status
Simulation time 8584276166 ps
CPU time 127.45 seconds
Started Jul 24 05:54:57 PM PDT 24
Finished Jul 24 05:57:04 PM PDT 24
Peak memory 255488 kb
Host smart-2fd67463-daf7-4ba4-9872-c3283a2e8f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616475477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.3616475477
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.316621847
Short name T431
Test name
Test status
Simulation time 678659150 ps
CPU time 14.4 seconds
Started Jul 24 05:54:46 PM PDT 24
Finished Jul 24 05:55:01 PM PDT 24
Peak memory 224776 kb
Host smart-4ee3e779-5437-4be8-b391-37eec83e6efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316621847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.316621847
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.1825726783
Short name T621
Test name
Test status
Simulation time 35639476 ps
CPU time 0.75 seconds
Started Jul 24 05:54:47 PM PDT 24
Finished Jul 24 05:54:48 PM PDT 24
Peak memory 215892 kb
Host smart-106e3c80-2daa-4205-9168-79e9d7725b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825726783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmd
s.1825726783
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_intercept.4003218833
Short name T399
Test name
Test status
Simulation time 60449509 ps
CPU time 3.03 seconds
Started Jul 24 05:54:46 PM PDT 24
Finished Jul 24 05:54:49 PM PDT 24
Peak memory 232828 kb
Host smart-ab9ecf25-b1cd-47a3-94fe-4cb41437687e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003218833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.4003218833
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.788537023
Short name T833
Test name
Test status
Simulation time 3930255567 ps
CPU time 24.13 seconds
Started Jul 24 05:54:47 PM PDT 24
Finished Jul 24 05:55:11 PM PDT 24
Peak memory 234272 kb
Host smart-6f61b76b-2cd0-4aa0-b17f-60927521f7ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788537023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.788537023
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.3822352493
Short name T573
Test name
Test status
Simulation time 84752437 ps
CPU time 2.8 seconds
Started Jul 24 05:54:45 PM PDT 24
Finished Jul 24 05:54:48 PM PDT 24
Peak memory 232880 kb
Host smart-d8585cf3-c331-40f5-8643-037f02624c67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822352493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.3822352493
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.2135705640
Short name T702
Test name
Test status
Simulation time 5913727576 ps
CPU time 22.43 seconds
Started Jul 24 05:54:45 PM PDT 24
Finished Jul 24 05:55:07 PM PDT 24
Peak memory 224772 kb
Host smart-e839961e-071c-4a99-aea8-db75c5b04f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135705640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.2135705640
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.1485818931
Short name T869
Test name
Test status
Simulation time 32842493760 ps
CPU time 19.3 seconds
Started Jul 24 05:54:46 PM PDT 24
Finished Jul 24 05:55:06 PM PDT 24
Peak memory 223344 kb
Host smart-06da3051-9bec-4bee-a20e-d556e26a65dc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1485818931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.1485818931
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.915538390
Short name T151
Test name
Test status
Simulation time 185126714754 ps
CPU time 606.03 seconds
Started Jul 24 05:54:48 PM PDT 24
Finished Jul 24 06:04:55 PM PDT 24
Peak memory 282164 kb
Host smart-269f182b-7122-4944-91d2-b7ce7263e619
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915538390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stres
s_all.915538390
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.3985733810
Short name T305
Test name
Test status
Simulation time 1369013738 ps
CPU time 15.73 seconds
Started Jul 24 05:54:49 PM PDT 24
Finished Jul 24 05:55:05 PM PDT 24
Peak memory 216656 kb
Host smart-0fa63f5d-4e59-4cf0-a416-b6a86d477f6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985733810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.3985733810
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.2629331272
Short name T442
Test name
Test status
Simulation time 7780203511 ps
CPU time 7 seconds
Started Jul 24 05:54:46 PM PDT 24
Finished Jul 24 05:54:53 PM PDT 24
Peak memory 216408 kb
Host smart-e00bdb0a-3fec-41fe-a6be-03800a8077de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629331272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.2629331272
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.3697444245
Short name T891
Test name
Test status
Simulation time 92551356 ps
CPU time 1.49 seconds
Started Jul 24 05:54:45 PM PDT 24
Finished Jul 24 05:54:47 PM PDT 24
Peak memory 216468 kb
Host smart-5956f704-1c26-40eb-a064-228be2650e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697444245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.3697444245
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.3041711804
Short name T87
Test name
Test status
Simulation time 271666735 ps
CPU time 0.85 seconds
Started Jul 24 05:54:47 PM PDT 24
Finished Jul 24 05:54:48 PM PDT 24
Peak memory 207120 kb
Host smart-3f424ca6-cf77-4dcb-9f53-a89357c1dd45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041711804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.3041711804
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.593597214
Short name T723
Test name
Test status
Simulation time 2841266236 ps
CPU time 10.78 seconds
Started Jul 24 05:54:46 PM PDT 24
Finished Jul 24 05:54:57 PM PDT 24
Peak memory 232920 kb
Host smart-0ebda034-9316-443c-8720-d6021f19d578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593597214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.593597214
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.3152069703
Short name T834
Test name
Test status
Simulation time 6782352644 ps
CPU time 7.28 seconds
Started Jul 24 05:54:49 PM PDT 24
Finished Jul 24 05:54:57 PM PDT 24
Peak memory 232916 kb
Host smart-e7f12381-2a74-4ddb-a345-680b0f0feb4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152069703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.3152069703
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.1744048387
Short name T575
Test name
Test status
Simulation time 16315598 ps
CPU time 0.72 seconds
Started Jul 24 05:54:43 PM PDT 24
Finished Jul 24 05:54:44 PM PDT 24
Peak memory 205688 kb
Host smart-88b24ebe-a7e3-445c-ae65-187f95795135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744048387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.1744048387
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.563706599
Short name T678
Test name
Test status
Simulation time 2643694314 ps
CPU time 33.82 seconds
Started Jul 24 05:55:00 PM PDT 24
Finished Jul 24 05:55:34 PM PDT 24
Peak memory 256828 kb
Host smart-baadc8fd-c646-499f-be86-a74a966c57cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563706599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.563706599
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.3091361497
Short name T928
Test name
Test status
Simulation time 17766708385 ps
CPU time 157.53 seconds
Started Jul 24 05:54:56 PM PDT 24
Finished Jul 24 05:57:34 PM PDT 24
Peak memory 257528 kb
Host smart-6daa85b9-35d3-4d96-a5ab-80574b4539ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091361497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.3091361497
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.3373101941
Short name T290
Test name
Test status
Simulation time 2611826058 ps
CPU time 13.02 seconds
Started Jul 24 05:54:51 PM PDT 24
Finished Jul 24 05:55:04 PM PDT 24
Peak memory 232872 kb
Host smart-e4d2015e-c9b9-403f-acae-07dff59c63cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373101941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.3373101941
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.702795782
Short name T882
Test name
Test status
Simulation time 23688856133 ps
CPU time 83.99 seconds
Started Jul 24 05:54:56 PM PDT 24
Finished Jul 24 05:56:20 PM PDT 24
Peak memory 235812 kb
Host smart-77351e8b-9a7b-4525-9918-7603630edd17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702795782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmds
.702795782
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_intercept.2446392921
Short name T594
Test name
Test status
Simulation time 587907032 ps
CPU time 5.67 seconds
Started Jul 24 05:54:56 PM PDT 24
Finished Jul 24 05:55:02 PM PDT 24
Peak memory 232892 kb
Host smart-ffe2bc4d-2c05-4632-9239-7bcf56df60c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446392921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.2446392921
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.3961115489
Short name T985
Test name
Test status
Simulation time 19337727485 ps
CPU time 102.42 seconds
Started Jul 24 05:54:51 PM PDT 24
Finished Jul 24 05:56:33 PM PDT 24
Peak memory 224796 kb
Host smart-b79784e1-ca75-4b61-bfb3-18219e571690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961115489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.3961115489
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.931184763
Short name T614
Test name
Test status
Simulation time 423723756 ps
CPU time 5.22 seconds
Started Jul 24 05:54:48 PM PDT 24
Finished Jul 24 05:54:54 PM PDT 24
Peak memory 228976 kb
Host smart-80554242-afd0-4aeb-b5f2-149d13fb7137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931184763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swap
.931184763
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.2240217725
Short name T918
Test name
Test status
Simulation time 1902529759 ps
CPU time 9.05 seconds
Started Jul 24 05:54:56 PM PDT 24
Finished Jul 24 05:55:05 PM PDT 24
Peak memory 235868 kb
Host smart-aa50d448-256c-4dad-a8bb-fa85e41f7f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240217725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.2240217725
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.1636545605
Short name T139
Test name
Test status
Simulation time 2205970579 ps
CPU time 12 seconds
Started Jul 24 05:54:53 PM PDT 24
Finished Jul 24 05:55:05 PM PDT 24
Peak memory 219080 kb
Host smart-7fb62c68-6609-41da-ab87-ffd2aafcd482
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1636545605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.1636545605
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.4196031491
Short name T7
Test name
Test status
Simulation time 196410450 ps
CPU time 1.07 seconds
Started Jul 24 05:54:50 PM PDT 24
Finished Jul 24 05:54:51 PM PDT 24
Peak memory 207240 kb
Host smart-4c7e46e5-bad2-404a-9843-291e58f3397a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196031491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.4196031491
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.1943157480
Short name T926
Test name
Test status
Simulation time 3290404734 ps
CPU time 28.31 seconds
Started Jul 24 05:54:56 PM PDT 24
Finished Jul 24 05:55:24 PM PDT 24
Peak memory 216556 kb
Host smart-78ebd4d1-fc02-4234-b677-eab1179da379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943157480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.1943157480
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.3538669874
Short name T359
Test name
Test status
Simulation time 10887948353 ps
CPU time 9.67 seconds
Started Jul 24 05:54:46 PM PDT 24
Finished Jul 24 05:54:56 PM PDT 24
Peak memory 216468 kb
Host smart-ff0b84d4-7b75-4bac-9c82-8e0a9f5d469b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538669874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.3538669874
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.2776216004
Short name T720
Test name
Test status
Simulation time 13278878 ps
CPU time 0.7 seconds
Started Jul 24 05:54:46 PM PDT 24
Finished Jul 24 05:54:46 PM PDT 24
Peak memory 205740 kb
Host smart-6dc07ef8-13b1-48c7-acfb-51c2ff49d6a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776216004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.2776216004
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.1872186906
Short name T962
Test name
Test status
Simulation time 96098425 ps
CPU time 0.87 seconds
Started Jul 24 05:54:48 PM PDT 24
Finished Jul 24 05:54:49 PM PDT 24
Peak memory 206136 kb
Host smart-31133a62-d6be-415f-916e-4a95d63659f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872186906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.1872186906
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.4204115531
Short name T711
Test name
Test status
Simulation time 7856361940 ps
CPU time 12.45 seconds
Started Jul 24 05:54:51 PM PDT 24
Finished Jul 24 05:55:04 PM PDT 24
Peak memory 234276 kb
Host smart-98e46a06-c9f0-4244-bcd5-0643e9d894fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204115531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.4204115531
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.1216477003
Short name T735
Test name
Test status
Simulation time 10911079 ps
CPU time 0.71 seconds
Started Jul 24 05:55:00 PM PDT 24
Finished Jul 24 05:55:01 PM PDT 24
Peak memory 205656 kb
Host smart-628d9e8a-24d5-4f9d-b58a-ff02ff5f81a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216477003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
1216477003
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.4189015424
Short name T362
Test name
Test status
Simulation time 1242288244 ps
CPU time 4.25 seconds
Started Jul 24 05:54:53 PM PDT 24
Finished Jul 24 05:54:57 PM PDT 24
Peak memory 232876 kb
Host smart-8573bed7-c777-4708-8a5b-0def30333d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189015424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.4189015424
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.2912043110
Short name T598
Test name
Test status
Simulation time 123452079 ps
CPU time 0.83 seconds
Started Jul 24 05:54:53 PM PDT 24
Finished Jul 24 05:54:54 PM PDT 24
Peak memory 206752 kb
Host smart-cb796095-2bcb-41f0-bdcd-ad84e7655b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912043110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.2912043110
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.2482305419
Short name T607
Test name
Test status
Simulation time 2027821089 ps
CPU time 12.46 seconds
Started Jul 24 05:54:59 PM PDT 24
Finished Jul 24 05:55:12 PM PDT 24
Peak memory 241092 kb
Host smart-d0088a1c-f008-4e53-a886-a38e8851d21d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482305419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.2482305419
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.3425693951
Short name T214
Test name
Test status
Simulation time 9699517366 ps
CPU time 86.57 seconds
Started Jul 24 05:54:51 PM PDT 24
Finished Jul 24 05:56:17 PM PDT 24
Peak memory 249408 kb
Host smart-250a2438-c567-4444-8555-ccef95ab59b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425693951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.3425693951
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.435736509
Short name T609
Test name
Test status
Simulation time 76782642438 ps
CPU time 144.97 seconds
Started Jul 24 05:54:51 PM PDT 24
Finished Jul 24 05:57:16 PM PDT 24
Peak memory 251904 kb
Host smart-631aeaa0-f53b-4763-bd04-513bab53b61d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435736509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idle
.435736509
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.4206765191
Short name T776
Test name
Test status
Simulation time 16096375850 ps
CPU time 61.39 seconds
Started Jul 24 05:54:59 PM PDT 24
Finished Jul 24 05:56:01 PM PDT 24
Peak memory 249356 kb
Host smart-8201f188-970a-44d1-88f5-e82a4765c5a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206765191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.4206765191
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.2157114879
Short name T241
Test name
Test status
Simulation time 9101929009 ps
CPU time 63.54 seconds
Started Jul 24 05:55:00 PM PDT 24
Finished Jul 24 05:56:03 PM PDT 24
Peak memory 265488 kb
Host smart-d410e77d-6409-4699-a88d-cf29395f2de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157114879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmd
s.2157114879
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/18.spi_device_intercept.4147250582
Short name T252
Test name
Test status
Simulation time 3311598629 ps
CPU time 21.1 seconds
Started Jul 24 05:54:55 PM PDT 24
Finished Jul 24 05:55:16 PM PDT 24
Peak memory 232884 kb
Host smart-b8a95a72-54d0-4cab-b676-a1cc7639eeae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147250582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.4147250582
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.208877837
Short name T468
Test name
Test status
Simulation time 949167192 ps
CPU time 7.56 seconds
Started Jul 24 05:54:50 PM PDT 24
Finished Jul 24 05:54:58 PM PDT 24
Peak memory 224724 kb
Host smart-4f2104d5-ab8d-4465-8e5e-7a58c2695fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208877837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.208877837
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.898964740
Short name T795
Test name
Test status
Simulation time 461797589 ps
CPU time 5.75 seconds
Started Jul 24 05:54:50 PM PDT 24
Finished Jul 24 05:54:56 PM PDT 24
Peak memory 232892 kb
Host smart-540df6c6-2393-4991-93e3-4e3e25dde44e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898964740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swap
.898964740
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.1858417423
Short name T110
Test name
Test status
Simulation time 157804370 ps
CPU time 2.94 seconds
Started Jul 24 05:54:52 PM PDT 24
Finished Jul 24 05:54:55 PM PDT 24
Peak memory 232848 kb
Host smart-3ccbdbb3-7cc8-46ed-b116-2e41b1f09260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858417423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.1858417423
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.3290289879
Short name T509
Test name
Test status
Simulation time 7450793690 ps
CPU time 17.99 seconds
Started Jul 24 05:54:53 PM PDT 24
Finished Jul 24 05:55:11 PM PDT 24
Peak memory 222268 kb
Host smart-a6561816-1c42-4e15-8e99-55ae93de7f14
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3290289879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.3290289879
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.3107517912
Short name T27
Test name
Test status
Simulation time 69387164 ps
CPU time 1.24 seconds
Started Jul 24 05:55:01 PM PDT 24
Finished Jul 24 05:55:02 PM PDT 24
Peak memory 207944 kb
Host smart-38ef38d3-6a6f-4a9d-8392-ed4450e7bdd5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107517912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.3107517912
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.2044669616
Short name T708
Test name
Test status
Simulation time 3228100470 ps
CPU time 3.11 seconds
Started Jul 24 05:55:00 PM PDT 24
Finished Jul 24 05:55:03 PM PDT 24
Peak memory 216456 kb
Host smart-aae74ecc-001c-49da-aebb-0967d696c453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044669616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.2044669616
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.3939806826
Short name T625
Test name
Test status
Simulation time 4966147617 ps
CPU time 4.87 seconds
Started Jul 24 05:54:50 PM PDT 24
Finished Jul 24 05:54:55 PM PDT 24
Peak memory 216496 kb
Host smart-d51b1d83-8a1b-4c6f-b528-0e05af0f2b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939806826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.3939806826
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.446608526
Short name T885
Test name
Test status
Simulation time 107062679 ps
CPU time 1.21 seconds
Started Jul 24 05:54:58 PM PDT 24
Finished Jul 24 05:54:59 PM PDT 24
Peak memory 216588 kb
Host smart-3ed8d749-4df4-4610-93f1-4365117696f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446608526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.446608526
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.658101248
Short name T731
Test name
Test status
Simulation time 67865807 ps
CPU time 0.86 seconds
Started Jul 24 05:54:54 PM PDT 24
Finished Jul 24 05:54:55 PM PDT 24
Peak memory 206436 kb
Host smart-1b5e502d-3b0e-4fdc-844b-a732b8759a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658101248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.658101248
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.1005684927
Short name T637
Test name
Test status
Simulation time 673426861 ps
CPU time 3.48 seconds
Started Jul 24 05:54:54 PM PDT 24
Finished Jul 24 05:54:58 PM PDT 24
Peak memory 232864 kb
Host smart-4ad8b0f3-fce2-4fe9-90f8-206845cbea58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005684927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.1005684927
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.551935318
Short name T645
Test name
Test status
Simulation time 36814964 ps
CPU time 0.8 seconds
Started Jul 24 05:55:02 PM PDT 24
Finished Jul 24 05:55:03 PM PDT 24
Peak memory 205576 kb
Host smart-16b5a06f-6d8c-463e-a1ed-ebc320686a19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551935318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.551935318
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.2137675137
Short name T184
Test name
Test status
Simulation time 25173528053 ps
CPU time 20.38 seconds
Started Jul 24 05:55:01 PM PDT 24
Finished Jul 24 05:55:22 PM PDT 24
Peak memory 224744 kb
Host smart-d9d7feb6-69cb-41db-9a04-ca79252f054e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137675137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.2137675137
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.677489419
Short name T512
Test name
Test status
Simulation time 24964686 ps
CPU time 0.82 seconds
Started Jul 24 05:55:01 PM PDT 24
Finished Jul 24 05:55:02 PM PDT 24
Peak memory 207052 kb
Host smart-9216ea66-a19b-4a62-a2e1-e25636c47e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677489419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.677489419
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.2004968747
Short name T72
Test name
Test status
Simulation time 34327115357 ps
CPU time 162.84 seconds
Started Jul 24 05:55:00 PM PDT 24
Finished Jul 24 05:57:43 PM PDT 24
Peak memory 263720 kb
Host smart-02309212-fdda-4300-9548-7e970e78d85e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004968747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.2004968747
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.847322006
Short name T626
Test name
Test status
Simulation time 17084282625 ps
CPU time 59.06 seconds
Started Jul 24 05:54:57 PM PDT 24
Finished Jul 24 05:55:56 PM PDT 24
Peak memory 224764 kb
Host smart-877b3d84-636f-45c9-94e9-e4e4d69275f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847322006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.847322006
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.2393834818
Short name T696
Test name
Test status
Simulation time 10261841781 ps
CPU time 46.57 seconds
Started Jul 24 05:54:57 PM PDT 24
Finished Jul 24 05:55:44 PM PDT 24
Peak memory 250396 kb
Host smart-c069f756-c1ff-4a23-9bfc-9f71d583accc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393834818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.2393834818
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.349596654
Short name T513
Test name
Test status
Simulation time 51691767 ps
CPU time 4.48 seconds
Started Jul 24 05:55:02 PM PDT 24
Finished Jul 24 05:55:06 PM PDT 24
Peak memory 232944 kb
Host smart-5bad39d1-9d47-4303-a03d-524a6fb40886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349596654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.349596654
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.3558227804
Short name T569
Test name
Test status
Simulation time 52220237 ps
CPU time 0.76 seconds
Started Jul 24 05:55:03 PM PDT 24
Finished Jul 24 05:55:04 PM PDT 24
Peak memory 215904 kb
Host smart-4db04687-bfea-42d8-9c72-3ed530816cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558227804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmd
s.3558227804
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_intercept.3597468818
Short name T893
Test name
Test status
Simulation time 2788987901 ps
CPU time 31.39 seconds
Started Jul 24 05:54:59 PM PDT 24
Finished Jul 24 05:55:31 PM PDT 24
Peak memory 228972 kb
Host smart-6a92f6f2-c65c-40f1-b1ce-29d69f3340a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597468818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.3597468818
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.1579200153
Short name T673
Test name
Test status
Simulation time 17325883019 ps
CPU time 37.46 seconds
Started Jul 24 05:54:59 PM PDT 24
Finished Jul 24 05:55:36 PM PDT 24
Peak memory 232924 kb
Host smart-914c43a3-f285-4600-8692-2de8cd84ff01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579200153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.1579200153
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.2682770669
Short name T832
Test name
Test status
Simulation time 283792021 ps
CPU time 2.23 seconds
Started Jul 24 05:54:58 PM PDT 24
Finished Jul 24 05:55:00 PM PDT 24
Peak memory 223188 kb
Host smart-377932a0-743e-4282-9414-98965101610b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682770669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.2682770669
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.3103305936
Short name T432
Test name
Test status
Simulation time 500739204 ps
CPU time 2.86 seconds
Started Jul 24 05:55:02 PM PDT 24
Finished Jul 24 05:55:05 PM PDT 24
Peak memory 224656 kb
Host smart-1deb85d9-cc39-4345-bf88-d73884ea551a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103305936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.3103305936
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.1096999257
Short name T813
Test name
Test status
Simulation time 2823789902 ps
CPU time 4.29 seconds
Started Jul 24 05:55:00 PM PDT 24
Finished Jul 24 05:55:04 PM PDT 24
Peak memory 220528 kb
Host smart-4e7ff06a-b6b4-4287-955e-0daba0efcde4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1096999257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.1096999257
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.962036396
Short name T439
Test name
Test status
Simulation time 20133583125 ps
CPU time 27.74 seconds
Started Jul 24 05:54:57 PM PDT 24
Finished Jul 24 05:55:25 PM PDT 24
Peak memory 220448 kb
Host smart-112654ee-3630-4f8d-849d-0b68e7d45917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962036396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.962036396
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.410029170
Short name T640
Test name
Test status
Simulation time 2178042911 ps
CPU time 6.62 seconds
Started Jul 24 05:55:00 PM PDT 24
Finished Jul 24 05:55:07 PM PDT 24
Peak memory 216448 kb
Host smart-ac7fc4cb-5eea-45a5-a586-7edd9372ff21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410029170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.410029170
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.3534609052
Short name T499
Test name
Test status
Simulation time 645671326 ps
CPU time 1.27 seconds
Started Jul 24 05:54:58 PM PDT 24
Finished Jul 24 05:55:00 PM PDT 24
Peak memory 208296 kb
Host smart-a684099d-689b-4aeb-be1c-beb2636d522c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534609052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.3534609052
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.718072146
Short name T86
Test name
Test status
Simulation time 82402866 ps
CPU time 0.8 seconds
Started Jul 24 05:54:59 PM PDT 24
Finished Jul 24 05:55:01 PM PDT 24
Peak memory 206116 kb
Host smart-a70021b8-deda-427c-9993-03c04024b05a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718072146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.718072146
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.512028802
Short name T469
Test name
Test status
Simulation time 33042170636 ps
CPU time 25.33 seconds
Started Jul 24 05:54:58 PM PDT 24
Finished Jul 24 05:55:24 PM PDT 24
Peak memory 224780 kb
Host smart-46bd8ba7-fadd-457f-87c6-54f33d02653c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512028802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.512028802
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.2222615463
Short name T786
Test name
Test status
Simulation time 16126785 ps
CPU time 0.76 seconds
Started Jul 24 05:53:57 PM PDT 24
Finished Jul 24 05:53:58 PM PDT 24
Peak memory 204948 kb
Host smart-41aad14d-43f5-4fe0-9234-2b4e29f3bf2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222615463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.2
222615463
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.219891049
Short name T952
Test name
Test status
Simulation time 454553916 ps
CPU time 5.31 seconds
Started Jul 24 05:53:57 PM PDT 24
Finished Jul 24 05:54:02 PM PDT 24
Peak memory 224700 kb
Host smart-5ef609e9-85be-4b59-bba2-d55f00f88f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219891049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.219891049
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.2805442884
Short name T964
Test name
Test status
Simulation time 47925472 ps
CPU time 0.8 seconds
Started Jul 24 05:53:59 PM PDT 24
Finished Jul 24 05:54:00 PM PDT 24
Peak memory 206728 kb
Host smart-20537802-4edb-4c52-81e5-5c69055470fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805442884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.2805442884
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.2014338669
Short name T281
Test name
Test status
Simulation time 113035339166 ps
CPU time 256.41 seconds
Started Jul 24 05:53:57 PM PDT 24
Finished Jul 24 05:58:14 PM PDT 24
Peak memory 255460 kb
Host smart-8302516d-6640-4505-aec1-ae074ba4d6b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014338669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.2014338669
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.3776587348
Short name T26
Test name
Test status
Simulation time 234940838201 ps
CPU time 238.23 seconds
Started Jul 24 05:53:56 PM PDT 24
Finished Jul 24 05:57:55 PM PDT 24
Peak memory 256916 kb
Host smart-0383dfa7-25dc-452c-928d-f09d100878ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776587348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.3776587348
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.2415956754
Short name T261
Test name
Test status
Simulation time 20905183317 ps
CPU time 91.78 seconds
Started Jul 24 05:53:59 PM PDT 24
Finished Jul 24 05:55:31 PM PDT 24
Peak memory 257036 kb
Host smart-e3bdec0b-b32d-4311-bce7-c4ddb3de6051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415956754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.2415956754
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.1446083838
Short name T293
Test name
Test status
Simulation time 2418445240 ps
CPU time 19.16 seconds
Started Jul 24 05:54:01 PM PDT 24
Finished Jul 24 05:54:20 PM PDT 24
Peak memory 224712 kb
Host smart-9c98d63c-ad7c-4075-9295-5eb90d08b290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446083838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.1446083838
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.760021884
Short name T92
Test name
Test status
Simulation time 11137110169 ps
CPU time 60.67 seconds
Started Jul 24 05:53:56 PM PDT 24
Finished Jul 24 05:54:57 PM PDT 24
Peak memory 257536 kb
Host smart-b03e4ebf-289f-4bd0-b0cc-f94c4407f88b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760021884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds.
760021884
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_intercept.4293739780
Short name T464
Test name
Test status
Simulation time 160465260 ps
CPU time 3.35 seconds
Started Jul 24 05:53:55 PM PDT 24
Finished Jul 24 05:53:59 PM PDT 24
Peak memory 232904 kb
Host smart-88f861e9-10da-4186-a16f-6c05d7e92d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293739780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.4293739780
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.1099150160
Short name T236
Test name
Test status
Simulation time 578641215 ps
CPU time 6.8 seconds
Started Jul 24 05:53:56 PM PDT 24
Finished Jul 24 05:54:03 PM PDT 24
Peak memory 240868 kb
Host smart-6a39985d-53c9-45a1-84dd-7d9d69ac9c85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099150160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.1099150160
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.1110473359
Short name T476
Test name
Test status
Simulation time 71865035993 ps
CPU time 24.49 seconds
Started Jul 24 05:53:59 PM PDT 24
Finished Jul 24 05:54:24 PM PDT 24
Peak memory 241056 kb
Host smart-30ff3475-6d2e-4a48-9167-b9077c5442b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110473359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.1110473359
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.4058069207
Short name T984
Test name
Test status
Simulation time 1140701575 ps
CPU time 8.84 seconds
Started Jul 24 05:53:59 PM PDT 24
Finished Jul 24 05:54:08 PM PDT 24
Peak memory 249764 kb
Host smart-37b9907a-31f4-48f8-a30b-1b045342b36f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058069207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.4058069207
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.1948945114
Short name T822
Test name
Test status
Simulation time 334547845 ps
CPU time 4.01 seconds
Started Jul 24 05:53:58 PM PDT 24
Finished Jul 24 05:54:02 PM PDT 24
Peak memory 223236 kb
Host smart-c6ce76fa-fe99-46a5-9704-d35c26cb016a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1948945114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.1948945114
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.1362655966
Short name T65
Test name
Test status
Simulation time 535054627 ps
CPU time 1.07 seconds
Started Jul 24 05:53:55 PM PDT 24
Finished Jul 24 05:53:56 PM PDT 24
Peak memory 236512 kb
Host smart-89d4b001-0f59-4b38-b969-abd79b44ad93
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362655966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.1362655966
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.502344110
Short name T29
Test name
Test status
Simulation time 146169954368 ps
CPU time 160.5 seconds
Started Jul 24 05:53:56 PM PDT 24
Finished Jul 24 05:56:37 PM PDT 24
Peak memory 249364 kb
Host smart-420fe229-5364-458c-b72d-c463b9cd1d85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502344110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stress
_all.502344110
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.4125630794
Short name T804
Test name
Test status
Simulation time 1073230059 ps
CPU time 18.05 seconds
Started Jul 24 05:53:56 PM PDT 24
Finished Jul 24 05:54:14 PM PDT 24
Peak memory 216476 kb
Host smart-ff465b04-779f-4453-9f75-a1cedb6fdc6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125630794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.4125630794
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.2855358138
Short name T543
Test name
Test status
Simulation time 2274608409 ps
CPU time 6.93 seconds
Started Jul 24 05:53:59 PM PDT 24
Finished Jul 24 05:54:06 PM PDT 24
Peak memory 216464 kb
Host smart-11fddf19-4b3a-4dfe-9252-602989b8e726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855358138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.2855358138
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.1073160448
Short name T954
Test name
Test status
Simulation time 75922385 ps
CPU time 1.2 seconds
Started Jul 24 05:53:58 PM PDT 24
Finished Jul 24 05:53:59 PM PDT 24
Peak memory 216260 kb
Host smart-d95bd0a8-d861-4959-bf1c-2e474fd587cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073160448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.1073160448
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.3557188673
Short name T311
Test name
Test status
Simulation time 13514043 ps
CPU time 0.71 seconds
Started Jul 24 05:53:57 PM PDT 24
Finished Jul 24 05:53:58 PM PDT 24
Peak memory 205628 kb
Host smart-cdb2649c-6bf5-443c-b69e-0be1f9c981ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557188673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.3557188673
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.2575712385
Short name T919
Test name
Test status
Simulation time 13658362673 ps
CPU time 12.91 seconds
Started Jul 24 05:53:58 PM PDT 24
Finished Jul 24 05:54:11 PM PDT 24
Peak memory 224772 kb
Host smart-57c93b93-8204-4c55-b1be-045a3a426f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575712385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.2575712385
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.3667307398
Short name T403
Test name
Test status
Simulation time 14043189 ps
CPU time 0.76 seconds
Started Jul 24 05:55:05 PM PDT 24
Finished Jul 24 05:55:06 PM PDT 24
Peak memory 205552 kb
Host smart-9e51762b-cdf1-43fd-9468-fb0359ba6033
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667307398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
3667307398
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.2890635756
Short name T689
Test name
Test status
Simulation time 1933853095 ps
CPU time 15.07 seconds
Started Jul 24 05:55:00 PM PDT 24
Finished Jul 24 05:55:15 PM PDT 24
Peak memory 232888 kb
Host smart-fb054620-de6e-494a-9195-5a5bbafae21f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890635756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.2890635756
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.3805484392
Short name T522
Test name
Test status
Simulation time 16994581 ps
CPU time 0.78 seconds
Started Jul 24 05:54:58 PM PDT 24
Finished Jul 24 05:54:59 PM PDT 24
Peak memory 206772 kb
Host smart-dc68ac84-ceea-4bc1-8940-a30e0e295d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805484392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.3805484392
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.2827195126
Short name T77
Test name
Test status
Simulation time 20268831370 ps
CPU time 159.12 seconds
Started Jul 24 05:55:03 PM PDT 24
Finished Jul 24 05:57:42 PM PDT 24
Peak memory 252660 kb
Host smart-bb5f05be-b4eb-4a19-8278-755a781614f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827195126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.2827195126
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.928737755
Short name T303
Test name
Test status
Simulation time 2747993444 ps
CPU time 12.36 seconds
Started Jul 24 05:55:01 PM PDT 24
Finished Jul 24 05:55:14 PM PDT 24
Peak memory 217980 kb
Host smart-e28d8b7a-356e-4a33-aa7f-926170c9e978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928737755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.928737755
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.1271916626
Short name T852
Test name
Test status
Simulation time 53898239353 ps
CPU time 53.72 seconds
Started Jul 24 05:55:04 PM PDT 24
Finished Jul 24 05:55:58 PM PDT 24
Peak memory 249412 kb
Host smart-30cdd42a-a067-41d5-9438-282927c314bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271916626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.1271916626
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.3463432752
Short name T777
Test name
Test status
Simulation time 54558296657 ps
CPU time 48.09 seconds
Started Jul 24 05:55:04 PM PDT 24
Finished Jul 24 05:55:53 PM PDT 24
Peak memory 232980 kb
Host smart-67741f73-f175-47bd-a702-7bcfb6e2f502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463432752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.3463432752
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.1991454866
Short name T381
Test name
Test status
Simulation time 6651784338 ps
CPU time 46.87 seconds
Started Jul 24 05:55:05 PM PDT 24
Finished Jul 24 05:55:52 PM PDT 24
Peak memory 249344 kb
Host smart-cfbd2bb7-b086-4e08-85ac-58d8e5d5261a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991454866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmd
s.1991454866
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_intercept.2145831572
Short name T716
Test name
Test status
Simulation time 1585455631 ps
CPU time 10.35 seconds
Started Jul 24 05:55:01 PM PDT 24
Finished Jul 24 05:55:12 PM PDT 24
Peak memory 232860 kb
Host smart-815fea8e-1138-40fd-9085-61684dcf65f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145831572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.2145831572
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.1657464004
Short name T936
Test name
Test status
Simulation time 859718521 ps
CPU time 10.26 seconds
Started Jul 24 05:55:01 PM PDT 24
Finished Jul 24 05:55:11 PM PDT 24
Peak memory 240820 kb
Host smart-c2acb047-e5a5-499a-9fc3-271ef5e248f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657464004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.1657464004
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.2716028652
Short name T779
Test name
Test status
Simulation time 611198050 ps
CPU time 5.5 seconds
Started Jul 24 05:54:59 PM PDT 24
Finished Jul 24 05:55:05 PM PDT 24
Peak memory 224748 kb
Host smart-29b08ac8-e526-49ba-9343-fecd3a70944c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716028652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.2716028652
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.34720624
Short name T634
Test name
Test status
Simulation time 447339201 ps
CPU time 7.25 seconds
Started Jul 24 05:55:04 PM PDT 24
Finished Jul 24 05:55:12 PM PDT 24
Peak memory 240428 kb
Host smart-c8d20dd7-a03b-4c00-bc87-5aa8d6e0221f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34720624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.34720624
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.4149159791
Short name T516
Test name
Test status
Simulation time 4483096826 ps
CPU time 13.82 seconds
Started Jul 24 05:55:09 PM PDT 24
Finished Jul 24 05:55:23 PM PDT 24
Peak memory 222004 kb
Host smart-3ff32b6d-dc09-4058-802a-6acfe313e38b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4149159791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.4149159791
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.1153655246
Short name T46
Test name
Test status
Simulation time 24184868964 ps
CPU time 254.73 seconds
Started Jul 24 05:55:08 PM PDT 24
Finished Jul 24 05:59:23 PM PDT 24
Peak memory 253428 kb
Host smart-5e221634-f42a-41ee-a30f-e1b7e7f379ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153655246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.1153655246
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.3732085288
Short name T948
Test name
Test status
Simulation time 4729594979 ps
CPU time 13.32 seconds
Started Jul 24 05:55:00 PM PDT 24
Finished Jul 24 05:55:13 PM PDT 24
Peak memory 217624 kb
Host smart-7ea9ae56-e5a6-442b-a640-bd64c217d76b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732085288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.3732085288
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.1536936471
Short name T377
Test name
Test status
Simulation time 518399731 ps
CPU time 1.95 seconds
Started Jul 24 05:54:58 PM PDT 24
Finished Jul 24 05:55:00 PM PDT 24
Peak memory 208040 kb
Host smart-559673a1-d529-484d-8b74-b38372025a2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536936471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.1536936471
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.2160257718
Short name T428
Test name
Test status
Simulation time 37304186 ps
CPU time 0.68 seconds
Started Jul 24 05:54:59 PM PDT 24
Finished Jul 24 05:55:00 PM PDT 24
Peak memory 205768 kb
Host smart-6c8a8de1-0f77-4be6-8b0d-013867ec8f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160257718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.2160257718
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.2022363833
Short name T380
Test name
Test status
Simulation time 30963303 ps
CPU time 0.74 seconds
Started Jul 24 05:54:58 PM PDT 24
Finished Jul 24 05:54:59 PM PDT 24
Peak memory 206072 kb
Host smart-d470a627-d192-43ed-8f63-c264d9c64c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022363833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.2022363833
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.2129402458
Short name T74
Test name
Test status
Simulation time 28413710371 ps
CPU time 32.53 seconds
Started Jul 24 05:55:04 PM PDT 24
Finished Jul 24 05:55:37 PM PDT 24
Peak memory 241096 kb
Host smart-6021700f-2ea3-40dc-be65-965270965e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129402458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.2129402458
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.1487024038
Short name T709
Test name
Test status
Simulation time 12542005 ps
CPU time 0.76 seconds
Started Jul 24 05:55:04 PM PDT 24
Finished Jul 24 05:55:05 PM PDT 24
Peak memory 205592 kb
Host smart-9cb06204-3601-4f69-9548-058ae07a7bed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487024038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
1487024038
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.3664858403
Short name T375
Test name
Test status
Simulation time 4506203148 ps
CPU time 14.42 seconds
Started Jul 24 05:55:09 PM PDT 24
Finished Jul 24 05:55:23 PM PDT 24
Peak memory 232940 kb
Host smart-aeea9f59-f910-44f2-bfef-19f359148ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664858403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.3664858403
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.1799282362
Short name T867
Test name
Test status
Simulation time 29126742 ps
CPU time 0.74 seconds
Started Jul 24 05:55:04 PM PDT 24
Finished Jul 24 05:55:05 PM PDT 24
Peak memory 206020 kb
Host smart-0f8fe066-bd10-4c68-8a9c-5a94830081ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799282362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.1799282362
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.3393884361
Short name T216
Test name
Test status
Simulation time 145270561365 ps
CPU time 548.54 seconds
Started Jul 24 05:55:04 PM PDT 24
Finished Jul 24 06:04:13 PM PDT 24
Peak memory 264004 kb
Host smart-8cbf9414-d574-4908-967d-03fffd02021a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393884361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.3393884361
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.3390768033
Short name T1003
Test name
Test status
Simulation time 14702674612 ps
CPU time 67.05 seconds
Started Jul 24 05:55:02 PM PDT 24
Finished Jul 24 05:56:09 PM PDT 24
Peak memory 249400 kb
Host smart-1a7ffc07-6f04-4457-bd4f-09095f003862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390768033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.3390768033
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.290727428
Short name T266
Test name
Test status
Simulation time 24732125815 ps
CPU time 87.28 seconds
Started Jul 24 05:55:08 PM PDT 24
Finished Jul 24 05:56:36 PM PDT 24
Peak memory 255884 kb
Host smart-696a21d4-1675-46a9-a5a0-7af03842a7c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290727428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idle
.290727428
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.2682132373
Short name T672
Test name
Test status
Simulation time 451704862 ps
CPU time 2.7 seconds
Started Jul 24 05:55:04 PM PDT 24
Finished Jul 24 05:55:07 PM PDT 24
Peak memory 224660 kb
Host smart-6af318f9-d58f-47f0-8c0e-90fd94e60115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682132373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.2682132373
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.419515635
Short name T179
Test name
Test status
Simulation time 24985936200 ps
CPU time 172.69 seconds
Started Jul 24 05:55:04 PM PDT 24
Finished Jul 24 05:57:57 PM PDT 24
Peak memory 250068 kb
Host smart-feddf8e8-993e-4c64-a1d7-d9c79196d175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419515635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmds
.419515635
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_intercept.3000534931
Short name T849
Test name
Test status
Simulation time 187146622 ps
CPU time 4.25 seconds
Started Jul 24 05:55:02 PM PDT 24
Finished Jul 24 05:55:06 PM PDT 24
Peak memory 232912 kb
Host smart-8b7b07b3-bb93-440d-ae29-d27c37e977f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000534931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.3000534931
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.4226209585
Short name T355
Test name
Test status
Simulation time 2135222153 ps
CPU time 10.68 seconds
Started Jul 24 05:55:06 PM PDT 24
Finished Jul 24 05:55:16 PM PDT 24
Peak memory 232864 kb
Host smart-5895712b-ba90-4044-b3b4-ef0e5a5a37aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226209585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.4226209585
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.4061966249
Short name T213
Test name
Test status
Simulation time 3059231534 ps
CPU time 6.46 seconds
Started Jul 24 05:55:04 PM PDT 24
Finished Jul 24 05:55:10 PM PDT 24
Peak memory 224700 kb
Host smart-ea1f95f4-385b-4435-b54e-2bcf20515f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061966249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.4061966249
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.3211962371
Short name T865
Test name
Test status
Simulation time 2927973491 ps
CPU time 12.16 seconds
Started Jul 24 05:55:04 PM PDT 24
Finished Jul 24 05:55:17 PM PDT 24
Peak memory 232912 kb
Host smart-8ccbfab3-af53-4246-b613-8f792b29b667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211962371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.3211962371
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.2412268459
Short name T424
Test name
Test status
Simulation time 352679680 ps
CPU time 6.24 seconds
Started Jul 24 05:55:05 PM PDT 24
Finished Jul 24 05:55:11 PM PDT 24
Peak memory 220412 kb
Host smart-b34d7bb2-6b5d-4a5b-b435-a73625156cb4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2412268459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.2412268459
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.31127462
Short name T247
Test name
Test status
Simulation time 13816773406 ps
CPU time 104.21 seconds
Started Jul 24 05:55:05 PM PDT 24
Finished Jul 24 05:56:49 PM PDT 24
Peak memory 254380 kb
Host smart-a20b50b4-7218-4220-8232-fa3ee20f9036
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31127462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stress
_all.31127462
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.3598907712
Short name T963
Test name
Test status
Simulation time 1103217640 ps
CPU time 9.18 seconds
Started Jul 24 05:55:05 PM PDT 24
Finished Jul 24 05:55:15 PM PDT 24
Peak memory 216396 kb
Host smart-86763351-9fba-4998-bc40-00ab38639075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598907712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.3598907712
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.740669612
Short name T863
Test name
Test status
Simulation time 7021552880 ps
CPU time 10.04 seconds
Started Jul 24 05:55:11 PM PDT 24
Finished Jul 24 05:55:21 PM PDT 24
Peak memory 216520 kb
Host smart-c878124b-09bd-4689-aeea-acfa7d83c45e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740669612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.740669612
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.4162358909
Short name T323
Test name
Test status
Simulation time 129358385 ps
CPU time 0.95 seconds
Started Jul 24 05:55:03 PM PDT 24
Finished Jul 24 05:55:04 PM PDT 24
Peak memory 207168 kb
Host smart-47e16003-b80d-487e-b073-5011d6781ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162358909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.4162358909
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.1982761027
Short name T742
Test name
Test status
Simulation time 51635414 ps
CPU time 0.79 seconds
Started Jul 24 05:55:07 PM PDT 24
Finished Jul 24 05:55:08 PM PDT 24
Peak memory 206104 kb
Host smart-ab8f71db-ee4f-4486-946a-98be8434d96b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982761027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.1982761027
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.381353536
Short name T473
Test name
Test status
Simulation time 4722101038 ps
CPU time 9.6 seconds
Started Jul 24 05:55:07 PM PDT 24
Finished Jul 24 05:55:17 PM PDT 24
Peak memory 232892 kb
Host smart-ef971ab1-0219-41ac-bae2-8ce010bf05a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381353536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.381353536
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.2557998598
Short name T463
Test name
Test status
Simulation time 59834550 ps
CPU time 0.72 seconds
Started Jul 24 05:55:07 PM PDT 24
Finished Jul 24 05:55:08 PM PDT 24
Peak memory 205932 kb
Host smart-4f91a9a0-14e4-4c70-b0fe-0dec07b59921
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557998598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
2557998598
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.3013582881
Short name T732
Test name
Test status
Simulation time 1443062147 ps
CPU time 4.92 seconds
Started Jul 24 05:55:09 PM PDT 24
Finished Jul 24 05:55:14 PM PDT 24
Peak memory 224716 kb
Host smart-63397b4a-7ecf-4278-a3ce-9a545fe17fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013582881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.3013582881
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.1017530764
Short name T646
Test name
Test status
Simulation time 83847243 ps
CPU time 0.77 seconds
Started Jul 24 05:55:04 PM PDT 24
Finished Jul 24 05:55:05 PM PDT 24
Peak memory 207092 kb
Host smart-2fb18b82-d448-4f8a-b779-9332a2e10fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017530764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.1017530764
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.3631839152
Short name T204
Test name
Test status
Simulation time 5837531213 ps
CPU time 46.19 seconds
Started Jul 24 05:55:08 PM PDT 24
Finished Jul 24 05:55:54 PM PDT 24
Peak memory 222832 kb
Host smart-8859e3b4-ca5c-4fcd-b779-b8594e07f6d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631839152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.3631839152
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.3666266927
Short name T851
Test name
Test status
Simulation time 22296961708 ps
CPU time 116.3 seconds
Started Jul 24 05:55:09 PM PDT 24
Finished Jul 24 05:57:06 PM PDT 24
Peak memory 270280 kb
Host smart-5fa8a9d9-36b3-483b-aafd-31e3b1d6ad68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666266927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.3666266927
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.3883577251
Short name T559
Test name
Test status
Simulation time 176503002 ps
CPU time 5.71 seconds
Started Jul 24 05:55:10 PM PDT 24
Finished Jul 24 05:55:16 PM PDT 24
Peak memory 232808 kb
Host smart-e12a30f9-4d9d-4b5e-80ac-c53d1df0cfcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883577251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.3883577251
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.3363329400
Short name T774
Test name
Test status
Simulation time 215440580469 ps
CPU time 393.69 seconds
Started Jul 24 05:55:08 PM PDT 24
Finished Jul 24 06:01:42 PM PDT 24
Peak memory 265688 kb
Host smart-7e595510-6aae-47f4-9932-45e305f20631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363329400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmd
s.3363329400
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_intercept.1887964345
Short name T199
Test name
Test status
Simulation time 3847734042 ps
CPU time 11.45 seconds
Started Jul 24 05:55:06 PM PDT 24
Finished Jul 24 05:55:18 PM PDT 24
Peak memory 220048 kb
Host smart-6650fe53-0565-4abe-9899-f2c6a2a7e371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887964345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.1887964345
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.3068385088
Short name T534
Test name
Test status
Simulation time 14490577315 ps
CPU time 26.22 seconds
Started Jul 24 05:55:05 PM PDT 24
Finished Jul 24 05:55:32 PM PDT 24
Peak memory 239732 kb
Host smart-c75bb036-6f77-451f-83c1-17f69aef0e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068385088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.3068385088
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.2069214714
Short name T248
Test name
Test status
Simulation time 704214998 ps
CPU time 4.67 seconds
Started Jul 24 05:55:07 PM PDT 24
Finished Jul 24 05:55:12 PM PDT 24
Peak memory 224624 kb
Host smart-22d354cc-8f2a-4486-aa03-9376ed0961f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069214714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.2069214714
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.3282327476
Short name T458
Test name
Test status
Simulation time 2746979479 ps
CPU time 11.52 seconds
Started Jul 24 05:55:04 PM PDT 24
Finished Jul 24 05:55:16 PM PDT 24
Peak memory 232932 kb
Host smart-595fec20-fd1d-4d73-b0c1-9eb51f4d0c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282327476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.3282327476
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.1552627174
Short name T140
Test name
Test status
Simulation time 753169473 ps
CPU time 11.99 seconds
Started Jul 24 05:55:12 PM PDT 24
Finished Jul 24 05:55:24 PM PDT 24
Peak memory 223312 kb
Host smart-43d0efde-dbc5-4b9b-9bfc-c99404987782
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1552627174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.1552627174
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.3705263297
Short name T386
Test name
Test status
Simulation time 46418181 ps
CPU time 0.97 seconds
Started Jul 24 05:56:52 PM PDT 24
Finished Jul 24 05:56:53 PM PDT 24
Peak memory 207516 kb
Host smart-b9eba670-2bad-4495-b589-49b94ce70080
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705263297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.3705263297
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.1866441538
Short name T528
Test name
Test status
Simulation time 1231168356 ps
CPU time 4.48 seconds
Started Jul 24 05:55:08 PM PDT 24
Finished Jul 24 05:55:13 PM PDT 24
Peak memory 216380 kb
Host smart-c40f69f2-e079-4228-807a-99cc239175d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866441538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.1866441538
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.2291918041
Short name T461
Test name
Test status
Simulation time 7574456737 ps
CPU time 9.15 seconds
Started Jul 24 05:55:04 PM PDT 24
Finished Jul 24 05:55:13 PM PDT 24
Peak memory 216492 kb
Host smart-e4e6a552-d7c5-48cb-a83c-52bd8e1626c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291918041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.2291918041
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.1405955683
Short name T376
Test name
Test status
Simulation time 22363818 ps
CPU time 0.93 seconds
Started Jul 24 05:55:00 PM PDT 24
Finished Jul 24 05:55:01 PM PDT 24
Peak memory 207144 kb
Host smart-b015d9f2-7743-402a-a56a-ab2d4fd84979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405955683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.1405955683
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.2430178685
Short name T531
Test name
Test status
Simulation time 81082902 ps
CPU time 0.78 seconds
Started Jul 24 05:55:07 PM PDT 24
Finished Jul 24 05:55:07 PM PDT 24
Peak memory 206172 kb
Host smart-b6903311-957b-4e9b-aa98-d640c949712f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430178685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.2430178685
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.2425162565
Short name T451
Test name
Test status
Simulation time 1535688891 ps
CPU time 9.48 seconds
Started Jul 24 05:55:10 PM PDT 24
Finished Jul 24 05:55:20 PM PDT 24
Peak memory 232964 kb
Host smart-3b5fde13-ebbc-4c3e-b54b-b048c71b9cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425162565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.2425162565
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.904895362
Short name T326
Test name
Test status
Simulation time 41851080 ps
CPU time 0.73 seconds
Started Jul 24 05:55:13 PM PDT 24
Finished Jul 24 05:55:14 PM PDT 24
Peak memory 205608 kb
Host smart-1ab5fa1b-0968-4658-b35c-3bd60fc7ded7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904895362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.904895362
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.3366571760
Short name T691
Test name
Test status
Simulation time 200891923 ps
CPU time 2.91 seconds
Started Jul 24 05:55:13 PM PDT 24
Finished Jul 24 05:55:16 PM PDT 24
Peak memory 232940 kb
Host smart-61528a69-65cd-4f95-9415-e709c1156da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366571760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.3366571760
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.2089123941
Short name T387
Test name
Test status
Simulation time 63507709 ps
CPU time 0.78 seconds
Started Jul 24 05:55:11 PM PDT 24
Finished Jul 24 05:55:12 PM PDT 24
Peak memory 206016 kb
Host smart-045e2b8c-d218-4889-b143-8c8658950f55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089123941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.2089123941
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.2756939497
Short name T478
Test name
Test status
Simulation time 173111789692 ps
CPU time 196.42 seconds
Started Jul 24 05:55:12 PM PDT 24
Finished Jul 24 05:58:28 PM PDT 24
Peak memory 249408 kb
Host smart-14216814-f51a-411f-b9e4-f1fc9b2e5fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756939497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.2756939497
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.3220506549
Short name T80
Test name
Test status
Simulation time 15332560476 ps
CPU time 186.43 seconds
Started Jul 24 05:55:14 PM PDT 24
Finished Jul 24 05:58:20 PM PDT 24
Peak memory 255484 kb
Host smart-9ae8d202-77ea-4c2f-bd38-408d9f269eb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220506549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.3220506549
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.2261816702
Short name T809
Test name
Test status
Simulation time 414413310 ps
CPU time 10.12 seconds
Started Jul 24 05:55:12 PM PDT 24
Finished Jul 24 05:55:22 PM PDT 24
Peak memory 240984 kb
Host smart-5a721113-cd42-4500-80cf-46e129add26b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261816702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.2261816702
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.3336289411
Short name T457
Test name
Test status
Simulation time 1536249790 ps
CPU time 15.9 seconds
Started Jul 24 05:55:08 PM PDT 24
Finished Jul 24 05:55:24 PM PDT 24
Peak memory 232848 kb
Host smart-cca2465d-c180-4112-be8c-62ecf14748a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336289411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.3336289411
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.766349654
Short name T694
Test name
Test status
Simulation time 184478086074 ps
CPU time 359.86 seconds
Started Jul 24 05:55:12 PM PDT 24
Finished Jul 24 06:01:12 PM PDT 24
Peak memory 250888 kb
Host smart-11efcafe-0bd5-426a-8772-8573bde2dc69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766349654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmds
.766349654
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_intercept.2156858969
Short name T847
Test name
Test status
Simulation time 16154080222 ps
CPU time 36.26 seconds
Started Jul 24 05:55:08 PM PDT 24
Finished Jul 24 05:55:45 PM PDT 24
Peak memory 224660 kb
Host smart-e21b405d-b499-4cf7-9d1a-7793617dac37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156858969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.2156858969
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.2667305060
Short name T501
Test name
Test status
Simulation time 2126732779 ps
CPU time 14.72 seconds
Started Jul 24 05:55:12 PM PDT 24
Finished Jul 24 05:55:27 PM PDT 24
Peak memory 232888 kb
Host smart-a9cbeac5-7c91-4ee2-8a0d-ff8d1edd1d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667305060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.2667305060
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.4219001083
Short name T269
Test name
Test status
Simulation time 23258394101 ps
CPU time 35.22 seconds
Started Jul 24 05:55:08 PM PDT 24
Finished Jul 24 05:55:43 PM PDT 24
Peak memory 239148 kb
Host smart-76c28f20-ada3-4d0f-816d-a46b9f344f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219001083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.4219001083
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.3527744150
Short name T238
Test name
Test status
Simulation time 11268984428 ps
CPU time 31.03 seconds
Started Jul 24 05:55:08 PM PDT 24
Finished Jul 24 05:55:39 PM PDT 24
Peak memory 232960 kb
Host smart-f75453b8-fa6c-4788-9d6f-e837ae911ef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527744150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.3527744150
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.3462755766
Short name T789
Test name
Test status
Simulation time 989032049 ps
CPU time 11.72 seconds
Started Jul 24 05:55:13 PM PDT 24
Finished Jul 24 05:55:25 PM PDT 24
Peak memory 220832 kb
Host smart-40556baa-c71f-4a56-8bd6-891a687db011
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3462755766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.3462755766
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.3944843211
Short name T28
Test name
Test status
Simulation time 38043402 ps
CPU time 0.94 seconds
Started Jul 24 05:55:13 PM PDT 24
Finished Jul 24 05:55:15 PM PDT 24
Peak memory 206108 kb
Host smart-c128e7bf-6325-4a76-9ed4-e7af73218a36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944843211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.3944843211
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.3998502265
Short name T157
Test name
Test status
Simulation time 75951585443 ps
CPU time 51.92 seconds
Started Jul 24 05:55:08 PM PDT 24
Finished Jul 24 05:56:00 PM PDT 24
Peak memory 216504 kb
Host smart-9804b5a4-76d3-43d5-826e-845cb57d90d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998502265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.3998502265
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.1129146418
Short name T557
Test name
Test status
Simulation time 2252222846 ps
CPU time 6.43 seconds
Started Jul 24 05:55:11 PM PDT 24
Finished Jul 24 05:55:18 PM PDT 24
Peak memory 216500 kb
Host smart-188215a9-9bcd-4c5a-838e-1d71d116ea79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129146418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.1129146418
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.495541120
Short name T829
Test name
Test status
Simulation time 68380427 ps
CPU time 2.35 seconds
Started Jul 24 05:55:07 PM PDT 24
Finished Jul 24 05:55:09 PM PDT 24
Peak memory 216256 kb
Host smart-319cc294-74bb-4779-84e6-4829919fae99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495541120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.495541120
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.1678320889
Short name T465
Test name
Test status
Simulation time 89272476 ps
CPU time 0.83 seconds
Started Jul 24 05:55:09 PM PDT 24
Finished Jul 24 05:55:10 PM PDT 24
Peak memory 206100 kb
Host smart-60974c80-531a-491b-9483-9d8718390118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678320889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.1678320889
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.4018936119
Short name T219
Test name
Test status
Simulation time 1983569031 ps
CPU time 2.5 seconds
Started Jul 24 05:55:12 PM PDT 24
Finished Jul 24 05:55:14 PM PDT 24
Peak memory 224684 kb
Host smart-91285669-cc9c-4221-ac07-a0740c8deda8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018936119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.4018936119
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.913279450
Short name T334
Test name
Test status
Simulation time 15291349 ps
CPU time 0.73 seconds
Started Jul 24 05:55:17 PM PDT 24
Finished Jul 24 05:55:18 PM PDT 24
Peak memory 205012 kb
Host smart-19632324-def0-4ef2-8e5a-48906c245c5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913279450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.913279450
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.3425108217
Short name T493
Test name
Test status
Simulation time 1222815438 ps
CPU time 7.61 seconds
Started Jul 24 05:55:12 PM PDT 24
Finished Jul 24 05:55:20 PM PDT 24
Peak memory 224644 kb
Host smart-b225fa80-636a-45fa-bd11-e75ee23b6656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425108217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.3425108217
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.3640793433
Short name T490
Test name
Test status
Simulation time 77410684 ps
CPU time 0.9 seconds
Started Jul 24 05:55:13 PM PDT 24
Finished Jul 24 05:55:14 PM PDT 24
Peak memory 206688 kb
Host smart-d04714b2-ed2c-4c5b-8d1e-0da33e5b80b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640793433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.3640793433
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.2742155243
Short name T192
Test name
Test status
Simulation time 59499548499 ps
CPU time 238.14 seconds
Started Jul 24 05:55:13 PM PDT 24
Finished Jul 24 05:59:12 PM PDT 24
Peak memory 269864 kb
Host smart-3ff8a6f2-c29f-4566-9669-f516487441f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742155243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.2742155243
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.2219740874
Short name T778
Test name
Test status
Simulation time 38496241939 ps
CPU time 159.34 seconds
Started Jul 24 05:55:13 PM PDT 24
Finished Jul 24 05:57:52 PM PDT 24
Peak memory 240912 kb
Host smart-49582602-39eb-4ce7-a7e9-5d2b028e57f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219740874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.2219740874
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.1043941230
Short name T724
Test name
Test status
Simulation time 10850186346 ps
CPU time 49.91 seconds
Started Jul 24 05:55:13 PM PDT 24
Finished Jul 24 05:56:03 PM PDT 24
Peak memory 233896 kb
Host smart-6a9c14fb-950a-475e-985e-dc333334f167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043941230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.1043941230
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.2496454031
Short name T757
Test name
Test status
Simulation time 45251257692 ps
CPU time 83.03 seconds
Started Jul 24 05:55:12 PM PDT 24
Finished Jul 24 05:56:36 PM PDT 24
Peak memory 241128 kb
Host smart-f4b961f5-e15f-4d6f-a9cd-6ef74e710cca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496454031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmd
s.2496454031
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/24.spi_device_intercept.1682433222
Short name T336
Test name
Test status
Simulation time 3024641093 ps
CPU time 7.47 seconds
Started Jul 24 05:55:13 PM PDT 24
Finished Jul 24 05:55:21 PM PDT 24
Peak memory 232976 kb
Host smart-69652d76-c9a4-4aec-93ce-1bda6a469d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682433222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.1682433222
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.2206832123
Short name T729
Test name
Test status
Simulation time 3563565603 ps
CPU time 31.25 seconds
Started Jul 24 05:55:17 PM PDT 24
Finished Jul 24 05:55:49 PM PDT 24
Peak memory 232868 kb
Host smart-7def3b46-fc8b-4fcb-92b1-02bc595c6712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206832123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.2206832123
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.1309704470
Short name T685
Test name
Test status
Simulation time 7873286436 ps
CPU time 8.11 seconds
Started Jul 24 05:55:16 PM PDT 24
Finished Jul 24 05:55:24 PM PDT 24
Peak memory 224748 kb
Host smart-36f878e5-9c27-42f0-b9f7-3884b2df8dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309704470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.1309704470
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.375429714
Short name T466
Test name
Test status
Simulation time 171273149 ps
CPU time 3.02 seconds
Started Jul 24 05:55:11 PM PDT 24
Finished Jul 24 05:55:15 PM PDT 24
Peak memory 224596 kb
Host smart-c152f995-96a5-4d66-a126-81ec4dbbc5e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375429714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.375429714
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.3609041835
Short name T973
Test name
Test status
Simulation time 333972324 ps
CPU time 5.3 seconds
Started Jul 24 05:55:11 PM PDT 24
Finished Jul 24 05:55:17 PM PDT 24
Peak memory 223264 kb
Host smart-5a7c8411-12bf-429d-a9f5-b52567e6d055
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3609041835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.3609041835
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.3753398064
Short name T913
Test name
Test status
Simulation time 31522594719 ps
CPU time 169.48 seconds
Started Jul 24 05:55:17 PM PDT 24
Finished Jul 24 05:58:06 PM PDT 24
Peak memory 271464 kb
Host smart-43e1086a-6353-4465-a71d-7349ec80cdfe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753398064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.3753398064
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.2299572050
Short name T521
Test name
Test status
Simulation time 2809634044 ps
CPU time 19.85 seconds
Started Jul 24 05:55:15 PM PDT 24
Finished Jul 24 05:55:35 PM PDT 24
Peak memory 216492 kb
Host smart-a358edd2-4476-41ca-b21e-226d838fdf03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299572050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.2299572050
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.536831988
Short name T654
Test name
Test status
Simulation time 1381936128 ps
CPU time 5.24 seconds
Started Jul 24 05:55:14 PM PDT 24
Finished Jul 24 05:55:20 PM PDT 24
Peak memory 216352 kb
Host smart-df3521d7-28a1-4519-a5c1-d532c65503d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536831988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.536831988
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.3242221218
Short name T367
Test name
Test status
Simulation time 163987735 ps
CPU time 1.2 seconds
Started Jul 24 05:55:15 PM PDT 24
Finished Jul 24 05:55:16 PM PDT 24
Peak memory 208224 kb
Host smart-b6df2c6b-ea7a-409a-96de-9ea4ca0e8d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242221218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.3242221218
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.593647410
Short name T876
Test name
Test status
Simulation time 33175935 ps
CPU time 0.75 seconds
Started Jul 24 05:55:13 PM PDT 24
Finished Jul 24 05:55:14 PM PDT 24
Peak memory 206124 kb
Host smart-5127fa64-a5e6-4800-881f-3936741da35a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593647410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.593647410
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.3597596213
Short name T881
Test name
Test status
Simulation time 860632532 ps
CPU time 9.09 seconds
Started Jul 24 05:55:15 PM PDT 24
Finished Jul 24 05:55:24 PM PDT 24
Peak memory 224672 kb
Host smart-8dc7cc13-5dbc-4da0-a7ab-0c96fbadc67e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597596213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.3597596213
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.2774954143
Short name T444
Test name
Test status
Simulation time 16496010 ps
CPU time 0.74 seconds
Started Jul 24 05:55:19 PM PDT 24
Finished Jul 24 05:55:20 PM PDT 24
Peak memory 205564 kb
Host smart-ea8f97e4-4f9e-4656-8c6e-61a9aa2223f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774954143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
2774954143
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.3569168114
Short name T388
Test name
Test status
Simulation time 1161568746 ps
CPU time 2.99 seconds
Started Jul 24 05:55:19 PM PDT 24
Finished Jul 24 05:55:22 PM PDT 24
Peak memory 224696 kb
Host smart-fb11cca4-ef74-4f55-b3ba-0691a505eb15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569168114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.3569168114
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.1555958305
Short name T447
Test name
Test status
Simulation time 46757097 ps
CPU time 0.77 seconds
Started Jul 24 05:55:12 PM PDT 24
Finished Jul 24 05:55:13 PM PDT 24
Peak memory 205728 kb
Host smart-e92fddf9-e9ca-43ed-831e-b4ede4d8aeef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555958305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.1555958305
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.2221653848
Short name T664
Test name
Test status
Simulation time 4093713873 ps
CPU time 17.56 seconds
Started Jul 24 05:55:20 PM PDT 24
Finished Jul 24 05:55:39 PM PDT 24
Peak memory 234320 kb
Host smart-ac13273e-5c8a-4d42-bd54-83d57597c719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221653848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.2221653848
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.1486314337
Short name T32
Test name
Test status
Simulation time 16181418601 ps
CPU time 139.9 seconds
Started Jul 24 05:55:20 PM PDT 24
Finished Jul 24 05:57:40 PM PDT 24
Peak memory 236256 kb
Host smart-373430ee-906d-4d25-b959-71a2cccb19f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486314337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.1486314337
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.3096318303
Short name T30
Test name
Test status
Simulation time 54198372157 ps
CPU time 146.37 seconds
Started Jul 24 05:55:23 PM PDT 24
Finished Jul 24 05:57:49 PM PDT 24
Peak memory 249380 kb
Host smart-caa08e78-276b-48ea-bd34-3aa136f9c2a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096318303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.3096318303
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.2592351539
Short name T976
Test name
Test status
Simulation time 1032617903 ps
CPU time 11.89 seconds
Started Jul 24 05:55:23 PM PDT 24
Finished Jul 24 05:55:35 PM PDT 24
Peak memory 249308 kb
Host smart-ccd4ca49-fca9-4545-9c70-f1ac5f3bfdd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592351539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.2592351539
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.4261782297
Short name T887
Test name
Test status
Simulation time 12202501980 ps
CPU time 42.17 seconds
Started Jul 24 05:55:18 PM PDT 24
Finished Jul 24 05:56:01 PM PDT 24
Peak memory 256128 kb
Host smart-2fe65323-e517-4336-a2a9-762359a9480b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261782297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmd
s.4261782297
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_intercept.2357894038
Short name T739
Test name
Test status
Simulation time 670523435 ps
CPU time 5.42 seconds
Started Jul 24 05:55:19 PM PDT 24
Finished Jul 24 05:55:24 PM PDT 24
Peak memory 232900 kb
Host smart-078a17a6-9c6f-45ca-9ec1-a04654cb478b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357894038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.2357894038
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.1455705915
Short name T410
Test name
Test status
Simulation time 34952839059 ps
CPU time 81.75 seconds
Started Jul 24 05:55:20 PM PDT 24
Finished Jul 24 05:56:42 PM PDT 24
Peak memory 224724 kb
Host smart-7bf61b62-cca3-4da2-b851-0a93fba5d918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455705915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.1455705915
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.4184649189
Short name T245
Test name
Test status
Simulation time 284333592 ps
CPU time 2.84 seconds
Started Jul 24 05:55:18 PM PDT 24
Finished Jul 24 05:55:21 PM PDT 24
Peak memory 224628 kb
Host smart-14bcc388-2a8f-4b10-90bd-4fadc4ab1a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184649189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.4184649189
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.1410275492
Short name T695
Test name
Test status
Simulation time 5880460351 ps
CPU time 9.06 seconds
Started Jul 24 05:55:17 PM PDT 24
Finished Jul 24 05:55:27 PM PDT 24
Peak memory 224608 kb
Host smart-7a392b1f-c89f-4dbb-b28f-57db70b183b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410275492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.1410275492
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.4279157771
Short name T339
Test name
Test status
Simulation time 247692981 ps
CPU time 3.32 seconds
Started Jul 24 05:55:21 PM PDT 24
Finished Jul 24 05:55:25 PM PDT 24
Peak memory 222876 kb
Host smart-5dc1c8e4-67f8-4225-becf-820c8f9aca46
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4279157771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.4279157771
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.2370136473
Short name T862
Test name
Test status
Simulation time 30851787 ps
CPU time 0.89 seconds
Started Jul 24 05:55:24 PM PDT 24
Finished Jul 24 05:55:26 PM PDT 24
Peak memory 206028 kb
Host smart-917e1796-f1c8-443e-8840-b6956966c6ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370136473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.2370136473
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.2161477315
Short name T591
Test name
Test status
Simulation time 1784086556 ps
CPU time 10.77 seconds
Started Jul 24 05:55:12 PM PDT 24
Finished Jul 24 05:55:23 PM PDT 24
Peak memory 219404 kb
Host smart-9ecd149f-b9b7-40b9-997c-47402736b096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161477315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.2161477315
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.4033714839
Short name T500
Test name
Test status
Simulation time 633458945 ps
CPU time 4.13 seconds
Started Jul 24 05:55:14 PM PDT 24
Finished Jul 24 05:55:18 PM PDT 24
Peak memory 216448 kb
Host smart-73e5ec42-cb75-4293-ab57-63afd36f2725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033714839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.4033714839
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.2919635617
Short name T975
Test name
Test status
Simulation time 221793667 ps
CPU time 2.1 seconds
Started Jul 24 05:55:14 PM PDT 24
Finished Jul 24 05:55:16 PM PDT 24
Peak memory 216500 kb
Host smart-a547b761-a3ef-4ba2-8c02-5eab02abcc6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919635617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.2919635617
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.1592707849
Short name T874
Test name
Test status
Simulation time 17060886 ps
CPU time 0.71 seconds
Started Jul 24 05:55:14 PM PDT 24
Finished Jul 24 05:55:15 PM PDT 24
Peak memory 205704 kb
Host smart-46d66cc0-0051-4f08-a510-705f0b2ed4b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592707849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.1592707849
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.1097352325
Short name T596
Test name
Test status
Simulation time 1169978812 ps
CPU time 8.3 seconds
Started Jul 24 05:55:20 PM PDT 24
Finished Jul 24 05:55:29 PM PDT 24
Peak memory 224636 kb
Host smart-472f17b3-c299-4b2a-9ef2-e3fbbf8c9526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097352325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.1097352325
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.41866897
Short name T706
Test name
Test status
Simulation time 11894628 ps
CPU time 0.74 seconds
Started Jul 24 05:55:20 PM PDT 24
Finished Jul 24 05:55:21 PM PDT 24
Peak memory 205892 kb
Host smart-09ea82a7-3910-44bc-92d2-94d9a069f655
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41866897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.41866897
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.436461728
Short name T518
Test name
Test status
Simulation time 509343306 ps
CPU time 3.49 seconds
Started Jul 24 05:55:19 PM PDT 24
Finished Jul 24 05:55:23 PM PDT 24
Peak memory 224732 kb
Host smart-4bf6286e-e36c-4166-a49a-91cbba911ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436461728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.436461728
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.3160604952
Short name T488
Test name
Test status
Simulation time 29732692 ps
CPU time 0.76 seconds
Started Jul 24 05:55:19 PM PDT 24
Finished Jul 24 05:55:19 PM PDT 24
Peak memory 207052 kb
Host smart-dba8ba6c-f1c1-4293-9d53-4e256ad10d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160604952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.3160604952
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.2540105846
Short name T911
Test name
Test status
Simulation time 43373878668 ps
CPU time 76.55 seconds
Started Jul 24 05:55:19 PM PDT 24
Finished Jul 24 05:56:35 PM PDT 24
Peak memory 232964 kb
Host smart-8f2b1e9c-4b1b-4409-95ea-5787028449ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540105846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.2540105846
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.4113014655
Short name T267
Test name
Test status
Simulation time 19085985541 ps
CPU time 75.78 seconds
Started Jul 24 05:55:21 PM PDT 24
Finished Jul 24 05:56:38 PM PDT 24
Peak memory 257620 kb
Host smart-60e3d729-0fe2-45f9-b9ad-b92675256ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113014655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.4113014655
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.351408158
Short name T968
Test name
Test status
Simulation time 16621593334 ps
CPU time 95.71 seconds
Started Jul 24 05:55:20 PM PDT 24
Finished Jul 24 05:56:57 PM PDT 24
Peak memory 257288 kb
Host smart-1dc886fd-5031-4ebe-9b8e-3a13a808744c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351408158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idle
.351408158
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.2350949866
Short name T48
Test name
Test status
Simulation time 1548681603 ps
CPU time 8.3 seconds
Started Jul 24 05:55:18 PM PDT 24
Finished Jul 24 05:55:26 PM PDT 24
Peak memory 232900 kb
Host smart-1fbd4161-50b7-4eab-bfc1-ed9e68effc6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350949866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.2350949866
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.3110758841
Short name T616
Test name
Test status
Simulation time 116321917837 ps
CPU time 209.17 seconds
Started Jul 24 05:55:22 PM PDT 24
Finished Jul 24 05:58:51 PM PDT 24
Peak memory 265060 kb
Host smart-8861342a-fb07-450b-8563-4315fcfc2d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110758841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmd
s.3110758841
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_intercept.1214522573
Short name T886
Test name
Test status
Simulation time 2471497968 ps
CPU time 6.09 seconds
Started Jul 24 05:55:21 PM PDT 24
Finished Jul 24 05:55:28 PM PDT 24
Peak memory 224692 kb
Host smart-97463f5a-52d9-416e-8e0c-b71e42e900f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214522573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.1214522573
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.2815277525
Short name T752
Test name
Test status
Simulation time 789916541 ps
CPU time 4.23 seconds
Started Jul 24 05:55:19 PM PDT 24
Finished Jul 24 05:55:24 PM PDT 24
Peak memory 224620 kb
Host smart-0226b749-dd53-4e9b-8f7c-02d48a25abc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815277525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.2815277525
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.3761579901
Short name T94
Test name
Test status
Simulation time 632074829 ps
CPU time 5.57 seconds
Started Jul 24 05:55:23 PM PDT 24
Finished Jul 24 05:55:29 PM PDT 24
Peak memory 224688 kb
Host smart-4120e8df-102b-40ae-83ce-1a5ba953ca0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761579901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.3761579901
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.2030749256
Short name T978
Test name
Test status
Simulation time 6078907699 ps
CPU time 11.55 seconds
Started Jul 24 05:55:18 PM PDT 24
Finished Jul 24 05:55:30 PM PDT 24
Peak memory 240996 kb
Host smart-b016d244-a3c7-4cca-8799-6ae8e52ac0d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030749256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.2030749256
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.468879305
Short name T638
Test name
Test status
Simulation time 1682048717 ps
CPU time 18.83 seconds
Started Jul 24 05:55:21 PM PDT 24
Finished Jul 24 05:55:41 PM PDT 24
Peak memory 222804 kb
Host smart-1a98db52-667f-4428-8f7c-2a9a1679f91a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=468879305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dire
ct.468879305
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.1061898792
Short name T797
Test name
Test status
Simulation time 167687568 ps
CPU time 0.96 seconds
Started Jul 24 05:55:23 PM PDT 24
Finished Jul 24 05:55:25 PM PDT 24
Peak memory 206928 kb
Host smart-3bcc60f0-0a28-4cb2-a8e0-7222145144bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061898792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.1061898792
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.2735293734
Short name T969
Test name
Test status
Simulation time 709139938 ps
CPU time 4.35 seconds
Started Jul 24 05:55:19 PM PDT 24
Finished Jul 24 05:55:24 PM PDT 24
Peak memory 216464 kb
Host smart-548dddf4-12da-4432-9b2e-fa1b7847a62f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735293734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.2735293734
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.2997221242
Short name T378
Test name
Test status
Simulation time 385977529 ps
CPU time 2.27 seconds
Started Jul 24 05:55:20 PM PDT 24
Finished Jul 24 05:55:23 PM PDT 24
Peak memory 216412 kb
Host smart-674401a5-52f6-4ff1-8382-602499373569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997221242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.2997221242
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.1713386596
Short name T681
Test name
Test status
Simulation time 12466258 ps
CPU time 0.78 seconds
Started Jul 24 05:55:20 PM PDT 24
Finished Jul 24 05:55:21 PM PDT 24
Peak memory 206092 kb
Host smart-cf06240a-1e5a-41d8-9f43-1b22ad990ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713386596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.1713386596
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.3646344963
Short name T344
Test name
Test status
Simulation time 188914234 ps
CPU time 0.87 seconds
Started Jul 24 05:55:19 PM PDT 24
Finished Jul 24 05:55:20 PM PDT 24
Peak memory 206140 kb
Host smart-00eb5f41-3dd8-403e-8441-c3ebb405bf4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646344963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.3646344963
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.3383255062
Short name T511
Test name
Test status
Simulation time 3162008985 ps
CPU time 8.33 seconds
Started Jul 24 05:55:18 PM PDT 24
Finished Jul 24 05:55:26 PM PDT 24
Peak memory 232928 kb
Host smart-edb27a02-8b02-4c0a-b88d-0c0bcbc4f4d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383255062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.3383255062
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.1056593459
Short name T429
Test name
Test status
Simulation time 27323505 ps
CPU time 0.72 seconds
Started Jul 24 05:55:26 PM PDT 24
Finished Jul 24 05:55:27 PM PDT 24
Peak memory 205908 kb
Host smart-30732199-0c2d-488a-9ed8-6f152c149b3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056593459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
1056593459
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.818495379
Short name T699
Test name
Test status
Simulation time 131216767 ps
CPU time 2.45 seconds
Started Jul 24 05:55:26 PM PDT 24
Finished Jul 24 05:55:29 PM PDT 24
Peak memory 232872 kb
Host smart-aef177e6-14d7-4e9a-a6c7-f2f3989b1814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818495379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.818495379
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.64046510
Short name T1009
Test name
Test status
Simulation time 52831515 ps
CPU time 0.78 seconds
Started Jul 24 05:55:19 PM PDT 24
Finished Jul 24 05:55:20 PM PDT 24
Peak memory 206712 kb
Host smart-e44dce62-076f-4294-af95-d0f4f99c2c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64046510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.64046510
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.2752699422
Short name T203
Test name
Test status
Simulation time 6494690351 ps
CPU time 114.6 seconds
Started Jul 24 05:55:24 PM PDT 24
Finished Jul 24 05:57:19 PM PDT 24
Peak memory 257264 kb
Host smart-53a60ea7-92d2-483d-a51e-fa6cf4e970ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752699422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.2752699422
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.3542372499
Short name T276
Test name
Test status
Simulation time 130884934976 ps
CPU time 626.95 seconds
Started Jul 24 05:55:25 PM PDT 24
Finished Jul 24 06:05:52 PM PDT 24
Peak memory 255620 kb
Host smart-76bfcb78-a7cc-4896-a0fe-67bc1c59a2ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542372499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.3542372499
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.3803219763
Short name T755
Test name
Test status
Simulation time 51519548660 ps
CPU time 82.09 seconds
Started Jul 24 05:55:25 PM PDT 24
Finished Jul 24 05:56:47 PM PDT 24
Peak memory 236292 kb
Host smart-9e0b3ddd-7d67-4e59-8e32-3829c11d6abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803219763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.3803219763
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.28442824
Short name T265
Test name
Test status
Simulation time 84338687481 ps
CPU time 208.6 seconds
Started Jul 24 05:55:25 PM PDT 24
Finished Jul 24 05:58:54 PM PDT 24
Peak memory 250792 kb
Host smart-90d65e96-ebd9-463f-ae32-0588cb24fb9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28442824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmds.28442824
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_intercept.1639436573
Short name T396
Test name
Test status
Simulation time 76337613 ps
CPU time 2.37 seconds
Started Jul 24 05:55:26 PM PDT 24
Finished Jul 24 05:55:28 PM PDT 24
Peak memory 224008 kb
Host smart-9f1c8d5d-3b8e-4411-b291-595e2b6d7551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639436573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.1639436573
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.3149805605
Short name T870
Test name
Test status
Simulation time 91898274 ps
CPU time 2.23 seconds
Started Jul 24 05:55:24 PM PDT 24
Finished Jul 24 05:55:27 PM PDT 24
Peak memory 224028 kb
Host smart-ac784669-3bc2-4b92-9e94-1112eb52d8f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149805605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.3149805605
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.687495439
Short name T606
Test name
Test status
Simulation time 2251748525 ps
CPU time 8.45 seconds
Started Jul 24 05:55:23 PM PDT 24
Finished Jul 24 05:55:32 PM PDT 24
Peak memory 232916 kb
Host smart-53de1719-8c0d-4ff3-94da-52884a0b6768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687495439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swap
.687495439
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.2401717986
Short name T161
Test name
Test status
Simulation time 906810653 ps
CPU time 7.72 seconds
Started Jul 24 05:55:20 PM PDT 24
Finished Jul 24 05:55:27 PM PDT 24
Peak memory 232928 kb
Host smart-e7d965fb-893c-4183-81ac-07f97a32562f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401717986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.2401717986
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.3945179039
Short name T35
Test name
Test status
Simulation time 1049634924 ps
CPU time 8.09 seconds
Started Jul 24 05:55:24 PM PDT 24
Finished Jul 24 05:55:33 PM PDT 24
Peak memory 219080 kb
Host smart-d48d70c2-76b1-4aad-bca2-726b83b1d965
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3945179039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.3945179039
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.1694984325
Short name T19
Test name
Test status
Simulation time 709735058 ps
CPU time 1.17 seconds
Started Jul 24 05:55:26 PM PDT 24
Finished Jul 24 05:55:27 PM PDT 24
Peak memory 207356 kb
Host smart-71067957-568d-4178-b563-aea0c8e02375
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694984325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.1694984325
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.300396451
Short name T297
Test name
Test status
Simulation time 3739718351 ps
CPU time 26.4 seconds
Started Jul 24 05:55:22 PM PDT 24
Finished Jul 24 05:55:48 PM PDT 24
Peak memory 216432 kb
Host smart-c3291b1a-d1a8-452c-b2a5-f1be65f512c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300396451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.300396451
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.3412293214
Short name T126
Test name
Test status
Simulation time 8241041766 ps
CPU time 6.4 seconds
Started Jul 24 05:55:18 PM PDT 24
Finished Jul 24 05:55:24 PM PDT 24
Peak memory 217760 kb
Host smart-aeb099b7-317b-463d-9ef8-a7f9008a978b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412293214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.3412293214
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.1722522918
Short name T316
Test name
Test status
Simulation time 209339677 ps
CPU time 2.63 seconds
Started Jul 24 05:55:21 PM PDT 24
Finished Jul 24 05:55:24 PM PDT 24
Peak memory 216408 kb
Host smart-4c20116d-cdf9-49c2-874d-9e0bff236653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722522918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.1722522918
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.3960395835
Short name T347
Test name
Test status
Simulation time 84956758 ps
CPU time 0.78 seconds
Started Jul 24 05:55:20 PM PDT 24
Finished Jul 24 05:55:21 PM PDT 24
Peak memory 206108 kb
Host smart-6b0ca0a9-57c3-4f96-84d9-620a61377443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960395835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.3960395835
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.629426335
Short name T727
Test name
Test status
Simulation time 962544079 ps
CPU time 5.77 seconds
Started Jul 24 05:55:24 PM PDT 24
Finished Jul 24 05:55:31 PM PDT 24
Peak memory 232812 kb
Host smart-db63f3ad-7b0f-4557-bdae-a3ad2cfe6d0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629426335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.629426335
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.3112422911
Short name T603
Test name
Test status
Simulation time 11967670 ps
CPU time 0.74 seconds
Started Jul 24 05:55:35 PM PDT 24
Finished Jul 24 05:55:36 PM PDT 24
Peak memory 205904 kb
Host smart-61fb3a06-9ab3-4faf-9c80-2a38e5ab80eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112422911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
3112422911
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.2942892159
Short name T818
Test name
Test status
Simulation time 1932059551 ps
CPU time 2.75 seconds
Started Jul 24 05:55:26 PM PDT 24
Finished Jul 24 05:55:29 PM PDT 24
Peak memory 224680 kb
Host smart-bb84ac8a-bc4d-4f78-908e-2584b0ad97da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942892159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.2942892159
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.708853245
Short name T332
Test name
Test status
Simulation time 16401936 ps
CPU time 0.84 seconds
Started Jul 24 05:55:25 PM PDT 24
Finished Jul 24 05:55:26 PM PDT 24
Peak memory 206744 kb
Host smart-184353a1-2432-4a43-976b-242029ce62bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708853245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.708853245
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.2313669542
Short name T601
Test name
Test status
Simulation time 17144997069 ps
CPU time 41.74 seconds
Started Jul 24 05:55:35 PM PDT 24
Finished Jul 24 05:56:17 PM PDT 24
Peak memory 251552 kb
Host smart-ddbe8850-d0cf-4486-833a-9b48f1b459f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313669542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.2313669542
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.2422930537
Short name T896
Test name
Test status
Simulation time 7816913465 ps
CPU time 31.35 seconds
Started Jul 24 05:55:32 PM PDT 24
Finished Jul 24 05:56:04 PM PDT 24
Peak memory 233044 kb
Host smart-ad9bea57-4d74-4ffd-9c74-7b8434a15476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422930537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.2422930537
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.2989966936
Short name T535
Test name
Test status
Simulation time 27022083271 ps
CPU time 91.49 seconds
Started Jul 24 05:55:33 PM PDT 24
Finished Jul 24 05:57:05 PM PDT 24
Peak memory 257480 kb
Host smart-890d09c9-58af-47c8-bea0-f8d430e82b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989966936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.2989966936
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.348181341
Short name T90
Test name
Test status
Simulation time 156806434 ps
CPU time 5.7 seconds
Started Jul 24 05:55:28 PM PDT 24
Finished Jul 24 05:55:34 PM PDT 24
Peak memory 224664 kb
Host smart-36fae9a7-299b-416d-ae49-89297bf38f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348181341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.348181341
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.69025315
Short name T533
Test name
Test status
Simulation time 54260200180 ps
CPU time 84.27 seconds
Started Jul 24 05:55:24 PM PDT 24
Finished Jul 24 05:56:49 PM PDT 24
Peak memory 255896 kb
Host smart-222bdaed-12c4-49a8-a7d3-0a354b4bcdd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69025315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmds.69025315
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.3852431740
Short name T546
Test name
Test status
Simulation time 268248695 ps
CPU time 3.27 seconds
Started Jul 24 05:55:26 PM PDT 24
Finished Jul 24 05:55:30 PM PDT 24
Peak memory 232900 kb
Host smart-a86cf36e-3ed3-4bbd-8af6-39850571bd59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852431740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.3852431740
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.3723014464
Short name T903
Test name
Test status
Simulation time 614775124 ps
CPU time 5.36 seconds
Started Jul 24 05:55:24 PM PDT 24
Finished Jul 24 05:55:30 PM PDT 24
Peak memory 236744 kb
Host smart-2c2056dc-69bb-4355-90ef-5f4ef81c4133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723014464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.3723014464
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.2181970198
Short name T613
Test name
Test status
Simulation time 14414323048 ps
CPU time 8.64 seconds
Started Jul 24 05:55:25 PM PDT 24
Finished Jul 24 05:55:34 PM PDT 24
Peak memory 232948 kb
Host smart-82fb10cb-4ac0-4a58-9508-258d72e7e9b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181970198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.2181970198
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.801258253
Short name T540
Test name
Test status
Simulation time 93238277 ps
CPU time 2.5 seconds
Started Jul 24 05:55:26 PM PDT 24
Finished Jul 24 05:55:29 PM PDT 24
Peak memory 224660 kb
Host smart-61d585ae-2112-43c6-a2de-9185922c1213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801258253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.801258253
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.2933264995
Short name T1007
Test name
Test status
Simulation time 540686265 ps
CPU time 5.56 seconds
Started Jul 24 05:55:25 PM PDT 24
Finished Jul 24 05:55:31 PM PDT 24
Peak memory 223228 kb
Host smart-ac4cd5bf-bca8-4538-882e-0332e0cf3c95
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2933264995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.2933264995
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.3431427063
Short name T149
Test name
Test status
Simulation time 10861354851 ps
CPU time 36.94 seconds
Started Jul 24 05:55:34 PM PDT 24
Finished Jul 24 05:56:11 PM PDT 24
Peak memory 239996 kb
Host smart-53286586-c735-41ee-8f32-f19abc320d56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431427063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.3431427063
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.4183386177
Short name T558
Test name
Test status
Simulation time 17014763772 ps
CPU time 25.88 seconds
Started Jul 24 05:55:24 PM PDT 24
Finished Jul 24 05:55:50 PM PDT 24
Peak memory 216448 kb
Host smart-92f83b12-6270-461c-a5c6-de8c924cbcfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183386177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.4183386177
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.3471936354
Short name T327
Test name
Test status
Simulation time 2379475494 ps
CPU time 3.33 seconds
Started Jul 24 05:55:27 PM PDT 24
Finished Jul 24 05:55:31 PM PDT 24
Peak memory 216508 kb
Host smart-ae3c7d12-e0d9-4698-8f25-c1aff9a4be63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471936354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.3471936354
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.1365178092
Short name T418
Test name
Test status
Simulation time 416891396 ps
CPU time 2.8 seconds
Started Jul 24 05:55:24 PM PDT 24
Finished Jul 24 05:55:27 PM PDT 24
Peak memory 216324 kb
Host smart-f8c7768f-516c-4b6b-ae80-5bcc5eeaeccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365178092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.1365178092
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.2088518279
Short name T704
Test name
Test status
Simulation time 56539478 ps
CPU time 0.92 seconds
Started Jul 24 05:55:25 PM PDT 24
Finished Jul 24 05:55:26 PM PDT 24
Peak memory 206116 kb
Host smart-e419f506-da2a-4bb0-9bee-b2a4c3a3ca13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088518279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.2088518279
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.1651817859
Short name T229
Test name
Test status
Simulation time 12333042034 ps
CPU time 11.46 seconds
Started Jul 24 05:55:24 PM PDT 24
Finished Jul 24 05:55:36 PM PDT 24
Peak memory 224628 kb
Host smart-89e17d47-785b-4994-8cf5-2443a0933222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651817859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.1651817859
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.86840615
Short name T848
Test name
Test status
Simulation time 66578241 ps
CPU time 0.73 seconds
Started Jul 24 05:55:33 PM PDT 24
Finished Jul 24 05:55:34 PM PDT 24
Peak memory 205528 kb
Host smart-e8e5ef83-5672-4802-b0be-6f59a97b161c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86840615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.86840615
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.705581557
Short name T744
Test name
Test status
Simulation time 183487778 ps
CPU time 2.19 seconds
Started Jul 24 05:55:32 PM PDT 24
Finished Jul 24 05:55:34 PM PDT 24
Peak memory 224580 kb
Host smart-135efb43-b42a-4608-a3da-edbeb6dd3c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705581557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.705581557
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.3440983272
Short name T401
Test name
Test status
Simulation time 19615150 ps
CPU time 0.78 seconds
Started Jul 24 05:55:33 PM PDT 24
Finished Jul 24 05:55:34 PM PDT 24
Peak memory 206732 kb
Host smart-96370097-7bf5-44a9-aaf0-526f020cde6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440983272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.3440983272
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.3466868365
Short name T187
Test name
Test status
Simulation time 72764898435 ps
CPU time 82.7 seconds
Started Jul 24 05:55:30 PM PDT 24
Finished Jul 24 05:56:53 PM PDT 24
Peak memory 241164 kb
Host smart-0fc07fad-7dbc-4fa0-800a-a4186bee0dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466868365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.3466868365
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.3794950495
Short name T264
Test name
Test status
Simulation time 2354000769 ps
CPU time 43.06 seconds
Started Jul 24 05:55:33 PM PDT 24
Finished Jul 24 05:56:16 PM PDT 24
Peak memory 255608 kb
Host smart-745f8bc5-59a3-4344-8139-32989fc84ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794950495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.3794950495
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.1362974088
Short name T291
Test name
Test status
Simulation time 430817544 ps
CPU time 10.24 seconds
Started Jul 24 05:55:31 PM PDT 24
Finished Jul 24 05:55:41 PM PDT 24
Peak memory 224732 kb
Host smart-ee90956b-8c03-4dd7-8008-d148f92e3d1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362974088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.1362974088
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.4167474481
Short name T828
Test name
Test status
Simulation time 8451305906 ps
CPU time 49.55 seconds
Started Jul 24 05:55:34 PM PDT 24
Finished Jul 24 05:56:24 PM PDT 24
Peak memory 257272 kb
Host smart-e0ba6c01-4ff7-49ef-8ee0-5eec4487db93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167474481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmd
s.4167474481
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_intercept.3709063094
Short name T191
Test name
Test status
Simulation time 7576231308 ps
CPU time 19.9 seconds
Started Jul 24 05:55:33 PM PDT 24
Finished Jul 24 05:55:53 PM PDT 24
Peak memory 232900 kb
Host smart-1b0f52d5-92b7-4c92-ac5d-4ca6af7e52ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709063094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.3709063094
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.2655257616
Short name T221
Test name
Test status
Simulation time 16774061262 ps
CPU time 44.44 seconds
Started Jul 24 05:55:31 PM PDT 24
Finished Jul 24 05:56:16 PM PDT 24
Peak memory 241116 kb
Host smart-92db5613-2d96-4469-a0c4-013a40f5c867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655257616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.2655257616
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.787549814
Short name T128
Test name
Test status
Simulation time 1543964447 ps
CPU time 12.62 seconds
Started Jul 24 05:55:33 PM PDT 24
Finished Jul 24 05:55:46 PM PDT 24
Peak memory 232820 kb
Host smart-31e69876-0fba-4935-9dd3-7a92f5753a39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787549814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swap
.787549814
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.1899780896
Short name T520
Test name
Test status
Simulation time 14887263120 ps
CPU time 14.06 seconds
Started Jul 24 05:55:30 PM PDT 24
Finished Jul 24 05:55:45 PM PDT 24
Peak memory 232956 kb
Host smart-87f71fc7-8a8f-49b1-bc52-61840441c2ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899780896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.1899780896
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.261656109
Short name T398
Test name
Test status
Simulation time 601905791 ps
CPU time 3.46 seconds
Started Jul 24 05:55:32 PM PDT 24
Finished Jul 24 05:55:36 PM PDT 24
Peak memory 219224 kb
Host smart-058e088e-895f-431e-8a0e-60ceec4c9522
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=261656109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dire
ct.261656109
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.2945956244
Short name T372
Test name
Test status
Simulation time 183630012 ps
CPU time 0.98 seconds
Started Jul 24 05:55:33 PM PDT 24
Finished Jul 24 05:55:34 PM PDT 24
Peak memory 206764 kb
Host smart-d71ff48c-2fe8-44b9-afca-c400b5c73755
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945956244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.2945956244
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.3801498184
Short name T909
Test name
Test status
Simulation time 5924198734 ps
CPU time 33.96 seconds
Started Jul 24 05:55:34 PM PDT 24
Finished Jul 24 05:56:08 PM PDT 24
Peak memory 216448 kb
Host smart-de0c5fc9-90ae-4e42-b061-cc251c7b1b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801498184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.3801498184
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.3588486374
Short name T553
Test name
Test status
Simulation time 2659818028 ps
CPU time 8.46 seconds
Started Jul 24 05:55:32 PM PDT 24
Finished Jul 24 05:55:40 PM PDT 24
Peak memory 216384 kb
Host smart-37b5967b-d9e9-4d7c-aa78-b408b5495592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588486374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.3588486374
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.2637498631
Short name T314
Test name
Test status
Simulation time 65496860 ps
CPU time 0.84 seconds
Started Jul 24 05:55:35 PM PDT 24
Finished Jul 24 05:55:36 PM PDT 24
Peak memory 206124 kb
Host smart-199c6b3f-9bcb-47a1-894f-0a5f3a7c0a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637498631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.2637498631
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.373501547
Short name T510
Test name
Test status
Simulation time 222862595 ps
CPU time 0.87 seconds
Started Jul 24 05:55:33 PM PDT 24
Finished Jul 24 05:55:34 PM PDT 24
Peak memory 206108 kb
Host smart-b9dd1f86-74da-4d8b-9a79-67117d48497f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373501547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.373501547
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.2732089393
Short name T855
Test name
Test status
Simulation time 1336005538 ps
CPU time 3.09 seconds
Started Jul 24 05:55:34 PM PDT 24
Finished Jul 24 05:55:37 PM PDT 24
Peak memory 224712 kb
Host smart-223b8ca6-6150-4543-a345-77916cd9ca8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732089393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.2732089393
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.1999707476
Short name T57
Test name
Test status
Simulation time 141790539 ps
CPU time 0.74 seconds
Started Jul 24 05:54:05 PM PDT 24
Finished Jul 24 05:54:06 PM PDT 24
Peak memory 205556 kb
Host smart-89271647-838a-4240-a7c1-a1de55a8c1e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999707476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.1
999707476
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.3554664914
Short name T89
Test name
Test status
Simulation time 1093333756 ps
CPU time 4.41 seconds
Started Jul 24 05:54:05 PM PDT 24
Finished Jul 24 05:54:10 PM PDT 24
Peak memory 232904 kb
Host smart-840c16c1-5d87-4c7a-b7bd-8b8f9da10f77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554664914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.3554664914
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.1329646311
Short name T627
Test name
Test status
Simulation time 63078779 ps
CPU time 0.77 seconds
Started Jul 24 05:53:57 PM PDT 24
Finished Jul 24 05:53:58 PM PDT 24
Peak memory 206968 kb
Host smart-b9f13f3e-9b0d-4ffa-aad6-91e9bf57be2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329646311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.1329646311
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.3305168859
Short name T935
Test name
Test status
Simulation time 1739844335 ps
CPU time 22.62 seconds
Started Jul 24 05:54:04 PM PDT 24
Finished Jul 24 05:54:27 PM PDT 24
Peak memory 249300 kb
Host smart-7e69934d-1261-45d3-8f29-e93da5d64412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305168859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.3305168859
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.186672198
Short name T942
Test name
Test status
Simulation time 2001437084 ps
CPU time 33.84 seconds
Started Jul 24 05:54:02 PM PDT 24
Finished Jul 24 05:54:36 PM PDT 24
Peak memory 232972 kb
Host smart-4c5f6603-0a2d-43a6-a513-a23f8adc5bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186672198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.186672198
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.3884880905
Short name T753
Test name
Test status
Simulation time 4226915773 ps
CPU time 60.36 seconds
Started Jul 24 05:54:03 PM PDT 24
Finished Jul 24 05:55:03 PM PDT 24
Peak memory 250744 kb
Host smart-f5509467-912b-4a79-a960-d01d5b022e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884880905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.3884880905
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.563849332
Short name T156
Test name
Test status
Simulation time 769637364 ps
CPU time 13.66 seconds
Started Jul 24 05:54:06 PM PDT 24
Finished Jul 24 05:54:20 PM PDT 24
Peak memory 235384 kb
Host smart-63f7cc47-518e-41e6-a183-a0177ebf8540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563849332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.563849332
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.2540391966
Short name T91
Test name
Test status
Simulation time 15119959664 ps
CPU time 156.56 seconds
Started Jul 24 05:54:03 PM PDT 24
Finished Jul 24 05:56:40 PM PDT 24
Peak memory 255428 kb
Host smart-1d609b88-d035-46e8-9359-8312e8d2dc13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540391966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds
.2540391966
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_intercept.690235982
Short name T769
Test name
Test status
Simulation time 1842275816 ps
CPU time 22.79 seconds
Started Jul 24 05:54:05 PM PDT 24
Finished Jul 24 05:54:28 PM PDT 24
Peak memory 224704 kb
Host smart-63bc5205-54c5-4a00-b378-29cdfa3e002a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690235982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.690235982
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.3192999395
Short name T374
Test name
Test status
Simulation time 3351056199 ps
CPU time 21.96 seconds
Started Jul 24 05:54:03 PM PDT 24
Finished Jul 24 05:54:25 PM PDT 24
Peak memory 238204 kb
Host smart-0251ab64-88b8-47a1-9f70-52fa4b9d4319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192999395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.3192999395
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.3122243752
Short name T682
Test name
Test status
Simulation time 214615855 ps
CPU time 3.18 seconds
Started Jul 24 05:54:02 PM PDT 24
Finished Jul 24 05:54:05 PM PDT 24
Peak memory 224648 kb
Host smart-9379a6ce-5410-4d23-9664-a537639a8618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122243752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.3122243752
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.1325295249
Short name T408
Test name
Test status
Simulation time 8363241359 ps
CPU time 7.22 seconds
Started Jul 24 05:54:00 PM PDT 24
Finished Jul 24 05:54:07 PM PDT 24
Peak memory 224672 kb
Host smart-fd307c47-4a37-4eff-a92c-01ae8d246547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325295249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.1325295249
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.4033464935
Short name T788
Test name
Test status
Simulation time 123936928 ps
CPU time 4.09 seconds
Started Jul 24 05:54:02 PM PDT 24
Finished Jul 24 05:54:06 PM PDT 24
Peak memory 219580 kb
Host smart-c3d3c701-80d0-4d71-815e-8178bc773b00
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4033464935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.4033464935
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.2478520008
Short name T55
Test name
Test status
Simulation time 3246062860 ps
CPU time 22.54 seconds
Started Jul 24 05:53:59 PM PDT 24
Finished Jul 24 05:54:22 PM PDT 24
Peak memory 216424 kb
Host smart-bb85af0a-da27-4b91-8d1f-a02c211797fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478520008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.2478520008
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.4110520114
Short name T4
Test name
Test status
Simulation time 27312474961 ps
CPU time 19.75 seconds
Started Jul 24 05:54:03 PM PDT 24
Finished Jul 24 05:54:23 PM PDT 24
Peak memory 216516 kb
Host smart-2f6eb305-dc7a-448a-ad06-3bf7f9395012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110520114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.4110520114
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.2287266046
Short name T713
Test name
Test status
Simulation time 321601425 ps
CPU time 1.7 seconds
Started Jul 24 05:54:05 PM PDT 24
Finished Jul 24 05:54:07 PM PDT 24
Peak memory 216380 kb
Host smart-4e803dda-8e47-4c9c-8014-d36759e602f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287266046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.2287266046
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.3279456596
Short name T324
Test name
Test status
Simulation time 49022280 ps
CPU time 0.79 seconds
Started Jul 24 05:54:03 PM PDT 24
Finished Jul 24 05:54:04 PM PDT 24
Peak memory 206108 kb
Host smart-e95c7b1f-8506-44bc-a639-0a98b2504ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279456596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.3279456596
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.3254143828
Short name T474
Test name
Test status
Simulation time 210087632 ps
CPU time 2.87 seconds
Started Jul 24 05:54:02 PM PDT 24
Finished Jul 24 05:54:05 PM PDT 24
Peak memory 232748 kb
Host smart-da5905fd-01fd-4f68-80d5-b62244145499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254143828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.3254143828
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.3995112913
Short name T915
Test name
Test status
Simulation time 51440696 ps
CPU time 0.73 seconds
Started Jul 24 05:55:36 PM PDT 24
Finished Jul 24 05:55:37 PM PDT 24
Peak memory 205576 kb
Host smart-7903a94e-027d-4202-af9c-f64cb40fb73f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995112913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
3995112913
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.1319443909
Short name T953
Test name
Test status
Simulation time 116232533 ps
CPU time 2.94 seconds
Started Jul 24 05:55:38 PM PDT 24
Finished Jul 24 05:55:41 PM PDT 24
Peak memory 232880 kb
Host smart-7487cd69-f2bf-4280-870a-802f619c7212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319443909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.1319443909
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.2328098972
Short name T866
Test name
Test status
Simulation time 16850911 ps
CPU time 0.82 seconds
Started Jul 24 05:55:31 PM PDT 24
Finished Jul 24 05:55:32 PM PDT 24
Peak memory 207068 kb
Host smart-7ec740e9-e850-4675-9c88-7c913aa5b3c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328098972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.2328098972
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.2416405662
Short name T801
Test name
Test status
Simulation time 169691027836 ps
CPU time 242.13 seconds
Started Jul 24 05:55:36 PM PDT 24
Finished Jul 24 05:59:38 PM PDT 24
Peak memory 249332 kb
Host smart-1edca301-5b41-48de-a585-1a622c1a1bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416405662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.2416405662
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.4015962271
Short name T25
Test name
Test status
Simulation time 4326960312 ps
CPU time 58.96 seconds
Started Jul 24 05:55:39 PM PDT 24
Finished Jul 24 05:56:38 PM PDT 24
Peak memory 257564 kb
Host smart-b3cd73e1-98cd-4eb1-8163-43122c9595a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015962271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.4015962271
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.1629967388
Short name T302
Test name
Test status
Simulation time 2311277845 ps
CPU time 13.44 seconds
Started Jul 24 05:55:38 PM PDT 24
Finished Jul 24 05:55:52 PM PDT 24
Peak memory 241252 kb
Host smart-5893edd4-81d5-41d0-853a-d82fe401d2b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629967388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.1629967388
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.2822475885
Short name T824
Test name
Test status
Simulation time 122889290 ps
CPU time 3.95 seconds
Started Jul 24 05:55:39 PM PDT 24
Finished Jul 24 05:55:43 PM PDT 24
Peak memory 232872 kb
Host smart-1db714c2-c8fa-4838-8601-1f2babdecf64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822475885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.2822475885
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.3079004114
Short name T701
Test name
Test status
Simulation time 3047689219 ps
CPU time 9.24 seconds
Started Jul 24 05:55:36 PM PDT 24
Finished Jul 24 05:55:46 PM PDT 24
Peak memory 232888 kb
Host smart-c414d619-2eab-4ca6-a416-e29fe01825e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079004114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.3079004114
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.1984587973
Short name T307
Test name
Test status
Simulation time 198073092 ps
CPU time 2.29 seconds
Started Jul 24 05:55:36 PM PDT 24
Finished Jul 24 05:55:39 PM PDT 24
Peak memory 232596 kb
Host smart-273438ae-8fb2-4b77-89d4-c25de9fbe2f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984587973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.1984587973
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.1632253396
Short name T243
Test name
Test status
Simulation time 248493739 ps
CPU time 5.02 seconds
Started Jul 24 05:55:36 PM PDT 24
Finished Jul 24 05:55:41 PM PDT 24
Peak memory 219908 kb
Host smart-e32714a3-49b6-4a8f-bb70-9341df0620ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632253396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.1632253396
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.2366942197
Short name T209
Test name
Test status
Simulation time 6927701505 ps
CPU time 6.9 seconds
Started Jul 24 05:55:37 PM PDT 24
Finished Jul 24 05:55:44 PM PDT 24
Peak memory 224684 kb
Host smart-09dc300d-9381-4c35-9282-f2dd0fc3c911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366942197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.2366942197
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.3036320842
Short name T644
Test name
Test status
Simulation time 693309710 ps
CPU time 3.63 seconds
Started Jul 24 05:55:37 PM PDT 24
Finished Jul 24 05:55:41 PM PDT 24
Peak memory 218724 kb
Host smart-f475a058-c995-4420-bcc8-8865d0134925
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3036320842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.3036320842
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.3295979328
Short name T299
Test name
Test status
Simulation time 2411314663 ps
CPU time 32.67 seconds
Started Jul 24 05:55:33 PM PDT 24
Finished Jul 24 05:56:06 PM PDT 24
Peak memory 216548 kb
Host smart-7d3122d3-a940-46d3-8c51-61dfd9dc3659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295979328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.3295979328
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.4080085721
Short name T668
Test name
Test status
Simulation time 20943906937 ps
CPU time 13.95 seconds
Started Jul 24 05:55:31 PM PDT 24
Finished Jul 24 05:55:46 PM PDT 24
Peak memory 216516 kb
Host smart-354b388c-dd10-43c0-b2e6-b08f64f46e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080085721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.4080085721
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.2292309781
Short name T904
Test name
Test status
Simulation time 18831005 ps
CPU time 0.8 seconds
Started Jul 24 05:55:36 PM PDT 24
Finished Jul 24 05:55:37 PM PDT 24
Peak memory 206096 kb
Host smart-3d4b63e0-5aaa-4093-9717-c3c88830b73b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292309781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.2292309781
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.3359219452
Short name T346
Test name
Test status
Simulation time 301286740 ps
CPU time 0.98 seconds
Started Jul 24 05:55:37 PM PDT 24
Finished Jul 24 05:55:38 PM PDT 24
Peak memory 207108 kb
Host smart-f13f362d-2822-4cd6-a283-418a423d8f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359219452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.3359219452
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.2021987523
Short name T604
Test name
Test status
Simulation time 14225487291 ps
CPU time 27.94 seconds
Started Jul 24 05:55:38 PM PDT 24
Finished Jul 24 05:56:06 PM PDT 24
Peak memory 232972 kb
Host smart-53a2e100-868b-4cb3-8818-1a7f0092ee3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021987523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.2021987523
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.63761162
Short name T675
Test name
Test status
Simulation time 48670801 ps
CPU time 0.74 seconds
Started Jul 24 05:55:42 PM PDT 24
Finished Jul 24 05:55:44 PM PDT 24
Peak memory 204956 kb
Host smart-15aa14a4-9e48-424a-b6be-e98c8e1ba083
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63761162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.63761162
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.3235656670
Short name T335
Test name
Test status
Simulation time 1516546857 ps
CPU time 10.96 seconds
Started Jul 24 05:55:42 PM PDT 24
Finished Jul 24 05:55:53 PM PDT 24
Peak memory 232912 kb
Host smart-43bf56e6-c714-4f51-82c3-353dbe8af651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235656670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.3235656670
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.1832220018
Short name T850
Test name
Test status
Simulation time 49960634 ps
CPU time 0.74 seconds
Started Jul 24 05:55:36 PM PDT 24
Finished Jul 24 05:55:36 PM PDT 24
Peak memory 206044 kb
Host smart-12ac04ef-24f8-48d2-9443-a93f7c1f4c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832220018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.1832220018
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.1724000437
Short name T211
Test name
Test status
Simulation time 28865913302 ps
CPU time 100.96 seconds
Started Jul 24 05:55:42 PM PDT 24
Finished Jul 24 05:57:23 PM PDT 24
Peak memory 254240 kb
Host smart-64867c66-acca-4b54-bb6b-c665e66b7971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724000437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.1724000437
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.1075535065
Short name T982
Test name
Test status
Simulation time 76468132444 ps
CPU time 178.15 seconds
Started Jul 24 05:55:42 PM PDT 24
Finished Jul 24 05:58:41 PM PDT 24
Peak memory 249380 kb
Host smart-171bfaab-91fb-4421-b9e9-d6e2d84e5c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075535065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.1075535065
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.3857152445
Short name T295
Test name
Test status
Simulation time 41225671203 ps
CPU time 195.93 seconds
Started Jul 24 05:55:41 PM PDT 24
Finished Jul 24 05:58:57 PM PDT 24
Peak memory 250972 kb
Host smart-33fc4988-0cb6-4cf2-abd9-47595e205e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857152445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.3857152445
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.3524717215
Short name T707
Test name
Test status
Simulation time 149868133 ps
CPU time 4.39 seconds
Started Jul 24 05:55:41 PM PDT 24
Finished Jul 24 05:55:46 PM PDT 24
Peak memory 232912 kb
Host smart-84701cf4-a5cf-46d5-8425-552ea5767e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524717215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.3524717215
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.2768180609
Short name T280
Test name
Test status
Simulation time 106232864759 ps
CPU time 193.97 seconds
Started Jul 24 05:55:41 PM PDT 24
Finished Jul 24 05:58:55 PM PDT 24
Peak memory 273180 kb
Host smart-5f9db76d-a296-4fd9-9bfd-70fe6c47633b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768180609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmd
s.2768180609
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/31.spi_device_intercept.2340042262
Short name T551
Test name
Test status
Simulation time 155829580 ps
CPU time 4.95 seconds
Started Jul 24 05:55:36 PM PDT 24
Finished Jul 24 05:55:41 PM PDT 24
Peak memory 224708 kb
Host smart-ea606c2c-f231-4d21-adac-7a38c5343b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340042262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.2340042262
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.2618822603
Short name T566
Test name
Test status
Simulation time 722720188 ps
CPU time 17.59 seconds
Started Jul 24 05:55:38 PM PDT 24
Finished Jul 24 05:55:55 PM PDT 24
Peak memory 252072 kb
Host smart-c2d8d25b-de70-40db-ada5-a679e7ac4bc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618822603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.2618822603
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.2356939891
Short name T946
Test name
Test status
Simulation time 144140002 ps
CPU time 2.83 seconds
Started Jul 24 05:55:39 PM PDT 24
Finished Jul 24 05:55:42 PM PDT 24
Peak memory 224628 kb
Host smart-4ef79f18-a7a9-470c-8801-131d1810f075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356939891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.2356939891
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.4023448299
Short name T623
Test name
Test status
Simulation time 1439062179 ps
CPU time 4.9 seconds
Started Jul 24 05:55:40 PM PDT 24
Finished Jul 24 05:55:45 PM PDT 24
Peak memory 232900 kb
Host smart-d6494a90-e436-45f7-80da-cf9a6d33a9ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023448299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.4023448299
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.3335815680
Short name T966
Test name
Test status
Simulation time 1898762455 ps
CPU time 8.2 seconds
Started Jul 24 05:55:43 PM PDT 24
Finished Jul 24 05:55:51 PM PDT 24
Peak memory 223324 kb
Host smart-61dad9fd-6dfc-453b-b0b5-cc35c2cb9281
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3335815680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.3335815680
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.1300474845
Short name T508
Test name
Test status
Simulation time 5422699188 ps
CPU time 60.28 seconds
Started Jul 24 05:55:42 PM PDT 24
Finished Jul 24 05:56:42 PM PDT 24
Peak memory 249412 kb
Host smart-9b05eaf3-c855-4167-895a-a5d0d9b4c3b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300474845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.1300474845
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.1077323373
Short name T961
Test name
Test status
Simulation time 11643518375 ps
CPU time 12.01 seconds
Started Jul 24 05:55:37 PM PDT 24
Finished Jul 24 05:55:49 PM PDT 24
Peak memory 216432 kb
Host smart-17818b12-3a97-4f40-9732-0bca5050d68d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077323373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.1077323373
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.181035956
Short name T330
Test name
Test status
Simulation time 1145385001 ps
CPU time 5.65 seconds
Started Jul 24 05:55:38 PM PDT 24
Finished Jul 24 05:55:43 PM PDT 24
Peak memory 216320 kb
Host smart-718d0d84-9d23-494d-b375-23aaa7138d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181035956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.181035956
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.3272862201
Short name T825
Test name
Test status
Simulation time 454602255 ps
CPU time 1.58 seconds
Started Jul 24 05:55:37 PM PDT 24
Finished Jul 24 05:55:39 PM PDT 24
Peak memory 216416 kb
Host smart-feed8c3c-5fc9-4fea-b111-887c352d36df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272862201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.3272862201
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.3569740426
Short name T590
Test name
Test status
Simulation time 61711699 ps
CPU time 0.95 seconds
Started Jul 24 05:55:39 PM PDT 24
Finished Jul 24 05:55:40 PM PDT 24
Peak memory 206388 kb
Host smart-e098eab4-1c53-4de2-9fa5-cf3896a7472d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569740426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.3569740426
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.3730995995
Short name T385
Test name
Test status
Simulation time 94329107 ps
CPU time 2.46 seconds
Started Jul 24 05:55:41 PM PDT 24
Finished Jul 24 05:55:44 PM PDT 24
Peak memory 224732 kb
Host smart-ba5add12-e34c-4aa6-86f9-5325bb255b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730995995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.3730995995
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.3442912424
Short name T322
Test name
Test status
Simulation time 13879729 ps
CPU time 0.69 seconds
Started Jul 24 05:55:44 PM PDT 24
Finished Jul 24 05:55:45 PM PDT 24
Peak memory 205024 kb
Host smart-d94b168a-1852-4044-b4ae-4d5760f513e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442912424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
3442912424
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.1471828004
Short name T483
Test name
Test status
Simulation time 1745669531 ps
CPU time 13.97 seconds
Started Jul 24 05:55:40 PM PDT 24
Finished Jul 24 05:55:54 PM PDT 24
Peak memory 224680 kb
Host smart-a5f88155-243a-481e-818d-a8038669673a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471828004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.1471828004
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.841009624
Short name T878
Test name
Test status
Simulation time 27854640 ps
CPU time 0.78 seconds
Started Jul 24 05:55:45 PM PDT 24
Finished Jul 24 05:55:46 PM PDT 24
Peak memory 206736 kb
Host smart-4e4ab246-321e-49b2-a3df-fafec5dddbdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841009624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.841009624
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.1504054065
Short name T589
Test name
Test status
Simulation time 3354503806 ps
CPU time 61.1 seconds
Started Jul 24 05:55:44 PM PDT 24
Finished Jul 24 05:56:46 PM PDT 24
Peak memory 254128 kb
Host smart-22ab2f9f-c192-4b2a-bb59-4a76ab7e1279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504054065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.1504054065
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.2369366455
Short name T515
Test name
Test status
Simulation time 2671120942 ps
CPU time 23.5 seconds
Started Jul 24 05:55:43 PM PDT 24
Finished Jul 24 05:56:07 PM PDT 24
Peak memory 217740 kb
Host smart-6fa6cf82-5f45-41f0-bd8d-ef5711a98366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369366455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.2369366455
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.2364549487
Short name T259
Test name
Test status
Simulation time 7560712080 ps
CPU time 77.66 seconds
Started Jul 24 05:55:44 PM PDT 24
Finished Jul 24 05:57:02 PM PDT 24
Peak memory 257564 kb
Host smart-a4c94d77-b1b9-48ff-9ff3-829bf3c5b1dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364549487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.2364549487
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.2753640390
Short name T565
Test name
Test status
Simulation time 83542979 ps
CPU time 2.79 seconds
Started Jul 24 05:55:44 PM PDT 24
Finished Jul 24 05:55:47 PM PDT 24
Peak memory 232884 kb
Host smart-8025715b-b94b-456f-9e7d-4df72691c8c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753640390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.2753640390
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.1616553656
Short name T791
Test name
Test status
Simulation time 85906567441 ps
CPU time 124.46 seconds
Started Jul 24 05:55:41 PM PDT 24
Finished Jul 24 05:57:45 PM PDT 24
Peak memory 238536 kb
Host smart-deb9c7d2-acbe-4fcc-b447-73b24b6adddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616553656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmd
s.1616553656
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_intercept.3496252010
Short name T351
Test name
Test status
Simulation time 902614862 ps
CPU time 8.24 seconds
Started Jul 24 05:55:44 PM PDT 24
Finished Jul 24 05:55:53 PM PDT 24
Peak memory 232816 kb
Host smart-a472426a-eba2-44e6-9343-2b6519138f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496252010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.3496252010
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.3915282529
Short name T232
Test name
Test status
Simulation time 3614503885 ps
CPU time 19.67 seconds
Started Jul 24 05:55:40 PM PDT 24
Finished Jul 24 05:56:00 PM PDT 24
Peak memory 239268 kb
Host smart-0bb733f7-1e10-44c5-a0b8-41bb387c80f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915282529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.3915282529
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.2467748541
Short name T246
Test name
Test status
Simulation time 4089647257 ps
CPU time 6.95 seconds
Started Jul 24 05:55:41 PM PDT 24
Finished Jul 24 05:55:48 PM PDT 24
Peak memory 232980 kb
Host smart-6c086cc5-e931-48c8-a892-fb98463392d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467748541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.2467748541
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.1073917069
Short name T1001
Test name
Test status
Simulation time 13907147343 ps
CPU time 13.07 seconds
Started Jul 24 05:55:40 PM PDT 24
Finished Jul 24 05:55:54 PM PDT 24
Peak memory 232912 kb
Host smart-90a84483-3371-4375-9a53-5813df479eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073917069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.1073917069
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.1211350202
Short name T846
Test name
Test status
Simulation time 3859401130 ps
CPU time 10.71 seconds
Started Jul 24 05:55:41 PM PDT 24
Finished Jul 24 05:55:51 PM PDT 24
Peak memory 219712 kb
Host smart-f25c7971-456f-413f-a546-a1722eaf3109
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1211350202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.1211350202
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.1276363552
Short name T710
Test name
Test status
Simulation time 25862331146 ps
CPU time 28.18 seconds
Started Jul 24 05:55:44 PM PDT 24
Finished Jul 24 05:56:12 PM PDT 24
Peak memory 216528 kb
Host smart-95f226e4-69fa-4f4e-8378-6217d0e8903a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276363552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.1276363552
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.3858601206
Short name T602
Test name
Test status
Simulation time 732651898 ps
CPU time 2.23 seconds
Started Jul 24 05:55:42 PM PDT 24
Finished Jul 24 05:55:45 PM PDT 24
Peak memory 216472 kb
Host smart-e218fa1b-1d42-4227-99bd-412df7e9e73c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858601206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.3858601206
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.2408964374
Short name T301
Test name
Test status
Simulation time 172222166 ps
CPU time 4.45 seconds
Started Jul 24 05:55:41 PM PDT 24
Finished Jul 24 05:55:45 PM PDT 24
Peak memory 216364 kb
Host smart-4b14bae1-5730-4d75-a802-21b372f0efa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408964374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.2408964374
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.1294980838
Short name T912
Test name
Test status
Simulation time 513774681 ps
CPU time 0.89 seconds
Started Jul 24 05:55:43 PM PDT 24
Finished Jul 24 05:55:45 PM PDT 24
Peak memory 206100 kb
Host smart-593fdba9-1f98-44c1-b725-77f4535b4d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294980838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.1294980838
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.90719391
Short name T234
Test name
Test status
Simulation time 9429940060 ps
CPU time 31.92 seconds
Started Jul 24 05:55:43 PM PDT 24
Finished Jul 24 05:56:15 PM PDT 24
Peak memory 239476 kb
Host smart-df8373db-3c83-49f6-9107-ba21716e12ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90719391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.90719391
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.4242595165
Short name T394
Test name
Test status
Simulation time 21758055 ps
CPU time 0.7 seconds
Started Jul 24 05:55:49 PM PDT 24
Finished Jul 24 05:55:50 PM PDT 24
Peak memory 205556 kb
Host smart-0506be7b-21e2-4e15-9e27-e97c62b841a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242595165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
4242595165
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.2792203949
Short name T854
Test name
Test status
Simulation time 664778060 ps
CPU time 3.92 seconds
Started Jul 24 05:55:49 PM PDT 24
Finished Jul 24 05:55:53 PM PDT 24
Peak memory 232888 kb
Host smart-de06b60c-9344-47e1-a4a6-a116f1e2d325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792203949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.2792203949
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.848558124
Short name T927
Test name
Test status
Simulation time 35326969 ps
CPU time 0.78 seconds
Started Jul 24 05:55:43 PM PDT 24
Finished Jul 24 05:55:45 PM PDT 24
Peak memory 207020 kb
Host smart-060ebe88-d4d9-4f64-8c44-6a748005ce13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848558124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.848558124
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.1157449137
Short name T840
Test name
Test status
Simulation time 21886326 ps
CPU time 0.74 seconds
Started Jul 24 05:55:48 PM PDT 24
Finished Jul 24 05:55:48 PM PDT 24
Peak memory 215940 kb
Host smart-f4570af6-93f0-4eeb-9e7d-b731755351e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157449137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.1157449137
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.3634832749
Short name T33
Test name
Test status
Simulation time 17077935653 ps
CPU time 63.85 seconds
Started Jul 24 05:55:49 PM PDT 24
Finished Jul 24 05:56:53 PM PDT 24
Peak memory 254936 kb
Host smart-129f8e83-9389-4cb2-a92b-65a6bbcc97d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634832749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.3634832749
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.3911880151
Short name T633
Test name
Test status
Simulation time 88310383023 ps
CPU time 171.62 seconds
Started Jul 24 05:55:50 PM PDT 24
Finished Jul 24 05:58:41 PM PDT 24
Peak memory 255888 kb
Host smart-effe36ce-5e9e-4b89-99fb-18c585654a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911880151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.3911880151
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.148334714
Short name T988
Test name
Test status
Simulation time 226879199 ps
CPU time 6.06 seconds
Started Jul 24 05:55:52 PM PDT 24
Finished Jul 24 05:55:58 PM PDT 24
Peak memory 232880 kb
Host smart-ea5c89f1-4151-4213-a10f-288e03477663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148334714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.148334714
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.455212753
Short name T725
Test name
Test status
Simulation time 2877937568 ps
CPU time 8.7 seconds
Started Jul 24 05:55:50 PM PDT 24
Finished Jul 24 05:55:59 PM PDT 24
Peak memory 235240 kb
Host smart-ba71c7c7-a208-4807-9d32-39bcd3ece9c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455212753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmds
.455212753
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_intercept.2081038022
Short name T486
Test name
Test status
Simulation time 401401530 ps
CPU time 6.63 seconds
Started Jul 24 05:55:47 PM PDT 24
Finished Jul 24 05:55:54 PM PDT 24
Peak memory 232888 kb
Host smart-244bea3c-33f5-4efd-a5e9-4618c3e70e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081038022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.2081038022
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.2800761372
Short name T6
Test name
Test status
Simulation time 838858769 ps
CPU time 12.01 seconds
Started Jul 24 05:55:47 PM PDT 24
Finished Jul 24 05:55:59 PM PDT 24
Peak memory 240928 kb
Host smart-72f8499a-342e-4707-9084-12da4cbad432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800761372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.2800761372
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.4079181745
Short name T467
Test name
Test status
Simulation time 4111531612 ps
CPU time 13.37 seconds
Started Jul 24 05:55:50 PM PDT 24
Finished Jul 24 05:56:03 PM PDT 24
Peak memory 224720 kb
Host smart-4e863d28-9b1e-4ba8-aead-c35e1ebfd5b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079181745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.4079181745
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.427329869
Short name T51
Test name
Test status
Simulation time 3973315207 ps
CPU time 15.27 seconds
Started Jul 24 05:55:46 PM PDT 24
Finished Jul 24 05:56:01 PM PDT 24
Peak memory 234436 kb
Host smart-9fc95c48-1b9f-47e2-9605-ffc139512948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427329869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.427329869
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.3827839579
Short name T895
Test name
Test status
Simulation time 2434586113 ps
CPU time 11.9 seconds
Started Jul 24 05:55:46 PM PDT 24
Finished Jul 24 05:55:58 PM PDT 24
Peak memory 222720 kb
Host smart-7de89d02-48f7-4054-b016-d55c1ebd2366
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3827839579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.3827839579
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.3781946245
Short name T148
Test name
Test status
Simulation time 1636234831 ps
CPU time 10.8 seconds
Started Jul 24 05:55:48 PM PDT 24
Finished Jul 24 05:55:59 PM PDT 24
Peak memory 218068 kb
Host smart-41d8515c-291a-405a-9d0d-cbfaa47ced97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781946245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.3781946245
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.3101774372
Short name T562
Test name
Test status
Simulation time 3090586962 ps
CPU time 6.53 seconds
Started Jul 24 05:56:28 PM PDT 24
Finished Jul 24 05:56:35 PM PDT 24
Peak memory 216516 kb
Host smart-752ba633-3c19-43ba-867d-cdd361eb73f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101774372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.3101774372
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.1370643749
Short name T548
Test name
Test status
Simulation time 441929616 ps
CPU time 2.16 seconds
Started Jul 24 05:55:47 PM PDT 24
Finished Jul 24 05:55:50 PM PDT 24
Peak memory 216452 kb
Host smart-f505c572-132c-4d38-b965-f6fdf6063905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370643749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.1370643749
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.3474903201
Short name T631
Test name
Test status
Simulation time 170650148 ps
CPU time 1.16 seconds
Started Jul 24 05:55:47 PM PDT 24
Finished Jul 24 05:55:48 PM PDT 24
Peak memory 208032 kb
Host smart-b2bbb982-5284-4712-bc68-3019c28aa7a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474903201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.3474903201
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.359409438
Short name T665
Test name
Test status
Simulation time 121986898 ps
CPU time 0.9 seconds
Started Jul 24 05:55:47 PM PDT 24
Finished Jul 24 05:55:48 PM PDT 24
Peak memory 206408 kb
Host smart-7c91e180-ab6b-4df2-b2ad-dbd82b282394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359409438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.359409438
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.470877699
Short name T382
Test name
Test status
Simulation time 5991865858 ps
CPU time 14.89 seconds
Started Jul 24 05:55:46 PM PDT 24
Finished Jul 24 05:56:01 PM PDT 24
Peak memory 232900 kb
Host smart-399d85fe-2a86-45a1-a6f7-d3016a94f48b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470877699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.470877699
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.310233353
Short name T503
Test name
Test status
Simulation time 31044789 ps
CPU time 0.72 seconds
Started Jul 24 05:55:52 PM PDT 24
Finished Jul 24 05:55:53 PM PDT 24
Peak memory 205516 kb
Host smart-159e81e4-d7d3-41e5-80bb-b549e575f999
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310233353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.310233353
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.1970696646
Short name T537
Test name
Test status
Simulation time 951790775 ps
CPU time 3.84 seconds
Started Jul 24 05:55:53 PM PDT 24
Finished Jul 24 05:55:57 PM PDT 24
Peak memory 224608 kb
Host smart-a0754c77-141b-4966-b53c-c90230592576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970696646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.1970696646
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.728197669
Short name T529
Test name
Test status
Simulation time 14434255 ps
CPU time 0.77 seconds
Started Jul 24 05:55:47 PM PDT 24
Finished Jul 24 05:55:48 PM PDT 24
Peak memory 205716 kb
Host smart-6cdf609e-1c58-492c-a690-b14c757bf969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728197669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.728197669
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.3926185092
Short name T38
Test name
Test status
Simulation time 51540742845 ps
CPU time 338.26 seconds
Started Jul 24 05:55:52 PM PDT 24
Finished Jul 24 06:01:30 PM PDT 24
Peak memory 265704 kb
Host smart-234ebfe6-e24d-4ff9-bd79-b85a74afa11f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926185092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.3926185092
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.1340430259
Short name T53
Test name
Test status
Simulation time 8129244061 ps
CPU time 35.62 seconds
Started Jul 24 05:55:54 PM PDT 24
Finished Jul 24 05:56:30 PM PDT 24
Peak memory 255508 kb
Host smart-45811677-5391-40c9-b7e9-7a6ee2e004d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340430259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.1340430259
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.932287342
Short name T220
Test name
Test status
Simulation time 58396493356 ps
CPU time 132.71 seconds
Started Jul 24 05:55:53 PM PDT 24
Finished Jul 24 05:58:06 PM PDT 24
Peak memory 241212 kb
Host smart-ecde21a1-a3a4-471a-990c-224603ec6ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932287342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idle
.932287342
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.3629343024
Short name T287
Test name
Test status
Simulation time 1094658100 ps
CPU time 10.77 seconds
Started Jul 24 05:55:52 PM PDT 24
Finished Jul 24 05:56:03 PM PDT 24
Peak memory 224608 kb
Host smart-627e7f52-4872-4b9e-addf-a0ebc5bd415d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629343024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.3629343024
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.3688168189
Short name T971
Test name
Test status
Simulation time 7172107140 ps
CPU time 19.78 seconds
Started Jul 24 05:55:54 PM PDT 24
Finished Jul 24 05:56:14 PM PDT 24
Peak memory 235716 kb
Host smart-6571410e-ae70-455d-a289-61d1c1e2f5df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688168189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmd
s.3688168189
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/34.spi_device_intercept.1624967925
Short name T349
Test name
Test status
Simulation time 99242140 ps
CPU time 2.13 seconds
Started Jul 24 05:55:47 PM PDT 24
Finished Jul 24 05:55:50 PM PDT 24
Peak memory 224288 kb
Host smart-8ff62db8-fe63-4415-a6fc-9f57fa0d0d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624967925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.1624967925
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.2409914190
Short name T662
Test name
Test status
Simulation time 3497635516 ps
CPU time 17.61 seconds
Started Jul 24 05:55:52 PM PDT 24
Finished Jul 24 05:56:10 PM PDT 24
Peak memory 239608 kb
Host smart-a1cacc17-8f7c-44fe-b40b-f42874029ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409914190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.2409914190
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.3254274207
Short name T481
Test name
Test status
Simulation time 651621753 ps
CPU time 4.37 seconds
Started Jul 24 05:55:47 PM PDT 24
Finished Jul 24 05:55:51 PM PDT 24
Peak memory 224656 kb
Host smart-1a648cd8-9dfa-4f55-815d-5eb6f7b969ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254274207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.3254274207
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.3440688613
Short name T342
Test name
Test status
Simulation time 1331044517 ps
CPU time 7.36 seconds
Started Jul 24 05:55:49 PM PDT 24
Finished Jul 24 05:55:56 PM PDT 24
Peak memory 224680 kb
Host smart-c23d386e-f9d5-4739-9489-f247aafd3eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440688613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.3440688613
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.538050154
Short name T1004
Test name
Test status
Simulation time 406405887 ps
CPU time 6.92 seconds
Started Jul 24 05:55:54 PM PDT 24
Finished Jul 24 05:56:01 PM PDT 24
Peak memory 222376 kb
Host smart-7dfb3c35-e507-4c41-8e28-4ff5be9a62e5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=538050154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dire
ct.538050154
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.3915085187
Short name T993
Test name
Test status
Simulation time 3052451613 ps
CPU time 48.39 seconds
Started Jul 24 05:55:56 PM PDT 24
Finished Jul 24 05:56:45 PM PDT 24
Peak memory 250124 kb
Host smart-db2dd86a-950b-47c3-8d3c-2b9fede77ffe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915085187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.3915085187
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.3809666664
Short name T517
Test name
Test status
Simulation time 1944258748 ps
CPU time 7.58 seconds
Started Jul 24 05:55:45 PM PDT 24
Finished Jul 24 05:55:53 PM PDT 24
Peak memory 216312 kb
Host smart-2460b72f-bcd3-4fcc-90b1-68e08cd72925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809666664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.3809666664
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.1613906417
Short name T756
Test name
Test status
Simulation time 53523843 ps
CPU time 1.08 seconds
Started Jul 24 05:55:49 PM PDT 24
Finished Jul 24 05:55:50 PM PDT 24
Peak memory 207264 kb
Host smart-212a01d3-b0e8-4a8a-9744-a9fc212aa54b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613906417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.1613906417
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.1863309922
Short name T844
Test name
Test status
Simulation time 146769843 ps
CPU time 1.45 seconds
Started Jul 24 05:55:48 PM PDT 24
Finished Jul 24 05:55:50 PM PDT 24
Peak memory 216380 kb
Host smart-ace0a587-57a9-49db-89db-a208e578ddd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863309922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.1863309922
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.1638257024
Short name T343
Test name
Test status
Simulation time 157498544 ps
CPU time 0.99 seconds
Started Jul 24 05:55:47 PM PDT 24
Finished Jul 24 05:55:48 PM PDT 24
Peak memory 207092 kb
Host smart-2437ab0c-0f81-4852-a2dd-92a90b932347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638257024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.1638257024
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.1817768424
Short name T905
Test name
Test status
Simulation time 547108465 ps
CPU time 5.3 seconds
Started Jul 24 05:55:53 PM PDT 24
Finished Jul 24 05:55:59 PM PDT 24
Peak memory 224700 kb
Host smart-87eae71b-3b5a-42d2-8672-172b3d1f72ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817768424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.1817768424
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.3133134708
Short name T759
Test name
Test status
Simulation time 13195611 ps
CPU time 0.7 seconds
Started Jul 24 05:55:59 PM PDT 24
Finished Jul 24 05:56:00 PM PDT 24
Peak memory 205668 kb
Host smart-dc644bf3-af6a-4e8e-bae5-427684702efb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133134708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
3133134708
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.3680052843
Short name T308
Test name
Test status
Simulation time 77650966 ps
CPU time 2.21 seconds
Started Jul 24 05:55:54 PM PDT 24
Finished Jul 24 05:55:56 PM PDT 24
Peak memory 224312 kb
Host smart-94c108de-bc89-40c6-829e-6be831c8fb9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680052843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.3680052843
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.3556147224
Short name T577
Test name
Test status
Simulation time 87395117 ps
CPU time 0.77 seconds
Started Jul 24 05:55:52 PM PDT 24
Finished Jul 24 05:55:53 PM PDT 24
Peak memory 207072 kb
Host smart-a1da749e-269c-40df-a391-5d5ab4c910f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556147224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.3556147224
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.3780859410
Short name T49
Test name
Test status
Simulation time 13670364 ps
CPU time 0.76 seconds
Started Jul 24 05:55:53 PM PDT 24
Finished Jul 24 05:55:54 PM PDT 24
Peak memory 215920 kb
Host smart-3ffc35ed-795f-4d4d-8af5-53f47eb6c00c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780859410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.3780859410
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.3831985833
Short name T996
Test name
Test status
Simulation time 63655505474 ps
CPU time 130.72 seconds
Started Jul 24 05:55:53 PM PDT 24
Finished Jul 24 05:58:04 PM PDT 24
Peak memory 249408 kb
Host smart-a92d9aa6-5ecf-421c-a9c7-337385479fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831985833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.3831985833
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.895607731
Short name T475
Test name
Test status
Simulation time 217609434 ps
CPU time 6.44 seconds
Started Jul 24 05:55:53 PM PDT 24
Finished Jul 24 05:56:00 PM PDT 24
Peak memory 232920 kb
Host smart-d6275e79-5ec8-49ac-b0f4-ff528984df0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895607731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.895607731
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_intercept.862577160
Short name T922
Test name
Test status
Simulation time 189734882 ps
CPU time 3.04 seconds
Started Jul 24 05:55:53 PM PDT 24
Finished Jul 24 05:55:57 PM PDT 24
Peak memory 232848 kb
Host smart-78cae8fe-ce02-4c32-b6e7-2be0b116d1ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862577160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.862577160
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.2027421820
Short name T718
Test name
Test status
Simulation time 612319824 ps
CPU time 6.4 seconds
Started Jul 24 05:55:52 PM PDT 24
Finished Jul 24 05:55:59 PM PDT 24
Peak memory 232892 kb
Host smart-d5a4a683-cece-43ac-bb70-e9abde986d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027421820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.2027421820
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.984948425
Short name T726
Test name
Test status
Simulation time 73831486204 ps
CPU time 15.09 seconds
Started Jul 24 05:55:53 PM PDT 24
Finished Jul 24 05:56:08 PM PDT 24
Peak memory 232952 kb
Host smart-b0454b24-83e1-4e32-886a-2652df274a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984948425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swap
.984948425
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.3841253907
Short name T317
Test name
Test status
Simulation time 291428974 ps
CPU time 2.22 seconds
Started Jul 24 05:55:54 PM PDT 24
Finished Jul 24 05:55:56 PM PDT 24
Peak memory 223200 kb
Host smart-c6b39beb-763b-4b71-946a-13b244a29cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841253907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.3841253907
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.4090521125
Short name T1005
Test name
Test status
Simulation time 3509267873 ps
CPU time 13.01 seconds
Started Jul 24 05:55:53 PM PDT 24
Finished Jul 24 05:56:06 PM PDT 24
Peak memory 223464 kb
Host smart-336d2644-fdb7-4efa-88f8-c1d2d7aead9b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4090521125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.4090521125
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.2268189904
Short name T75
Test name
Test status
Simulation time 402516443 ps
CPU time 2.51 seconds
Started Jul 24 05:55:52 PM PDT 24
Finished Jul 24 05:55:55 PM PDT 24
Peak memory 218432 kb
Host smart-6af7eae0-f3a4-4957-876c-5c6fdcda194d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268189904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.2268189904
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.1744853131
Short name T419
Test name
Test status
Simulation time 12559251611 ps
CPU time 9.15 seconds
Started Jul 24 05:55:53 PM PDT 24
Finished Jul 24 05:56:03 PM PDT 24
Peak memory 217984 kb
Host smart-6fbb3181-a876-4886-b520-96ae2bf148d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744853131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.1744853131
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.2453026016
Short name T12
Test name
Test status
Simulation time 49122140 ps
CPU time 1.42 seconds
Started Jul 24 05:55:54 PM PDT 24
Finished Jul 24 05:55:56 PM PDT 24
Peak memory 208284 kb
Host smart-1010f949-9820-4e63-ac98-aeca783d8a36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453026016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.2453026016
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.2753200381
Short name T369
Test name
Test status
Simulation time 19246516 ps
CPU time 0.74 seconds
Started Jul 24 05:55:51 PM PDT 24
Finished Jul 24 05:55:52 PM PDT 24
Peak memory 206108 kb
Host smart-179c034b-d030-4122-b2fd-94e5ffcd451b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753200381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.2753200381
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.4075183431
Short name T929
Test name
Test status
Simulation time 977675860 ps
CPU time 4.52 seconds
Started Jul 24 05:55:53 PM PDT 24
Finished Jul 24 05:55:58 PM PDT 24
Peak memory 224608 kb
Host smart-4b0e0dfe-7f3b-4095-99e4-e4e515a6d1cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075183431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.4075183431
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.3296482345
Short name T352
Test name
Test status
Simulation time 42680276 ps
CPU time 0.69 seconds
Started Jul 24 05:55:56 PM PDT 24
Finished Jul 24 05:55:57 PM PDT 24
Peak memory 205020 kb
Host smart-8b050a7c-75db-4c4d-a665-c634936e5b45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296482345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
3296482345
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.1682385054
Short name T226
Test name
Test status
Simulation time 41810404 ps
CPU time 2.83 seconds
Started Jul 24 05:55:59 PM PDT 24
Finished Jul 24 05:56:02 PM PDT 24
Peak memory 232788 kb
Host smart-4af3d368-9b2c-4c89-8650-d397d38dd9de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682385054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.1682385054
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.2642816583
Short name T441
Test name
Test status
Simulation time 20384734 ps
CPU time 0.81 seconds
Started Jul 24 05:56:00 PM PDT 24
Finished Jul 24 05:56:01 PM PDT 24
Peak memory 206704 kb
Host smart-dd454d6c-adcc-4590-b827-041139b9c466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642816583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.2642816583
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.286153690
Short name T166
Test name
Test status
Simulation time 4848734995 ps
CPU time 16.12 seconds
Started Jul 24 05:56:01 PM PDT 24
Finished Jul 24 05:56:17 PM PDT 24
Peak memory 249264 kb
Host smart-1f5b289f-00b3-4c9f-a813-07fb092a0be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286153690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.286153690
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.3806304323
Short name T275
Test name
Test status
Simulation time 90535681498 ps
CPU time 316.52 seconds
Started Jul 24 05:56:00 PM PDT 24
Finished Jul 24 06:01:17 PM PDT 24
Peak memory 264928 kb
Host smart-2c3a88e7-582d-4929-b85e-3cb621db1f52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806304323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.3806304323
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.898023446
Short name T582
Test name
Test status
Simulation time 200899566 ps
CPU time 6.14 seconds
Started Jul 24 05:55:57 PM PDT 24
Finished Jul 24 05:56:03 PM PDT 24
Peak memory 221996 kb
Host smart-cb85a27a-8516-4405-b8e3-6823126b30c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898023446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.898023446
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.636058717
Short name T858
Test name
Test status
Simulation time 30650671693 ps
CPU time 228.43 seconds
Started Jul 24 05:56:02 PM PDT 24
Finished Jul 24 05:59:50 PM PDT 24
Peak memory 255952 kb
Host smart-27723d94-77c4-4685-a478-74e8c1ae5f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636058717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmds
.636058717
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_intercept.3106848373
Short name T41
Test name
Test status
Simulation time 337221767 ps
CPU time 5.1 seconds
Started Jul 24 05:56:07 PM PDT 24
Finished Jul 24 05:56:12 PM PDT 24
Peak memory 224624 kb
Host smart-562077bd-d9ae-4e64-b2ee-9a332b511c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106848373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.3106848373
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.2872965926
Short name T737
Test name
Test status
Simulation time 15894913552 ps
CPU time 111.5 seconds
Started Jul 24 05:55:58 PM PDT 24
Finished Jul 24 05:57:50 PM PDT 24
Peak memory 224768 kb
Host smart-55052bfd-1291-4924-ac0e-ffeab6fc4bd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872965926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.2872965926
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.4253928457
Short name T239
Test name
Test status
Simulation time 269961779 ps
CPU time 2.79 seconds
Started Jul 24 05:55:56 PM PDT 24
Finished Jul 24 05:55:59 PM PDT 24
Peak memory 232856 kb
Host smart-823293f0-c9ca-4c10-a886-d0ff17410c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253928457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.4253928457
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.1470302264
Short name T600
Test name
Test status
Simulation time 97014439 ps
CPU time 2.28 seconds
Started Jul 24 05:56:02 PM PDT 24
Finished Jul 24 05:56:05 PM PDT 24
Peak memory 232556 kb
Host smart-bd3c6f76-1bc9-4fe4-8e60-b6c098eae64b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470302264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.1470302264
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.736863395
Short name T803
Test name
Test status
Simulation time 175069343 ps
CPU time 4.51 seconds
Started Jul 24 05:56:00 PM PDT 24
Finished Jul 24 05:56:04 PM PDT 24
Peak memory 220620 kb
Host smart-339f8956-5112-4d44-85bb-ce1e4c43f0d0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=736863395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dire
ct.736863395
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.3866300503
Short name T21
Test name
Test status
Simulation time 10574272166 ps
CPU time 51.72 seconds
Started Jul 24 05:55:58 PM PDT 24
Finished Jul 24 05:56:50 PM PDT 24
Peak memory 256760 kb
Host smart-b3f05f64-6b33-44f8-ad00-4b308b17a00e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866300503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.3866300503
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.3120318606
Short name T775
Test name
Test status
Simulation time 28413411122 ps
CPU time 37.19 seconds
Started Jul 24 05:56:01 PM PDT 24
Finished Jul 24 05:56:38 PM PDT 24
Peak memory 216520 kb
Host smart-144f0510-5ac4-4a30-b988-b01a7f1bdbf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120318606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.3120318606
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.2091062769
Short name T487
Test name
Test status
Simulation time 341776577 ps
CPU time 3.07 seconds
Started Jul 24 05:55:56 PM PDT 24
Finished Jul 24 05:56:00 PM PDT 24
Peak memory 216372 kb
Host smart-733c38e3-0ac0-4bd5-83c5-70256ee193f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091062769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.2091062769
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.8479785
Short name T669
Test name
Test status
Simulation time 353169353 ps
CPU time 2.45 seconds
Started Jul 24 05:56:00 PM PDT 24
Finished Jul 24 05:56:02 PM PDT 24
Peak memory 216364 kb
Host smart-4a184101-8585-41ac-83d3-b656829b623b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8479785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.8479785
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.3439403452
Short name T427
Test name
Test status
Simulation time 105903288 ps
CPU time 0.86 seconds
Started Jul 24 05:55:57 PM PDT 24
Finished Jul 24 05:55:58 PM PDT 24
Peak memory 206032 kb
Host smart-10d85644-bd04-466c-b6a6-4e32abfc5630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439403452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.3439403452
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.3485151413
Short name T576
Test name
Test status
Simulation time 1729806964 ps
CPU time 4.15 seconds
Started Jul 24 05:56:07 PM PDT 24
Finished Jul 24 05:56:11 PM PDT 24
Peak memory 236500 kb
Host smart-1b33d74b-f690-4a7d-98c0-4c10d28f63f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485151413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.3485151413
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.2902045754
Short name T967
Test name
Test status
Simulation time 21940626 ps
CPU time 0.81 seconds
Started Jul 24 05:56:01 PM PDT 24
Finished Jul 24 05:56:02 PM PDT 24
Peak memory 204992 kb
Host smart-02d9e716-9c62-4558-b346-e908822877a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902045754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
2902045754
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.532592800
Short name T940
Test name
Test status
Simulation time 54139135 ps
CPU time 2.72 seconds
Started Jul 24 05:56:01 PM PDT 24
Finished Jul 24 05:56:04 PM PDT 24
Peak memory 232580 kb
Host smart-2c6fce61-2b2d-4106-aacc-0b146fdce9cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532592800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.532592800
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.3179969920
Short name T949
Test name
Test status
Simulation time 167830267 ps
CPU time 0.8 seconds
Started Jul 24 05:55:57 PM PDT 24
Finished Jul 24 05:55:58 PM PDT 24
Peak memory 206696 kb
Host smart-b72fa998-e1e2-48a0-b6c3-4b0b7c015ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179969920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.3179969920
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.3353159366
Short name T471
Test name
Test status
Simulation time 4587112387 ps
CPU time 33.03 seconds
Started Jul 24 05:55:59 PM PDT 24
Finished Jul 24 05:56:33 PM PDT 24
Peak memory 241160 kb
Host smart-d528ffef-c89d-4db0-b1bf-cc7d4a4b85a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353159366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.3353159366
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.1379173586
Short name T588
Test name
Test status
Simulation time 5669107396 ps
CPU time 63.26 seconds
Started Jul 24 05:55:58 PM PDT 24
Finished Jul 24 05:57:02 PM PDT 24
Peak memory 249328 kb
Host smart-14cfc1d8-c242-4014-a9dd-5aa45cf19fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379173586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.1379173586
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.4155540535
Short name T812
Test name
Test status
Simulation time 216613005593 ps
CPU time 198.11 seconds
Started Jul 24 05:56:00 PM PDT 24
Finished Jul 24 05:59:18 PM PDT 24
Peak memory 250088 kb
Host smart-767c3016-cd2d-4b30-8941-b46aa7d2a2ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155540535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.4155540535
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.3088166977
Short name T395
Test name
Test status
Simulation time 711604613 ps
CPU time 17.14 seconds
Started Jul 24 05:55:56 PM PDT 24
Finished Jul 24 05:56:13 PM PDT 24
Peak memory 233448 kb
Host smart-839026b2-2256-48de-b255-4981bc39525a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088166977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.3088166977
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.869811108
Short name T877
Test name
Test status
Simulation time 6226110176 ps
CPU time 54.37 seconds
Started Jul 24 05:55:58 PM PDT 24
Finished Jul 24 05:56:53 PM PDT 24
Peak memory 237632 kb
Host smart-d7bcfbea-1ff7-4848-93d5-843d1f22187a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869811108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmds
.869811108
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_intercept.4048907268
Short name T207
Test name
Test status
Simulation time 3059591806 ps
CPU time 16.69 seconds
Started Jul 24 05:55:59 PM PDT 24
Finished Jul 24 05:56:16 PM PDT 24
Peak memory 232936 kb
Host smart-832b6fca-c91b-43ae-96d4-7442cb6a224f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048907268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.4048907268
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.3896198834
Short name T560
Test name
Test status
Simulation time 2630709209 ps
CPU time 25.1 seconds
Started Jul 24 05:55:57 PM PDT 24
Finished Jul 24 05:56:22 PM PDT 24
Peak memory 235324 kb
Host smart-b00060c1-c685-443d-b1e0-3296a7229ea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896198834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.3896198834
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.1233446524
Short name T745
Test name
Test status
Simulation time 304601374 ps
CPU time 3.03 seconds
Started Jul 24 05:56:07 PM PDT 24
Finished Jul 24 05:56:10 PM PDT 24
Peak memory 232800 kb
Host smart-094927e6-8527-4a17-8a70-352887e65055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233446524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.1233446524
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.725136644
Short name T1002
Test name
Test status
Simulation time 48536671 ps
CPU time 2.38 seconds
Started Jul 24 05:55:57 PM PDT 24
Finished Jul 24 05:56:00 PM PDT 24
Peak memory 224640 kb
Host smart-30ea17d4-346e-4322-88fc-8728b08f3551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725136644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.725136644
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.1145426652
Short name T459
Test name
Test status
Simulation time 485607533 ps
CPU time 9.52 seconds
Started Jul 24 05:56:03 PM PDT 24
Finished Jul 24 05:56:12 PM PDT 24
Peak memory 220672 kb
Host smart-5b9964fc-573f-4c7e-89da-93bafdec6716
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1145426652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.1145426652
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.1581982316
Short name T663
Test name
Test status
Simulation time 395987112387 ps
CPU time 593.39 seconds
Started Jul 24 05:56:00 PM PDT 24
Finished Jul 24 06:05:53 PM PDT 24
Peak memory 272588 kb
Host smart-ecea246a-5fe6-494c-a432-c510df2ff170
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581982316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.1581982316
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.3467563967
Short name T781
Test name
Test status
Simulation time 1420466638 ps
CPU time 12.99 seconds
Started Jul 24 05:56:01 PM PDT 24
Finished Jul 24 05:56:14 PM PDT 24
Peak memory 216628 kb
Host smart-937feeb9-acaf-42c9-b8d8-965594c5fa8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467563967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.3467563967
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.2008702060
Short name T884
Test name
Test status
Simulation time 5929021574 ps
CPU time 8.5 seconds
Started Jul 24 05:55:58 PM PDT 24
Finished Jul 24 05:56:07 PM PDT 24
Peak memory 216548 kb
Host smart-cb22281b-b904-4cd1-a5d9-93b336cae065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008702060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.2008702060
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.3224188375
Short name T356
Test name
Test status
Simulation time 97514096 ps
CPU time 2.14 seconds
Started Jul 24 05:56:07 PM PDT 24
Finished Jul 24 05:56:09 PM PDT 24
Peak memory 216368 kb
Host smart-344a7555-3019-4767-81e7-fbb8ecba4ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224188375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.3224188375
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.1089371731
Short name T541
Test name
Test status
Simulation time 62880437 ps
CPU time 0.91 seconds
Started Jul 24 05:56:07 PM PDT 24
Finished Jul 24 05:56:08 PM PDT 24
Peak memory 206092 kb
Host smart-7e63fc7a-46de-4a4e-8abc-0d24cd041097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089371731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.1089371731
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.2800888449
Short name T160
Test name
Test status
Simulation time 15882179348 ps
CPU time 13.38 seconds
Started Jul 24 05:55:59 PM PDT 24
Finished Jul 24 05:56:12 PM PDT 24
Peak memory 232916 kb
Host smart-8572e842-d7f5-4000-b087-3e9ee7c22596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800888449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.2800888449
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.2623762227
Short name T390
Test name
Test status
Simulation time 13790321 ps
CPU time 0.72 seconds
Started Jul 24 05:56:04 PM PDT 24
Finished Jul 24 05:56:05 PM PDT 24
Peak memory 205004 kb
Host smart-1628c12d-d7b4-44a6-98a6-a2025983a7bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623762227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
2623762227
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.852673496
Short name T472
Test name
Test status
Simulation time 2358302404 ps
CPU time 8.39 seconds
Started Jul 24 05:56:04 PM PDT 24
Finished Jul 24 05:56:13 PM PDT 24
Peak memory 224680 kb
Host smart-0789a114-3713-4d43-8fce-43eda0104756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852673496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.852673496
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.4153285332
Short name T325
Test name
Test status
Simulation time 63262544 ps
CPU time 0.79 seconds
Started Jul 24 05:55:59 PM PDT 24
Finished Jul 24 05:56:00 PM PDT 24
Peak memory 207028 kb
Host smart-38255c7d-4ebd-481c-bc31-c5a6538e8798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153285332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.4153285332
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.3230908932
Short name T734
Test name
Test status
Simulation time 8134899747 ps
CPU time 14.54 seconds
Started Jul 24 05:56:05 PM PDT 24
Finished Jul 24 05:56:19 PM PDT 24
Peak memory 234524 kb
Host smart-028949a2-a0e8-4863-b491-1d6a44103fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230908932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.3230908932
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.750493626
Short name T990
Test name
Test status
Simulation time 5888840438 ps
CPU time 39.22 seconds
Started Jul 24 05:56:04 PM PDT 24
Finished Jul 24 05:56:43 PM PDT 24
Peak memory 238972 kb
Host smart-ea5cd6ad-4b90-403b-bc16-6da89a6d38ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750493626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.750493626
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.768259139
Short name T440
Test name
Test status
Simulation time 46269631130 ps
CPU time 128.12 seconds
Started Jul 24 05:56:07 PM PDT 24
Finished Jul 24 05:58:15 PM PDT 24
Peak memory 249260 kb
Host smart-ba1fac94-4d50-4a7d-b8bb-4d95f6307ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768259139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idle
.768259139
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.2762037006
Short name T592
Test name
Test status
Simulation time 197200016 ps
CPU time 5.25 seconds
Started Jul 24 05:56:06 PM PDT 24
Finished Jul 24 05:56:11 PM PDT 24
Peak memory 232844 kb
Host smart-d7f983ed-328e-4c61-bdbf-1338730a78f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762037006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.2762037006
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.918059583
Short name T628
Test name
Test status
Simulation time 96819274805 ps
CPU time 168.82 seconds
Started Jul 24 05:56:05 PM PDT 24
Finished Jul 24 05:58:54 PM PDT 24
Peak memory 254620 kb
Host smart-f004f6d7-4fa4-43ae-b430-83e608a78ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918059583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmds
.918059583
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_intercept.2294300397
Short name T687
Test name
Test status
Simulation time 104250124 ps
CPU time 2.33 seconds
Started Jul 24 05:56:04 PM PDT 24
Finished Jul 24 05:56:06 PM PDT 24
Peak memory 223204 kb
Host smart-7d10756d-6f5d-4a14-aef2-de5ac0301ebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294300397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.2294300397
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.763853804
Short name T932
Test name
Test status
Simulation time 2880102177 ps
CPU time 14.76 seconds
Started Jul 24 05:56:05 PM PDT 24
Finished Jul 24 05:56:20 PM PDT 24
Peak memory 232920 kb
Host smart-dd4d68e7-0c22-4b17-8172-c57bb80b6070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763853804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.763853804
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.989391798
Short name T242
Test name
Test status
Simulation time 1400371254 ps
CPU time 7.46 seconds
Started Jul 24 05:56:03 PM PDT 24
Finished Jul 24 05:56:10 PM PDT 24
Peak memory 232868 kb
Host smart-166208b9-cfc6-4fc2-a42f-3c347ebde326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989391798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swap
.989391798
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.3186967461
Short name T750
Test name
Test status
Simulation time 5673477487 ps
CPU time 6.78 seconds
Started Jul 24 05:56:04 PM PDT 24
Finished Jul 24 05:56:11 PM PDT 24
Peak memory 224580 kb
Host smart-f1cb54e0-ec33-4af5-a6cf-a8772b4bb1b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186967461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.3186967461
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.4015205217
Short name T892
Test name
Test status
Simulation time 1634782411 ps
CPU time 5.01 seconds
Started Jul 24 05:56:07 PM PDT 24
Finished Jul 24 05:56:12 PM PDT 24
Peak memory 222804 kb
Host smart-70d5db47-df26-40da-afc4-d587c83dbd24
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4015205217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.4015205217
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.4239679954
Short name T670
Test name
Test status
Simulation time 38454211197 ps
CPU time 321.35 seconds
Started Jul 24 05:56:07 PM PDT 24
Finished Jul 24 06:01:29 PM PDT 24
Peak memory 250368 kb
Host smart-40053266-5957-475f-9f5a-b18efb3f0ff2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239679954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.4239679954
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.1879193955
Short name T823
Test name
Test status
Simulation time 32612269681 ps
CPU time 41.7 seconds
Started Jul 24 05:56:04 PM PDT 24
Finished Jul 24 05:56:46 PM PDT 24
Peak memory 216440 kb
Host smart-c0a77a2e-0383-4109-860e-cf164c7a90f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879193955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.1879193955
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.1779847662
Short name T406
Test name
Test status
Simulation time 83989784427 ps
CPU time 13.3 seconds
Started Jul 24 05:56:07 PM PDT 24
Finished Jul 24 05:56:20 PM PDT 24
Peak memory 216512 kb
Host smart-53756dbd-872d-4b09-8d10-4b65d9f388da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779847662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.1779847662
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.4249380889
Short name T8
Test name
Test status
Simulation time 11921453 ps
CPU time 0.71 seconds
Started Jul 24 05:56:05 PM PDT 24
Finished Jul 24 05:56:06 PM PDT 24
Peak memory 205788 kb
Host smart-d69eb2e6-decc-426b-a18f-7cb663a97cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249380889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.4249380889
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.3417773211
Short name T816
Test name
Test status
Simulation time 96284116 ps
CPU time 1.04 seconds
Started Jul 24 05:56:05 PM PDT 24
Finished Jul 24 05:56:06 PM PDT 24
Peak memory 207104 kb
Host smart-93aae189-ad71-4492-a5ec-8aaee46e5b6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417773211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.3417773211
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.3164202679
Short name T109
Test name
Test status
Simulation time 2031406180 ps
CPU time 7.13 seconds
Started Jul 24 05:56:03 PM PDT 24
Finished Jul 24 05:56:10 PM PDT 24
Peak memory 232876 kb
Host smart-bbb4dc1a-3790-4e20-8431-1ddeb7bf915d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164202679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.3164202679
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.4201503926
Short name T384
Test name
Test status
Simulation time 28431466 ps
CPU time 0.72 seconds
Started Jul 24 05:56:10 PM PDT 24
Finished Jul 24 05:56:10 PM PDT 24
Peak memory 205568 kb
Host smart-fbce714a-cda5-4e10-86e6-a4bfbc737226
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201503926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
4201503926
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.3601727051
Short name T619
Test name
Test status
Simulation time 200712519 ps
CPU time 3.67 seconds
Started Jul 24 05:56:05 PM PDT 24
Finished Jul 24 05:56:09 PM PDT 24
Peak memory 224628 kb
Host smart-72321cc5-8f38-449f-a77a-bbc4337c9675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601727051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.3601727051
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.2853082857
Short name T449
Test name
Test status
Simulation time 177720915 ps
CPU time 0.74 seconds
Started Jul 24 05:56:05 PM PDT 24
Finished Jul 24 05:56:05 PM PDT 24
Peak memory 206008 kb
Host smart-06e2ce51-6051-42fa-a5ae-f799736acced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853082857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.2853082857
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.1400676689
Short name T164
Test name
Test status
Simulation time 1740540063 ps
CPU time 37.9 seconds
Started Jul 24 05:56:10 PM PDT 24
Finished Jul 24 05:56:48 PM PDT 24
Peak memory 249672 kb
Host smart-2e3713c9-dad7-4509-8d23-fd5e60def62d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400676689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.1400676689
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.2530585931
Short name T400
Test name
Test status
Simulation time 3193597493 ps
CPU time 23.99 seconds
Started Jul 24 05:56:08 PM PDT 24
Finished Jul 24 05:56:32 PM PDT 24
Peak memory 252400 kb
Host smart-fcc3f8f9-21e6-4f3e-9b6a-4007e2bea8f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530585931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.2530585931
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.2141908635
Short name T289
Test name
Test status
Simulation time 4031812863 ps
CPU time 59.57 seconds
Started Jul 24 05:56:10 PM PDT 24
Finished Jul 24 05:57:10 PM PDT 24
Peak memory 233248 kb
Host smart-7ff1f829-b3b2-4c90-82ab-7fbea49fb3ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141908635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.2141908635
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.1104239127
Short name T999
Test name
Test status
Simulation time 24670756572 ps
CPU time 78.82 seconds
Started Jul 24 05:56:09 PM PDT 24
Finished Jul 24 05:57:28 PM PDT 24
Peak memory 255480 kb
Host smart-62117459-fdee-4702-811a-95752d934628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104239127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmd
s.1104239127
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/39.spi_device_intercept.2568717900
Short name T479
Test name
Test status
Simulation time 64411023 ps
CPU time 2.67 seconds
Started Jul 24 05:56:05 PM PDT 24
Finished Jul 24 05:56:08 PM PDT 24
Peak memory 224704 kb
Host smart-25ca61bc-ef68-4ba8-b41e-883593ed3c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568717900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.2568717900
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.2787590996
Short name T420
Test name
Test status
Simulation time 2278497734 ps
CPU time 12.09 seconds
Started Jul 24 05:56:04 PM PDT 24
Finished Jul 24 05:56:17 PM PDT 24
Peak memory 234280 kb
Host smart-52dc22d9-678f-478e-adcd-d4e8f78ae65a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787590996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.2787590996
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.3306053722
Short name T790
Test name
Test status
Simulation time 29158674 ps
CPU time 2.01 seconds
Started Jul 24 05:56:04 PM PDT 24
Finished Jul 24 05:56:06 PM PDT 24
Peak memory 224176 kb
Host smart-d9383e69-b2d7-422a-a03c-a24429322f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306053722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.3306053722
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.4192733403
Short name T127
Test name
Test status
Simulation time 5415758159 ps
CPU time 16.52 seconds
Started Jul 24 05:56:05 PM PDT 24
Finished Jul 24 05:56:22 PM PDT 24
Peak memory 249904 kb
Host smart-e8281cbc-18b1-41bf-a689-8c811c826a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192733403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.4192733403
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.1321037720
Short name T857
Test name
Test status
Simulation time 116476683 ps
CPU time 3.95 seconds
Started Jul 24 05:56:09 PM PDT 24
Finished Jul 24 05:56:13 PM PDT 24
Peak memory 222856 kb
Host smart-c98d0b2b-1daa-4231-9484-83bc3aef3d1d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1321037720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.1321037720
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.1532693409
Short name T955
Test name
Test status
Simulation time 26625881107 ps
CPU time 118.18 seconds
Started Jul 24 05:56:11 PM PDT 24
Finished Jul 24 05:58:09 PM PDT 24
Peak memory 255528 kb
Host smart-ce5a140d-79ea-41f1-a025-d439cbb4f5e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532693409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.1532693409
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.1143432904
Short name T300
Test name
Test status
Simulation time 983513131 ps
CPU time 7.08 seconds
Started Jul 24 05:56:07 PM PDT 24
Finished Jul 24 05:56:14 PM PDT 24
Peak memory 216380 kb
Host smart-3ff1d502-44e9-49cb-8342-68c454b0f79c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143432904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.1143432904
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.3133080057
Short name T585
Test name
Test status
Simulation time 638968311 ps
CPU time 4.62 seconds
Started Jul 24 05:56:07 PM PDT 24
Finished Jul 24 05:56:12 PM PDT 24
Peak memory 216428 kb
Host smart-10d874dc-57c1-4753-9ee5-afb431d9ae09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133080057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.3133080057
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.271922173
Short name T679
Test name
Test status
Simulation time 171185792 ps
CPU time 1.68 seconds
Started Jul 24 05:56:06 PM PDT 24
Finished Jul 24 05:56:08 PM PDT 24
Peak memory 216376 kb
Host smart-8f37050f-12bf-434e-b4fd-09b3162d4d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271922173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.271922173
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.497134265
Short name T329
Test name
Test status
Simulation time 27342533 ps
CPU time 0.76 seconds
Started Jul 24 05:56:04 PM PDT 24
Finished Jul 24 05:56:05 PM PDT 24
Peak memory 206064 kb
Host smart-3fa94adc-1a91-42e5-aceb-90b3dc9324f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497134265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.497134265
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.2822724232
Short name T218
Test name
Test status
Simulation time 1872588550 ps
CPU time 7.99 seconds
Started Jul 24 05:56:01 PM PDT 24
Finished Jul 24 05:56:09 PM PDT 24
Peak memory 232816 kb
Host smart-9a0ebbad-add6-4699-869e-6481d0709f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822724232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.2822724232
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.1023627674
Short name T504
Test name
Test status
Simulation time 11851927 ps
CPU time 0.74 seconds
Started Jul 24 05:54:07 PM PDT 24
Finished Jul 24 05:54:08 PM PDT 24
Peak memory 204956 kb
Host smart-f2474c3c-a204-489a-9024-72266a06c48d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023627674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.1
023627674
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.3929498738
Short name T934
Test name
Test status
Simulation time 1880670487 ps
CPU time 11.96 seconds
Started Jul 24 05:54:04 PM PDT 24
Finished Jul 24 05:54:16 PM PDT 24
Peak memory 224712 kb
Host smart-ea13a765-20e8-436c-918c-2adf3146ce41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929498738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.3929498738
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.442432032
Short name T808
Test name
Test status
Simulation time 122501299 ps
CPU time 0.82 seconds
Started Jul 24 05:54:02 PM PDT 24
Finished Jul 24 05:54:04 PM PDT 24
Peak memory 206740 kb
Host smart-cf40b263-f728-40f7-ad41-16c36261070f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442432032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.442432032
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.2444536137
Short name T422
Test name
Test status
Simulation time 5796062617 ps
CPU time 21.09 seconds
Started Jul 24 05:54:09 PM PDT 24
Finished Jul 24 05:54:30 PM PDT 24
Peak memory 224824 kb
Host smart-a17b21f0-e2ee-47db-9623-56d5846009ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444536137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.2444536137
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.590693700
Short name T491
Test name
Test status
Simulation time 5885427177 ps
CPU time 62.98 seconds
Started Jul 24 05:54:02 PM PDT 24
Finished Jul 24 05:55:05 PM PDT 24
Peak memory 249552 kb
Host smart-2f46cd4f-a651-4887-9f45-c9c0cea389c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590693700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.590693700
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.4710244
Short name T40
Test name
Test status
Simulation time 214215362369 ps
CPU time 464.17 seconds
Started Jul 24 05:54:06 PM PDT 24
Finished Jul 24 06:01:50 PM PDT 24
Peak memory 262272 kb
Host smart-56341df6-4a46-4447-8e1b-a249235ed216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4710244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle.4710244
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.937235180
Short name T815
Test name
Test status
Simulation time 2907568790 ps
CPU time 44.5 seconds
Started Jul 24 05:54:02 PM PDT 24
Finished Jul 24 05:54:47 PM PDT 24
Peak memory 224712 kb
Host smart-0b86e19f-9594-4959-ba4f-fdb8bb19664b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937235180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.937235180
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.2291715995
Short name T42
Test name
Test status
Simulation time 27520984016 ps
CPU time 99.76 seconds
Started Jul 24 05:54:04 PM PDT 24
Finished Jul 24 05:55:44 PM PDT 24
Peak memory 253300 kb
Host smart-887d81de-60cb-43d5-a618-353021d03ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291715995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds
.2291715995
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/4.spi_device_intercept.1886134144
Short name T880
Test name
Test status
Simulation time 664933548 ps
CPU time 6.87 seconds
Started Jul 24 05:54:04 PM PDT 24
Finished Jul 24 05:54:11 PM PDT 24
Peak memory 224612 kb
Host smart-ab5948ac-bad7-454f-8332-a19b19f30e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886134144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.1886134144
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.2024827559
Short name T489
Test name
Test status
Simulation time 1274536926 ps
CPU time 12.34 seconds
Started Jul 24 05:54:03 PM PDT 24
Finished Jul 24 05:54:15 PM PDT 24
Peak memory 232908 kb
Host smart-afb9402d-f34d-4a3c-9665-72d2cdac27d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024827559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.2024827559
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.175378682
Short name T416
Test name
Test status
Simulation time 1067196212 ps
CPU time 5.77 seconds
Started Jul 24 05:54:03 PM PDT 24
Finished Jul 24 05:54:09 PM PDT 24
Peak memory 224684 kb
Host smart-09115f88-ae0a-4390-9df5-e32c1dfa68a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175378682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap.
175378682
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.2264262380
Short name T495
Test name
Test status
Simulation time 6413185321 ps
CPU time 18.72 seconds
Started Jul 24 05:54:02 PM PDT 24
Finished Jul 24 05:54:21 PM PDT 24
Peak memory 232876 kb
Host smart-f0cd62d0-368b-445f-91c5-6029891a4b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264262380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.2264262380
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.2616791229
Short name T800
Test name
Test status
Simulation time 84801759 ps
CPU time 3.88 seconds
Started Jul 24 05:54:03 PM PDT 24
Finished Jul 24 05:54:07 PM PDT 24
Peak memory 222720 kb
Host smart-dc34e76d-2f2a-4b2d-a825-76ce156e8947
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2616791229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.2616791229
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.2379753433
Short name T63
Test name
Test status
Simulation time 123181539 ps
CPU time 1.24 seconds
Started Jul 24 05:54:09 PM PDT 24
Finished Jul 24 05:54:11 PM PDT 24
Peak memory 236468 kb
Host smart-a4a14663-064a-4a36-8439-823eb1cfed30
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379753433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.2379753433
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.448097
Short name T263
Test name
Test status
Simulation time 50642440351 ps
CPU time 205.29 seconds
Started Jul 24 05:54:03 PM PDT 24
Finished Jul 24 05:57:29 PM PDT 24
Peak memory 267396 kb
Host smart-d22cb18f-91f5-4a3f-859c-d264bed3c028
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stress_all.448097
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.3823940003
Short name T826
Test name
Test status
Simulation time 1453642070 ps
CPU time 10.06 seconds
Started Jul 24 05:54:04 PM PDT 24
Finished Jul 24 05:54:15 PM PDT 24
Peak memory 216468 kb
Host smart-ae998a72-c98d-4b7d-a6ff-5b775f7f2ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823940003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.3823940003
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.570646108
Short name T532
Test name
Test status
Simulation time 38936013153 ps
CPU time 13.98 seconds
Started Jul 24 05:54:02 PM PDT 24
Finished Jul 24 05:54:16 PM PDT 24
Peak memory 216656 kb
Host smart-4b0b6df5-a801-4609-86b1-7347937a6594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570646108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.570646108
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.2281434404
Short name T747
Test name
Test status
Simulation time 96363784 ps
CPU time 1.61 seconds
Started Jul 24 05:54:00 PM PDT 24
Finished Jul 24 05:54:02 PM PDT 24
Peak memory 216456 kb
Host smart-9940925a-e27d-4497-aa6f-12e1be05ef38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281434404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.2281434404
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.729807165
Short name T353
Test name
Test status
Simulation time 262187475 ps
CPU time 1 seconds
Started Jul 24 05:54:06 PM PDT 24
Finished Jul 24 05:54:07 PM PDT 24
Peak memory 207192 kb
Host smart-68f52141-ed56-4714-974f-48bfa24b59e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729807165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.729807165
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.1103783931
Short name T206
Test name
Test status
Simulation time 1787730922 ps
CPU time 11.38 seconds
Started Jul 24 05:54:02 PM PDT 24
Finished Jul 24 05:54:14 PM PDT 24
Peak memory 236000 kb
Host smart-ca9ccc3d-4939-4878-9c6a-a97af10b25d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103783931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.1103783931
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.4120158244
Short name T315
Test name
Test status
Simulation time 20565085 ps
CPU time 0.75 seconds
Started Jul 24 05:56:21 PM PDT 24
Finished Jul 24 05:56:21 PM PDT 24
Peak memory 204956 kb
Host smart-6839a211-03d2-4b29-8de6-6a8886e8cd87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120158244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
4120158244
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.322740856
Short name T838
Test name
Test status
Simulation time 331884624 ps
CPU time 4.16 seconds
Started Jul 24 05:56:09 PM PDT 24
Finished Jul 24 05:56:14 PM PDT 24
Peak memory 224760 kb
Host smart-2223b43c-3baf-4fd1-918f-803f8d82162e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322740856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.322740856
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.2751539901
Short name T319
Test name
Test status
Simulation time 67606207 ps
CPU time 0.82 seconds
Started Jul 24 05:56:12 PM PDT 24
Finished Jul 24 05:56:13 PM PDT 24
Peak memory 206764 kb
Host smart-d1101494-f508-42bb-9680-257b1fdd6b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751539901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.2751539901
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.573774056
Short name T185
Test name
Test status
Simulation time 9566676879 ps
CPU time 64.58 seconds
Started Jul 24 05:56:09 PM PDT 24
Finished Jul 24 05:57:13 PM PDT 24
Peak memory 256472 kb
Host smart-de50795f-4dcb-4ea5-a557-20a318f30331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573774056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.573774056
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.1640175375
Short name T820
Test name
Test status
Simulation time 39557046 ps
CPU time 0.85 seconds
Started Jul 24 05:56:08 PM PDT 24
Finished Jul 24 05:56:09 PM PDT 24
Peak memory 217208 kb
Host smart-655d55f0-d71b-4ec0-9525-45177c98914b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640175375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.1640175375
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.263706290
Short name T456
Test name
Test status
Simulation time 13323116237 ps
CPU time 51.11 seconds
Started Jul 24 05:56:23 PM PDT 24
Finished Jul 24 05:57:15 PM PDT 24
Peak memory 224744 kb
Host smart-3fe3fadd-32cc-470f-a973-01aa110aaf22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263706290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idle
.263706290
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.2588793341
Short name T758
Test name
Test status
Simulation time 794540612 ps
CPU time 14.05 seconds
Started Jul 24 05:56:08 PM PDT 24
Finished Jul 24 05:56:22 PM PDT 24
Peak memory 241088 kb
Host smart-ad193bd6-2c1f-42a7-87a4-1ac28d75ca84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588793341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.2588793341
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.4017654338
Short name T796
Test name
Test status
Simulation time 16889945429 ps
CPU time 68.84 seconds
Started Jul 24 05:57:21 PM PDT 24
Finished Jul 24 05:58:30 PM PDT 24
Peak memory 257576 kb
Host smart-f52e357f-afa4-45a1-a80b-b38a478e9e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017654338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmd
s.4017654338
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_intercept.2231384128
Short name T224
Test name
Test status
Simulation time 385631644 ps
CPU time 3.63 seconds
Started Jul 24 05:56:13 PM PDT 24
Finished Jul 24 05:56:16 PM PDT 24
Peak memory 224644 kb
Host smart-72382e02-c957-4555-8bb4-a8c6263a9d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231384128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.2231384128
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.3176130566
Short name T593
Test name
Test status
Simulation time 3171218069 ps
CPU time 11.06 seconds
Started Jul 24 05:56:09 PM PDT 24
Finished Jul 24 05:56:20 PM PDT 24
Peak memory 232884 kb
Host smart-e3f603ee-e19a-410c-b717-4eac2a6c916d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176130566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.3176130566
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.3775773767
Short name T930
Test name
Test status
Simulation time 71520949 ps
CPU time 2.76 seconds
Started Jul 24 05:56:11 PM PDT 24
Finished Jul 24 05:56:13 PM PDT 24
Peak memory 232864 kb
Host smart-e213376d-ea4f-49fa-b614-310f84990017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775773767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.3775773767
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.3855030264
Short name T379
Test name
Test status
Simulation time 1020767685 ps
CPU time 6.75 seconds
Started Jul 24 05:56:12 PM PDT 24
Finished Jul 24 05:56:19 PM PDT 24
Peak memory 224728 kb
Host smart-cb0fe326-1bd3-4777-b74d-df8716bd5cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855030264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.3855030264
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.587558402
Short name T622
Test name
Test status
Simulation time 119705424 ps
CPU time 4.31 seconds
Started Jul 24 05:56:08 PM PDT 24
Finished Jul 24 05:56:13 PM PDT 24
Peak memory 219088 kb
Host smart-80af60e5-f5e2-46c0-8f3a-680f6f781d31
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=587558402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dire
ct.587558402
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.1919112105
Short name T983
Test name
Test status
Simulation time 131686440232 ps
CPU time 645.69 seconds
Started Jul 24 05:56:18 PM PDT 24
Finished Jul 24 06:07:03 PM PDT 24
Peak memory 274000 kb
Host smart-c36b59ce-4148-4e1b-9714-c49a24fbe74d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919112105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.1919112105
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.4007754340
Short name T667
Test name
Test status
Simulation time 3814160095 ps
CPU time 17.14 seconds
Started Jul 24 05:56:09 PM PDT 24
Finished Jul 24 05:56:26 PM PDT 24
Peak memory 216556 kb
Host smart-03a841a0-6bd2-4785-82b7-b41d4283d4e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007754340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.4007754340
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.2359389951
Short name T814
Test name
Test status
Simulation time 470565751 ps
CPU time 3.96 seconds
Started Jul 24 05:56:09 PM PDT 24
Finished Jul 24 05:56:14 PM PDT 24
Peak memory 216432 kb
Host smart-d6f8a206-a6c9-448c-a131-fd4d3aef8216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359389951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.2359389951
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.1754157961
Short name T860
Test name
Test status
Simulation time 62634940 ps
CPU time 1.24 seconds
Started Jul 24 05:56:11 PM PDT 24
Finished Jul 24 05:56:12 PM PDT 24
Peak memory 208020 kb
Host smart-5b92ea1d-47ae-418b-ab21-342b121974b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754157961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.1754157961
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.715717961
Short name T981
Test name
Test status
Simulation time 104071479 ps
CPU time 0.84 seconds
Started Jul 24 05:56:11 PM PDT 24
Finished Jul 24 05:56:12 PM PDT 24
Peak memory 206168 kb
Host smart-65cdd20c-b2c7-4f7e-979c-f5c87e5cfc5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715717961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.715717961
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.2587169897
Short name T71
Test name
Test status
Simulation time 10756167190 ps
CPU time 4.48 seconds
Started Jul 24 05:56:12 PM PDT 24
Finished Jul 24 05:56:16 PM PDT 24
Peak memory 224704 kb
Host smart-9a5491e9-5034-4614-bcf1-04b0c096174d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587169897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.2587169897
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.1467635161
Short name T581
Test name
Test status
Simulation time 20505484 ps
CPU time 0.77 seconds
Started Jul 24 05:56:24 PM PDT 24
Finished Jul 24 05:56:25 PM PDT 24
Peak memory 205036 kb
Host smart-af5d837e-ad10-4f9a-92da-8a2c74b5299a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467635161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
1467635161
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.3556938543
Short name T88
Test name
Test status
Simulation time 195896360 ps
CPU time 3.16 seconds
Started Jul 24 05:56:19 PM PDT 24
Finished Jul 24 05:56:22 PM PDT 24
Peak memory 232816 kb
Host smart-8854e683-a959-4ae3-87b8-fe6af8b3c539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556938543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.3556938543
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.3834208574
Short name T405
Test name
Test status
Simulation time 15227524 ps
CPU time 0.78 seconds
Started Jul 24 05:56:19 PM PDT 24
Finished Jul 24 05:56:20 PM PDT 24
Peak memory 206736 kb
Host smart-36875e64-0386-4aa3-a936-504481268f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834208574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.3834208574
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.2093072221
Short name T253
Test name
Test status
Simulation time 4880111516 ps
CPU time 13.09 seconds
Started Jul 24 05:56:19 PM PDT 24
Finished Jul 24 05:56:32 PM PDT 24
Peak memory 249336 kb
Host smart-47403224-b467-4d52-8d95-754a5aabf509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093072221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.2093072221
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.1837061930
Short name T24
Test name
Test status
Simulation time 16235377917 ps
CPU time 140.75 seconds
Started Jul 24 05:56:18 PM PDT 24
Finished Jul 24 05:58:39 PM PDT 24
Peak memory 265824 kb
Host smart-7efc546a-9a15-479b-b137-91742429c5c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837061930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.1837061930
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.4040549992
Short name T271
Test name
Test status
Simulation time 210204265793 ps
CPU time 458.93 seconds
Started Jul 24 05:56:19 PM PDT 24
Finished Jul 24 06:03:58 PM PDT 24
Peak memory 268944 kb
Host smart-9ecc96af-ec70-4475-8cea-64a3fb1a6541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040549992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.4040549992
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.3169499813
Short name T286
Test name
Test status
Simulation time 4183199405 ps
CPU time 14.5 seconds
Started Jul 24 05:56:18 PM PDT 24
Finished Jul 24 05:56:33 PM PDT 24
Peak memory 249360 kb
Host smart-e2565330-83d4-4f20-9e92-7faf91257b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169499813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.3169499813
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.3275211968
Short name T960
Test name
Test status
Simulation time 32762595195 ps
CPU time 27.45 seconds
Started Jul 24 05:56:14 PM PDT 24
Finished Jul 24 05:56:42 PM PDT 24
Peak memory 241172 kb
Host smart-dd9f6257-f655-4ef2-aa81-def219dc4ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275211968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmd
s.3275211968
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.3807497385
Short name T743
Test name
Test status
Simulation time 2162897353 ps
CPU time 22.08 seconds
Started Jul 24 05:56:22 PM PDT 24
Finished Jul 24 05:56:44 PM PDT 24
Peak memory 232948 kb
Host smart-1d544514-e7f2-44f1-92d6-e15ddba11221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807497385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.3807497385
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.3383870152
Short name T413
Test name
Test status
Simulation time 30780986 ps
CPU time 2.12 seconds
Started Jul 24 05:56:17 PM PDT 24
Finished Jul 24 05:56:19 PM PDT 24
Peak memory 224388 kb
Host smart-8ac18e6a-7e89-41f6-ad7d-7fa16d4aff2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383870152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.3383870152
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.1819819626
Short name T194
Test name
Test status
Simulation time 74502344 ps
CPU time 2.37 seconds
Started Jul 24 05:56:19 PM PDT 24
Finished Jul 24 05:56:22 PM PDT 24
Peak memory 224636 kb
Host smart-86d9d595-8fb0-4054-9db7-87a122fe89a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819819626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.1819819626
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.2851974439
Short name T198
Test name
Test status
Simulation time 4224546467 ps
CPU time 8.7 seconds
Started Jul 24 05:56:16 PM PDT 24
Finished Jul 24 05:56:25 PM PDT 24
Peak memory 224736 kb
Host smart-abfc6c17-e37b-4472-af03-3af1ff81be6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851974439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.2851974439
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.1893909592
Short name T360
Test name
Test status
Simulation time 707800220 ps
CPU time 8.09 seconds
Started Jul 24 05:56:17 PM PDT 24
Finished Jul 24 05:56:25 PM PDT 24
Peak memory 220524 kb
Host smart-52b96463-5c9e-4313-a140-f5f0723dbd87
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1893909592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.1893909592
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.4160619995
Short name T920
Test name
Test status
Simulation time 40366029790 ps
CPU time 163.09 seconds
Started Jul 24 05:56:22 PM PDT 24
Finished Jul 24 05:59:05 PM PDT 24
Peak memory 250820 kb
Host smart-b1341955-dec3-4c59-9386-24f70324deee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160619995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.4160619995
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.1782207300
Short name T875
Test name
Test status
Simulation time 3831483642 ps
CPU time 5.98 seconds
Started Jul 24 05:56:16 PM PDT 24
Finished Jul 24 05:56:22 PM PDT 24
Peak memory 216484 kb
Host smart-fe27a184-5f02-4958-9d1a-04654c2571a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782207300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.1782207300
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.4220723618
Short name T563
Test name
Test status
Simulation time 29090992193 ps
CPU time 19.74 seconds
Started Jul 24 05:56:18 PM PDT 24
Finished Jul 24 05:56:38 PM PDT 24
Peak memory 217884 kb
Host smart-57611a75-6773-4070-bcef-1cc3633fc677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220723618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.4220723618
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.1868982334
Short name T309
Test name
Test status
Simulation time 38226332 ps
CPU time 0.79 seconds
Started Jul 24 05:56:18 PM PDT 24
Finished Jul 24 05:56:19 PM PDT 24
Peak memory 205760 kb
Host smart-aaa2bb28-29ad-4c98-bc57-6fdd200a0e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868982334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.1868982334
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.4168417528
Short name T842
Test name
Test status
Simulation time 97720560 ps
CPU time 0.92 seconds
Started Jul 24 05:56:21 PM PDT 24
Finished Jul 24 05:56:22 PM PDT 24
Peak memory 206088 kb
Host smart-e03d4dcc-90bd-44d8-8df2-d061f6d833b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168417528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.4168417528
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.2924498987
Short name T859
Test name
Test status
Simulation time 9069812191 ps
CPU time 26.16 seconds
Started Jul 24 05:56:16 PM PDT 24
Finished Jul 24 05:56:43 PM PDT 24
Peak memory 224784 kb
Host smart-23cb1483-13b3-4e4e-a8f2-6880306bc914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924498987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.2924498987
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.1853552849
Short name T686
Test name
Test status
Simulation time 44040282 ps
CPU time 0.73 seconds
Started Jul 24 05:56:23 PM PDT 24
Finished Jul 24 05:56:24 PM PDT 24
Peak memory 204992 kb
Host smart-db974311-89ac-4583-a20b-4dd600cfb085
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853552849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
1853552849
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.4096807882
Short name T835
Test name
Test status
Simulation time 3195691870 ps
CPU time 7.33 seconds
Started Jul 24 05:56:25 PM PDT 24
Finished Jul 24 05:56:33 PM PDT 24
Peak memory 232976 kb
Host smart-df76056d-e2d0-437f-9ab3-b15204bb3f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096807882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.4096807882
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.1970632580
Short name T341
Test name
Test status
Simulation time 270623809 ps
CPU time 0.8 seconds
Started Jul 24 05:56:25 PM PDT 24
Finished Jul 24 05:56:25 PM PDT 24
Peak memory 206732 kb
Host smart-dc189de2-3e4c-4243-896b-dfea6c469e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970632580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.1970632580
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.2476539694
Short name T130
Test name
Test status
Simulation time 4559799493 ps
CPU time 26.03 seconds
Started Jul 24 05:56:21 PM PDT 24
Finished Jul 24 05:56:47 PM PDT 24
Peak memory 256532 kb
Host smart-d4aa5d2c-90a7-4f8e-a0f3-6bae5a9bb1f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476539694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.2476539694
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.2858747650
Short name T764
Test name
Test status
Simulation time 7759489841 ps
CPU time 37.14 seconds
Started Jul 24 05:56:21 PM PDT 24
Finished Jul 24 05:56:58 PM PDT 24
Peak memory 233632 kb
Host smart-4e9ea152-0776-49fe-a32d-aeca4e9e3952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858747650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.2858747650
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.911889030
Short name T728
Test name
Test status
Simulation time 308344052906 ps
CPU time 184.43 seconds
Started Jul 24 05:56:21 PM PDT 24
Finished Jul 24 05:59:26 PM PDT 24
Peak memory 249300 kb
Host smart-235a3cf2-2a1b-4b28-b69e-400dad661da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911889030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idle
.911889030
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.3673846186
Short name T714
Test name
Test status
Simulation time 1561383166 ps
CPU time 13.45 seconds
Started Jul 24 05:56:24 PM PDT 24
Finished Jul 24 05:56:37 PM PDT 24
Peak memory 224664 kb
Host smart-c5657d28-b630-464d-a326-9bc85f23e6fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673846186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.3673846186
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.2018396176
Short name T659
Test name
Test status
Simulation time 73407670577 ps
CPU time 147.6 seconds
Started Jul 24 05:56:26 PM PDT 24
Finished Jul 24 05:58:53 PM PDT 24
Peak memory 255596 kb
Host smart-fc0f42c2-4fb2-451f-b609-3e29ff67dbd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018396176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmd
s.2018396176
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_intercept.3131897682
Short name T652
Test name
Test status
Simulation time 4955854693 ps
CPU time 6.09 seconds
Started Jul 24 05:56:23 PM PDT 24
Finished Jul 24 05:56:29 PM PDT 24
Peak memory 232904 kb
Host smart-fb3313d7-e962-468e-95cd-2a203c3697c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131897682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.3131897682
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.903816184
Short name T872
Test name
Test status
Simulation time 20668318167 ps
CPU time 115.63 seconds
Started Jul 24 05:56:22 PM PDT 24
Finished Jul 24 05:58:18 PM PDT 24
Peak memory 250640 kb
Host smart-cfc75e65-8b38-431d-8fc0-6950afaaae0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903816184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.903816184
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.3079474972
Short name T624
Test name
Test status
Simulation time 6686825312 ps
CPU time 11.85 seconds
Started Jul 24 05:56:22 PM PDT 24
Finished Jul 24 05:56:34 PM PDT 24
Peak memory 240724 kb
Host smart-aa54904a-ea1c-4574-9f40-9726c48efcf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079474972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.3079474972
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.941314097
Short name T693
Test name
Test status
Simulation time 28241306993 ps
CPU time 20.32 seconds
Started Jul 24 05:56:24 PM PDT 24
Finished Jul 24 05:56:44 PM PDT 24
Peak memory 232912 kb
Host smart-a5ea94be-cedd-44d7-a358-b721f1678ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941314097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.941314097
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.1535720761
Short name T656
Test name
Test status
Simulation time 1165840647 ps
CPU time 4.22 seconds
Started Jul 24 05:56:24 PM PDT 24
Finished Jul 24 05:56:28 PM PDT 24
Peak memory 220156 kb
Host smart-a6361786-2cca-4dfa-872e-49a70f000531
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1535720761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.1535720761
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.720429693
Short name T460
Test name
Test status
Simulation time 39865740939 ps
CPU time 146.16 seconds
Started Jul 24 05:56:26 PM PDT 24
Finished Jul 24 05:58:53 PM PDT 24
Peak memory 254132 kb
Host smart-4941e7be-25ff-4082-9137-ae12f344a350
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720429693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stres
s_all.720429693
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.3017072638
Short name T780
Test name
Test status
Simulation time 1178517342 ps
CPU time 12.4 seconds
Started Jul 24 05:56:22 PM PDT 24
Finished Jul 24 05:56:34 PM PDT 24
Peak memory 216516 kb
Host smart-2b28fd3b-069c-4c7f-98cc-dbc700fba538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017072638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.3017072638
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.2353517847
Short name T700
Test name
Test status
Simulation time 6523361532 ps
CPU time 15.29 seconds
Started Jul 24 05:56:25 PM PDT 24
Finished Jul 24 05:56:40 PM PDT 24
Peak memory 216524 kb
Host smart-6c6d0e81-4181-43b1-8023-cf2a6fa84fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353517847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.2353517847
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.3412933485
Short name T783
Test name
Test status
Simulation time 30995749 ps
CPU time 1.17 seconds
Started Jul 24 05:56:25 PM PDT 24
Finished Jul 24 05:56:26 PM PDT 24
Peak memory 216260 kb
Host smart-dd1702fc-15ed-40fd-96ee-1f7bf5b1516e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412933485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.3412933485
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.653776423
Short name T357
Test name
Test status
Simulation time 70094568 ps
CPU time 0.89 seconds
Started Jul 24 05:56:24 PM PDT 24
Finished Jul 24 05:56:25 PM PDT 24
Peak memory 206084 kb
Host smart-09bc6d39-d12d-493b-93ef-2a71df508e20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653776423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.653776423
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.848850231
Short name T802
Test name
Test status
Simulation time 31487120011 ps
CPU time 12.88 seconds
Started Jul 24 05:56:24 PM PDT 24
Finished Jul 24 05:56:37 PM PDT 24
Peak memory 224776 kb
Host smart-c21685e9-0314-45fd-9249-76edb529e841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848850231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.848850231
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.895986874
Short name T925
Test name
Test status
Simulation time 16592058 ps
CPU time 0.79 seconds
Started Jul 24 05:56:23 PM PDT 24
Finished Jul 24 05:56:24 PM PDT 24
Peak memory 205540 kb
Host smart-cb2ae052-bf2b-46b8-833f-80cab1099819
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895986874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.895986874
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.1908298575
Short name T250
Test name
Test status
Simulation time 276143423 ps
CPU time 5.87 seconds
Started Jul 24 05:56:25 PM PDT 24
Finished Jul 24 05:56:31 PM PDT 24
Peak memory 224628 kb
Host smart-c8ba5c08-85bb-4092-b6ff-af82167fb242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908298575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.1908298575
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.3716759749
Short name T587
Test name
Test status
Simulation time 50014245 ps
CPU time 0.75 seconds
Started Jul 24 05:56:25 PM PDT 24
Finished Jul 24 05:56:26 PM PDT 24
Peak memory 206772 kb
Host smart-061fcf2e-2ac1-4ea0-a828-40aa2ca180bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716759749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.3716759749
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.2201487511
Short name T958
Test name
Test status
Simulation time 5090421275 ps
CPU time 42.96 seconds
Started Jul 24 05:56:27 PM PDT 24
Finished Jul 24 05:57:10 PM PDT 24
Peak memory 236852 kb
Host smart-804744b9-81dd-4615-a3f7-d07554166e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201487511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.2201487511
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.2811665153
Short name T477
Test name
Test status
Simulation time 4596265795 ps
CPU time 32.98 seconds
Started Jul 24 05:56:23 PM PDT 24
Finished Jul 24 05:56:56 PM PDT 24
Peak memory 241216 kb
Host smart-2bf2c29e-464f-4b43-a438-b6ff3fda2d68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811665153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.2811665153
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.1104825219
Short name T642
Test name
Test status
Simulation time 1771215887 ps
CPU time 9.91 seconds
Started Jul 24 05:56:21 PM PDT 24
Finished Jul 24 05:56:31 PM PDT 24
Peak memory 232900 kb
Host smart-2fcea4c5-ee48-4e5c-8a10-2f7c06f94c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104825219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.1104825219
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.750848090
Short name T230
Test name
Test status
Simulation time 3229424146 ps
CPU time 60.26 seconds
Started Jul 24 05:56:24 PM PDT 24
Finished Jul 24 05:57:25 PM PDT 24
Peak memory 251040 kb
Host smart-6ca1ead8-a18c-4c21-a382-75dd79bd6bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750848090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmds
.750848090
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_intercept.529253979
Short name T830
Test name
Test status
Simulation time 11567116355 ps
CPU time 23.43 seconds
Started Jul 24 05:56:23 PM PDT 24
Finished Jul 24 05:56:47 PM PDT 24
Peak memory 220576 kb
Host smart-df2b0fcf-2e07-415e-a767-7d496fc71541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529253979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.529253979
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.1413368891
Short name T318
Test name
Test status
Simulation time 420769006 ps
CPU time 2.3 seconds
Started Jul 24 05:56:27 PM PDT 24
Finished Jul 24 05:56:29 PM PDT 24
Peak memory 223200 kb
Host smart-14a8aea6-7c33-4754-a510-690ee67d2cba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413368891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.1413368891
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.516806271
Short name T452
Test name
Test status
Simulation time 987127061 ps
CPU time 3.77 seconds
Started Jul 24 05:56:19 PM PDT 24
Finished Jul 24 05:56:23 PM PDT 24
Peak memory 232840 kb
Host smart-ddcd87cc-d602-4492-a002-8cdfcf1ac879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516806271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swap
.516806271
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.3711455486
Short name T692
Test name
Test status
Simulation time 2204489198 ps
CPU time 5.41 seconds
Started Jul 24 05:56:22 PM PDT 24
Finished Jul 24 05:56:27 PM PDT 24
Peak memory 232924 kb
Host smart-748574f6-880b-4df4-96b7-1af02b8176eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711455486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.3711455486
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.2757582510
Short name T889
Test name
Test status
Simulation time 605678980 ps
CPU time 7.35 seconds
Started Jul 24 05:56:22 PM PDT 24
Finished Jul 24 05:56:29 PM PDT 24
Peak memory 222316 kb
Host smart-ea0125e2-226f-436c-81ba-1180ed987a98
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2757582510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.2757582510
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.1897626279
Short name T358
Test name
Test status
Simulation time 73529352 ps
CPU time 0.97 seconds
Started Jul 24 05:56:24 PM PDT 24
Finished Jul 24 05:56:25 PM PDT 24
Peak memory 207880 kb
Host smart-590c9db0-87fa-4c3b-8dd5-804684a53852
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897626279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.1897626279
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.863954567
Short name T496
Test name
Test status
Simulation time 34220935655 ps
CPU time 42.59 seconds
Started Jul 24 05:56:24 PM PDT 24
Finished Jul 24 05:57:07 PM PDT 24
Peak memory 216508 kb
Host smart-c54959b6-adcd-48ef-bfbc-0a439e7d1037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863954567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.863954567
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.3327647956
Short name T409
Test name
Test status
Simulation time 5673301445 ps
CPU time 13.47 seconds
Started Jul 24 05:56:22 PM PDT 24
Finished Jul 24 05:56:35 PM PDT 24
Peak memory 216356 kb
Host smart-cc87bb84-55f5-4bd6-852a-8ffe09756d60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327647956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.3327647956
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.603695129
Short name T907
Test name
Test status
Simulation time 106731995 ps
CPU time 1.98 seconds
Started Jul 24 05:56:23 PM PDT 24
Finished Jul 24 05:56:25 PM PDT 24
Peak memory 216332 kb
Host smart-dbeef803-07a7-475d-ab87-db598f93a348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603695129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.603695129
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.2762798372
Short name T354
Test name
Test status
Simulation time 60523702 ps
CPU time 0.94 seconds
Started Jul 24 05:56:22 PM PDT 24
Finished Jul 24 05:56:23 PM PDT 24
Peak memory 207152 kb
Host smart-ca664409-e49a-4082-b5d1-455b8c441f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762798372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.2762798372
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.880258820
Short name T423
Test name
Test status
Simulation time 5248646638 ps
CPU time 10.16 seconds
Started Jul 24 05:56:22 PM PDT 24
Finished Jul 24 05:56:32 PM PDT 24
Peak memory 228996 kb
Host smart-9aa72159-6610-4f65-b762-ec242aa15677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880258820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.880258820
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.840946979
Short name T921
Test name
Test status
Simulation time 14189796 ps
CPU time 0.72 seconds
Started Jul 24 05:56:30 PM PDT 24
Finished Jul 24 05:56:31 PM PDT 24
Peak memory 205568 kb
Host smart-29e49f92-7880-43a6-aa90-0d2c1a64892c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840946979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.840946979
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.368998924
Short name T888
Test name
Test status
Simulation time 312013519 ps
CPU time 2.39 seconds
Started Jul 24 05:56:29 PM PDT 24
Finished Jul 24 05:56:32 PM PDT 24
Peak memory 224616 kb
Host smart-a68d3150-a0a6-45b9-8dbd-e89c3f4d4d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368998924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.368998924
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.1602492710
Short name T782
Test name
Test status
Simulation time 27912035 ps
CPU time 0.77 seconds
Started Jul 24 05:56:23 PM PDT 24
Finished Jul 24 05:56:24 PM PDT 24
Peak memory 206772 kb
Host smart-dd4f7c6b-6737-404d-9088-25ee56202126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602492710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.1602492710
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.1715849810
Short name T188
Test name
Test status
Simulation time 2263927829 ps
CPU time 30.87 seconds
Started Jul 24 05:56:29 PM PDT 24
Finished Jul 24 05:57:00 PM PDT 24
Peak memory 238200 kb
Host smart-095de8f0-de85-46c6-b290-411da98db218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715849810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.1715849810
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.3535799038
Short name T688
Test name
Test status
Simulation time 9803477423 ps
CPU time 72.15 seconds
Started Jul 24 05:56:29 PM PDT 24
Finished Jul 24 05:57:42 PM PDT 24
Peak memory 253228 kb
Host smart-de739d39-1f10-49c2-be85-15d499ec536c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535799038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.3535799038
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.1154771602
Short name T200
Test name
Test status
Simulation time 50431847558 ps
CPU time 197.07 seconds
Started Jul 24 05:56:30 PM PDT 24
Finished Jul 24 05:59:47 PM PDT 24
Peak memory 273740 kb
Host smart-d6570d7e-b9f1-432f-955f-9ea7039c6c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154771602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.1154771602
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.3015128396
Short name T684
Test name
Test status
Simulation time 180484200 ps
CPU time 3.63 seconds
Started Jul 24 05:56:28 PM PDT 24
Finished Jul 24 05:56:32 PM PDT 24
Peak memory 241036 kb
Host smart-28027094-bded-4ec1-98a4-c62ac9d216b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015128396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.3015128396
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.375934083
Short name T273
Test name
Test status
Simulation time 72918549923 ps
CPU time 385.28 seconds
Started Jul 24 05:56:31 PM PDT 24
Finished Jul 24 06:02:56 PM PDT 24
Peak memory 265588 kb
Host smart-c9639f40-3d18-4603-9255-e070e1ef1614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375934083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmds
.375934083
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_intercept.3852836492
Short name T660
Test name
Test status
Simulation time 1365515345 ps
CPU time 5.26 seconds
Started Jul 24 05:56:32 PM PDT 24
Finished Jul 24 05:56:38 PM PDT 24
Peak memory 224640 kb
Host smart-0f0db567-927e-4f2a-939f-11d9fc5ae54a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852836492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.3852836492
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.2498544161
Short name T68
Test name
Test status
Simulation time 1021364641 ps
CPU time 14.61 seconds
Started Jul 24 05:56:28 PM PDT 24
Finished Jul 24 05:56:42 PM PDT 24
Peak memory 232848 kb
Host smart-fca3dd3a-3d93-4830-b40f-ddb5fa3d41f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498544161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.2498544161
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.1910700966
Short name T67
Test name
Test status
Simulation time 430798533 ps
CPU time 3.81 seconds
Started Jul 24 05:56:29 PM PDT 24
Finished Jul 24 05:56:33 PM PDT 24
Peak memory 224656 kb
Host smart-38dccb18-b5be-4b19-b3f2-1c0f1cca7d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910700966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.1910700966
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.4202856125
Short name T129
Test name
Test status
Simulation time 9338474211 ps
CPU time 9.57 seconds
Started Jul 24 05:56:30 PM PDT 24
Finished Jul 24 05:56:40 PM PDT 24
Peak memory 232932 kb
Host smart-1ee9dcbd-9afe-4cf1-a809-52288db1655a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202856125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.4202856125
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.3897784027
Short name T748
Test name
Test status
Simulation time 1477419217 ps
CPU time 7.69 seconds
Started Jul 24 05:56:27 PM PDT 24
Finished Jul 24 05:56:35 PM PDT 24
Peak memory 223348 kb
Host smart-23818362-58ad-4764-9fc8-0d8d2ba97824
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3897784027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.3897784027
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.4064945253
Short name T155
Test name
Test status
Simulation time 79036697532 ps
CPU time 191.88 seconds
Started Jul 24 05:56:29 PM PDT 24
Finished Jul 24 05:59:41 PM PDT 24
Peak memory 257564 kb
Host smart-7477bb4c-6858-48c6-9178-8e23c9e118ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064945253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.4064945253
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.3040586669
Short name T898
Test name
Test status
Simulation time 2513356050 ps
CPU time 8.92 seconds
Started Jul 24 05:56:30 PM PDT 24
Finished Jul 24 05:56:39 PM PDT 24
Peak memory 216644 kb
Host smart-f2a1cf2e-d5a8-46ba-bec8-cb7601304a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040586669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.3040586669
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.2254678141
Short name T417
Test name
Test status
Simulation time 13168814 ps
CPU time 0.74 seconds
Started Jul 24 05:56:26 PM PDT 24
Finished Jul 24 05:56:27 PM PDT 24
Peak memory 206144 kb
Host smart-a7215800-59c4-48ef-8bdf-5c53cb48ae74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254678141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.2254678141
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.1186027488
Short name T906
Test name
Test status
Simulation time 1091275955 ps
CPU time 2.38 seconds
Started Jul 24 05:56:28 PM PDT 24
Finished Jul 24 05:56:30 PM PDT 24
Peak memory 216432 kb
Host smart-ccd08a97-8726-4d2e-8f95-caedf5e6531c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186027488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.1186027488
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.2167113070
Short name T632
Test name
Test status
Simulation time 56311429 ps
CPU time 0.94 seconds
Started Jul 24 05:56:28 PM PDT 24
Finished Jul 24 05:56:29 PM PDT 24
Peak memory 206172 kb
Host smart-54d1d770-ac3a-4ab1-8262-96385a08aa8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167113070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.2167113070
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.436005275
Short name T527
Test name
Test status
Simulation time 5850439964 ps
CPU time 8.34 seconds
Started Jul 24 05:56:27 PM PDT 24
Finished Jul 24 05:56:36 PM PDT 24
Peak memory 232872 kb
Host smart-62d5b476-be9a-4649-91c9-70e26bc9acb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436005275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.436005275
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.2944893836
Short name T571
Test name
Test status
Simulation time 14675898 ps
CPU time 0.74 seconds
Started Jul 24 05:56:33 PM PDT 24
Finished Jul 24 05:56:34 PM PDT 24
Peak memory 205532 kb
Host smart-5ba7785d-19f6-4688-b355-4d3a5edaa1d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944893836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
2944893836
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.419688600
Short name T223
Test name
Test status
Simulation time 138212813 ps
CPU time 3.03 seconds
Started Jul 24 05:56:35 PM PDT 24
Finished Jul 24 05:56:38 PM PDT 24
Peak memory 232884 kb
Host smart-d191ea53-439c-46bd-bb32-777b40b68a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419688600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.419688600
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.3391875342
Short name T618
Test name
Test status
Simulation time 19398151 ps
CPU time 0.77 seconds
Started Jul 24 05:56:28 PM PDT 24
Finished Jul 24 05:56:29 PM PDT 24
Peak memory 205616 kb
Host smart-ed130b53-7a7a-4382-a164-154df903b209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391875342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.3391875342
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.1578605988
Short name T278
Test name
Test status
Simulation time 248091493895 ps
CPU time 397.4 seconds
Started Jul 24 05:56:35 PM PDT 24
Finished Jul 24 06:03:12 PM PDT 24
Peak memory 254852 kb
Host smart-2e392ddd-8b5e-4493-821e-c5948f761d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578605988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.1578605988
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.2392717464
Short name T811
Test name
Test status
Simulation time 76721560774 ps
CPU time 164.39 seconds
Started Jul 24 05:56:35 PM PDT 24
Finished Jul 24 05:59:19 PM PDT 24
Peak memory 252060 kb
Host smart-c2f680a4-7c54-4d4f-af88-6cb081f40521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392717464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.2392717464
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.1556621531
Short name T578
Test name
Test status
Simulation time 54934820 ps
CPU time 2.79 seconds
Started Jul 24 05:56:35 PM PDT 24
Finished Jul 24 05:56:38 PM PDT 24
Peak memory 224628 kb
Host smart-892d631b-dadf-4593-b8be-51833f21a7f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556621531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.1556621531
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.1329105996
Short name T987
Test name
Test status
Simulation time 67787677908 ps
CPU time 161.29 seconds
Started Jul 24 05:56:38 PM PDT 24
Finished Jul 24 05:59:19 PM PDT 24
Peak memory 261204 kb
Host smart-23170874-0530-4eb0-a597-c05d1b42cd96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329105996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmd
s.1329105996
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_intercept.1834489947
Short name T977
Test name
Test status
Simulation time 339407877 ps
CPU time 5.76 seconds
Started Jul 24 05:56:28 PM PDT 24
Finished Jul 24 05:56:34 PM PDT 24
Peak memory 232808 kb
Host smart-0eea940e-f679-4e76-ac25-7b3ba7ac53d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834489947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.1834489947
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.4131556403
Short name T233
Test name
Test status
Simulation time 8314279398 ps
CPU time 14.93 seconds
Started Jul 24 05:56:34 PM PDT 24
Finished Jul 24 05:56:49 PM PDT 24
Peak memory 237568 kb
Host smart-d5748d73-d3f3-4631-bc9f-fa52530c7d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131556403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.4131556403
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.3713786878
Short name T505
Test name
Test status
Simulation time 13529483666 ps
CPU time 9.11 seconds
Started Jul 24 05:56:29 PM PDT 24
Finished Jul 24 05:56:38 PM PDT 24
Peak memory 240948 kb
Host smart-25bc7ac0-c627-4c12-8dc9-f850f7552bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713786878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.3713786878
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.411387299
Short name T494
Test name
Test status
Simulation time 11469362606 ps
CPU time 23.73 seconds
Started Jul 24 05:56:27 PM PDT 24
Finished Jul 24 05:56:51 PM PDT 24
Peak memory 232912 kb
Host smart-50eba811-802e-4995-88c5-fa4bee495d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411387299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.411387299
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.4102542359
Short name T629
Test name
Test status
Simulation time 6797763253 ps
CPU time 19.18 seconds
Started Jul 24 05:56:34 PM PDT 24
Finished Jul 24 05:56:54 PM PDT 24
Peak memory 220836 kb
Host smart-8e92bd51-9513-40a6-bd68-c5d718b4df47
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4102542359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.4102542359
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.3373246435
Short name T279
Test name
Test status
Simulation time 199683595122 ps
CPU time 573.49 seconds
Started Jul 24 05:56:33 PM PDT 24
Finished Jul 24 06:06:07 PM PDT 24
Peak memory 273912 kb
Host smart-4fffcef9-8295-40e5-b55b-78726c31b6d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373246435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.3373246435
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.3723427568
Short name T950
Test name
Test status
Simulation time 4114135371 ps
CPU time 7.39 seconds
Started Jul 24 05:56:27 PM PDT 24
Finished Jul 24 05:56:35 PM PDT 24
Peak memory 220384 kb
Host smart-5184dd77-31b9-45f5-9a70-7c13cd0e2169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723427568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.3723427568
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.4110858312
Short name T620
Test name
Test status
Simulation time 322996284 ps
CPU time 1.17 seconds
Started Jul 24 05:56:29 PM PDT 24
Finished Jul 24 05:56:31 PM PDT 24
Peak memory 208000 kb
Host smart-55ffca05-4e78-438a-8ea2-16979e830ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110858312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.4110858312
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.972171121
Short name T502
Test name
Test status
Simulation time 73549955 ps
CPU time 1.07 seconds
Started Jul 24 05:56:28 PM PDT 24
Finished Jul 24 05:56:29 PM PDT 24
Peak memory 207896 kb
Host smart-5f40357c-0719-432b-b570-b49c627dd407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972171121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.972171121
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.3292734135
Short name T70
Test name
Test status
Simulation time 38446696 ps
CPU time 0.86 seconds
Started Jul 24 05:56:27 PM PDT 24
Finished Jul 24 05:56:28 PM PDT 24
Peak memory 207128 kb
Host smart-09b2f912-a5cd-49cb-b7ec-28097659371c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292734135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.3292734135
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.359148664
Short name T256
Test name
Test status
Simulation time 351112751 ps
CPU time 2.87 seconds
Started Jul 24 05:56:35 PM PDT 24
Finished Jul 24 05:56:38 PM PDT 24
Peak memory 240980 kb
Host smart-7b2872da-289b-4f80-aa28-e3bb9efb2a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359148664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.359148664
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.2871405425
Short name T599
Test name
Test status
Simulation time 38366599 ps
CPU time 0.7 seconds
Started Jul 24 05:56:35 PM PDT 24
Finished Jul 24 05:56:36 PM PDT 24
Peak memory 205032 kb
Host smart-1a57d9e0-809d-404e-b3b5-e49f2fead262
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871405425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
2871405425
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.1519706471
Short name T583
Test name
Test status
Simulation time 647807491 ps
CPU time 2.38 seconds
Started Jul 24 05:56:37 PM PDT 24
Finished Jul 24 05:56:40 PM PDT 24
Peak memory 224320 kb
Host smart-0caa34dd-c6c3-467b-b236-c260e05c122e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519706471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.1519706471
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.946284283
Short name T370
Test name
Test status
Simulation time 18661737 ps
CPU time 0.78 seconds
Started Jul 24 05:56:35 PM PDT 24
Finished Jul 24 05:56:36 PM PDT 24
Peak memory 207088 kb
Host smart-7e33a3ff-af18-4f2a-a74b-3d6205108dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946284283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.946284283
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.2238199558
Short name T883
Test name
Test status
Simulation time 15890575178 ps
CPU time 153.66 seconds
Started Jul 24 05:56:38 PM PDT 24
Finished Jul 24 05:59:12 PM PDT 24
Peak memory 249336 kb
Host smart-e06666d6-daa7-46b2-87a3-eb98c16f3dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238199558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.2238199558
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.3743327445
Short name T298
Test name
Test status
Simulation time 12985893527 ps
CPU time 115.18 seconds
Started Jul 24 05:56:36 PM PDT 24
Finished Jul 24 05:58:32 PM PDT 24
Peak memory 256480 kb
Host smart-c94bc04b-78f0-4667-89ec-97df2587497f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743327445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.3743327445
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.2155293437
Short name T393
Test name
Test status
Simulation time 2167199895 ps
CPU time 22.35 seconds
Started Jul 24 05:56:37 PM PDT 24
Finished Jul 24 05:56:59 PM PDT 24
Peak memory 249108 kb
Host smart-c6bd7d73-0e69-4fca-a78f-d7e686928d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155293437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.2155293437
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.2103927397
Short name T956
Test name
Test status
Simulation time 191451288 ps
CPU time 2.85 seconds
Started Jul 24 05:56:34 PM PDT 24
Finished Jul 24 05:56:37 PM PDT 24
Peak memory 224700 kb
Host smart-48a349ab-a6a4-41a5-9291-501c868f27b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103927397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.2103927397
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.2705106409
Short name T186
Test name
Test status
Simulation time 52856528234 ps
CPU time 236.66 seconds
Started Jul 24 05:56:37 PM PDT 24
Finished Jul 24 06:00:34 PM PDT 24
Peak memory 250460 kb
Host smart-a89d6027-4d75-49b4-8906-51f830778e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705106409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmd
s.2705106409
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.2388288299
Short name T450
Test name
Test status
Simulation time 464239656 ps
CPU time 7.72 seconds
Started Jul 24 05:56:37 PM PDT 24
Finished Jul 24 05:56:45 PM PDT 24
Peak memory 232968 kb
Host smart-cff64217-03b4-4694-ab2e-c6e3301fe0be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388288299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.2388288299
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.1385380131
Short name T437
Test name
Test status
Simulation time 148753239467 ps
CPU time 169.37 seconds
Started Jul 24 05:56:38 PM PDT 24
Finished Jul 24 05:59:27 PM PDT 24
Peak memory 239456 kb
Host smart-59f6ebc9-6eda-4334-9bb0-e1ea87954c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385380131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.1385380131
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.601216776
Short name T651
Test name
Test status
Simulation time 65678349 ps
CPU time 2.59 seconds
Started Jul 24 05:56:37 PM PDT 24
Finished Jul 24 05:56:40 PM PDT 24
Peak memory 232616 kb
Host smart-03b2e05e-035d-42ee-9236-650dad9475b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601216776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swap
.601216776
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.2569718737
Short name T391
Test name
Test status
Simulation time 123642111 ps
CPU time 3.43 seconds
Started Jul 24 05:56:34 PM PDT 24
Finished Jul 24 05:56:37 PM PDT 24
Peak memory 232816 kb
Host smart-008eb613-b857-40c9-8d92-102260d3706c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569718737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.2569718737
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.2003594319
Short name T868
Test name
Test status
Simulation time 199537752 ps
CPU time 4.06 seconds
Started Jul 24 05:56:39 PM PDT 24
Finished Jul 24 05:56:43 PM PDT 24
Peak memory 222892 kb
Host smart-9ac980c7-f382-4919-b37c-f32d54144732
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2003594319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.2003594319
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.588755252
Short name T430
Test name
Test status
Simulation time 6461116697 ps
CPU time 57.49 seconds
Started Jul 24 05:56:38 PM PDT 24
Finished Jul 24 05:57:36 PM PDT 24
Peak memory 235060 kb
Host smart-68580cac-7ff7-47ac-aef1-5cb6364f3b87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588755252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stres
s_all.588755252
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.1230912388
Short name T1
Test name
Test status
Simulation time 3715047163 ps
CPU time 21.24 seconds
Started Jul 24 05:56:36 PM PDT 24
Finished Jul 24 05:56:57 PM PDT 24
Peak memory 216544 kb
Host smart-061d4974-e6ab-4d6c-baac-7435e47b328f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230912388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.1230912388
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.1249488028
Short name T523
Test name
Test status
Simulation time 1349964551 ps
CPU time 2.43 seconds
Started Jul 24 05:56:39 PM PDT 24
Finished Jul 24 05:56:42 PM PDT 24
Peak memory 208024 kb
Host smart-4a8ef4d9-7b6c-41f6-b6da-f6981aa5a50e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249488028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.1249488028
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.1423321037
Short name T650
Test name
Test status
Simulation time 21817769 ps
CPU time 1.35 seconds
Started Jul 24 05:56:33 PM PDT 24
Finished Jul 24 05:56:35 PM PDT 24
Peak memory 216460 kb
Host smart-210f77c8-0b9e-4cf7-b298-84e77fe05766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423321037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.1423321037
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.280486743
Short name T666
Test name
Test status
Simulation time 120838427 ps
CPU time 0.88 seconds
Started Jul 24 05:56:34 PM PDT 24
Finished Jul 24 05:56:35 PM PDT 24
Peak memory 206080 kb
Host smart-ba273868-cdcf-424b-abac-566f85a8eb20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280486743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.280486743
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.482726957
Short name T703
Test name
Test status
Simulation time 2673611035 ps
CPU time 5.8 seconds
Started Jul 24 05:56:36 PM PDT 24
Finished Jul 24 05:56:42 PM PDT 24
Peak memory 224780 kb
Host smart-593a22c9-8905-4d9a-be9a-8dadab0b3f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482726957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.482726957
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.2297394163
Short name T331
Test name
Test status
Simulation time 19318730 ps
CPU time 0.73 seconds
Started Jul 24 05:56:41 PM PDT 24
Finished Jul 24 05:56:42 PM PDT 24
Peak memory 205532 kb
Host smart-34a2d658-b944-43f3-8a42-3f00f6348996
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297394163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
2297394163
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.3804849230
Short name T605
Test name
Test status
Simulation time 237437391 ps
CPU time 3.2 seconds
Started Jul 24 05:56:40 PM PDT 24
Finished Jul 24 05:56:44 PM PDT 24
Peak memory 232860 kb
Host smart-f57c8bf6-a08e-40ec-9601-89f3b012f401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804849230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.3804849230
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.1758248947
Short name T13
Test name
Test status
Simulation time 25977844 ps
CPU time 0.75 seconds
Started Jul 24 05:56:39 PM PDT 24
Finished Jul 24 05:56:40 PM PDT 24
Peak memory 206028 kb
Host smart-cdaf57c1-9e59-422c-a634-0545e3889cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758248947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.1758248947
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.1111214055
Short name T163
Test name
Test status
Simulation time 14312661555 ps
CPU time 52.89 seconds
Started Jul 24 05:56:38 PM PDT 24
Finished Jul 24 05:57:32 PM PDT 24
Peak memory 240332 kb
Host smart-17550bdd-be70-4c02-a229-e0375599a5e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111214055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.1111214055
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.2242100176
Short name T827
Test name
Test status
Simulation time 48721268458 ps
CPU time 92.75 seconds
Started Jul 24 05:56:41 PM PDT 24
Finished Jul 24 05:58:14 PM PDT 24
Peak memory 255348 kb
Host smart-656bcde1-ff0a-4a02-8ea5-1f5239aab569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242100176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.2242100176
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.3192456092
Short name T165
Test name
Test status
Simulation time 11116727489 ps
CPU time 41.68 seconds
Started Jul 24 05:56:37 PM PDT 24
Finished Jul 24 05:57:19 PM PDT 24
Peak memory 232876 kb
Host smart-508ff32c-811d-4c84-91ef-809dc90d0902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192456092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.3192456092
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.2318897399
Short name T697
Test name
Test status
Simulation time 1100858381 ps
CPU time 7.55 seconds
Started Jul 24 05:56:42 PM PDT 24
Finished Jul 24 05:56:49 PM PDT 24
Peak memory 232916 kb
Host smart-cab3c590-ffe1-45ac-909c-b26af4ec6f52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318897399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.2318897399
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_intercept.2064884424
Short name T574
Test name
Test status
Simulation time 28589451212 ps
CPU time 17.4 seconds
Started Jul 24 05:56:38 PM PDT 24
Finished Jul 24 05:56:56 PM PDT 24
Peak memory 232864 kb
Host smart-eb75c969-afb2-4c0f-ad78-01545073bf24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064884424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.2064884424
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.2060657556
Short name T320
Test name
Test status
Simulation time 1015939798 ps
CPU time 5.59 seconds
Started Jul 24 05:56:40 PM PDT 24
Finished Jul 24 05:56:46 PM PDT 24
Peak memory 239860 kb
Host smart-9daa51ad-da37-4f88-936b-2618bc103328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060657556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.2060657556
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.1126668545
Short name T761
Test name
Test status
Simulation time 11258962556 ps
CPU time 9.31 seconds
Started Jul 24 05:56:41 PM PDT 24
Finished Jul 24 05:56:51 PM PDT 24
Peak memory 232928 kb
Host smart-b51f2a21-6577-4ab7-bb76-0a81d6aca772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126668545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.1126668545
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.3896182152
Short name T545
Test name
Test status
Simulation time 34718391467 ps
CPU time 26.03 seconds
Started Jul 24 05:56:38 PM PDT 24
Finished Jul 24 05:57:04 PM PDT 24
Peak memory 248756 kb
Host smart-aae14994-64ed-4507-a9d9-d31cb500cc1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896182152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.3896182152
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.2468666533
Short name T951
Test name
Test status
Simulation time 591544512 ps
CPU time 8.21 seconds
Started Jul 24 05:56:39 PM PDT 24
Finished Jul 24 05:56:47 PM PDT 24
Peak memory 222448 kb
Host smart-12909f8b-1bd5-4def-a971-5ecf8b269df6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2468666533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.2468666533
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.3382024271
Short name T970
Test name
Test status
Simulation time 45238293596 ps
CPU time 394.96 seconds
Started Jul 24 05:56:38 PM PDT 24
Finished Jul 24 06:03:13 PM PDT 24
Peak memory 252224 kb
Host smart-5961a1f9-39fb-4756-866e-4df6b622169e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382024271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.3382024271
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.743646415
Short name T294
Test name
Test status
Simulation time 1827997135 ps
CPU time 23.38 seconds
Started Jul 24 05:56:34 PM PDT 24
Finished Jul 24 05:56:58 PM PDT 24
Peak memory 220292 kb
Host smart-c4b4059c-c2e1-4c12-8e84-eb90cb8443ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743646415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.743646415
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.2382669958
Short name T366
Test name
Test status
Simulation time 3550658271 ps
CPU time 15.59 seconds
Started Jul 24 05:56:35 PM PDT 24
Finished Jul 24 05:56:51 PM PDT 24
Peak memory 216504 kb
Host smart-8d54dd8f-d6d3-419d-b76d-c84f846549a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382669958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.2382669958
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.1051556498
Short name T763
Test name
Test status
Simulation time 220549006 ps
CPU time 4.45 seconds
Started Jul 24 05:56:39 PM PDT 24
Finished Jul 24 05:56:43 PM PDT 24
Peak memory 216408 kb
Host smart-f7d098a9-2199-4c39-817c-16fa4bed5659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051556498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.1051556498
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.1715506779
Short name T749
Test name
Test status
Simulation time 39893657 ps
CPU time 0.78 seconds
Started Jul 24 05:56:34 PM PDT 24
Finished Jul 24 05:56:34 PM PDT 24
Peak memory 206100 kb
Host smart-24d87cf8-19e8-4fcf-b95f-abcfbce8beea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715506779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.1715506779
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.819430153
Short name T538
Test name
Test status
Simulation time 296499072 ps
CPU time 3.2 seconds
Started Jul 24 05:56:40 PM PDT 24
Finished Jul 24 05:56:43 PM PDT 24
Peak memory 224660 kb
Host smart-00b85b0a-716f-45a5-a201-df7b32eead84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819430153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.819430153
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.203123122
Short name T454
Test name
Test status
Simulation time 27390515 ps
CPU time 0.7 seconds
Started Jul 24 05:56:48 PM PDT 24
Finished Jul 24 05:56:49 PM PDT 24
Peak memory 204988 kb
Host smart-5b997bfa-3a7f-46bb-b345-4bb1177469b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203123122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.203123122
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.1666873826
Short name T426
Test name
Test status
Simulation time 120232100 ps
CPU time 2.61 seconds
Started Jul 24 05:56:40 PM PDT 24
Finished Jul 24 05:56:43 PM PDT 24
Peak memory 224696 kb
Host smart-af1e0cce-a14e-481f-b8a4-d8f4383d2786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666873826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.1666873826
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.1520826437
Short name T674
Test name
Test status
Simulation time 45697245 ps
CPU time 0.77 seconds
Started Jul 24 05:56:40 PM PDT 24
Finished Jul 24 05:56:41 PM PDT 24
Peak memory 206732 kb
Host smart-d7ea259e-49c4-42d6-b2b3-74615a5bb31c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520826437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.1520826437
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.1126684274
Short name T270
Test name
Test status
Simulation time 19387264257 ps
CPU time 206.52 seconds
Started Jul 24 05:56:45 PM PDT 24
Finished Jul 24 06:00:11 PM PDT 24
Peak memory 267512 kb
Host smart-e39dba9b-a691-41e4-9ba7-832714abc5b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126684274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.1126684274
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.1791791551
Short name T453
Test name
Test status
Simulation time 33247507891 ps
CPU time 208.14 seconds
Started Jul 24 05:56:44 PM PDT 24
Finished Jul 24 06:00:12 PM PDT 24
Peak memory 267400 kb
Host smart-517cf50c-21ea-4845-95a0-9862339b5692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791791551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.1791791551
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.2153416017
Short name T556
Test name
Test status
Simulation time 4377411991 ps
CPU time 24.63 seconds
Started Jul 24 05:56:47 PM PDT 24
Finished Jul 24 05:57:12 PM PDT 24
Peak memory 241160 kb
Host smart-233dfc7c-2652-4d24-9e25-3f7691e345b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153416017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.2153416017
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.1359356941
Short name T434
Test name
Test status
Simulation time 294981565 ps
CPU time 2.43 seconds
Started Jul 24 05:56:41 PM PDT 24
Finished Jul 24 05:56:44 PM PDT 24
Peak memory 224712 kb
Host smart-21835bfa-367d-48e5-9c75-4e4be930c4de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359356941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.1359356941
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.2890040510
Short name T570
Test name
Test status
Simulation time 12931363 ps
CPU time 0.76 seconds
Started Jul 24 05:56:48 PM PDT 24
Finished Jul 24 05:56:49 PM PDT 24
Peak memory 207624 kb
Host smart-9143ca35-3a93-4d9f-902c-1bfe79f6d022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890040510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmd
s.2890040510
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_intercept.1687392868
Short name T690
Test name
Test status
Simulation time 262249265 ps
CPU time 5.65 seconds
Started Jul 24 05:56:38 PM PDT 24
Finished Jul 24 05:56:44 PM PDT 24
Peak memory 232868 kb
Host smart-5f22640c-b96d-4d3e-a3f5-f4c3aba85dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687392868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.1687392868
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.179602313
Short name T683
Test name
Test status
Simulation time 549627815 ps
CPU time 10.8 seconds
Started Jul 24 05:56:38 PM PDT 24
Finished Jul 24 05:56:49 PM PDT 24
Peak memory 232836 kb
Host smart-d8dcbe3b-a12f-49be-a67a-31e3d83156ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179602313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.179602313
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.199784300
Short name T992
Test name
Test status
Simulation time 147853328 ps
CPU time 2.25 seconds
Started Jul 24 05:56:39 PM PDT 24
Finished Jul 24 05:56:41 PM PDT 24
Peak memory 232604 kb
Host smart-8f409f3f-af2e-4aaa-85cd-569b1c9e1c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199784300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swap
.199784300
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.505667691
Short name T225
Test name
Test status
Simulation time 17687698889 ps
CPU time 17.88 seconds
Started Jul 24 05:56:40 PM PDT 24
Finished Jul 24 05:56:58 PM PDT 24
Peak memory 233020 kb
Host smart-a7947db5-6b2b-4598-bdaf-882646d641ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505667691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.505667691
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.76625433
Short name T649
Test name
Test status
Simulation time 264501991 ps
CPU time 4.48 seconds
Started Jul 24 05:56:48 PM PDT 24
Finished Jul 24 05:56:52 PM PDT 24
Peak memory 222940 kb
Host smart-a212d521-7b73-47bb-9282-bd3402a46cc9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=76625433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_direc
t.76625433
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.584054383
Short name T421
Test name
Test status
Simulation time 47857997 ps
CPU time 0.99 seconds
Started Jul 24 05:56:45 PM PDT 24
Finished Jul 24 05:56:46 PM PDT 24
Peak memory 207868 kb
Host smart-5b89579d-0c27-4007-b31f-2c01afed809d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584054383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stres
s_all.584054383
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.281482148
Short name T972
Test name
Test status
Simulation time 4064080935 ps
CPU time 16.33 seconds
Started Jul 24 05:56:40 PM PDT 24
Finished Jul 24 05:56:56 PM PDT 24
Peak memory 216472 kb
Host smart-06eb752e-b154-4d0e-a727-01fbc0b43692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281482148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.281482148
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.2921733925
Short name T792
Test name
Test status
Simulation time 4699384689 ps
CPU time 7.37 seconds
Started Jul 24 05:56:41 PM PDT 24
Finished Jul 24 05:56:49 PM PDT 24
Peak memory 216444 kb
Host smart-09a92e84-7e3c-4765-a2a4-37f15fa41c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921733925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.2921733925
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.2621281813
Short name T611
Test name
Test status
Simulation time 46924768 ps
CPU time 1.69 seconds
Started Jul 24 05:56:39 PM PDT 24
Finished Jul 24 05:56:41 PM PDT 24
Peak memory 216456 kb
Host smart-c6582180-11cd-4f75-b970-40693e1f1585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621281813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.2621281813
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.1886580965
Short name T719
Test name
Test status
Simulation time 115875856 ps
CPU time 0.98 seconds
Started Jul 24 05:56:39 PM PDT 24
Finished Jul 24 05:56:40 PM PDT 24
Peak memory 206112 kb
Host smart-8e9cccd0-03b6-475d-ab5c-ae1bc028a17b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886580965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.1886580965
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.2256411366
Short name T73
Test name
Test status
Simulation time 376115654 ps
CPU time 3.51 seconds
Started Jul 24 05:56:40 PM PDT 24
Finished Jul 24 05:56:44 PM PDT 24
Peak memory 224736 kb
Host smart-63b815ce-127e-4343-a980-ecb4901600aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256411366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.2256411366
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.554586082
Short name T831
Test name
Test status
Simulation time 43791877 ps
CPU time 0.7 seconds
Started Jul 24 05:56:48 PM PDT 24
Finished Jul 24 05:56:49 PM PDT 24
Peak memory 205888 kb
Host smart-03f48cf5-d8ec-47b3-b0ff-f7afc7d28271
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554586082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.554586082
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.2297026589
Short name T914
Test name
Test status
Simulation time 4373619700 ps
CPU time 14.2 seconds
Started Jul 24 05:56:45 PM PDT 24
Finished Jul 24 05:57:00 PM PDT 24
Peak memory 224636 kb
Host smart-3019024b-1b18-42d1-8e40-62898aa57ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297026589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.2297026589
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.616287354
Short name T340
Test name
Test status
Simulation time 33412674 ps
CPU time 0.83 seconds
Started Jul 24 05:56:44 PM PDT 24
Finished Jul 24 05:56:45 PM PDT 24
Peak memory 206740 kb
Host smart-9f9eadb5-36ae-4330-9b3b-a9350dbb59a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616287354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.616287354
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.3260743460
Short name T810
Test name
Test status
Simulation time 6640181121 ps
CPU time 11.95 seconds
Started Jul 24 05:56:47 PM PDT 24
Finished Jul 24 05:57:00 PM PDT 24
Peak memory 236672 kb
Host smart-035e6c73-6012-4527-8f91-b48328dfbcba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260743460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.3260743460
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.2288116571
Short name T1008
Test name
Test status
Simulation time 60659515919 ps
CPU time 232.27 seconds
Started Jul 24 05:56:47 PM PDT 24
Finished Jul 24 06:00:39 PM PDT 24
Peak memory 253112 kb
Host smart-cf7dee41-5366-4a06-91bf-cc07308e2db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288116571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.2288116571
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.1818643275
Short name T549
Test name
Test status
Simulation time 6438276924 ps
CPU time 41.95 seconds
Started Jul 24 05:56:46 PM PDT 24
Finished Jul 24 05:57:28 PM PDT 24
Peak memory 251308 kb
Host smart-76ee4ffb-6bfe-4d29-93bb-ec5f37d5a3fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818643275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.1818643275
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.3379623023
Short name T138
Test name
Test status
Simulation time 529366608 ps
CPU time 12.62 seconds
Started Jul 24 05:56:48 PM PDT 24
Finished Jul 24 05:57:01 PM PDT 24
Peak memory 241112 kb
Host smart-333b5681-6a5d-465e-b947-72f0a275369a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379623023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.3379623023
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.3000878695
Short name T902
Test name
Test status
Simulation time 3885203993 ps
CPU time 32.25 seconds
Started Jul 24 05:56:44 PM PDT 24
Finished Jul 24 05:57:16 PM PDT 24
Peak memory 235072 kb
Host smart-88ad9cd6-a669-4f13-822e-b13ba0825548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000878695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmd
s.3000878695
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_intercept.1757812206
Short name T698
Test name
Test status
Simulation time 761292065 ps
CPU time 5.8 seconds
Started Jul 24 05:56:46 PM PDT 24
Finished Jul 24 05:56:52 PM PDT 24
Peak memory 232828 kb
Host smart-e6a68050-9ff3-4b1b-8d43-51ab897dde55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757812206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.1757812206
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.3927250324
Short name T554
Test name
Test status
Simulation time 23622926694 ps
CPU time 47.64 seconds
Started Jul 24 05:56:47 PM PDT 24
Finished Jul 24 05:57:35 PM PDT 24
Peak memory 232932 kb
Host smart-1d760390-eaf2-4489-b502-bdf508cc728a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927250324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.3927250324
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.3128986696
Short name T561
Test name
Test status
Simulation time 16970527170 ps
CPU time 13.61 seconds
Started Jul 24 05:56:47 PM PDT 24
Finished Jul 24 05:57:01 PM PDT 24
Peak memory 224680 kb
Host smart-3f35216d-099b-4c94-b74d-018e60a3eea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128986696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.3128986696
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.384203403
Short name T845
Test name
Test status
Simulation time 4228771405 ps
CPU time 9.89 seconds
Started Jul 24 05:56:44 PM PDT 24
Finished Jul 24 05:56:54 PM PDT 24
Peak memory 232884 kb
Host smart-513fca6a-6c23-48e6-87c8-9ba1f6ab46a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384203403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.384203403
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.1844583763
Short name T485
Test name
Test status
Simulation time 440922431 ps
CPU time 4.9 seconds
Started Jul 24 05:56:45 PM PDT 24
Finished Jul 24 05:56:51 PM PDT 24
Peak memory 220584 kb
Host smart-5671c651-432b-4747-83a3-10ff23753847
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1844583763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.1844583763
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.487436150
Short name T945
Test name
Test status
Simulation time 43887578631 ps
CPU time 446.02 seconds
Started Jul 24 05:56:48 PM PDT 24
Finished Jul 24 06:04:14 PM PDT 24
Peak memory 282184 kb
Host smart-28f0dd02-7719-4dc7-8a8d-f343d6c1aa4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487436150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stres
s_all.487436150
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.2815585636
Short name T2
Test name
Test status
Simulation time 3962046768 ps
CPU time 8.71 seconds
Started Jul 24 05:56:47 PM PDT 24
Finished Jul 24 05:56:56 PM PDT 24
Peak memory 216588 kb
Host smart-3dafe339-6099-42d5-a643-e1ffafc8057b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815585636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.2815585636
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.4082891503
Short name T643
Test name
Test status
Simulation time 2134984803 ps
CPU time 9.51 seconds
Started Jul 24 05:56:44 PM PDT 24
Finished Jul 24 05:56:54 PM PDT 24
Peak memory 216288 kb
Host smart-fe40c2a7-617c-40c9-928b-d7a3ca4faa68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082891503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.4082891503
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.1483265980
Short name T159
Test name
Test status
Simulation time 25773552 ps
CPU time 1.07 seconds
Started Jul 24 05:56:45 PM PDT 24
Finished Jul 24 05:56:47 PM PDT 24
Peak memory 207772 kb
Host smart-9543f0a1-ea65-4d4c-a269-8b1ff9bbfeaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483265980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.1483265980
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.2398389396
Short name T944
Test name
Test status
Simulation time 72873684 ps
CPU time 0.92 seconds
Started Jul 24 05:56:47 PM PDT 24
Finished Jul 24 05:56:48 PM PDT 24
Peak memory 206080 kb
Host smart-1bcde095-6f23-4ea2-80e3-a37a332704ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398389396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.2398389396
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.4221897914
Short name T480
Test name
Test status
Simulation time 1799914410 ps
CPU time 8.15 seconds
Started Jul 24 05:56:43 PM PDT 24
Finished Jul 24 05:56:52 PM PDT 24
Peak memory 232892 kb
Host smart-5ba9a1f4-af79-476c-a6e5-252d2c572368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221897914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.4221897914
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.1938562625
Short name T864
Test name
Test status
Simulation time 14620926 ps
CPU time 0.75 seconds
Started Jul 24 05:54:11 PM PDT 24
Finished Jul 24 05:54:12 PM PDT 24
Peak memory 205932 kb
Host smart-f87b0ace-2811-45bc-a6f8-84eb5a111775
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938562625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.1
938562625
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.1244984985
Short name T787
Test name
Test status
Simulation time 814269008 ps
CPU time 4.98 seconds
Started Jul 24 05:54:10 PM PDT 24
Finished Jul 24 05:54:15 PM PDT 24
Peak memory 224676 kb
Host smart-3bdfd60a-00b3-48b1-912c-97df42eb55d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244984985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.1244984985
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.2365354529
Short name T525
Test name
Test status
Simulation time 156683396 ps
CPU time 0.8 seconds
Started Jul 24 05:54:09 PM PDT 24
Finished Jul 24 05:54:10 PM PDT 24
Peak memory 207060 kb
Host smart-2878af1d-d0a0-4087-b39f-73af8c973207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365354529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.2365354529
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.4287720574
Short name T1006
Test name
Test status
Simulation time 9770829676 ps
CPU time 66.34 seconds
Started Jul 24 05:54:09 PM PDT 24
Finished Jul 24 05:55:16 PM PDT 24
Peak memory 257488 kb
Host smart-e7599e96-feb4-406b-992a-579aba21601c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287720574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.4287720574
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.2822303788
Short name T438
Test name
Test status
Simulation time 2496114078 ps
CPU time 28.87 seconds
Started Jul 24 05:54:08 PM PDT 24
Finished Jul 24 05:54:37 PM PDT 24
Peak memory 237612 kb
Host smart-31333e94-c4e5-45a5-a772-f129ce4711b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822303788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.2822303788
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.3242477020
Short name T310
Test name
Test status
Simulation time 815487233 ps
CPU time 8.75 seconds
Started Jul 24 05:54:08 PM PDT 24
Finished Jul 24 05:54:16 PM PDT 24
Peak memory 224700 kb
Host smart-0cf6ca6b-05c3-4dd4-bb4c-3cd784b69df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242477020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.3242477020
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.2359967999
Short name T760
Test name
Test status
Simulation time 5359650260 ps
CPU time 29.73 seconds
Started Jul 24 05:54:08 PM PDT 24
Finished Jul 24 05:54:38 PM PDT 24
Peak memory 249724 kb
Host smart-4fbdeefc-1009-44b0-a861-8936dd1251e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359967999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds
.2359967999
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_intercept.3006403566
Short name T93
Test name
Test status
Simulation time 297289732 ps
CPU time 3.44 seconds
Started Jul 24 05:54:07 PM PDT 24
Finished Jul 24 05:54:11 PM PDT 24
Peak memory 232744 kb
Host smart-8dba50e1-9914-4313-b1b1-8138025621b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006403566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.3006403566
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.1606577875
Short name T837
Test name
Test status
Simulation time 2227253833 ps
CPU time 12.62 seconds
Started Jul 24 05:54:08 PM PDT 24
Finished Jul 24 05:54:21 PM PDT 24
Peak memory 232976 kb
Host smart-a15b84bd-d905-4771-bdf7-959693781a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606577875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.1606577875
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.2660235770
Short name T272
Test name
Test status
Simulation time 52563045958 ps
CPU time 31.4 seconds
Started Jul 24 05:54:07 PM PDT 24
Finished Jul 24 05:54:39 PM PDT 24
Peak memory 232908 kb
Host smart-ffe64a8a-f188-4165-bd8e-e88883a33cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660235770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.2660235770
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.365707096
Short name T397
Test name
Test status
Simulation time 6710845741 ps
CPU time 13.31 seconds
Started Jul 24 05:54:06 PM PDT 24
Finished Jul 24 05:54:19 PM PDT 24
Peak memory 224792 kb
Host smart-f2c7ffe6-220c-43c9-8679-e68823e5b172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365707096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.365707096
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.3758694305
Short name T338
Test name
Test status
Simulation time 504593981 ps
CPU time 5.95 seconds
Started Jul 24 05:54:07 PM PDT 24
Finished Jul 24 05:54:13 PM PDT 24
Peak memory 219480 kb
Host smart-d46fbbad-b6bd-4318-933c-b7f7bba7fb7e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3758694305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.3758694305
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.3073102298
Short name T507
Test name
Test status
Simulation time 4197850948 ps
CPU time 20.85 seconds
Started Jul 24 05:54:07 PM PDT 24
Finished Jul 24 05:54:28 PM PDT 24
Peak memory 216464 kb
Host smart-b92b71e3-b287-4032-a1bb-c30531febd78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073102298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.3073102298
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.1833190735
Short name T555
Test name
Test status
Simulation time 379266325 ps
CPU time 1.86 seconds
Started Jul 24 05:54:11 PM PDT 24
Finished Jul 24 05:54:13 PM PDT 24
Peak memory 207984 kb
Host smart-5432ec30-110d-40bf-a750-c605cb392288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833190735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.1833190735
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.2156462081
Short name T131
Test name
Test status
Simulation time 33310021 ps
CPU time 1.32 seconds
Started Jul 24 05:54:06 PM PDT 24
Finished Jul 24 05:54:08 PM PDT 24
Peak memory 216464 kb
Host smart-94d890fd-9b0a-424c-909f-47db93ead47e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156462081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.2156462081
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.213318295
Short name T373
Test name
Test status
Simulation time 65623271 ps
CPU time 0.89 seconds
Started Jul 24 05:54:08 PM PDT 24
Finished Jul 24 05:54:09 PM PDT 24
Peak memory 206096 kb
Host smart-a944b048-ea76-416a-b357-4ceab4affea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213318295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.213318295
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.1431342703
Short name T986
Test name
Test status
Simulation time 18260924007 ps
CPU time 10.27 seconds
Started Jul 24 05:54:10 PM PDT 24
Finished Jul 24 05:54:20 PM PDT 24
Peak memory 224776 kb
Host smart-fd4d26d6-46bb-4a70-b78e-242592fdec3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431342703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.1431342703
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.1218614005
Short name T924
Test name
Test status
Simulation time 32127173 ps
CPU time 0.7 seconds
Started Jul 24 05:54:19 PM PDT 24
Finished Jul 24 05:54:20 PM PDT 24
Peak memory 205928 kb
Host smart-15a46f3e-dbd9-48e8-8dce-b090da5e77ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218614005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.1
218614005
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.3846201593
Short name T3
Test name
Test status
Simulation time 72290516 ps
CPU time 2.53 seconds
Started Jul 24 05:54:13 PM PDT 24
Finished Jul 24 05:54:16 PM PDT 24
Peak memory 232872 kb
Host smart-f3740e6c-05b3-472c-af19-d128735abbb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846201593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.3846201593
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.755410783
Short name T784
Test name
Test status
Simulation time 16944649 ps
CPU time 0.76 seconds
Started Jul 24 05:54:08 PM PDT 24
Finished Jul 24 05:54:09 PM PDT 24
Peak memory 207072 kb
Host smart-4d59988a-75a4-4175-90bb-1fc45d320431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755410783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.755410783
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.1428819128
Short name T841
Test name
Test status
Simulation time 39898674 ps
CPU time 0.74 seconds
Started Jul 24 05:54:11 PM PDT 24
Finished Jul 24 05:54:12 PM PDT 24
Peak memory 215852 kb
Host smart-5e3dbcbd-fd65-42be-b112-074b4e94fd95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428819128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.1428819128
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.643091955
Short name T134
Test name
Test status
Simulation time 37474030848 ps
CPU time 203.64 seconds
Started Jul 24 05:54:10 PM PDT 24
Finished Jul 24 05:57:33 PM PDT 24
Peak memory 271680 kb
Host smart-1996dd48-2ab2-4cd1-a4b4-0ccef8846473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643091955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.643091955
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.345389336
Short name T446
Test name
Test status
Simulation time 7466470510 ps
CPU time 52.71 seconds
Started Jul 24 05:54:11 PM PDT 24
Finished Jul 24 05:55:04 PM PDT 24
Peak memory 250112 kb
Host smart-d932d6ae-3485-4ad0-89d9-1978860b961a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345389336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle.
345389336
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.3286685706
Short name T404
Test name
Test status
Simulation time 595958552 ps
CPU time 6.71 seconds
Started Jul 24 05:54:12 PM PDT 24
Finished Jul 24 05:54:19 PM PDT 24
Peak memory 232960 kb
Host smart-fb49324a-bc0d-49ad-9ef6-8d743c5a9602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286685706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.3286685706
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_intercept.3308410911
Short name T817
Test name
Test status
Simulation time 1770811371 ps
CPU time 5.43 seconds
Started Jul 24 05:54:13 PM PDT 24
Finished Jul 24 05:54:19 PM PDT 24
Peak memory 224684 kb
Host smart-86703057-45e7-49a6-891a-1695d05e6347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308410911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.3308410911
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.223114720
Short name T979
Test name
Test status
Simulation time 393335820 ps
CPU time 8.31 seconds
Started Jul 24 05:54:10 PM PDT 24
Finished Jul 24 05:54:18 PM PDT 24
Peak memory 240816 kb
Host smart-07896701-9097-4403-a89d-9f19a0e76af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223114720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.223114720
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.4013118312
Short name T524
Test name
Test status
Simulation time 1150135888 ps
CPU time 5.34 seconds
Started Jul 24 05:54:11 PM PDT 24
Finished Jul 24 05:54:17 PM PDT 24
Peak memory 224648 kb
Host smart-46d386d6-5ab9-4e5c-9380-9767c3822f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013118312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.4013118312
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.503177684
Short name T612
Test name
Test status
Simulation time 1059484077 ps
CPU time 5.75 seconds
Started Jul 24 05:54:11 PM PDT 24
Finished Jul 24 05:54:17 PM PDT 24
Peak memory 232784 kb
Host smart-7e33215f-3e0d-439a-9204-d478cb143730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503177684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.503177684
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.2770431602
Short name T34
Test name
Test status
Simulation time 539480016 ps
CPU time 5.88 seconds
Started Jul 24 05:54:07 PM PDT 24
Finished Jul 24 05:54:13 PM PDT 24
Peak memory 223324 kb
Host smart-a312bacc-e407-489c-ab7e-da69271f4d37
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2770431602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.2770431602
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.283688693
Short name T933
Test name
Test status
Simulation time 68252603652 ps
CPU time 208.92 seconds
Started Jul 24 05:54:07 PM PDT 24
Finished Jul 24 05:57:36 PM PDT 24
Peak memory 256856 kb
Host smart-8ea69c52-8ef7-4a73-b307-3b1017e854ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283688693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stress
_all.283688693
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.2418768083
Short name T910
Test name
Test status
Simulation time 2711831025 ps
CPU time 7.99 seconds
Started Jul 24 05:54:10 PM PDT 24
Finished Jul 24 05:54:18 PM PDT 24
Peak memory 216592 kb
Host smart-79bbb763-69ae-4511-83ce-0f731406f922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418768083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.2418768083
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.1038320366
Short name T365
Test name
Test status
Simulation time 1293968927 ps
CPU time 5.45 seconds
Started Jul 24 05:54:11 PM PDT 24
Finished Jul 24 05:54:16 PM PDT 24
Peak memory 216448 kb
Host smart-ecf2530a-a8fa-43d7-923d-33e390fc3a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038320366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.1038320366
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.2418249832
Short name T328
Test name
Test status
Simulation time 57693968 ps
CPU time 1.36 seconds
Started Jul 24 05:54:09 PM PDT 24
Finished Jul 24 05:54:10 PM PDT 24
Peak memory 208256 kb
Host smart-d3af10b6-afee-4bd0-8709-569587d4f20a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418249832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.2418249832
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.3778536530
Short name T671
Test name
Test status
Simulation time 36646746 ps
CPU time 0.81 seconds
Started Jul 24 05:54:12 PM PDT 24
Finished Jul 24 05:54:13 PM PDT 24
Peak memory 206144 kb
Host smart-e7234fc5-2e4f-4f2f-a401-fe4b50eb4a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778536530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.3778536530
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.2269210247
Short name T371
Test name
Test status
Simulation time 79947724 ps
CPU time 2.54 seconds
Started Jul 24 05:54:12 PM PDT 24
Finished Jul 24 05:54:14 PM PDT 24
Peak memory 232788 kb
Host smart-4fcb06e6-d634-4fd3-a339-1be77f171b6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269210247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.2269210247
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.2055324332
Short name T9
Test name
Test status
Simulation time 25824753 ps
CPU time 0.77 seconds
Started Jul 24 05:54:15 PM PDT 24
Finished Jul 24 05:54:16 PM PDT 24
Peak memory 205904 kb
Host smart-f4ae6bb4-3ec5-4b68-aa7c-64ca533402ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055324332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.2
055324332
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.4265822601
Short name T536
Test name
Test status
Simulation time 72942566 ps
CPU time 3.17 seconds
Started Jul 24 05:54:17 PM PDT 24
Finished Jul 24 05:54:20 PM PDT 24
Peak memory 232908 kb
Host smart-a91fad0c-6f3b-49d6-b271-19d0204605b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265822601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.4265822601
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.1368076607
Short name T765
Test name
Test status
Simulation time 68348030 ps
CPU time 0.85 seconds
Started Jul 24 05:54:15 PM PDT 24
Finished Jul 24 05:54:16 PM PDT 24
Peak memory 206732 kb
Host smart-9104adbe-034a-46de-886a-615add1cb33f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368076607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.1368076607
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.1254832310
Short name T244
Test name
Test status
Simulation time 53613195850 ps
CPU time 131.65 seconds
Started Jul 24 05:54:15 PM PDT 24
Finished Jul 24 05:56:27 PM PDT 24
Peak memory 254164 kb
Host smart-a9cd974c-61a3-48d6-9e61-b80306de8dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254832310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.1254832310
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.3820873187
Short name T931
Test name
Test status
Simulation time 19899864129 ps
CPU time 143.04 seconds
Started Jul 24 05:54:16 PM PDT 24
Finished Jul 24 05:56:40 PM PDT 24
Peak memory 263108 kb
Host smart-95cc9399-e544-4c81-a8df-5ff611e2a673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820873187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.3820873187
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.2490219288
Short name T195
Test name
Test status
Simulation time 34930930057 ps
CPU time 202.93 seconds
Started Jul 24 05:54:19 PM PDT 24
Finished Jul 24 05:57:42 PM PDT 24
Peak memory 257552 kb
Host smart-69a15c05-5717-449b-b2ae-6e6e6cb910c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490219288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.2490219288
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.1992610767
Short name T530
Test name
Test status
Simulation time 1113869928 ps
CPU time 7.35 seconds
Started Jul 24 05:54:15 PM PDT 24
Finished Jul 24 05:54:23 PM PDT 24
Peak memory 224648 kb
Host smart-1b532f8f-fbf4-4dda-a757-3c2d9241fe0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992610767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.1992610767
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.3711475800
Short name T181
Test name
Test status
Simulation time 36234604645 ps
CPU time 59.08 seconds
Started Jul 24 05:54:16 PM PDT 24
Finished Jul 24 05:55:15 PM PDT 24
Peak memory 235828 kb
Host smart-fe0af8f5-60a6-47eb-bd5f-34e016104ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711475800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds
.3711475800
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.845161517
Short name T217
Test name
Test status
Simulation time 446471457 ps
CPU time 6.22 seconds
Started Jul 24 05:54:20 PM PDT 24
Finished Jul 24 05:54:27 PM PDT 24
Peak memory 229928 kb
Host smart-44d2bd78-702e-4bf4-85ff-b07913a76fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845161517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.845161517
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.2244089240
Short name T705
Test name
Test status
Simulation time 14924449279 ps
CPU time 41.91 seconds
Started Jul 24 05:54:16 PM PDT 24
Finished Jul 24 05:54:58 PM PDT 24
Peak memory 241184 kb
Host smart-b7a91677-a4c4-49a8-85ca-2ecb118a2c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244089240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.2244089240
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.3841045139
Short name T856
Test name
Test status
Simulation time 108389894 ps
CPU time 2.43 seconds
Started Jul 24 05:54:17 PM PDT 24
Finished Jul 24 05:54:20 PM PDT 24
Peak memory 224048 kb
Host smart-847c687e-7a55-47ea-a703-94453da9896e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841045139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.3841045139
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.2650359142
Short name T677
Test name
Test status
Simulation time 867587889 ps
CPU time 8.28 seconds
Started Jul 24 05:54:14 PM PDT 24
Finished Jul 24 05:54:22 PM PDT 24
Peak memory 223160 kb
Host smart-0468500b-1c72-437a-a454-f6c7086b7ce2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2650359142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.2650359142
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.2725771255
Short name T154
Test name
Test status
Simulation time 62661937451 ps
CPU time 338.58 seconds
Started Jul 24 05:54:15 PM PDT 24
Finished Jul 24 05:59:53 PM PDT 24
Peak memory 254616 kb
Host smart-6f2e5cb8-7b26-4b49-a03d-4c0f582d6fbd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725771255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.2725771255
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.3488087047
Short name T916
Test name
Test status
Simulation time 1308582877 ps
CPU time 2.69 seconds
Started Jul 24 05:54:20 PM PDT 24
Finished Jul 24 05:54:23 PM PDT 24
Peak memory 216392 kb
Host smart-0ae0e24b-7b7c-4895-bac1-9fe92120e799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488087047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.3488087047
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.2248989703
Short name T957
Test name
Test status
Simulation time 4753467323 ps
CPU time 12.65 seconds
Started Jul 24 05:54:14 PM PDT 24
Finished Jul 24 05:54:27 PM PDT 24
Peak memory 216444 kb
Host smart-8abd25ee-37c4-41b7-a9cc-8da60c990d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248989703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.2248989703
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.1094866639
Short name T132
Test name
Test status
Simulation time 228501204 ps
CPU time 1.93 seconds
Started Jul 24 05:54:16 PM PDT 24
Finished Jul 24 05:54:18 PM PDT 24
Peak memory 216440 kb
Host smart-dfbf031c-98cd-48e5-abb6-578dc45fb7d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094866639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.1094866639
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.2726534157
Short name T768
Test name
Test status
Simulation time 141302829 ps
CPU time 0.87 seconds
Started Jul 24 05:54:16 PM PDT 24
Finished Jul 24 05:54:17 PM PDT 24
Peak memory 206156 kb
Host smart-9285edd7-70df-46ed-9393-639f81260751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726534157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.2726534157
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.1781542661
Short name T980
Test name
Test status
Simulation time 1573981462 ps
CPU time 6.93 seconds
Started Jul 24 05:54:18 PM PDT 24
Finished Jul 24 05:54:25 PM PDT 24
Peak memory 232892 kb
Host smart-ab1b15fa-944c-49d4-b8b2-91c806827bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781542661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.1781542661
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.2578526143
Short name T56
Test name
Test status
Simulation time 12696853 ps
CPU time 0.71 seconds
Started Jul 24 05:54:23 PM PDT 24
Finished Jul 24 05:54:23 PM PDT 24
Peak memory 205008 kb
Host smart-da2581c8-571d-414c-8224-7bb83f82cd3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578526143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.2
578526143
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.4207275456
Short name T839
Test name
Test status
Simulation time 497044100 ps
CPU time 6.02 seconds
Started Jul 24 05:54:21 PM PDT 24
Finished Jul 24 05:54:27 PM PDT 24
Peak memory 224688 kb
Host smart-db7ddff8-73c0-49df-9c33-520679d06dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207275456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.4207275456
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.483590725
Short name T843
Test name
Test status
Simulation time 47077424 ps
CPU time 0.79 seconds
Started Jul 24 05:54:17 PM PDT 24
Finished Jul 24 05:54:18 PM PDT 24
Peak memory 206740 kb
Host smart-7696d0e6-d604-42f6-93be-5772c5c98f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483590725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.483590725
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.47949971
Short name T615
Test name
Test status
Simulation time 48924176705 ps
CPU time 82.65 seconds
Started Jul 24 05:54:25 PM PDT 24
Finished Jul 24 05:55:48 PM PDT 24
Peak memory 237624 kb
Host smart-dbfa23cf-87d6-4139-9b01-774879cda279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47949971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.47949971
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.3787814352
Short name T212
Test name
Test status
Simulation time 3625638165 ps
CPU time 56.35 seconds
Started Jul 24 05:54:28 PM PDT 24
Finished Jul 24 05:55:25 PM PDT 24
Peak memory 250276 kb
Host smart-dc0c63e8-144d-4be1-a3fc-25d48b61d699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787814352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.3787814352
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.43369710
Short name T79
Test name
Test status
Simulation time 76471387955 ps
CPU time 349.2 seconds
Started Jul 24 05:54:22 PM PDT 24
Finished Jul 24 06:00:11 PM PDT 24
Peak memory 263388 kb
Host smart-667ba7da-4544-43a8-94ca-18721ea71585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43369710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle.43369710
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.3634799987
Short name T730
Test name
Test status
Simulation time 57308478 ps
CPU time 3.35 seconds
Started Jul 24 05:54:24 PM PDT 24
Finished Jul 24 05:54:27 PM PDT 24
Peak memory 224728 kb
Host smart-6556a34d-5420-44eb-914f-6f3365c41a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634799987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.3634799987
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.1221480405
Short name T183
Test name
Test status
Simulation time 1177864655 ps
CPU time 18.89 seconds
Started Jul 24 05:54:26 PM PDT 24
Finished Jul 24 05:54:45 PM PDT 24
Peak memory 232960 kb
Host smart-c9870865-4be5-44ce-a088-6c9f1c681241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221480405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds
.1221480405
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/8.spi_device_intercept.51273955
Short name T568
Test name
Test status
Simulation time 96766174 ps
CPU time 2.25 seconds
Started Jul 24 05:54:19 PM PDT 24
Finished Jul 24 05:54:21 PM PDT 24
Peak memory 218820 kb
Host smart-82aaf38c-96bf-4a6a-962c-bd9e2af7b23d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51273955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.51273955
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.3440139633
Short name T443
Test name
Test status
Simulation time 23624241106 ps
CPU time 59.32 seconds
Started Jul 24 05:54:15 PM PDT 24
Finished Jul 24 05:55:14 PM PDT 24
Peak memory 232896 kb
Host smart-b717307e-cb7e-427b-accb-7ed99e299482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440139633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.3440139633
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.3706800274
Short name T274
Test name
Test status
Simulation time 3014308955 ps
CPU time 8.36 seconds
Started Jul 24 05:54:14 PM PDT 24
Finished Jul 24 05:54:23 PM PDT 24
Peak memory 232924 kb
Host smart-6c7a0710-d54d-47c4-87b3-cdccdce53d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706800274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.3706800274
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.953985803
Short name T237
Test name
Test status
Simulation time 30584850178 ps
CPU time 25.48 seconds
Started Jul 24 05:54:17 PM PDT 24
Finished Jul 24 05:54:42 PM PDT 24
Peak memory 252484 kb
Host smart-770ac4ed-c09d-4cad-8ec5-3d8452618faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953985803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.953985803
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.3706200548
Short name T736
Test name
Test status
Simulation time 898835079 ps
CPU time 4.69 seconds
Started Jul 24 05:54:25 PM PDT 24
Finished Jul 24 05:54:30 PM PDT 24
Peak memory 220560 kb
Host smart-7efe6140-836f-417b-a55d-ce50252811ad
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3706200548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.3706200548
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.1981969688
Short name T873
Test name
Test status
Simulation time 41305652 ps
CPU time 1.05 seconds
Started Jul 24 05:54:23 PM PDT 24
Finished Jul 24 05:54:24 PM PDT 24
Peak memory 207080 kb
Host smart-87e2fa39-3027-4376-ae63-011ccedb03e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981969688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.1981969688
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.225043652
Short name T653
Test name
Test status
Simulation time 1059297739 ps
CPU time 10.61 seconds
Started Jul 24 05:54:20 PM PDT 24
Finished Jul 24 05:54:31 PM PDT 24
Peak memory 220000 kb
Host smart-8789778b-b01b-4360-9a7f-ea75ab17ed26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225043652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.225043652
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.1383902981
Short name T635
Test name
Test status
Simulation time 27571570 ps
CPU time 0.71 seconds
Started Jul 24 05:54:18 PM PDT 24
Finished Jul 24 05:54:19 PM PDT 24
Peak memory 205844 kb
Host smart-853e4416-3759-471b-b5db-2097066a6a41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383902981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.1383902981
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.1436262809
Short name T773
Test name
Test status
Simulation time 241478545 ps
CPU time 2.45 seconds
Started Jul 24 05:54:17 PM PDT 24
Finished Jul 24 05:54:19 PM PDT 24
Peak memory 216440 kb
Host smart-ffcb3457-63bf-4fbc-90e1-85f6f05a147e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436262809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.1436262809
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.277885990
Short name T997
Test name
Test status
Simulation time 29331034 ps
CPU time 0.81 seconds
Started Jul 24 05:54:16 PM PDT 24
Finished Jul 24 05:54:17 PM PDT 24
Peak memory 206164 kb
Host smart-4812e1d4-d1a1-4772-93f7-e9e9ae16aa1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277885990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.277885990
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.272927228
Short name T227
Test name
Test status
Simulation time 1616632352 ps
CPU time 6.61 seconds
Started Jul 24 05:54:22 PM PDT 24
Finished Jul 24 05:54:29 PM PDT 24
Peak memory 232816 kb
Host smart-8603665b-9169-47aa-abf9-a8a2c8dbe964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272927228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.272927228
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.1871746168
Short name T584
Test name
Test status
Simulation time 14454515 ps
CPU time 0.71 seconds
Started Jul 24 05:54:23 PM PDT 24
Finished Jul 24 05:54:24 PM PDT 24
Peak memory 204996 kb
Host smart-c1acc2e1-1b2c-422c-80e3-61301d24f694
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871746168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.1
871746168
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.214779737
Short name T998
Test name
Test status
Simulation time 246668053 ps
CPU time 2.17 seconds
Started Jul 24 05:54:25 PM PDT 24
Finished Jul 24 05:54:27 PM PDT 24
Peak memory 224660 kb
Host smart-0d25be0a-3890-44b6-bed8-58ab3421bf79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214779737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.214779737
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.1247290365
Short name T712
Test name
Test status
Simulation time 17626717 ps
CPU time 0.83 seconds
Started Jul 24 05:54:26 PM PDT 24
Finished Jul 24 05:54:27 PM PDT 24
Peak memory 206724 kb
Host smart-10ab1e51-90d6-4d64-8f8f-3795ed10434b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247290365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.1247290365
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.1167749084
Short name T283
Test name
Test status
Simulation time 14765560901 ps
CPU time 156.49 seconds
Started Jul 24 05:54:24 PM PDT 24
Finished Jul 24 05:57:00 PM PDT 24
Peak memory 254204 kb
Host smart-485c1680-a6cf-4eb4-96a9-55d5b1feba51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167749084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.1167749084
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.2335434603
Short name T231
Test name
Test status
Simulation time 49061352229 ps
CPU time 127.71 seconds
Started Jul 24 05:54:23 PM PDT 24
Finished Jul 24 05:56:31 PM PDT 24
Peak memory 240160 kb
Host smart-d386b3f1-8c95-460a-8105-c7d266672bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335434603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.2335434603
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.2194988466
Short name T368
Test name
Test status
Simulation time 355592469 ps
CPU time 5.34 seconds
Started Jul 24 05:54:23 PM PDT 24
Finished Jul 24 05:54:28 PM PDT 24
Peak memory 233908 kb
Host smart-309e5f45-3b11-4078-be26-0626e0096ab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194988466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.2194988466
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_intercept.193935269
Short name T572
Test name
Test status
Simulation time 363781391 ps
CPU time 6.23 seconds
Started Jul 24 05:54:28 PM PDT 24
Finished Jul 24 05:54:35 PM PDT 24
Peak memory 224768 kb
Host smart-c92b4c48-a46c-44dd-bf75-82ede75aaf7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193935269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.193935269
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.3158584397
Short name T941
Test name
Test status
Simulation time 4939853833 ps
CPU time 11.38 seconds
Started Jul 24 05:54:21 PM PDT 24
Finished Jul 24 05:54:33 PM PDT 24
Peak memory 240536 kb
Host smart-81bf7abb-deb8-4eaf-98a8-d95f86511ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158584397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.3158584397
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.3024717964
Short name T506
Test name
Test status
Simulation time 10961161393 ps
CPU time 28.75 seconds
Started Jul 24 05:54:23 PM PDT 24
Finished Jul 24 05:54:52 PM PDT 24
Peak memory 240316 kb
Host smart-2b7cf132-3c08-4245-9b80-5948b831a90c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024717964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.3024717964
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.1765932624
Short name T1010
Test name
Test status
Simulation time 3099358930 ps
CPU time 6.35 seconds
Started Jul 24 05:54:23 PM PDT 24
Finished Jul 24 05:54:29 PM PDT 24
Peak memory 232900 kb
Host smart-1d0c94cb-2962-46e4-bec0-06e53b3ad6fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765932624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.1765932624
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.2723693070
Short name T141
Test name
Test status
Simulation time 621506688 ps
CPU time 4.57 seconds
Started Jul 24 05:54:26 PM PDT 24
Finished Jul 24 05:54:31 PM PDT 24
Peak memory 219004 kb
Host smart-32a30260-0f4e-48b2-a6d3-32bf525a5994
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2723693070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.2723693070
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.4258273335
Short name T363
Test name
Test status
Simulation time 173056865 ps
CPU time 1.05 seconds
Started Jul 24 05:54:27 PM PDT 24
Finished Jul 24 05:54:29 PM PDT 24
Peak memory 206936 kb
Host smart-5441d7b7-0a7f-41cf-b1a2-26986ff3d5c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258273335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.4258273335
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.4199006725
Short name T746
Test name
Test status
Simulation time 4827908941 ps
CPU time 27.61 seconds
Started Jul 24 05:54:22 PM PDT 24
Finished Jul 24 05:54:50 PM PDT 24
Peak memory 220496 kb
Host smart-f6aa6ddf-4b86-460a-8395-3f0a694735a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199006725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.4199006725
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.3003398924
Short name T345
Test name
Test status
Simulation time 493013724 ps
CPU time 1.58 seconds
Started Jul 24 05:54:22 PM PDT 24
Finished Jul 24 05:54:24 PM PDT 24
Peak memory 207988 kb
Host smart-355d2cce-6c4b-427f-b74d-c6faeca867c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003398924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.3003398924
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.3571473011
Short name T411
Test name
Test status
Simulation time 60868523 ps
CPU time 2.34 seconds
Started Jul 24 05:54:24 PM PDT 24
Finished Jul 24 05:54:26 PM PDT 24
Peak memory 216464 kb
Host smart-149adf6e-f8c6-4be8-a65d-8edb9918d323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571473011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.3571473011
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.1790485137
Short name T738
Test name
Test status
Simulation time 22735458 ps
CPU time 0.73 seconds
Started Jul 24 05:54:23 PM PDT 24
Finished Jul 24 05:54:24 PM PDT 24
Peak memory 206128 kb
Host smart-2418a871-4c2c-45b1-b7f7-9c1dfa04dae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790485137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.1790485137
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.1025636835
Short name T190
Test name
Test status
Simulation time 5325440671 ps
CPU time 10.85 seconds
Started Jul 24 05:54:25 PM PDT 24
Finished Jul 24 05:54:36 PM PDT 24
Peak memory 232944 kb
Host smart-50583e5c-1f33-499d-a9eb-a2a4ee4db718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025636835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.1025636835
Directory /workspace/9.spi_device_upload/latest
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