Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2591404	1			T1	1		T2	10454		T3	1
all_values[1]	2591404	1			T1	1		T2	10454		T3	1
all_values[2]	2591404	1			T1	1		T2	10454		T3	1
all_values[3]	2591404	1			T1	1		T2	10454		T3	1
all_values[4]	2591404	1			T1	1		T2	10454		T3	1
all_values[5]	2591404	1			T1	1		T2	10454		T3	1
all_values[6]	2591404	1			T1	1		T2	10454		T3	1
all_values[7]	2591404	1			T1	1		T2	10454		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20421423

1

T1

8

T2

83632

T3

8

auto[1]

309809

1

T16

95

T63

42

T18

45

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20705296

1

T1

8

T2

83632

T3

8

auto[1]

25936

1

T10

14

T11

226

T15

103

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2517462	1			T1	1		T2	10454		T3	1
all_values[0]	auto[0]	auto[1]	12384	1			T10	14		T11	147		T15	57
all_values[0]	auto[1]	auto[0]	61116	1			T16	9		T63	1		T18	3
all_values[0]	auto[1]	auto[1]	442	1			T16	7		T18	1		T19	2
all_values[1]	auto[0]	auto[0]	2565645	1			T1	1		T2	10454		T3	1
all_values[1]	auto[0]	auto[1]	7780	1			T11	45		T15	23		T30	108
all_values[1]	auto[1]	auto[0]	17728	1			T16	9		T63	7		T18	3
all_values[1]	auto[1]	auto[1]	251	1			T16	4		T63	3		T18	2
all_values[2]	auto[0]	auto[0]	2544298	1			T1	1		T2	10454		T3	1
all_values[2]	auto[0]	auto[1]	2835	1			T11	34		T15	23		T30	74
all_values[2]	auto[1]	auto[0]	43962	1			T16	7		T18	6		T19	4
all_values[2]	auto[1]	auto[1]	309	1			T16	7		T63	3		T18	2
all_values[3]	auto[0]	auto[0]	2529460	1			T1	1		T2	10454		T3	1
all_values[3]	auto[0]	auto[1]	206	1			T16	1		T63	1		T18	1
all_values[3]	auto[1]	auto[0]	61521	1			T16	10		T63	8		T18	4
all_values[3]	auto[1]	auto[1]	217	1			T16	9		T63	1		T19	1
all_values[4]	auto[0]	auto[0]	2590719	1			T1	1		T2	10454		T3	1
all_values[4]	auto[0]	auto[1]	210	1			T63	2		T19	3		T20	10
all_values[4]	auto[1]	auto[0]	277	1			T16	11		T63	7		T18	7
all_values[4]	auto[1]	auto[1]	198	1			T16	3		T18	3		T19	1
all_values[5]	auto[0]	auto[0]	2590743	1			T1	1		T2	10454		T3	1
all_values[5]	auto[0]	auto[1]	188	1			T16	5		T63	2		T18	2
all_values[5]	auto[1]	auto[0]	311	1			T16	3		T63	8		T18	6
all_values[5]	auto[1]	auto[1]	162	1			T63	1		T18	2		T20	5
all_values[6]	auto[0]	auto[0]	2529492	1			T1	1		T2	10454		T3	1
all_values[6]	auto[0]	auto[1]	173	1			T16	2		T63	3		T19	2
all_values[6]	auto[1]	auto[0]	61557	1			T16	4		T18	4		T19	3
all_values[6]	auto[1]	auto[1]	182	1			T16	1		T63	1		T19	2
all_values[7]	auto[0]	auto[0]	2529635	1			T1	1		T2	10454		T3	1
all_values[7]	auto[0]	auto[1]	193	1			T16	4		T63	3		T18	3
all_values[7]	auto[1]	auto[0]	61370	1			T16	9		T18	1		T19	3
all_values[7]	auto[1]	auto[1]	206	1			T16	2		T63	2		T18	1