Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	34788	1			T3	8		T4	10		T6	65
auto[SpiFlashAddrCfg]	7620	1			T4	8		T6	25		T8	1
auto[SpiFlashAddr3b]	9089	1			T4	8		T6	24		T10	38
auto[SpiFlashAddr4b]	7623	1			T6	26		T10	26		T11	14

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33585

1

T3

8

T4

26

T6

81

auto[1]

25535

1

T6

59

T10

52

T11

79

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31447

1

T3

8

T4

10

T6

85

auto[1]

27673

1

T4

16

T6

55

T8

1

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	39483	1			T3	8		T4	6		T6	73
values[1]	1157	1			T6	6		T10	7		T11	2
values[2]	1367	1			T6	5		T10	3		T11	1
values[3]	1450	1			T4	4		T6	3		T10	1
values[4]	1393	1			T6	2		T10	4		T11	4
values[5]	1505	1			T4	2		T6	9		T10	15
values[6]	1428	1			T4	2		T6	9		T10	4
values[7]	1506	1			T6	4		T10	3		T11	3
values[8]	9831	1			T4	12		T6	29		T8	1

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27690

1

T3

8

T4

26

T11

177

auto[1]

31430

1

T6

140

T8

1

T10

175

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

55687

1

T3

8

T4

26

T6

124

write

3433

1

T6

16

T10

3

T11

13

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

19362

1

T3

8

T4

22

T6

65

valids[0x1]

39758

1

T4

4

T6

75

T10

97

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1548	1			T6	6		T10	7		T11	2
internal_process_ops[0x5a]	1622	1			T6	4		T10	4		T11	3
internal_process_ops[0x05]	20581	1			T6	9		T10	23		T11	81
internal_process_ops[0x35]	1560	1			T6	7		T10	5		T11	4
internal_process_ops[0x15]	1602	1			T6	5		T10	11		T11	2
internal_process_ops[0x03]	991	1			T10	1		T11	3		T29	7
internal_process_ops[0x0b]	980	1			T10	1		T11	3		T14	2
internal_process_ops[0x3b]	1051	1			T4	2		T6	3		T8	1
internal_process_ops[0x6b]	1010	1			T10	1		T11	3		T14	2
internal_process_ops[0xbb]	1017	1			T4	2		T6	4		T11	3
internal_process_ops[0xeb]	1051	1			T4	2		T6	2		T10	1

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

57503

1

T3

8

T4

26

T6

126

auto[1]

1617

1

T6

14

T10

1

T11

8

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

56684

1

T3

8

T4

26

T6

129

auto[1]

2436

1

T6

11

T10

5

T11

12

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9162

1

T3

8

T4

10

T11

61

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

5444

1

T11

53

T29

67

T30

14

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2026

1

T4

8

T11

12

T12

4

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1658

1

T11

7

T14

2

T29

16

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2241

1

T4

8

T11

9

T12

10

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1979

1

T11

12

T14

4

T29

14

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1936

1

T11

6

T12

2

T29

12

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1695

1

T11

4

T14

2

T29

15

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

111

1

T11

2

T22

2

T17

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

59

1

T11

1

T22

1

T17

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

106

1

T17

2

T18

3

T46

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

105

1

T29

1

T17

3

T45

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

89

1

T22

3

T17

4

T154

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

74

1

T17

3

T46

1

T47

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

115

1

T30

2

T17

2

T18

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

100

1

T14

4

T29

3

T22

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

123

1

T29

1

T51

3

T22

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

89

1

T11

3

T29

3

T30

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

106

1

T11

3

T30

2

T22

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

89

1

T22

1

T17

1

T18

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

118

1

T30

2

T22

1

T17

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

78

1

T11

4

T30

4

T22

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

79

1

T51

1

T22

2

T18

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

108

1

T14

4

T17

2

T18

4

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

11237

1

T6

45

T10

64

T15

29

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

8049

1

T6

16

T10

16

T15

9

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1653

1

T6

4

T8

1

T10

12

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1483

1

T6

17

T10

16

T15

10

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2038

1

T6

12

T10

26

T15

3

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1944

1

T6

7

T10

12

T15

8

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1578

1

T6

13

T10

18

T15

2

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1564

1

T6

10

T10

8

T15

4

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

136

1

T10

2

T40

3

T41

4

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

133

1

T10

1

T41

3

T50

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

126

1

T41

3

T50

4

T16

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

120

1

T6

4

T41

1

T50

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

106

1

T6

2

T41

3

T16

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

116

1

T6

2

T41

2

T37

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

117

1

T41

1

T16

2

T38

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

83

1

T40

2

T41

2

T16

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

122

1

T41

5

T50

2

T16

4

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

111

1

T40

2

T41

4

T50

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

126

1

T16

1

T37

3

T147

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

121

1

T6

5

T15

2

T147

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

125

1

T40

1

T41

3

T50

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

124

1

T6

3

T40

1

T50

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

111

1

T15

1

T41

2

T37

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

107

1

T41

1

T155

1

T156

1

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3569	1			T3	8		T4	6		T11	24
auto[0]	values[0]	valids[0x1]	13758	1			T11	104		T12	2		T14	10
auto[0]	values[1]	valids[0x1]	518	1			T11	2		T12	8		T29	6
auto[0]	values[2]	valids[0x0]	469	1			T11	1		T29	5		T30	4
auto[0]	values[2]	valids[0x1]	216	1			T30	1		T22	1		T17	10
auto[0]	values[3]	valids[0x0]	464	1			T4	4		T11	4		T29	2
auto[0]	values[3]	valids[0x1]	319	1			T30	6		T51	1		T22	5
auto[0]	values[4]	valids[0x0]	491	1			T11	2		T14	2		T29	6
auto[0]	values[4]	valids[0x1]	252	1			T11	2		T30	3		T22	7
auto[0]	values[5]	valids[0x0]	551	1			T4	2		T11	3		T29	1
auto[0]	values[5]	valids[0x1]	279	1			T11	2		T29	1		T30	2
auto[0]	values[6]	valids[0x0]	518	1			T4	2		T11	1		T29	10
auto[0]	values[6]	valids[0x1]	263	1			T11	2		T12	4		T29	2
auto[0]	values[7]	valids[0x0]	522	1			T11	1		T29	3		T30	4
auto[0]	values[7]	valids[0x1]	291	1			T11	2		T29	1		T17	11
auto[0]	values[8]	valids[0x0]	3328	1			T4	8		T11	19		T12	4
auto[0]	values[8]	valids[0x1]	1882	1			T4	4		T11	8		T14	2
auto[1]	values[0]	valids[0x0]	4383	1			T6	27		T10	32		T15	14
auto[1]	values[0]	valids[0x1]	17773	1			T6	46		T10	60		T15	28
auto[1]	values[1]	valids[0x1]	639	1			T6	6		T10	7		T15	4
auto[1]	values[2]	valids[0x0]	383	1			T6	1		T10	2		T15	1
auto[1]	values[2]	valids[0x1]	299	1			T6	4		T10	1		T40	1
auto[1]	values[3]	valids[0x0]	395	1			T6	3		T40	6		T41	6
auto[1]	values[3]	valids[0x1]	272	1			T10	1		T40	2		T41	7
auto[1]	values[4]	valids[0x0]	402	1			T6	2		T10	3		T15	5
auto[1]	values[4]	valids[0x1]	248	1			T10	1		T15	2		T40	1
auto[1]	values[5]	valids[0x0]	406	1			T6	7		T10	9		T15	4
auto[1]	values[5]	valids[0x1]	269	1			T6	2		T10	6		T41	4
auto[1]	values[6]	valids[0x0]	356	1			T6	6		T10	1		T41	1
auto[1]	values[6]	valids[0x1]	291	1			T6	3		T10	3		T15	1
auto[1]	values[7]	valids[0x0]	419	1			T6	3		T10	3		T40	5
auto[1]	values[7]	valids[0x1]	274	1			T6	1		T15	1		T50	3
auto[1]	values[8]	valids[0x0]	2706	1			T6	16		T8	1		T10	28
auto[1]	values[8]	valids[0x1]	1915	1			T6	13		T10	18		T15	7