Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3344532

1

T1

1708

T2

1

T3

387

auto[1]

34227

1

T6

64

T10

15

T11

77

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

984043

1

T1

1708

T2

1

T3

387

auto[1]

2394716

1

T6

9955

T10

7420

T11

6777

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	665047	1			T2	1		T3	8		T4	1
auto[524288:1048575]	395058	1			T1	715		T6	6034		T10	2149
auto[1048576:1572863]	351613	1			T1	123		T3	244		T6	14
auto[1572864:2097151]	392929	1			T1	870		T3	2		T6	706
auto[2097152:2621439]	396422	1			T6	2720		T8	66		T10	5
auto[2621440:3145727]	435274	1			T6	157		T10	1142		T15	1
auto[3145728:3670015]	388081	1			T3	133		T6	28		T10	1247
auto[3670016:4194303]	354335	1			T6	23		T8	213		T10	9

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2429348

1

T1

11

T2

1

T3

375

auto[1]

949411

1

T1

1697

T3

12

T6

7

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2904916

1

T1

1708

T2

1

T3

249

auto[1]

473843

1

T3

138

T6

37

T10

2541

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	242202	1			T2	1		T3	6		T4	1
auto[0]	auto[0]	auto[0:524287]	auto[1]	364692	1			T6	535		T10	1		T11	5793
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	90833	1			T1	715		T6	35		T10	4
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	239821	1			T6	5952		T10	1768		T11	2
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	91385	1			T1	123		T3	241		T6	14
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	200311	1			T10	648		T11	260		T15	1
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	91626	1			T1	870		T3	2		T6	63
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	244383	1			T6	635		T10	703		T11	11
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	117852	1			T6	31		T8	66		T11	3
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	206482	1			T6	2686		T11	129		T40	129
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	124290	1			T6	25		T10	5		T15	1
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	243557	1			T6	128		T10	521		T29	2860
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	123504	1			T6	21		T10	4		T29	2
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	209316	1			T10	1242		T29	737		T40	133
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	88598	1			T6	7		T8	213		T10	4
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	196424	1			T10	1		T40	1186		T41	3
auto[0]	auto[1]	auto[0:524287]	auto[0]	2132	1			T3	2		T40	1		T41	14
auto[0]	auto[1]	auto[0:524287]	auto[1]	52327	1			T10	1		T15	584		T41	2918
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	955	1			T6	14		T10	4		T41	22
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	56527	1			T10	373		T15	128		T41	256
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	747	1			T3	3		T10	2		T29	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	56453	1			T10	516		T29	4		T41	1879
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	1806	1			T6	5		T10	2		T15	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	51603	1			T10	1021		T29	5		T41	232
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	901	1			T10	2		T11	4		T29	1
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	67432	1			T10	1		T11	514		T29	1767
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	1016	1			T6	2		T10	2		T41	12
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	62276	1			T10	614		T17	513		T37	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	1214	1			T3	133		T10	1		T15	3
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	50031	1			T15	258		T40	3		T16	258
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	831	1			T6	13		T11	1		T41	44
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	63005	1			T11	3		T40	4		T50	2485
auto[1]	auto[0]	auto[0:524287]	auto[0]	502	1			T6	13		T10	1		T11	3
auto[1]	auto[0]	auto[0:524287]	auto[1]	2739	1			T11	6		T40	6		T30	3
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	468	1			T6	14		T11	2		T15	1
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	5794	1			T6	19		T11	9		T15	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	416	1			T10	2		T11	4		T15	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	1824	1			T10	6		T11	31		T15	4
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	385	1			T6	3		T11	1		T29	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	2612	1			T11	1		T29	52		T40	16
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	343	1			T6	3		T11	1		T40	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2888	1			T11	3		T41	50		T50	41
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	471	1			T6	2		T40	1		T41	11
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	2975	1			T40	2		T41	1		T50	118
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	398	1			T6	7		T40	1		T41	9
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	2843	1			T40	37		T41	64		T17	24
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	472	1			T10	1		T41	13		T30	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	4510	1			T10	3		T30	1		T22	347
auto[1]	auto[1]	auto[0:524287]	auto[0]	94	1			T50	1		T18	6		T151	9
auto[1]	auto[1]	auto[0:524287]	auto[1]	359	1			T50	16		T18	10		T151	3
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	49	1			T17	2		T165	2		T47	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	611	1			T17	11		T47	1		T191	2
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	66	1			T16	1		T38	1		T147	3
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	411	1			T147	3		T156	46		T33	2
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	99	1			T41	11		T50	2		T17	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	415	1			T41	27		T50	5		T17	5
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	111	1			T10	1		T11	1		T50	2
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	413	1			T10	1		T11	15		T50	52
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	97	1			T17	1		T37	1		T165	3
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	592	1			T17	8		T37	3		T154	11
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	103	1			T15	2		T16	2		T147	4
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	672	1			T15	1		T16	1		T147	10
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	77	1			T6	3		T50	2		T166	3
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	418	1			T50	8		T204	10		T76	39

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1931192	1			T1	11		T2	1		T3	237
auto[0]	auto[0]	auto[1]	944084	1			T1	1697		T3	12		T8	431
auto[0]	auto[1]	auto[0]	464635	1			T3	138		T6	34		T10	2539
auto[0]	auto[1]	auto[1]	4621	1			T50	2		T170	1		T191	1
auto[1]	auto[0]	auto[0]	29059	1			T6	55		T10	13		T11	61
auto[1]	auto[0]	auto[1]	581	1			T6	6		T40	1		T41	16
auto[1]	auto[1]	auto[0]	4462	1			T6	2		T10	1		T11	16
auto[1]	auto[1]	auto[1]	125	1			T6	1		T10	1		T41	1