Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2591404	1			T1	1		T2	10454		T3	1
all_pins[1]	2591404	1			T1	1		T2	10454		T3	1
all_pins[2]	2591404	1			T1	1		T2	10454		T3	1
all_pins[3]	2591404	1			T1	1		T2	10454		T3	1
all_pins[4]	2591404	1			T1	1		T2	10454		T3	1
all_pins[5]	2591404	1			T1	1		T2	10454		T3	1
all_pins[6]	2591404	1			T1	1		T2	10454		T3	1
all_pins[7]	2591404	1			T1	1		T2	10454		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	20669186	1			T1	8		T2	83632		T3	8
values[0x1]	62046	1			T16	33		T63	11		T18	11
transitions[0x0=>0x1]	61535	1			T16	19		T63	6		T18	8
transitions[0x1=>0x0]	61545	1			T16	19		T63	6		T18	8

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2590931	1			T1	1		T2	10454		T3	1
all_pins[0]	values[0x1]	473	1			T16	7		T18	1		T19	2
all_pins[0]	transitions[0x0=>0x1]	344	1			T16	4		T19	2		T20	2
all_pins[0]	transitions[0x1=>0x0]	127	1			T16	1		T63	3		T18	1
all_pins[1]	values[0x0]	2591148	1			T1	1		T2	10454		T3	1
all_pins[1]	values[0x1]	256	1			T16	4		T63	3		T18	2
all_pins[1]	transitions[0x0=>0x1]	189	1			T16	2		T18	1		T20	1
all_pins[1]	transitions[0x1=>0x0]	252	1			T16	5		T18	1		T19	1
all_pins[2]	values[0x0]	2591085	1			T1	1		T2	10454		T3	1
all_pins[2]	values[0x1]	319	1			T16	7		T63	3		T18	2
all_pins[2]	transitions[0x0=>0x1]	243	1			T16	2		T63	2		T18	2
all_pins[2]	transitions[0x1=>0x0]	141	1			T16	4		T19	1		T21	1
all_pins[3]	values[0x0]	2591187	1			T1	1		T2	10454		T3	1
all_pins[3]	values[0x1]	217	1			T16	9		T63	1		T19	1
all_pins[3]	transitions[0x0=>0x1]	153	1			T16	6		T63	1		T19	1
all_pins[3]	transitions[0x1=>0x0]	134	1			T18	3		T19	1		T20	3
all_pins[4]	values[0x0]	2591206	1			T1	1		T2	10454		T3	1
all_pins[4]	values[0x1]	198	1			T16	3		T18	3		T19	1
all_pins[4]	transitions[0x0=>0x1]	163	1			T16	3		T18	2		T19	1
all_pins[4]	transitions[0x1=>0x0]	127	1			T63	1		T18	1		T20	4
all_pins[5]	values[0x0]	2591242	1			T1	1		T2	10454		T3	1
all_pins[5]	values[0x1]	162	1			T63	1		T18	2		T20	5
all_pins[5]	transitions[0x0=>0x1]	132	1			T63	1		T18	2		T20	5
all_pins[5]	transitions[0x1=>0x0]	60185	1			T16	1		T63	1		T19	2
all_pins[6]	values[0x0]	2531189	1			T1	1		T2	10454		T3	1
all_pins[6]	values[0x1]	60215	1			T16	1		T63	1		T19	2
all_pins[6]	transitions[0x0=>0x1]	60159	1			T16	1		T19	2		T20	3
all_pins[6]	transitions[0x1=>0x0]	150	1			T16	2		T63	1		T18	1
all_pins[7]	values[0x0]	2591198	1			T1	1		T2	10454		T3	1
all_pins[7]	values[0x1]	206	1			T16	2		T63	2		T18	1
all_pins[7]	transitions[0x0=>0x1]	152	1			T16	1		T63	2		T18	1
all_pins[7]	transitions[0x1=>0x0]	429	1			T16	6		T18	1		T19	2