Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16106

1

T3

8

T4

26

T11

98

auto[1]

11584

1

T11

79

T14

16

T29

116

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3641	1			T3	8		T29	93		T30	21
values[1]	3478	1			T11	20		T29	20		T30	45
values[2]	3386	1			T4	26		T11	53		T29	20
values[3]	3069	1			T11	48		T29	20		T51	50
values[4]	3587	1			T12	22		T29	20		T53	20
values[5]	3438	1			T14	16		T22	60		T17	40
values[6]	3647	1			T22	60		T17	73		T18	97
values[7]	3444	1			T11	56		T29	62		T30	68

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3631	1			T4	26		T11	20		T30	43
values[1]	3060	1			T11	36		T29	102		T51	30
values[2]	3594	1			T11	48		T30	23		T51	20
values[3]	2908	1			T22	60		T17	100		T46	20
values[4]	3453	1			T14	16		T29	20		T30	22
values[5]	3506	1			T3	8		T11	20		T12	22
values[6]	3684	1			T29	93		T22	40		T17	119
values[7]	3854	1			T11	53		T30	25		T53	20

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	353	1			T18	15		T185	4		T175	14
auto[0]	values[0]	values[1]	144	1			T29	10		T21	15		T33	16
auto[0]	values[0]	values[2]	189	1			T47	13		T166	11		T21	11
auto[0]	values[0]	values[3]	245	1			T22	9		T17	12		T177	9
auto[0]	values[0]	values[4]	263	1			T17	13		T137	14		T175	13
auto[0]	values[0]	values[5]	188	1			T3	8		T30	11		T191	21
auto[0]	values[0]	values[6]	361	1			T29	13		T191	10		T21	37
auto[0]	values[0]	values[7]	239	1			T18	10		T33	80		T171	9
auto[0]	values[1]	values[0]	214	1			T46	11		T47	34		T172	12
auto[0]	values[1]	values[1]	236	1			T55	4		T19	12		T220	8
auto[0]	values[1]	values[2]	233	1			T30	13		T18	13		T187	16
auto[0]	values[1]	values[3]	238	1			T17	13		T154	11		T201	12
auto[0]	values[1]	values[4]	321	1			T30	9		T17	8		T18	24
auto[0]	values[1]	values[5]	250	1			T11	9		T154	10		T33	17
auto[0]	values[1]	values[6]	171	1			T29	11		T17	11		T200	18
auto[0]	values[1]	values[7]	283	1			T18	9		T152	14		T166	17
auto[0]	values[2]	values[0]	428	1			T4	26		T22	13		T17	162
auto[0]	values[2]	values[1]	248	1			T29	10		T166	14		T171	44
auto[0]	values[2]	values[2]	239	1			T22	12		T18	18		T47	12
auto[0]	values[2]	values[3]	175	1			T22	13		T17	12		T46	7
auto[0]	values[2]	values[4]	135	1			T186	21		T221	16		T183	11
auto[0]	values[2]	values[5]	327	1			T210	68		T206	24		T177	11
auto[0]	values[2]	values[6]	162	1			T17	52		T47	19		T39	13
auto[0]	values[2]	values[7]	231	1			T11	16		T154	13		T166	11
auto[0]	values[3]	values[0]	186	1			T18	26		T166	10		T182	36
auto[0]	values[3]	values[1]	147	1			T51	12		T73	9		T52	11
auto[0]	values[3]	values[2]	156	1			T11	41		T51	11		T186	7
auto[0]	values[3]	values[3]	157	1			T154	14		T172	13		T202	13
auto[0]	values[3]	values[4]	144	1			T22	11		T17	28		T46	9
auto[0]	values[3]	values[5]	318	1			T29	13		T154	14		T222	8
auto[0]	values[3]	values[6]	231	1			T22	9		T171	12		T223	6
auto[0]	values[3]	values[7]	187	1			T200	14		T33	10		T137	12
auto[0]	values[4]	values[0]	235	1			T22	11		T200	11		T224	8
auto[0]	values[4]	values[1]	323	1			T18	6		T46	11		T154	13
auto[0]	values[4]	values[2]	170	1			T17	10		T21	26		T225	14
auto[0]	values[4]	values[3]	234	1			T17	12		T33	55		T226	6
auto[0]	values[4]	values[4]	264	1			T29	12		T25	13		T210	11
auto[0]	values[4]	values[5]	274	1			T12	22		T17	33		T191	17
auto[0]	values[4]	values[6]	493	1			T33	158		T227	16		T228	95
auto[0]	values[4]	values[7]	346	1			T17	14		T149	18		T46	11
auto[0]	values[5]	values[0]	239	1			T22	10		T229	6		T73	12
auto[0]	values[5]	values[1]	249	1			T45	12		T170	8		T73	12
auto[0]	values[5]	values[2]	346	1			T22	10		T17	10		T172	14
auto[0]	values[5]	values[3]	199	1			T154	16		T33	10		T171	10
auto[0]	values[5]	values[4]	234	1			T46	9		T230	4		T182	10
auto[0]	values[5]	values[5]	482	1			T47	112		T154	10		T200	12
auto[0]	values[5]	values[6]	228	1			T166	10		T200	17		T39	16
auto[0]	values[5]	values[7]	183	1			T22	12		T17	8		T191	9
auto[0]	values[6]	values[0]	182	1			T18	14		T231	12		T193	15
auto[0]	values[6]	values[1]	257	1			T154	15		T166	22		T39	7
auto[0]	values[6]	values[2]	394	1			T33	27		T171	19		T137	11
auto[0]	values[6]	values[3]	198	1			T22	13		T154	15		T21	18
auto[0]	values[6]	values[4]	388	1			T22	12		T17	14		T86	20
auto[0]	values[6]	values[5]	114	1			T18	15		T183	13		T232	10
auto[0]	values[6]	values[6]	362	1			T22	8		T17	11		T18	38
auto[0]	values[6]	values[7]	260	1			T17	6		T39	21		T213	45
auto[0]	values[7]	values[0]	474	1			T11	18		T30	26		T18	12
auto[0]	values[7]	values[1]	246	1			T11	14		T29	50		T46	9
auto[0]	values[7]	values[2]	132	1			T22	13		T47	15		T233	17
auto[0]	values[7]	values[3]	210	1			T182	9		T234	18		T235	10
auto[0]	values[7]	values[4]	222	1			T17	26		T46	7		T236	16
auto[0]	values[7]	values[5]	142	1			T17	11		T46	8		T191	10
auto[0]	values[7]	values[6]	285	1			T18	21		T194	9		T175	13
auto[0]	values[7]	values[7]	342	1			T30	12		T213	9		T206	12
auto[1]	values[0]	values[0]	218	1			T18	13		T175	6		T211	12
auto[1]	values[0]	values[1]	154	1			T29	10		T21	5		T33	4
auto[1]	values[0]	values[2]	181	1			T47	7		T166	9		T21	9
auto[1]	values[0]	values[3]	169	1			T22	11		T17	8		T237	10
auto[1]	values[0]	values[4]	230	1			T17	7		T137	6		T175	7
auto[1]	values[0]	values[5]	219	1			T30	10		T191	10		T206	6
auto[1]	values[0]	values[6]	317	1			T29	60		T191	10		T21	47
auto[1]	values[0]	values[7]	171	1			T18	12		T33	15		T171	11
auto[1]	values[1]	values[0]	157	1			T46	9		T47	6		T172	8
auto[1]	values[1]	values[1]	118	1			T19	8		T220	12		T180	11
auto[1]	values[1]	values[2]	139	1			T30	10		T18	9		T238	10
auto[1]	values[1]	values[3]	224	1			T17	7		T154	54		T201	8
auto[1]	values[1]	values[4]	304	1			T30	13		T17	21		T18	10
auto[1]	values[1]	values[5]	144	1			T11	11		T154	10		T33	3
auto[1]	values[1]	values[6]	165	1			T29	9		T17	12		T200	5
auto[1]	values[1]	values[7]	281	1			T18	11		T166	3		T199	13
auto[1]	values[2]	values[0]	131	1			T22	7		T17	9		T239	2
auto[1]	values[2]	values[1]	157	1			T29	10		T166	6		T171	10
auto[1]	values[2]	values[2]	338	1			T22	8		T18	5		T47	25
auto[1]	values[2]	values[3]	169	1			T22	7		T17	23		T46	13
auto[1]	values[2]	values[4]	132	1			T218	26		T186	6		T183	45
auto[1]	values[2]	values[5]	205	1			T210	15		T206	38		T177	9
auto[1]	values[2]	values[6]	107	1			T17	11		T47	1		T39	8
auto[1]	values[2]	values[7]	202	1			T11	37		T154	25		T166	9
auto[1]	values[3]	values[0]	186	1			T18	18		T166	10		T182	30
auto[1]	values[3]	values[1]	83	1			T51	18		T73	11		T52	12
auto[1]	values[3]	values[2]	312	1			T11	7		T51	9		T72	4
auto[1]	values[3]	values[3]	187	1			T154	41		T172	7		T202	7
auto[1]	values[3]	values[4]	78	1			T22	9		T17	28		T46	11
auto[1]	values[3]	values[5]	187	1			T29	7		T154	6		T203	27
auto[1]	values[3]	values[6]	128	1			T22	11		T171	12		T219	18
auto[1]	values[3]	values[7]	382	1			T200	8		T33	93		T137	9
auto[1]	values[4]	values[0]	168	1			T22	9		T200	9		T240	50
auto[1]	values[4]	values[1]	229	1			T18	14		T46	9		T154	7
auto[1]	values[4]	values[2]	95	1			T17	10		T21	14		T241	11
auto[1]	values[4]	values[3]	136	1			T17	13		T33	33		T176	7
auto[1]	values[4]	values[4]	215	1			T29	8		T25	7		T210	9
auto[1]	values[4]	values[5]	175	1			T17	13		T191	10		T206	6
auto[1]	values[4]	values[6]	57	1			T33	8		T242	6		T243	7
auto[1]	values[4]	values[7]	173	1			T53	20		T17	6		T149	5
auto[1]	values[5]	values[0]	100	1			T22	10		T73	8		T175	10
auto[1]	values[5]	values[1]	134	1			T45	8		T73	8		T202	10
auto[1]	values[5]	values[2]	220	1			T22	10		T17	10		T172	6
auto[1]	values[5]	values[3]	96	1			T154	4		T33	25		T171	14
auto[1]	values[5]	values[4]	166	1			T14	16		T46	11		T182	11
auto[1]	values[5]	values[5]	276	1			T47	15		T154	30		T200	8
auto[1]	values[5]	values[6]	104	1			T166	10		T200	3		T39	8
auto[1]	values[5]	values[7]	182	1			T22	8		T17	12		T191	28
auto[1]	values[6]	values[0]	155	1			T18	10		T193	5		T176	8
auto[1]	values[6]	values[1]	197	1			T154	6		T166	18		T39	13
auto[1]	values[6]	values[2]	318	1			T33	8		T171	30		T137	9
auto[1]	values[6]	values[3]	130	1			T22	7		T154	5		T21	3
auto[1]	values[6]	values[4]	154	1			T22	8		T17	6		T210	4
auto[1]	values[6]	values[5]	78	1			T18	12		T183	7		T244	13
auto[1]	values[6]	values[6]	281	1			T22	12		T17	22		T18	8
auto[1]	values[6]	values[7]	179	1			T17	14		T39	9		T213	16
auto[1]	values[7]	values[0]	205	1			T11	2		T30	17		T18	8
auto[1]	values[7]	values[1]	138	1			T11	22		T29	12		T46	11
auto[1]	values[7]	values[2]	132	1			T22	7		T47	7		T245	6
auto[1]	values[7]	values[3]	141	1			T182	13		T235	13		T202	9
auto[1]	values[7]	values[4]	203	1			T17	35		T46	13		T33	21
auto[1]	values[7]	values[5]	127	1			T17	25		T46	12		T191	10
auto[1]	values[7]	values[6]	232	1			T18	6		T194	12		T246	22
auto[1]	values[7]	values[7]	213	1			T30	13		T213	16		T206	9