Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	430	1			T11	6		T29	4		T30	5
auto[ReadAddrCrossIntoMailbox]	293	1			T11	2		T29	3		T30	3
auto[ReadAddrCrossOutOfMailbox]	319	1			T11	2		T29	6		T30	6
auto[ReadAddrCrossAllMailbox]	231	1			T11	1		T29	1		T30	1
auto[ReadAddrOutsideMailbox]	3165	1			T4	6		T11	9		T12	2

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2149

1

T4

3

T11

6

T12

1

auto[1]

2289

1

T4

3

T11

14

T12

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	715	1			T11	3		T29	7		T30	5
read_ops[0x0b]	718	1			T11	3		T14	2		T29	6
read_ops[0x3b]	760	1			T4	2		T11	4		T29	6
read_ops[0x6b]	725	1			T11	3		T14	2		T29	8
read_ops[0xbb]	745	1			T4	2		T11	3		T29	7
read_ops[0xeb]	775	1			T4	2		T11	4		T12	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	21	1			T47	1		T21	1		T33	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	34	1			T11	2		T17	1		T46	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	28	1			T17	1		T18	1		T21	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	27	1			T29	1		T22	1		T18	2
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	27	1			T22	1		T17	2		T46	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	30	1			T46	1		T154	1		T235	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T22	1		T17	1		T154	2
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	27	1			T22	1		T17	1		T18	2
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	248	1			T11	1		T29	4		T30	4
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	256	1			T29	2		T30	1		T22	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	43	1			T11	2		T29	1		T30	2
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	37	1			T11	1		T29	1		T22	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	15	1			T18	1		T39	1		T202	2
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	24	1			T17	2		T172	1		T247	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T22	2		T17	2		T47	2
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	32	1			T29	1		T30	1		T17	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	11	1			T18	1		T21	1		T177	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	18	1			T29	1		T17	1		T73	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	260	1			T14	1		T29	1		T30	2
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	255	1			T14	1		T29	1		T30	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	36	1			T29	1		T18	1		T47	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	32	1			T30	1		T22	1		T17	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	29	1			T29	1		T18	2		T46	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	27	1			T22	2		T17	2		T154	3
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	25	1			T29	1		T17	1		T171	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	36	1			T29	1		T30	2		T22	2
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T186	1		T177	1		T208	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	20	1			T30	1		T17	1		T154	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	268	1			T4	1		T11	1		T29	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	269	1			T4	1		T11	3		T30	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	29	1			T30	1		T18	1		T208	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	37	1			T17	1		T18	1		T154	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	15	1			T18	1		T47	1		T21	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	28	1			T22	1		T172	1		T206	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	21	1			T46	1		T191	1		T200	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	30	1			T11	1		T17	3		T18	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	13	1			T18	1		T193	1		T201	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	21	1			T17	2		T39	1		T175	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	252	1			T14	1		T29	1		T30	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	279	1			T11	2		T14	1		T29	7
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	49	1			T22	1		T17	2		T186	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	30	1			T30	1		T22	1		T21	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	24	1			T11	1		T22	1		T18	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	22	1			T30	3		T154	1		T206	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	22	1			T18	1		T248	1		T249	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	24	1			T11	1		T29	2		T30	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	23	1			T17	1		T18	1		T154	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	17	1			T211	1		T220	1		T250	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	245	1			T4	1		T29	5		T30	2
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	289	1			T4	1		T11	1		T30	4
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	42	1			T29	1		T18	1		T154	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	40	1			T11	1		T18	1		T47	2
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	31	1			T29	1		T22	1		T17	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	23	1			T11	1		T17	2		T47	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T29	1		T30	2		T17	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	26	1			T22	1		T175	1		T177	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	22	1			T17	1		T191	1		T247	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	24	1			T11	1		T17	1		T154	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	269	1			T4	1		T11	1		T12	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	275	1			T4	1		T12	1		T14	1