Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3159	1			T14	16		T29	40		T30	22
values[1]	3780	1			T3	8		T11	20		T29	20
values[2]	3086	1			T29	20		T22	40		T17	106
values[3]	3694	1			T11	36		T29	73		T30	21
values[4]	3675	1			T29	62		T22	40		T17	26
values[5]	2793	1			T11	20		T12	22		T30	23
values[6]	3607	1			T4	26		T11	48		T29	20
values[7]	3896	1			T11	53		T30	25		T22	20

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3083	1			T11	53		T29	82		T22	100
values[1]	3429	1			T4	26		T30	23		T17	35
values[2]	4178	1			T29	93		T30	20		T55	4
values[3]	3411	1			T11	48		T51	20		T53	20
values[4]	2836	1			T14	16		T29	40		T30	21
values[5]	3980	1			T3	8		T12	22		T30	25
values[6]	3177	1			T11	20		T30	23		T22	20
values[7]	3596	1			T11	56		T29	20		T30	22

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26988

1

T3

8

T4

26

T11

169

auto[1]

702

1

T11

8

T14

8

T29

7

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	309	1			T46	20		T172	20		T206	81
auto[0]	values[0]	values[1]	463	1			T21	18		T200	18		T225	14
auto[0]	values[0]	values[2]	583	1			T29	18		T22	20		T17	24
auto[0]	values[0]	values[3]	331	1			T22	20		T21	20		T171	20
auto[0]	values[0]	values[4]	197	1			T14	8		T29	19		T171	20
auto[0]	values[0]	values[5]	367	1			T39	24		T213	20		T175	20
auto[0]	values[0]	values[6]	384	1			T211	20		T208	23		T251	6
auto[0]	values[0]	values[7]	423	1			T30	21		T18	18		T154	52
auto[0]	values[1]	values[0]	452	1			T29	20		T33	35		T206	32
auto[0]	values[1]	values[1]	392	1			T18	31		T73	18		T221	16
auto[0]	values[1]	values[2]	533	1			T30	20		T194	20		T154	40
auto[0]	values[1]	values[3]	607	1			T51	20		T17	40		T18	25
auto[0]	values[1]	values[4]	484	1			T17	20		T18	19		T137	20
auto[0]	values[1]	values[5]	369	1			T3	8		T18	27		T154	19
auto[0]	values[1]	values[6]	427	1			T86	20		T33	20		T171	29
auto[0]	values[1]	values[7]	435	1			T11	18		T22	20		T33	54
auto[0]	values[2]	values[0]	337	1			T22	20		T154	20		T175	156
auto[0]	values[2]	values[1]	474	1			T21	20		T171	20		T39	19
auto[0]	values[2]	values[2]	468	1			T17	19		T46	20		T252	4
auto[0]	values[2]	values[3]	291	1			T17	59		T46	20		T19	19
auto[0]	values[2]	values[4]	592	1			T171	21		T237	8		T73	20
auto[0]	values[2]	values[5]	436	1			T22	20		T18	27		T137	21
auto[0]	values[2]	values[6]	222	1			T46	19		T253	12		T173	20
auto[0]	values[2]	values[7]	190	1			T29	19		T17	22		T183	35
auto[0]	values[3]	values[0]	104	1			T22	20		T182	20		T254	20
auto[0]	values[3]	values[1]	485	1			T46	20		T239	2		T33	20
auto[0]	values[3]	values[2]	538	1			T29	73		T55	4		T166	36
auto[0]	values[3]	values[3]	587	1			T154	20		T166	18		T191	19
auto[0]	values[3]	values[4]	248	1			T30	21		T154	20		T191	31
auto[0]	values[3]	values[5]	605	1			T154	62		T21	20		T206	27
auto[0]	values[3]	values[6]	554	1			T22	20		T18	20		T166	20
auto[0]	values[3]	values[7]	440	1			T11	35		T203	33		T172	18
auto[0]	values[4]	values[0]	499	1			T29	60		T166	20		T39	27
auto[0]	values[4]	values[1]	448	1			T45	19		T211	18		T177	20
auto[0]	values[4]	values[2]	476	1			T255	2		T211	19		T178	16
auto[0]	values[4]	values[3]	299	1			T22	20		T229	6		T33	74
auto[0]	values[4]	values[4]	315	1			T192	6		T200	19		T33	31
auto[0]	values[4]	values[5]	309	1			T22	18		T17	26		T47	37
auto[0]	values[4]	values[6]	437	1			T18	23		T33	101		T39	22
auto[0]	values[4]	values[7]	807	1			T46	18		T47	127		T210	20
auto[0]	values[5]	values[0]	340	1			T152	14		T182	25		T172	20
auto[0]	values[5]	values[1]	234	1			T21	21		T200	19		T256	4
auto[0]	values[5]	values[2]	273	1			T17	32		T166	20		T172	19
auto[0]	values[5]	values[3]	276	1			T21	51		T177	18		T257	18
auto[0]	values[5]	values[4]	285	1			T17	20		T154	20		T240	26
auto[0]	values[5]	values[5]	492	1			T12	22		T187	16		T191	44
auto[0]	values[5]	values[6]	371	1			T11	20		T30	23		T17	45
auto[0]	values[5]	values[7]	459	1			T51	30		T22	20		T17	29
auto[0]	values[6]	values[0]	462	1			T22	37		T46	20		T191	20
auto[0]	values[6]	values[1]	327	1			T4	26		T30	21		T170	8
auto[0]	values[6]	values[2]	528	1			T22	14		T17	33		T171	29
auto[0]	values[6]	values[3]	425	1			T11	48		T53	20		T17	20
auto[0]	values[6]	values[4]	463	1			T29	19		T17	38		T199	18
auto[0]	values[6]	values[5]	697	1			T46	16		T154	38		T166	20
auto[0]	values[6]	values[6]	265	1			T17	20		T149	23		T212	26
auto[0]	values[6]	values[7]	348	1			T18	20		T210	19		T186	25
auto[0]	values[7]	values[0]	523	1			T11	48		T22	20		T17	171
auto[0]	values[7]	values[1]	523	1			T17	35		T46	20		T47	36
auto[0]	values[7]	values[2]	663	1			T18	22		T222	8		T200	23
auto[0]	values[7]	values[3]	500	1			T25	20		T17	20		T258	12
auto[0]	values[7]	values[4]	179	1			T182	20		T175	35		T259	2
auto[0]	values[7]	values[5]	595	1			T30	23		T18	21		T182	20
auto[0]	values[7]	values[6]	441	1			T166	18		T191	27		T21	20
auto[0]	values[7]	values[7]	402	1			T17	67		T18	24		T236	16
auto[1]	values[0]	values[0]	12	1			T202	4		T260	1		T261	4
auto[1]	values[0]	values[1]	16	1			T21	2		T200	2		T119	1
auto[1]	values[0]	values[2]	21	1			T29	2		T17	1		T46	1
auto[1]	values[0]	values[3]	9	1			T21	2		T262	1		T190	2
auto[1]	values[0]	values[4]	11	1			T14	8		T29	1		T263	2
auto[1]	values[0]	values[5]	11	1			T52	3		T264	1		T265	2
auto[1]	values[0]	values[6]	8	1			T208	2		T249	1		T266	1
auto[1]	values[0]	values[7]	14	1			T30	1		T18	2		T154	3
auto[1]	values[1]	values[0]	12	1			T206	1		T267	5		T268	2
auto[1]	values[1]	values[1]	17	1			T18	3		T73	2		T189	1
auto[1]	values[1]	values[2]	9	1			T194	1		T33	4		T206	2
auto[1]	values[1]	values[3]	13	1			T18	1		T269	4		T270	1
auto[1]	values[1]	values[4]	6	1			T18	1		T208	1		T271	2
auto[1]	values[1]	values[5]	8	1			T154	1		T181	2		T272	2
auto[1]	values[1]	values[6]	4	1			T85	2		T273	1		T274	1
auto[1]	values[1]	values[7]	12	1			T11	2		T33	5		T275	4
auto[1]	values[2]	values[0]	3	1			T175	2		T276	1		-	-
auto[1]	values[2]	values[1]	9	1			T39	1		T73	1		T173	1
auto[1]	values[2]	values[2]	14	1			T17	1		T247	2		T85	3
auto[1]	values[2]	values[3]	8	1			T17	4		T19	1		T277	1
auto[1]	values[2]	values[4]	11	1			T171	1		T237	2		T278	2
auto[1]	values[2]	values[5]	17	1			T18	1		T175	3		T279	2
auto[1]	values[2]	values[6]	8	1			T46	1		T173	1		T244	1
auto[1]	values[2]	values[7]	6	1			T29	1		T17	1		T280	4
auto[1]	values[3]	values[0]	4	1			T280	4		-	-		-	-
auto[1]	values[3]	values[1]	6	1			T249	1		T266	2		T243	2
auto[1]	values[3]	values[2]	23	1			T166	4		T218	16		T183	1
auto[1]	values[3]	values[3]	27	1			T154	1		T166	2		T191	2
auto[1]	values[3]	values[4]	7	1			T272	2		T264	4		T281	1
auto[1]	values[3]	values[5]	29	1			T154	3		T233	7		T282	4
auto[1]	values[3]	values[6]	17	1			T191	4		T180	1		T283	2
auto[1]	values[3]	values[7]	20	1			T11	1		T203	4		T172	2
auto[1]	values[4]	values[0]	7	1			T29	2		T39	1		T249	4
auto[1]	values[4]	values[1]	13	1			T45	1		T211	2		T260	2
auto[1]	values[4]	values[2]	12	1			T211	1		T52	1		T284	1
auto[1]	values[4]	values[3]	5	1			T33	1		T175	2		T260	1
auto[1]	values[4]	values[4]	8	1			T200	3		T33	1		T193	1
auto[1]	values[4]	values[5]	11	1			T22	2		T47	3		T240	2
auto[1]	values[4]	values[6]	14	1			T33	2		T39	1		T213	2
auto[1]	values[4]	values[7]	15	1			T46	2		T186	2		T244	2
auto[1]	values[5]	values[0]	3	1			T182	1		T181	1		T285	1
auto[1]	values[5]	values[1]	7	1			T200	1		T141	1		T273	1
auto[1]	values[5]	values[2]	10	1			T17	4		T172	1		T247	2
auto[1]	values[5]	values[3]	13	1			T21	1		T177	2		T283	2
auto[1]	values[5]	values[4]	9	1			T240	1		T219	4		T181	1
auto[1]	values[5]	values[5]	5	1			T191	1		T262	1		T286	1
auto[1]	values[5]	values[6]	5	1			T17	1		T201	2		T287	2
auto[1]	values[5]	values[7]	11	1			T17	1		T18	2		T21	1
auto[1]	values[6]	values[0]	9	1			T22	3		T210	1		T238	2
auto[1]	values[6]	values[1]	9	1			T30	2		T180	3		T181	1
auto[1]	values[6]	values[2]	19	1			T22	6		T171	5		T206	2
auto[1]	values[6]	values[3]	7	1			T47	2		T173	2		T288	1
auto[1]	values[6]	values[4]	18	1			T29	1		T17	3		T199	3
auto[1]	values[6]	values[5]	14	1			T46	4		T202	2		T262	2
auto[1]	values[6]	values[6]	8	1			T212	3		T289	1		T284	4
auto[1]	values[6]	values[7]	8	1			T210	1		T186	2		T176	1
auto[1]	values[7]	values[0]	7	1			T11	5		T73	1		T268	1
auto[1]	values[7]	values[1]	6	1			T47	1		T201	1		T267	2
auto[1]	values[7]	values[2]	8	1			T213	2		T270	1		T243	2
auto[1]	values[7]	values[3]	13	1			T260	1		T277	4		T284	2
auto[1]	values[7]	values[4]	3	1			T290	3		-	-		-	-
auto[1]	values[7]	values[5]	15	1			T30	2		T18	1		T240	6
auto[1]	values[7]	values[6]	12	1			T166	2		T191	4		T33	4
auto[1]	values[7]	values[7]	6	1			T17	2		T244	1		T287	3