Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	817	1			T16	17		T63	7		T18	10
all_values[1]	817	1			T16	17		T63	7		T18	10
all_values[2]	817	1			T16	17		T63	7		T18	10
all_values[3]	817	1			T16	17		T63	7		T18	10
all_values[4]	817	1			T16	17		T63	7		T18	10
all_values[5]	817	1			T16	17		T63	7		T18	10
all_values[6]	817	1			T16	17		T63	7		T18	10
all_values[7]	817	1			T16	17		T63	7		T18	10

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3480

1

T16

68

T63

34

T18

41

auto[1]

3056

1

T16

68

T63

22

T18

39

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2598

1

T16

72

T63

26

T18

44

auto[1]

3938

1

T16

64

T63

30

T18

36

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3724

1

T16

92

T63

34

T18

53

auto[1]

2812

1

T16

44

T63

22

T18

27

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	176	1			T16	2		T63	6		T18	2
all_values[0]	auto[0]	auto[0]	auto[1]	67	1			T18	2		T19	1		T20	2
all_values[0]	auto[0]	auto[1]	auto[0]	136	1			T16	4		T18	3		T20	1
all_values[0]	auto[0]	auto[1]	auto[1]	77	1			T16	3		T19	1		T20	2
all_values[0]	auto[1]	auto[0]	auto[1]	197	1			T16	2		T63	1		T18	1
all_values[0]	auto[1]	auto[1]	auto[1]	164	1			T16	6		T18	2		T19	2
all_values[1]	auto[0]	auto[0]	auto[0]	173	1			T16	6		T18	3		T20	2
all_values[1]	auto[0]	auto[0]	auto[1]	70	1			T18	1		T19	1		T20	3
all_values[1]	auto[0]	auto[1]	auto[0]	157	1			T16	5		T63	2		T18	3
all_values[1]	auto[0]	auto[1]	auto[1]	62	1			T16	1		T63	3		T20	2
all_values[1]	auto[1]	auto[0]	auto[1]	189	1			T16	2		T63	1		T18	1
all_values[1]	auto[1]	auto[1]	auto[1]	166	1			T16	3		T63	1		T18	2
all_values[2]	auto[0]	auto[0]	auto[0]	132	1			T16	5		T63	1		T18	2
all_values[2]	auto[0]	auto[0]	auto[1]	94	1			T16	1		T63	1		T19	2
all_values[2]	auto[0]	auto[1]	auto[0]	152	1			T16	2		T18	1		T19	4
all_values[2]	auto[0]	auto[1]	auto[1]	84	1			T16	4		T18	1		T20	1
all_values[2]	auto[1]	auto[0]	auto[1]	188	1			T16	3		T63	3		T18	3
all_values[2]	auto[1]	auto[1]	auto[1]	167	1			T16	2		T63	2		T18	3
all_values[3]	auto[0]	auto[0]	auto[0]	145	1			T16	1		T18	6		T19	1
all_values[3]	auto[0]	auto[0]	auto[1]	87	1			T16	1		T19	1		T20	2
all_values[3]	auto[0]	auto[1]	auto[0]	120	1			T16	4		T63	4		T18	2
all_values[3]	auto[0]	auto[1]	auto[1]	85	1			T16	6		T31	1		T32	2
all_values[3]	auto[1]	auto[0]	auto[1]	202	1			T63	2		T18	1		T19	2
all_values[3]	auto[1]	auto[1]	auto[1]	178	1			T16	5		T63	1		T18	1
all_values[4]	auto[0]	auto[0]	auto[0]	168	1			T16	5		T63	3		T18	1
all_values[4]	auto[0]	auto[0]	auto[1]	84	1			T19	1		T20	6		T21	1
all_values[4]	auto[0]	auto[1]	auto[0]	130	1			T16	6		T63	2		T18	4
all_values[4]	auto[0]	auto[1]	auto[1]	91	1			T16	1		T18	2		T19	1
all_values[4]	auto[1]	auto[0]	auto[1]	187	1			T16	2		T63	2		T18	1
all_values[4]	auto[1]	auto[1]	auto[1]	157	1			T16	3		T18	2		T21	4
all_values[5]	auto[0]	auto[0]	auto[0]	266	1			T16	12		T18	4		T20	5
all_values[5]	auto[0]	auto[1]	auto[0]	201	1			T63	4		T18	2		T19	7
all_values[5]	auto[1]	auto[0]	auto[1]	199	1			T16	4		T63	2		T18	1
all_values[5]	auto[1]	auto[1]	auto[1]	151	1			T16	1		T63	1		T18	3
all_values[6]	auto[0]	auto[0]	auto[0]	174	1			T16	10		T63	2		T18	3
all_values[6]	auto[0]	auto[0]	auto[1]	81	1			T16	1		T63	1		T20	1
all_values[6]	auto[0]	auto[1]	auto[0]	157	1			T16	2		T18	5		T19	1
all_values[6]	auto[0]	auto[1]	auto[1]	79	1			T19	1		T20	2		T32	3
all_values[6]	auto[1]	auto[0]	auto[1]	167	1			T16	2		T63	3		T18	2
all_values[6]	auto[1]	auto[1]	auto[1]	159	1			T16	2		T63	1		T19	2
all_values[7]	auto[0]	auto[0]	auto[0]	178	1			T16	4		T63	2		T18	2
all_values[7]	auto[0]	auto[0]	auto[1]	89	1			T16	2		T63	3		T18	2
all_values[7]	auto[0]	auto[1]	auto[0]	133	1			T16	4		T18	1		T19	2
all_values[7]	auto[0]	auto[1]	auto[1]	76	1			T18	1		T20	3		T32	1
all_values[7]	auto[1]	auto[0]	auto[1]	167	1			T16	3		T63	1		T18	3
all_values[7]	auto[1]	auto[1]	auto[1]	174	1			T16	4		T63	1		T18	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal