Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1796

1

T2

10

T7

1

T9

3

auto[1]

1599

1

T2

10

T9

2

T10

5

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2003

1

T2

16

T7

1

T10

6

auto[1]

1392

1

T2

4

T9

5

T10

1

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2650

1

T2

16

T7

1

T9

5

auto[1]

745

1

T2

4

T10

4

T11

5

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	723	1			T2	9		T9	3		T10	1
valid[1]	694	1			T2	3		T9	1		T10	1
valid[2]	650	1			T2	1		T10	2		T11	2
valid[3]	684	1			T2	4		T7	1		T9	1
valid[4]	644	1			T2	3		T10	2		T11	2

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	133	1			T2	4		T27	1		T51	1
auto[0]	auto[0]	valid[0]	auto[1]	147	1			T2	1		T9	2		T11	1
auto[0]	auto[0]	valid[1]	auto[0]	133	1			T2	1		T27	1		T16	1
auto[0]	auto[0]	valid[1]	auto[1]	139	1			T9	1		T15	1		T35	3
auto[0]	auto[0]	valid[2]	auto[0]	133	1			T11	1		T27	1		T30	1
auto[0]	auto[0]	valid[2]	auto[1]	144	1			T56	2		T35	2		T36	5
auto[0]	auto[0]	valid[3]	auto[0]	127	1			T7	1		T27	2		T30	1
auto[0]	auto[0]	valid[3]	auto[1]	150	1			T2	1		T15	1		T56	3
auto[0]	auto[0]	valid[4]	auto[0]	134	1			T2	1		T10	1		T27	3
auto[0]	auto[0]	valid[4]	auto[1]	152	1			T56	3		T17	2		T35	2
auto[0]	auto[1]	valid[0]	auto[0]	140	1			T2	1		T27	1		T15	1
auto[0]	auto[1]	valid[0]	auto[1]	156	1			T9	1		T11	1		T36	5
auto[0]	auto[1]	valid[1]	auto[0]	118	1			T2	1		T17	1		T38	1
auto[0]	auto[1]	valid[1]	auto[1]	145	1			T11	1		T15	1		T56	5
auto[0]	auto[1]	valid[2]	auto[0]	104	1			T10	1		T15	1		T30	1
auto[0]	auto[1]	valid[2]	auto[1]	118	1			T2	1		T10	1		T11	1
auto[0]	auto[1]	valid[3]	auto[0]	120	1			T2	2		T11	1		T27	1
auto[0]	auto[1]	valid[3]	auto[1]	142	1			T2	1		T9	1		T56	1
auto[0]	auto[1]	valid[4]	auto[0]	116	1			T2	2		T11	1		T27	3
auto[0]	auto[1]	valid[4]	auto[1]	99	1			T15	2		T36	4		T38	1
auto[1]	auto[0]	valid[0]	auto[0]	68	1			T2	1		T27	1		T15	1
auto[1]	auto[0]	valid[1]	auto[0]	87	1			T2	1		T11	1		T15	1
auto[1]	auto[0]	valid[2]	auto[0]	83	1			T27	1		T15	1		T30	1
auto[1]	auto[0]	valid[3]	auto[0]	83	1			T10	1		T27	1		T15	1
auto[1]	auto[0]	valid[4]	auto[0]	83	1			T11	1		T50	2		T16	2
auto[1]	auto[1]	valid[0]	auto[0]	79	1			T2	2		T10	1		T11	1
auto[1]	auto[1]	valid[1]	auto[0]	72	1			T10	1		T11	2		T16	1
auto[1]	auto[1]	valid[2]	auto[0]	68	1			T15	1		T17	3		T38	3
auto[1]	auto[1]	valid[3]	auto[0]	62	1			T15	1		T18	1		T191	2
auto[1]	auto[1]	valid[4]	auto[0]	60	1			T10	1		T27	1		T50	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal