Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

51171

1

T2

394

T5

13

T7

8

auto[1]

14647

1

T2

90

T9

93

T10

32

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

47295

1

T2

336

T5

7

T7

2

auto[1]

18523

1

T2

148

T5

6

T7

6

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	33665	1			T2	246		T5	9		T7	2
others[1]	5654	1			T2	43		T7	1		T9	4
others[2]	5570	1			T2	33		T5	1		T7	2
others[3]	6302	1			T2	51		T5	1		T7	1
interest[1]	3714	1			T2	30		T5	1		T9	5
interest[4]	22045	1			T2	169		T5	6		T9	29
interest[64]	10913	1			T2	81		T5	1		T7	2

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	16546	1			T2	127		T5	5		T10	41
auto[0]	auto[0]	others[1]	2823	1			T2	21		T7	1		T10	11
auto[0]	auto[0]	others[2]	2767	1			T2	20		T10	4		T11	17
auto[0]	auto[0]	others[3]	3175	1			T2	18		T10	13		T11	12
auto[0]	auto[0]	interest[1]	1878	1			T2	17		T5	1		T10	3
auto[0]	auto[0]	interest[4]	10767	1			T2	94		T5	4		T10	26
auto[0]	auto[0]	interest[64]	5459	1			T2	43		T5	1		T7	1
auto[0]	auto[1]	others[0]	7743	1			T2	43		T9	44		T10	15
auto[0]	auto[1]	others[1]	1214	1			T2	7		T9	4		T10	6
auto[0]	auto[1]	others[2]	1231	1			T2	4		T9	8		T10	5
auto[0]	auto[1]	others[3]	1297	1			T2	15		T9	11		T11	5
auto[0]	auto[1]	interest[1]	809	1			T2	7		T9	5		T10	4
auto[0]	auto[1]	interest[4]	5222	1			T2	24		T9	29		T10	12
auto[0]	auto[1]	interest[64]	2353	1			T2	14		T9	21		T10	2
auto[1]	auto[0]	others[0]	9376	1			T2	76		T5	4		T7	2
auto[1]	auto[0]	others[1]	1617	1			T2	15		T10	2		T11	12
auto[1]	auto[0]	others[2]	1572	1			T2	9		T5	1		T7	2
auto[1]	auto[0]	others[3]	1830	1			T2	18		T5	1		T7	1
auto[1]	auto[0]	interest[1]	1027	1			T2	6		T10	2		T11	8
auto[1]	auto[0]	interest[4]	6056	1			T2	51		T5	2		T10	9
auto[1]	auto[0]	interest[64]	3101	1			T2	24		T7	1		T10	7

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal