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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.04 98.38 94.01 98.62 89.36 97.19 95.45 99.26


Total test records in report: 1131
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T1026 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.3310166821 Jul 25 06:28:53 PM PDT 24 Jul 25 06:28:54 PM PDT 24 90854151 ps
T110 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3200001188 Jul 25 06:28:43 PM PDT 24 Jul 25 06:28:46 PM PDT 24 709144314 ps
T111 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2385288539 Jul 25 06:28:52 PM PDT 24 Jul 25 06:28:53 PM PDT 24 195149453 ps
T98 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.3269586505 Jul 25 06:28:44 PM PDT 24 Jul 25 06:29:08 PM PDT 24 1096136271 ps
T1027 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.256499548 Jul 25 06:28:55 PM PDT 24 Jul 25 06:28:59 PM PDT 24 65560563 ps
T1028 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1590504369 Jul 25 06:28:51 PM PDT 24 Jul 25 06:28:55 PM PDT 24 127973898 ps
T112 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.1231619946 Jul 25 06:28:34 PM PDT 24 Jul 25 06:28:48 PM PDT 24 1314652434 ps
T100 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.971798963 Jul 25 06:28:28 PM PDT 24 Jul 25 06:28:32 PM PDT 24 461505201 ps
T1029 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3668099819 Jul 25 06:28:52 PM PDT 24 Jul 25 06:28:53 PM PDT 24 13182201 ps
T95 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.1044958283 Jul 25 06:28:43 PM PDT 24 Jul 25 06:28:48 PM PDT 24 156083116 ps
T1030 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.853937662 Jul 25 06:28:41 PM PDT 24 Jul 25 06:28:45 PM PDT 24 437489782 ps
T94 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.3256286260 Jul 25 06:28:47 PM PDT 24 Jul 25 06:28:50 PM PDT 24 74120772 ps
T1031 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.798589719 Jul 25 06:28:46 PM PDT 24 Jul 25 06:28:50 PM PDT 24 215947521 ps
T97 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.76619300 Jul 25 06:28:42 PM PDT 24 Jul 25 06:28:45 PM PDT 24 189160378 ps
T1032 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2627313514 Jul 25 06:28:47 PM PDT 24 Jul 25 06:28:49 PM PDT 24 298119107 ps
T1033 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.58047642 Jul 25 06:28:41 PM PDT 24 Jul 25 06:28:44 PM PDT 24 426759772 ps
T113 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.2027975441 Jul 25 06:28:31 PM PDT 24 Jul 25 06:28:46 PM PDT 24 840352073 ps
T1034 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3115566988 Jul 25 06:28:42 PM PDT 24 Jul 25 06:28:46 PM PDT 24 61896893 ps
T1035 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.1797650397 Jul 25 06:28:45 PM PDT 24 Jul 25 06:29:22 PM PDT 24 4528837597 ps
T1036 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1288096991 Jul 25 06:28:40 PM PDT 24 Jul 25 06:28:40 PM PDT 24 23172516 ps
T1037 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.1499913367 Jul 25 06:28:44 PM PDT 24 Jul 25 06:28:47 PM PDT 24 72943045 ps
T1038 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.311979821 Jul 25 06:28:59 PM PDT 24 Jul 25 06:29:04 PM PDT 24 224650687 ps
T1039 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.938732105 Jul 25 06:28:43 PM PDT 24 Jul 25 06:28:44 PM PDT 24 39835890 ps
T115 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.4046392907 Jul 25 06:28:30 PM PDT 24 Jul 25 06:29:07 PM PDT 24 7549091225 ps
T96 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.1805960359 Jul 25 06:28:27 PM PDT 24 Jul 25 06:28:30 PM PDT 24 1533979171 ps
T1040 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.780779545 Jul 25 06:28:52 PM PDT 24 Jul 25 06:28:55 PM PDT 24 214928107 ps
T158 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.645092825 Jul 25 06:28:29 PM PDT 24 Jul 25 06:28:36 PM PDT 24 2405946302 ps
T1041 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.2018271355 Jul 25 06:29:02 PM PDT 24 Jul 25 06:29:03 PM PDT 24 45814335 ps
T1042 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3541356526 Jul 25 06:28:40 PM PDT 24 Jul 25 06:28:44 PM PDT 24 347739129 ps
T116 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.571872784 Jul 25 06:28:45 PM PDT 24 Jul 25 06:28:48 PM PDT 24 1969993520 ps
T1043 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3668590377 Jul 25 06:29:01 PM PDT 24 Jul 25 06:29:02 PM PDT 24 15328517 ps
T162 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.3320457320 Jul 25 06:28:42 PM PDT 24 Jul 25 06:29:04 PM PDT 24 862070699 ps
T1044 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2727535881 Jul 25 06:28:42 PM PDT 24 Jul 25 06:28:44 PM PDT 24 35850847 ps
T117 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.2365143714 Jul 25 06:28:42 PM PDT 24 Jul 25 06:28:44 PM PDT 24 61824252 ps
T1045 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.724474469 Jul 25 06:28:40 PM PDT 24 Jul 25 06:28:52 PM PDT 24 749491044 ps
T1046 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.1680747499 Jul 25 06:28:34 PM PDT 24 Jul 25 06:29:11 PM PDT 24 12050904283 ps
T1047 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1512273151 Jul 25 06:28:42 PM PDT 24 Jul 25 06:28:44 PM PDT 24 26752936 ps
T1048 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.3310207552 Jul 25 06:28:31 PM PDT 24 Jul 25 06:28:32 PM PDT 24 153006602 ps
T77 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3429548047 Jul 25 06:28:29 PM PDT 24 Jul 25 06:28:30 PM PDT 24 83019245 ps
T160 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.3839292992 Jul 25 06:28:47 PM PDT 24 Jul 25 06:28:56 PM PDT 24 869271243 ps
T99 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.1249126430 Jul 25 06:28:33 PM PDT 24 Jul 25 06:28:36 PM PDT 24 51250631 ps
T1049 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.2251478577 Jul 25 06:29:01 PM PDT 24 Jul 25 06:29:02 PM PDT 24 38690556 ps
T1050 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.4217107819 Jul 25 06:28:42 PM PDT 24 Jul 25 06:28:51 PM PDT 24 1462068035 ps
T1051 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.1632072423 Jul 25 06:28:33 PM PDT 24 Jul 25 06:28:34 PM PDT 24 52423990 ps
T1052 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3367987684 Jul 25 06:28:44 PM PDT 24 Jul 25 06:28:49 PM PDT 24 247789075 ps
T1053 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2848428446 Jul 25 06:28:41 PM PDT 24 Jul 25 06:28:43 PM PDT 24 49420635 ps
T1054 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3717022249 Jul 25 06:28:32 PM PDT 24 Jul 25 06:28:35 PM PDT 24 145894774 ps
T1055 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.4269192713 Jul 25 06:28:40 PM PDT 24 Jul 25 06:28:44 PM PDT 24 120394803 ps
T1056 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3671314137 Jul 25 06:28:31 PM PDT 24 Jul 25 06:28:35 PM PDT 24 56671151 ps
T1057 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3826684876 Jul 25 06:28:42 PM PDT 24 Jul 25 06:28:48 PM PDT 24 193761144 ps
T1058 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3371860492 Jul 25 06:28:52 PM PDT 24 Jul 25 06:28:56 PM PDT 24 573066644 ps
T1059 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2201705073 Jul 25 06:29:01 PM PDT 24 Jul 25 06:29:02 PM PDT 24 43527004 ps
T1060 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.1574236539 Jul 25 06:28:59 PM PDT 24 Jul 25 06:29:00 PM PDT 24 13827163 ps
T1061 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2539353812 Jul 25 06:28:58 PM PDT 24 Jul 25 06:29:01 PM PDT 24 141838895 ps
T163 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.346959125 Jul 25 06:29:02 PM PDT 24 Jul 25 06:29:17 PM PDT 24 628635924 ps
T1062 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3371171614 Jul 25 06:28:32 PM PDT 24 Jul 25 06:28:35 PM PDT 24 101215285 ps
T1063 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.54766697 Jul 25 06:28:41 PM PDT 24 Jul 25 06:28:45 PM PDT 24 151293702 ps
T1064 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.807464986 Jul 25 06:28:39 PM PDT 24 Jul 25 06:28:40 PM PDT 24 17736908 ps
T1065 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.253866711 Jul 25 06:28:31 PM PDT 24 Jul 25 06:28:33 PM PDT 24 49047233 ps
T157 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.3706667242 Jul 25 06:28:42 PM PDT 24 Jul 25 06:28:46 PM PDT 24 187079713 ps
T1066 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.2328956600 Jul 25 06:28:59 PM PDT 24 Jul 25 06:29:00 PM PDT 24 26759825 ps
T1067 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2832675590 Jul 25 06:28:42 PM PDT 24 Jul 25 06:28:46 PM PDT 24 147983179 ps
T1068 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.4015239343 Jul 25 06:29:04 PM PDT 24 Jul 25 06:29:05 PM PDT 24 35747378 ps
T1069 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.322263195 Jul 25 06:28:59 PM PDT 24 Jul 25 06:29:00 PM PDT 24 12838169 ps
T1070 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.1718018276 Jul 25 06:28:42 PM PDT 24 Jul 25 06:28:45 PM PDT 24 472710831 ps
T1071 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.4224323022 Jul 25 06:28:40 PM PDT 24 Jul 25 06:28:58 PM PDT 24 1190974468 ps
T1072 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1963445415 Jul 25 06:28:45 PM PDT 24 Jul 25 06:28:48 PM PDT 24 154014544 ps
T1073 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1307209564 Jul 25 06:28:42 PM PDT 24 Jul 25 06:28:43 PM PDT 24 17754707 ps
T1074 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.852379912 Jul 25 06:28:40 PM PDT 24 Jul 25 06:28:41 PM PDT 24 15826480 ps
T1075 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.2387085706 Jul 25 06:28:43 PM PDT 24 Jul 25 06:29:07 PM PDT 24 3598137299 ps
T1076 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.470324721 Jul 25 06:28:50 PM PDT 24 Jul 25 06:28:52 PM PDT 24 51084623 ps
T1077 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2920116806 Jul 25 06:28:52 PM PDT 24 Jul 25 06:28:53 PM PDT 24 43635999 ps
T1078 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2201919189 Jul 25 06:28:53 PM PDT 24 Jul 25 06:28:56 PM PDT 24 322636306 ps
T1079 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.813925445 Jul 25 06:29:02 PM PDT 24 Jul 25 06:29:03 PM PDT 24 38740394 ps
T1080 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.246050284 Jul 25 06:28:58 PM PDT 24 Jul 25 06:29:00 PM PDT 24 29433710 ps
T1081 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3209676914 Jul 25 06:28:42 PM PDT 24 Jul 25 06:28:49 PM PDT 24 1017808549 ps
T1082 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.3758911969 Jul 25 06:28:59 PM PDT 24 Jul 25 06:29:00 PM PDT 24 34332196 ps
T1083 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.2268518812 Jul 25 06:29:02 PM PDT 24 Jul 25 06:29:03 PM PDT 24 36137553 ps
T1084 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2056811728 Jul 25 06:28:44 PM PDT 24 Jul 25 06:28:45 PM PDT 24 37232040 ps
T1085 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.3191757270 Jul 25 06:29:02 PM PDT 24 Jul 25 06:29:03 PM PDT 24 32302239 ps
T1086 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.976542104 Jul 25 06:28:40 PM PDT 24 Jul 25 06:28:44 PM PDT 24 886344359 ps
T1087 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.1856725116 Jul 25 06:29:02 PM PDT 24 Jul 25 06:29:03 PM PDT 24 23173585 ps
T1088 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3239287549 Jul 25 06:28:51 PM PDT 24 Jul 25 06:28:53 PM PDT 24 190424116 ps
T1089 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.1699611202 Jul 25 06:29:00 PM PDT 24 Jul 25 06:29:01 PM PDT 24 17470906 ps
T1090 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.800169368 Jul 25 06:29:02 PM PDT 24 Jul 25 06:29:03 PM PDT 24 45615870 ps
T1091 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.4196482507 Jul 25 06:28:39 PM PDT 24 Jul 25 06:29:00 PM PDT 24 3683746276 ps
T1092 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3470972439 Jul 25 06:28:45 PM PDT 24 Jul 25 06:28:46 PM PDT 24 85542631 ps
T1093 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2823453557 Jul 25 06:28:40 PM PDT 24 Jul 25 06:28:42 PM PDT 24 91645270 ps
T78 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1807817896 Jul 25 06:28:38 PM PDT 24 Jul 25 06:28:40 PM PDT 24 65828570 ps
T164 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.4097807304 Jul 25 06:28:41 PM PDT 24 Jul 25 06:28:47 PM PDT 24 98952719 ps
T1094 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1029287380 Jul 25 06:28:59 PM PDT 24 Jul 25 06:29:00 PM PDT 24 13718159 ps
T1095 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.3864629780 Jul 25 06:28:42 PM PDT 24 Jul 25 06:28:47 PM PDT 24 67714928 ps
T1096 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.54455216 Jul 25 06:28:30 PM PDT 24 Jul 25 06:28:32 PM PDT 24 63326021 ps
T1097 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.3391049347 Jul 25 06:28:42 PM PDT 24 Jul 25 06:28:45 PM PDT 24 400585849 ps
T1098 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3890446026 Jul 25 06:28:45 PM PDT 24 Jul 25 06:28:49 PM PDT 24 129279451 ps
T1099 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2361320273 Jul 25 06:28:48 PM PDT 24 Jul 25 06:28:50 PM PDT 24 36967169 ps
T1100 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1277303416 Jul 25 06:28:57 PM PDT 24 Jul 25 06:28:58 PM PDT 24 55758231 ps
T79 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2632754866 Jul 25 06:28:32 PM PDT 24 Jul 25 06:28:33 PM PDT 24 25877226 ps
T1101 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.1673077420 Jul 25 06:28:54 PM PDT 24 Jul 25 06:28:58 PM PDT 24 139363584 ps
T1102 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.2083856104 Jul 25 06:28:33 PM PDT 24 Jul 25 06:28:35 PM PDT 24 66553504 ps
T1103 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.3057859282 Jul 25 06:28:29 PM PDT 24 Jul 25 06:28:30 PM PDT 24 35131414 ps
T1104 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.3342063275 Jul 25 06:28:32 PM PDT 24 Jul 25 06:28:34 PM PDT 24 89421205 ps
T1105 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.2476455439 Jul 25 06:29:01 PM PDT 24 Jul 25 06:29:02 PM PDT 24 12711603 ps
T1106 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3623641172 Jul 25 06:28:51 PM PDT 24 Jul 25 06:28:54 PM PDT 24 184216155 ps
T1107 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3182957718 Jul 25 06:28:35 PM PDT 24 Jul 25 06:28:36 PM PDT 24 30336872 ps
T1108 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3768775771 Jul 25 06:28:39 PM PDT 24 Jul 25 06:28:44 PM PDT 24 224264536 ps
T1109 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.3950245579 Jul 25 06:28:43 PM PDT 24 Jul 25 06:28:44 PM PDT 24 50297484 ps
T1110 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2618888581 Jul 25 06:28:40 PM PDT 24 Jul 25 06:28:41 PM PDT 24 16972820 ps
T1111 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.2885983628 Jul 25 06:28:47 PM PDT 24 Jul 25 06:28:49 PM PDT 24 273241084 ps
T1112 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.1679659251 Jul 25 06:28:34 PM PDT 24 Jul 25 06:28:36 PM PDT 24 59501570 ps
T1113 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2013831287 Jul 25 06:28:44 PM PDT 24 Jul 25 06:28:45 PM PDT 24 11277136 ps
T1114 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.4060344954 Jul 25 06:29:03 PM PDT 24 Jul 25 06:29:04 PM PDT 24 45580522 ps
T1115 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.603206434 Jul 25 06:28:47 PM PDT 24 Jul 25 06:28:48 PM PDT 24 54564673 ps
T80 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2930069829 Jul 25 06:28:30 PM PDT 24 Jul 25 06:28:32 PM PDT 24 29945439 ps
T1116 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.4234088087 Jul 25 06:28:35 PM PDT 24 Jul 25 06:28:38 PM PDT 24 213701212 ps
T1117 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.241450250 Jul 25 06:29:02 PM PDT 24 Jul 25 06:29:03 PM PDT 24 40463112 ps
T1118 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.443547438 Jul 25 06:28:58 PM PDT 24 Jul 25 06:29:01 PM PDT 24 70229871 ps
T1119 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.37224317 Jul 25 06:28:36 PM PDT 24 Jul 25 06:28:37 PM PDT 24 20605025 ps
T1120 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.3493246862 Jul 25 06:29:00 PM PDT 24 Jul 25 06:29:00 PM PDT 24 14889663 ps
T1121 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2767414311 Jul 25 06:28:47 PM PDT 24 Jul 25 06:28:48 PM PDT 24 19285502 ps
T1122 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.2172246938 Jul 25 06:28:52 PM PDT 24 Jul 25 06:28:54 PM PDT 24 87647951 ps
T1123 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2433684277 Jul 25 06:28:38 PM PDT 24 Jul 25 06:28:41 PM PDT 24 84736349 ps
T161 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1911539002 Jul 25 06:28:50 PM PDT 24 Jul 25 06:29:09 PM PDT 24 1205229991 ps
T1124 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3144505107 Jul 25 06:28:42 PM PDT 24 Jul 25 06:28:45 PM PDT 24 170684866 ps
T1125 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.4083794274 Jul 25 06:28:52 PM PDT 24 Jul 25 06:29:11 PM PDT 24 4153402054 ps
T1126 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.4086820943 Jul 25 06:28:42 PM PDT 24 Jul 25 06:28:43 PM PDT 24 30580009 ps
T1127 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1195164414 Jul 25 06:28:43 PM PDT 24 Jul 25 06:28:47 PM PDT 24 424162656 ps
T1128 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3766355950 Jul 25 06:28:41 PM PDT 24 Jul 25 06:28:44 PM PDT 24 172575543 ps
T1129 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.385734960 Jul 25 06:29:02 PM PDT 24 Jul 25 06:29:03 PM PDT 24 62227496 ps
T1130 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1800161803 Jul 25 06:28:54 PM PDT 24 Jul 25 06:28:58 PM PDT 24 222114884 ps
T1131 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.974929023 Jul 25 06:28:29 PM PDT 24 Jul 25 06:28:30 PM PDT 24 18518095 ps

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.4064453146
Short name T10
Test name
Test status
Simulation time 32285466929 ps
CPU time 85.2 seconds
Started Jul 25 06:37:02 PM PDT 24
Finished Jul 25 06:38:27 PM PDT 24
Peak memory 249400 kb
Host smart-5175fe73-69c2-4e47-93cc-27eb9f5417ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064453146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.4064453146
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.4063539480
Short name T17
Test name
Test status
Simulation time 58322746643 ps
CPU time 280.92 seconds
Started Jul 25 06:36:24 PM PDT 24
Finished Jul 25 06:41:05 PM PDT 24
Peak memory 284932 kb
Host smart-e1a5b3f6-9ffe-4f3b-afce-73879b17ea8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063539480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.4063539480
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.2000855543
Short name T11
Test name
Test status
Simulation time 11187066022 ps
CPU time 75.31 seconds
Started Jul 25 06:38:25 PM PDT 24
Finished Jul 25 06:39:40 PM PDT 24
Peak memory 265260 kb
Host smart-2f63603a-8833-436b-9077-4f1dae35d681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000855543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.2000855543
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.1271340190
Short name T18
Test name
Test status
Simulation time 222061686087 ps
CPU time 538.11 seconds
Started Jul 25 06:37:17 PM PDT 24
Finished Jul 25 06:46:16 PM PDT 24
Peak memory 281672 kb
Host smart-5e4b1cc9-13ce-44c0-bb49-c99461168b00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271340190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.1271340190
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.1890637081
Short name T90
Test name
Test status
Simulation time 653491212 ps
CPU time 14.71 seconds
Started Jul 25 06:28:28 PM PDT 24
Finished Jul 25 06:28:43 PM PDT 24
Peak memory 215576 kb
Host smart-1be7d3e0-ecc0-4a78-9ab9-5efe028d7173
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890637081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.1890637081
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.3219499606
Short name T16
Test name
Test status
Simulation time 56191273960 ps
CPU time 498.41 seconds
Started Jul 25 06:37:22 PM PDT 24
Finished Jul 25 06:45:40 PM PDT 24
Peak memory 266216 kb
Host smart-769e87f5-f8da-4704-abe5-686e127ca210
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219499606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.3219499606
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.957808837
Short name T64
Test name
Test status
Simulation time 20703600 ps
CPU time 0.78 seconds
Started Jul 25 06:36:26 PM PDT 24
Finished Jul 25 06:36:27 PM PDT 24
Peak memory 216216 kb
Host smart-e850d9d8-7b6e-4383-b25a-f450d72906a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957808837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.957808837
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.1628442499
Short name T33
Test name
Test status
Simulation time 34613909460 ps
CPU time 210.29 seconds
Started Jul 25 06:37:27 PM PDT 24
Finished Jul 25 06:40:57 PM PDT 24
Peak memory 272888 kb
Host smart-d8fdcc60-d04e-49de-9f95-32cef861acf4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628442499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.1628442499
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.1357730765
Short name T22
Test name
Test status
Simulation time 3853943773 ps
CPU time 80.83 seconds
Started Jul 25 06:39:01 PM PDT 24
Finished Jul 25 06:40:22 PM PDT 24
Peak memory 270872 kb
Host smart-c3b422f6-a649-49bf-8a61-6db3af4e504a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357730765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmd
s.1357730765
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.3945387517
Short name T124
Test name
Test status
Simulation time 4099320481 ps
CPU time 60.26 seconds
Started Jul 25 06:39:09 PM PDT 24
Finished Jul 25 06:40:10 PM PDT 24
Peak memory 242100 kb
Host smart-524721bd-ceac-41f7-9523-80689d88b764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945387517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.3945387517
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.987051820
Short name T91
Test name
Test status
Simulation time 290289023 ps
CPU time 5.17 seconds
Started Jul 25 06:28:41 PM PDT 24
Finished Jul 25 06:28:46 PM PDT 24
Peak memory 215828 kb
Host smart-6f92d7fa-662c-4999-a68b-3dc668ce7aa6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987051820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.987051820
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.2755464471
Short name T52
Test name
Test status
Simulation time 97870031127 ps
CPU time 931.74 seconds
Started Jul 25 06:38:12 PM PDT 24
Finished Jul 25 06:53:44 PM PDT 24
Peak memory 303724 kb
Host smart-ef33a2cf-40de-4571-8b55-02f61c5437ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755464471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.2755464471
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.3776275976
Short name T328
Test name
Test status
Simulation time 44582983 ps
CPU time 0.72 seconds
Started Jul 25 06:37:02 PM PDT 24
Finished Jul 25 06:37:02 PM PDT 24
Peak memory 205636 kb
Host smart-5710843c-5aa6-43c2-97a2-f69263682846
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776275976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
3776275976
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.1632688476
Short name T260
Test name
Test status
Simulation time 10628850712 ps
CPU time 92.63 seconds
Started Jul 25 06:37:28 PM PDT 24
Finished Jul 25 06:39:00 PM PDT 24
Peak memory 254576 kb
Host smart-2cee3b7b-1b50-4dc7-bd04-c34e39194db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632688476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.1632688476
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.3169016976
Short name T154
Test name
Test status
Simulation time 267351604021 ps
CPU time 383.56 seconds
Started Jul 25 06:37:03 PM PDT 24
Finished Jul 25 06:43:26 PM PDT 24
Peak memory 263364 kb
Host smart-242c1221-20a7-4a6c-ad7c-abf47e5ace04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169016976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.3169016976
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.216655624
Short name T21
Test name
Test status
Simulation time 4011171290 ps
CPU time 103.82 seconds
Started Jul 25 06:37:40 PM PDT 24
Finished Jul 25 06:39:24 PM PDT 24
Peak memory 256840 kb
Host smart-a9bbc7a5-eea9-4a83-9ea4-7921d0395c44
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216655624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stres
s_all.216655624
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.233138484
Short name T109
Test name
Test status
Simulation time 252907339 ps
CPU time 7.44 seconds
Started Jul 25 06:28:32 PM PDT 24
Finished Jul 25 06:28:40 PM PDT 24
Peak memory 207232 kb
Host smart-fa14b2d1-a97e-4791-81e3-bd3dfb7f1ed3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233138484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_aliasing.233138484
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.2409460701
Short name T46
Test name
Test status
Simulation time 17886992098 ps
CPU time 113.17 seconds
Started Jul 25 06:37:25 PM PDT 24
Finished Jul 25 06:39:19 PM PDT 24
Peak memory 264860 kb
Host smart-c11d71e5-5233-4d02-8fd8-afafce9e1ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409460701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmd
s.2409460701
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.2292838582
Short name T32
Test name
Test status
Simulation time 3573054903 ps
CPU time 84.48 seconds
Started Jul 25 06:39:09 PM PDT 24
Finished Jul 25 06:40:34 PM PDT 24
Peak memory 254684 kb
Host smart-ac1aa0fe-dd6b-4c17-8171-106a4fafe108
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292838582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.2292838582
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.3175576733
Short name T68
Test name
Test status
Simulation time 74592282 ps
CPU time 1.01 seconds
Started Jul 25 06:36:29 PM PDT 24
Finished Jul 25 06:36:30 PM PDT 24
Peak memory 235936 kb
Host smart-af3c6f22-8dd0-4724-9b77-d11cd41005b5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175576733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.3175576733
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.2972751422
Short name T206
Test name
Test status
Simulation time 30521790154 ps
CPU time 228.28 seconds
Started Jul 25 06:37:17 PM PDT 24
Finished Jul 25 06:41:06 PM PDT 24
Peak memory 253296 kb
Host smart-b21d4351-79c5-47f7-a725-1e06dbf053d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972751422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.2972751422
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.2784161764
Short name T183
Test name
Test status
Simulation time 167761029015 ps
CPU time 320.9 seconds
Started Jul 25 06:38:44 PM PDT 24
Finished Jul 25 06:44:05 PM PDT 24
Peak memory 265528 kb
Host smart-a9238b36-d86f-42ec-80c1-7fd578269eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784161764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.2784161764
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.1456642358
Short name T208
Test name
Test status
Simulation time 280109752152 ps
CPU time 790.1 seconds
Started Jul 25 06:38:07 PM PDT 24
Finished Jul 25 06:51:18 PM PDT 24
Peak memory 272236 kb
Host smart-1fcc50bc-f2c1-450e-831e-354d88288674
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456642358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.1456642358
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.1352223797
Short name T50
Test name
Test status
Simulation time 6590452700 ps
CPU time 44.59 seconds
Started Jul 25 06:36:33 PM PDT 24
Finished Jul 25 06:37:18 PM PDT 24
Peak memory 250456 kb
Host smart-bc6fd1b6-67cc-4aa8-8955-7fe12dde6ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352223797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.1352223797
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.1136615484
Short name T285
Test name
Test status
Simulation time 45289980991 ps
CPU time 402.25 seconds
Started Jul 25 06:37:09 PM PDT 24
Finished Jul 25 06:43:51 PM PDT 24
Peak memory 281684 kb
Host smart-ef844699-db0a-4e05-ad85-5bf87c1c67b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136615484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.1136615484
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.2527729799
Short name T1002
Test name
Test status
Simulation time 11357236231 ps
CPU time 158.97 seconds
Started Jul 25 06:38:27 PM PDT 24
Finished Jul 25 06:41:06 PM PDT 24
Peak memory 265992 kb
Host smart-bb744987-ee06-4d09-ac46-f3960b4c5b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527729799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.2527729799
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.3600347602
Short name T273
Test name
Test status
Simulation time 87422434870 ps
CPU time 173.6 seconds
Started Jul 25 06:39:32 PM PDT 24
Finished Jul 25 06:42:26 PM PDT 24
Peak memory 253060 kb
Host smart-21e12bd7-54f8-45e4-9b1b-fbda4bdfe465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600347602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.3600347602
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.3839292992
Short name T160
Test name
Test status
Simulation time 869271243 ps
CPU time 8.15 seconds
Started Jul 25 06:28:47 PM PDT 24
Finished Jul 25 06:28:56 PM PDT 24
Peak memory 215880 kb
Host smart-46dc92e8-6096-4e10-80db-1f0f4b501082
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839292992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.3839292992
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.2645301462
Short name T262
Test name
Test status
Simulation time 368222510942 ps
CPU time 261.12 seconds
Started Jul 25 06:37:14 PM PDT 24
Finished Jul 25 06:41:35 PM PDT 24
Peak memory 259884 kb
Host smart-43a41038-60ed-4ced-b1b3-14523783c09f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645301462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.2645301462
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.323443289
Short name T176
Test name
Test status
Simulation time 70256410485 ps
CPU time 170.9 seconds
Started Jul 25 06:37:21 PM PDT 24
Finished Jul 25 06:40:12 PM PDT 24
Peak memory 257180 kb
Host smart-8b7701dd-0a6b-4928-872d-b75eca1cc351
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323443289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stres
s_all.323443289
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.1892692904
Short name T39
Test name
Test status
Simulation time 170869139611 ps
CPU time 400.31 seconds
Started Jul 25 06:38:28 PM PDT 24
Finished Jul 25 06:45:08 PM PDT 24
Peak memory 250756 kb
Host smart-456d1f9b-de80-485b-91f3-a4a54823287b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892692904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.1892692904
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.844478950
Short name T266
Test name
Test status
Simulation time 165516982332 ps
CPU time 204.46 seconds
Started Jul 25 06:36:34 PM PDT 24
Finished Jul 25 06:39:59 PM PDT 24
Peak memory 254448 kb
Host smart-aaccdd39-82ad-4207-8b6d-260a1e711f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844478950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds.
844478950
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.4097807304
Short name T164
Test name
Test status
Simulation time 98952719 ps
CPU time 6.36 seconds
Started Jul 25 06:28:41 PM PDT 24
Finished Jul 25 06:28:47 PM PDT 24
Peak memory 215988 kb
Host smart-415da73b-cf14-4a21-9f51-f7dca0ce27e6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097807304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.4097807304
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.2822560802
Short name T36
Test name
Test status
Simulation time 1075560861 ps
CPU time 5.98 seconds
Started Jul 25 06:36:20 PM PDT 24
Finished Jul 25 06:36:26 PM PDT 24
Peak memory 216416 kb
Host smart-246b8098-c538-450f-8194-fd66327d2ad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822560802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.2822560802
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.2593872790
Short name T14
Test name
Test status
Simulation time 26961198029 ps
CPU time 20.89 seconds
Started Jul 25 06:37:19 PM PDT 24
Finished Jul 25 06:37:40 PM PDT 24
Peak memory 233032 kb
Host smart-b26b1834-90b3-4a11-8c1b-1be655124f5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593872790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.2593872790
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.305919236
Short name T294
Test name
Test status
Simulation time 8595219703 ps
CPU time 31.7 seconds
Started Jul 25 06:37:32 PM PDT 24
Finished Jul 25 06:38:04 PM PDT 24
Peak memory 236148 kb
Host smart-2f1dbaf2-e068-428d-ae35-97e25640c82a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305919236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.305919236
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.489864693
Short name T281
Test name
Test status
Simulation time 89610080535 ps
CPU time 148.13 seconds
Started Jul 25 06:38:26 PM PDT 24
Finished Jul 25 06:40:54 PM PDT 24
Peak memory 257456 kb
Host smart-68848f9d-ef61-4230-b8bf-d95121a5acae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489864693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stres
s_all.489864693
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.3565990666
Short name T191
Test name
Test status
Simulation time 13625696709 ps
CPU time 109.84 seconds
Started Jul 25 06:39:02 PM PDT 24
Finished Jul 25 06:40:52 PM PDT 24
Peak memory 257608 kb
Host smart-cb885033-76b1-45fe-805f-cde0033eb2c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565990666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.3565990666
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.1249126430
Short name T99
Test name
Test status
Simulation time 51250631 ps
CPU time 2.73 seconds
Started Jul 25 06:28:33 PM PDT 24
Finished Jul 25 06:28:36 PM PDT 24
Peak memory 216672 kb
Host smart-c015322c-6cdf-4e38-a3bc-5430a0fa678a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249126430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.1
249126430
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.4083794274
Short name T1125
Test name
Test status
Simulation time 4153402054 ps
CPU time 18.39 seconds
Started Jul 25 06:28:52 PM PDT 24
Finished Jul 25 06:29:11 PM PDT 24
Peak memory 215560 kb
Host smart-3d69b5ec-bc8f-4f4b-9682-86c730da3f5d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083794274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.4083794274
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.3613058803
Short name T280
Test name
Test status
Simulation time 63553987214 ps
CPU time 142 seconds
Started Jul 25 06:37:14 PM PDT 24
Finished Jul 25 06:39:36 PM PDT 24
Peak memory 252812 kb
Host smart-32f94be6-2f1f-41bf-abaf-40b75db066e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613058803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.3613058803
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.1720994888
Short name T988
Test name
Test status
Simulation time 4842680430 ps
CPU time 84.51 seconds
Started Jul 25 06:37:13 PM PDT 24
Finished Jul 25 06:38:38 PM PDT 24
Peak memory 266732 kb
Host smart-41c4961c-dd95-4f4b-ae31-5415387791f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720994888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmd
s.1720994888
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.1135625689
Short name T129
Test name
Test status
Simulation time 9841742245 ps
CPU time 26.62 seconds
Started Jul 25 06:37:18 PM PDT 24
Finished Jul 25 06:37:45 PM PDT 24
Peak memory 224760 kb
Host smart-0dfb07d2-2d3e-46ea-bb9c-27f85ad354cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135625689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.1135625689
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.243295258
Short name T296
Test name
Test status
Simulation time 214431541 ps
CPU time 8.54 seconds
Started Jul 25 06:37:47 PM PDT 24
Finished Jul 25 06:37:56 PM PDT 24
Peak memory 241028 kb
Host smart-e10062a8-b2fe-42b7-9bef-9ea6eb959c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243295258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.243295258
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.835604819
Short name T156
Test name
Test status
Simulation time 24794233512 ps
CPU time 86.67 seconds
Started Jul 25 06:37:57 PM PDT 24
Finished Jul 25 06:39:24 PM PDT 24
Peak memory 257264 kb
Host smart-65685380-7b1d-460e-bf82-05d3ba8de2c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835604819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.835604819
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.4122928567
Short name T212
Test name
Test status
Simulation time 1792423782 ps
CPU time 21.05 seconds
Started Jul 25 06:36:35 PM PDT 24
Finished Jul 25 06:36:57 PM PDT 24
Peak memory 230080 kb
Host smart-d3ffcf97-f205-4ad7-987c-321cfb84b21c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122928567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.4122928567
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.3286862376
Short name T290
Test name
Test status
Simulation time 19721466986 ps
CPU time 169.61 seconds
Started Jul 25 06:38:44 PM PDT 24
Finished Jul 25 06:41:34 PM PDT 24
Peak memory 253972 kb
Host smart-8a20d687-82ab-474e-b872-ffef5f84b287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286862376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmd
s.3286862376
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.1320367289
Short name T175
Test name
Test status
Simulation time 11511397526 ps
CPU time 70.2 seconds
Started Jul 25 06:38:54 PM PDT 24
Finished Jul 25 06:40:04 PM PDT 24
Peak memory 257076 kb
Host smart-00400cca-be9f-4f32-a794-fe4ec8debd09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320367289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.1320367289
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_intercept.517711795
Short name T902
Test name
Test status
Simulation time 1178839729 ps
CPU time 12.39 seconds
Started Jul 25 06:36:16 PM PDT 24
Finished Jul 25 06:36:28 PM PDT 24
Peak memory 232876 kb
Host smart-624b81dd-d66d-4737-96b9-b1742f552b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517711795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.517711795
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.3240143669
Short name T192
Test name
Test status
Simulation time 6777942884 ps
CPU time 20.38 seconds
Started Jul 25 06:37:27 PM PDT 24
Finished Jul 25 06:37:47 PM PDT 24
Peak memory 241212 kb
Host smart-06591c30-0417-41fd-9eeb-5f8e3c5d890a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240143669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.3240143669
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2930069829
Short name T80
Test name
Test status
Simulation time 29945439 ps
CPU time 1.19 seconds
Started Jul 25 06:28:30 PM PDT 24
Finished Jul 25 06:28:32 PM PDT 24
Peak memory 207284 kb
Host smart-e6fd8d3f-0a71-428b-992a-7323473abd77
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930069829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.2930069829
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2701779456
Short name T62
Test name
Test status
Simulation time 156821337 ps
CPU time 3.91 seconds
Started Jul 25 06:28:28 PM PDT 24
Finished Jul 25 06:28:32 PM PDT 24
Peak memory 215616 kb
Host smart-97e05100-e3ae-47fc-a563-cb16d98ed4c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701779456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.2
701779456
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.3269586505
Short name T98
Test name
Test status
Simulation time 1096136271 ps
CPU time 24.21 seconds
Started Jul 25 06:28:44 PM PDT 24
Finished Jul 25 06:29:08 PM PDT 24
Peak memory 215524 kb
Host smart-034067fb-6023-4a8b-945c-75c8c7b7e337
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269586505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.3269586505
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.4046392907
Short name T115
Test name
Test status
Simulation time 7549091225 ps
CPU time 36.73 seconds
Started Jul 25 06:28:30 PM PDT 24
Finished Jul 25 06:29:07 PM PDT 24
Peak memory 215540 kb
Host smart-46525822-d0ba-4b8b-b0ca-7d705db029b8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046392907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.4046392907
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.971798963
Short name T100
Test name
Test status
Simulation time 461505201 ps
CPU time 3.48 seconds
Started Jul 25 06:28:28 PM PDT 24
Finished Jul 25 06:28:32 PM PDT 24
Peak memory 217428 kb
Host smart-440c8bf7-7c62-4a92-8d7c-94772fae4ad7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971798963 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.971798963
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2256730740
Short name T133
Test name
Test status
Simulation time 193506103 ps
CPU time 1.44 seconds
Started Jul 25 06:28:31 PM PDT 24
Finished Jul 25 06:28:32 PM PDT 24
Peak memory 215484 kb
Host smart-90cc21b4-8baa-4e5c-9da5-851ac541c317
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256730740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.2
256730740
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.1869548712
Short name T1020
Test name
Test status
Simulation time 52619642 ps
CPU time 0.77 seconds
Started Jul 25 06:28:28 PM PDT 24
Finished Jul 25 06:28:29 PM PDT 24
Peak memory 204296 kb
Host smart-b1129a41-3709-45b2-b12e-96ac68b48bd2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869548712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.1
869548712
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.2083856104
Short name T1102
Test name
Test status
Simulation time 66553504 ps
CPU time 2.13 seconds
Started Jul 25 06:28:33 PM PDT 24
Finished Jul 25 06:28:35 PM PDT 24
Peak memory 215420 kb
Host smart-c18a8359-f7a0-4b37-8c6c-4f7134bb6186
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083856104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.2083856104
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.974929023
Short name T1131
Test name
Test status
Simulation time 18518095 ps
CPU time 0.66 seconds
Started Jul 25 06:28:29 PM PDT 24
Finished Jul 25 06:28:30 PM PDT 24
Peak memory 203940 kb
Host smart-01f58e3d-94b4-43a3-b0dc-beee9d2055e1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974929023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_mem
_walk.974929023
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3671314137
Short name T1056
Test name
Test status
Simulation time 56671151 ps
CPU time 3.55 seconds
Started Jul 25 06:28:31 PM PDT 24
Finished Jul 25 06:28:35 PM PDT 24
Peak memory 215544 kb
Host smart-7d2ad2c5-0f8e-4a56-b68d-f935d58c973b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671314137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.3671314137
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.1285328225
Short name T136
Test name
Test status
Simulation time 2014538324 ps
CPU time 22.69 seconds
Started Jul 25 06:28:30 PM PDT 24
Finished Jul 25 06:28:53 PM PDT 24
Peak memory 215496 kb
Host smart-85ed4dac-037b-41c0-9bc0-c4335f7ff011
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285328225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.1285328225
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.2027975441
Short name T113
Test name
Test status
Simulation time 840352073 ps
CPU time 14.14 seconds
Started Jul 25 06:28:31 PM PDT 24
Finished Jul 25 06:28:46 PM PDT 24
Peak memory 215480 kb
Host smart-bd9414a5-a24b-41b0-afc7-65989026c0df
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027975441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.2027975441
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.1680747499
Short name T1046
Test name
Test status
Simulation time 12050904283 ps
CPU time 36.3 seconds
Started Jul 25 06:28:34 PM PDT 24
Finished Jul 25 06:29:11 PM PDT 24
Peak memory 215528 kb
Host smart-a645c305-8d6c-4480-87e6-7b3d00e16fb4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680747499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.1680747499
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3429548047
Short name T77
Test name
Test status
Simulation time 83019245 ps
CPU time 0.95 seconds
Started Jul 25 06:28:29 PM PDT 24
Finished Jul 25 06:28:30 PM PDT 24
Peak memory 207172 kb
Host smart-365c9538-4249-45de-b011-a227caf25738
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429548047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.3429548047
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.253866711
Short name T1065
Test name
Test status
Simulation time 49047233 ps
CPU time 1.74 seconds
Started Jul 25 06:28:31 PM PDT 24
Finished Jul 25 06:28:33 PM PDT 24
Peak memory 215484 kb
Host smart-ac66b0d3-81cc-454e-9b13-058edb8f62a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253866711 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.253866711
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.54455216
Short name T1096
Test name
Test status
Simulation time 63326021 ps
CPU time 1.95 seconds
Started Jul 25 06:28:30 PM PDT 24
Finished Jul 25 06:28:32 PM PDT 24
Peak memory 215540 kb
Host smart-cbbaf47b-76c5-4a8c-88a4-55e3410497de
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54455216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.54455216
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3182957718
Short name T1107
Test name
Test status
Simulation time 30336872 ps
CPU time 0.75 seconds
Started Jul 25 06:28:35 PM PDT 24
Finished Jul 25 06:28:36 PM PDT 24
Peak memory 203984 kb
Host smart-41385655-a975-49b8-bebe-8ae359b78383
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182957718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.3
182957718
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.1632072423
Short name T1051
Test name
Test status
Simulation time 52423990 ps
CPU time 1.69 seconds
Started Jul 25 06:28:33 PM PDT 24
Finished Jul 25 06:28:34 PM PDT 24
Peak memory 215480 kb
Host smart-f4e13075-6fd2-47b1-9aa0-3d9dde2db0d2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632072423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.1632072423
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.37224317
Short name T1119
Test name
Test status
Simulation time 20605025 ps
CPU time 0.65 seconds
Started Jul 25 06:28:36 PM PDT 24
Finished Jul 25 06:28:37 PM PDT 24
Peak memory 203936 kb
Host smart-abfb8070-56d2-4ce4-939c-3b1ca2a93a26
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37224317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem_
walk.37224317
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3734699863
Short name T123
Test name
Test status
Simulation time 519652061 ps
CPU time 2.77 seconds
Started Jul 25 06:28:31 PM PDT 24
Finished Jul 25 06:28:34 PM PDT 24
Peak memory 215468 kb
Host smart-25c52f22-984b-41d3-8b39-ba25df35ba3c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734699863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.3734699863
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.1805960359
Short name T96
Test name
Test status
Simulation time 1533979171 ps
CPU time 2.51 seconds
Started Jul 25 06:28:27 PM PDT 24
Finished Jul 25 06:28:30 PM PDT 24
Peak memory 215656 kb
Host smart-015a264c-79f5-430f-a241-9f6fa7a4f687
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805960359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.1
805960359
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.853937662
Short name T1030
Test name
Test status
Simulation time 437489782 ps
CPU time 3.42 seconds
Started Jul 25 06:28:41 PM PDT 24
Finished Jul 25 06:28:45 PM PDT 24
Peak memory 217256 kb
Host smart-fd7464cb-ee9f-4ad3-bab3-40d061b99a38
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853937662 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.853937662
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2361320273
Short name T1099
Test name
Test status
Simulation time 36967169 ps
CPU time 1.36 seconds
Started Jul 25 06:28:48 PM PDT 24
Finished Jul 25 06:28:50 PM PDT 24
Peak memory 215564 kb
Host smart-a45226a7-caca-498b-91dc-14bcdcf1d318
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361320273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
2361320273
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2767414311
Short name T1121
Test name
Test status
Simulation time 19285502 ps
CPU time 0.72 seconds
Started Jul 25 06:28:47 PM PDT 24
Finished Jul 25 06:28:48 PM PDT 24
Peak memory 204012 kb
Host smart-85728f00-09d7-4dde-807b-28a36d244d8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767414311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
2767414311
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1195164414
Short name T1127
Test name
Test status
Simulation time 424162656 ps
CPU time 4.05 seconds
Started Jul 25 06:28:43 PM PDT 24
Finished Jul 25 06:28:47 PM PDT 24
Peak memory 215532 kb
Host smart-8944d979-1d8b-4a48-b793-5d02f2fcf38a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195164414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.1195164414
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2848428446
Short name T1053
Test name
Test status
Simulation time 49420635 ps
CPU time 1.66 seconds
Started Jul 25 06:28:41 PM PDT 24
Finished Jul 25 06:28:43 PM PDT 24
Peak memory 215648 kb
Host smart-9e54ca98-cef4-466a-954b-2206719b9e4e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848428446 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.2848428446
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.3145664831
Short name T1022
Test name
Test status
Simulation time 30308038 ps
CPU time 1.91 seconds
Started Jul 25 06:28:47 PM PDT 24
Finished Jul 25 06:28:50 PM PDT 24
Peak memory 215384 kb
Host smart-4eeb1267-2ea6-4555-a8df-456d025b48ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145664831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
3145664831
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1307209564
Short name T1073
Test name
Test status
Simulation time 17754707 ps
CPU time 0.74 seconds
Started Jul 25 06:28:42 PM PDT 24
Finished Jul 25 06:28:43 PM PDT 24
Peak memory 203992 kb
Host smart-4ebf5acb-c41a-4592-a0f3-d9149881c7a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307209564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
1307209564
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2832675590
Short name T1067
Test name
Test status
Simulation time 147983179 ps
CPU time 3.21 seconds
Started Jul 25 06:28:42 PM PDT 24
Finished Jul 25 06:28:46 PM PDT 24
Peak memory 215476 kb
Host smart-a461ea51-c39c-4d92-b508-323238498ea4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832675590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.2832675590
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3826684876
Short name T1057
Test name
Test status
Simulation time 193761144 ps
CPU time 5.15 seconds
Started Jul 25 06:28:42 PM PDT 24
Finished Jul 25 06:28:48 PM PDT 24
Peak memory 215664 kb
Host smart-6c5cdd76-5e3d-48b0-87a2-7ef50a9aff8c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826684876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
3826684876
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3209676914
Short name T1081
Test name
Test status
Simulation time 1017808549 ps
CPU time 6.77 seconds
Started Jul 25 06:28:42 PM PDT 24
Finished Jul 25 06:28:49 PM PDT 24
Peak memory 215612 kb
Host smart-628a3e24-ee9e-495d-ba3f-cdc665908cf2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209676914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.3209676914
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3255660876
Short name T101
Test name
Test status
Simulation time 79493237 ps
CPU time 1.97 seconds
Started Jul 25 06:28:44 PM PDT 24
Finished Jul 25 06:28:47 PM PDT 24
Peak memory 215576 kb
Host smart-0557a2d9-ce0a-40ce-b19f-c9dadd9c89b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255660876 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.3255660876
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.571872784
Short name T116
Test name
Test status
Simulation time 1969993520 ps
CPU time 3 seconds
Started Jul 25 06:28:45 PM PDT 24
Finished Jul 25 06:28:48 PM PDT 24
Peak memory 215480 kb
Host smart-2da11d19-2fa4-4a1c-8b7c-b0416e4f1a81
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571872784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.571872784
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.2884701094
Short name T1011
Test name
Test status
Simulation time 69702379 ps
CPU time 0.68 seconds
Started Jul 25 06:28:41 PM PDT 24
Finished Jul 25 06:28:41 PM PDT 24
Peak memory 203976 kb
Host smart-ebab3a6f-633e-4fa1-8193-4d999a6819ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884701094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
2884701094
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3367987684
Short name T1052
Test name
Test status
Simulation time 247789075 ps
CPU time 4.1 seconds
Started Jul 25 06:28:44 PM PDT 24
Finished Jul 25 06:28:49 PM PDT 24
Peak memory 215540 kb
Host smart-886f5ece-aae4-4a5c-ab87-606c15b67320
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367987684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.3367987684
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3890446026
Short name T1098
Test name
Test status
Simulation time 129279451 ps
CPU time 3.82 seconds
Started Jul 25 06:28:45 PM PDT 24
Finished Jul 25 06:28:49 PM PDT 24
Peak memory 215696 kb
Host smart-55945411-c607-45f7-9462-4123c0bcc63a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890446026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
3890446026
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.798589719
Short name T1031
Test name
Test status
Simulation time 215947521 ps
CPU time 3.81 seconds
Started Jul 25 06:28:46 PM PDT 24
Finished Jul 25 06:28:50 PM PDT 24
Peak memory 218820 kb
Host smart-d798b88b-2caa-41ce-9e3a-6a2febe1b114
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798589719 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.798589719
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3200001188
Short name T110
Test name
Test status
Simulation time 709144314 ps
CPU time 2.85 seconds
Started Jul 25 06:28:43 PM PDT 24
Finished Jul 25 06:28:46 PM PDT 24
Peak memory 207320 kb
Host smart-ad336256-e301-4ab0-a4e1-34887aabc8e3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200001188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
3200001188
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.938732105
Short name T1039
Test name
Test status
Simulation time 39835890 ps
CPU time 0.76 seconds
Started Jul 25 06:28:43 PM PDT 24
Finished Jul 25 06:28:44 PM PDT 24
Peak memory 203980 kb
Host smart-cd5cb0b9-d940-4de0-a532-eb57deb9fe2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938732105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.938732105
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.2577763679
Short name T132
Test name
Test status
Simulation time 145187836 ps
CPU time 1.77 seconds
Started Jul 25 06:28:45 PM PDT 24
Finished Jul 25 06:28:48 PM PDT 24
Peak memory 215556 kb
Host smart-bc6b0ae7-a16e-4ff7-8da6-4878dc5f0946
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577763679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.2577763679
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2727535881
Short name T1044
Test name
Test status
Simulation time 35850847 ps
CPU time 1.38 seconds
Started Jul 25 06:28:42 PM PDT 24
Finished Jul 25 06:28:44 PM PDT 24
Peak memory 215652 kb
Host smart-42ad5529-1d3b-43c4-874a-b4889ea7462e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727535881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
2727535881
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.4224323022
Short name T1071
Test name
Test status
Simulation time 1190974468 ps
CPU time 18.03 seconds
Started Jul 25 06:28:40 PM PDT 24
Finished Jul 25 06:28:58 PM PDT 24
Peak memory 215492 kb
Host smart-aaf82979-ccd7-401b-9637-2c931e575b1f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224323022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.4224323022
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1590504369
Short name T1028
Test name
Test status
Simulation time 127973898 ps
CPU time 3.93 seconds
Started Jul 25 06:28:51 PM PDT 24
Finished Jul 25 06:28:55 PM PDT 24
Peak memory 217696 kb
Host smart-58eb468b-9d29-4091-968f-59caa7163cd8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590504369 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.1590504369
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.4250064687
Short name T107
Test name
Test status
Simulation time 1779802264 ps
CPU time 2.9 seconds
Started Jul 25 06:28:42 PM PDT 24
Finished Jul 25 06:28:46 PM PDT 24
Peak memory 215476 kb
Host smart-5f994849-4c4f-4f9a-942f-b056ad5a69cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250064687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
4250064687
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2013831287
Short name T1113
Test name
Test status
Simulation time 11277136 ps
CPU time 0.68 seconds
Started Jul 25 06:28:44 PM PDT 24
Finished Jul 25 06:28:45 PM PDT 24
Peak memory 204312 kb
Host smart-64806e0a-685f-46fe-8716-5f4e403d7854
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013831287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
2013831287
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3115566988
Short name T1034
Test name
Test status
Simulation time 61896893 ps
CPU time 3.44 seconds
Started Jul 25 06:28:42 PM PDT 24
Finished Jul 25 06:28:46 PM PDT 24
Peak memory 215496 kb
Host smart-db60ad66-938a-46f5-ab78-fbcf962fa511
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115566988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.3115566988
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.1044958283
Short name T95
Test name
Test status
Simulation time 156083116 ps
CPU time 4.25 seconds
Started Jul 25 06:28:43 PM PDT 24
Finished Jul 25 06:28:48 PM PDT 24
Peak memory 215572 kb
Host smart-aefc2b79-8649-41e4-a524-cc5a48cd891b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044958283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
1044958283
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.3320457320
Short name T162
Test name
Test status
Simulation time 862070699 ps
CPU time 22.3 seconds
Started Jul 25 06:28:42 PM PDT 24
Finished Jul 25 06:29:04 PM PDT 24
Peak memory 215712 kb
Host smart-e168e0d2-dff9-4ff8-9f8b-4ec00eb9e249
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320457320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.3320457320
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3239287549
Short name T1088
Test name
Test status
Simulation time 190424116 ps
CPU time 1.68 seconds
Started Jul 25 06:28:51 PM PDT 24
Finished Jul 25 06:28:53 PM PDT 24
Peak memory 215556 kb
Host smart-0b8fe996-7706-417f-b888-c6f97ce2a785
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239287549 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.3239287549
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.4112430700
Short name T105
Test name
Test status
Simulation time 272713255 ps
CPU time 1.89 seconds
Started Jul 25 06:28:51 PM PDT 24
Finished Jul 25 06:28:53 PM PDT 24
Peak memory 215568 kb
Host smart-c943f6d1-a4dd-4a06-a3af-e4bc5f9e27ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112430700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
4112430700
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.3310166821
Short name T1026
Test name
Test status
Simulation time 90854151 ps
CPU time 0.77 seconds
Started Jul 25 06:28:53 PM PDT 24
Finished Jul 25 06:28:54 PM PDT 24
Peak memory 203996 kb
Host smart-7913ed56-3854-4fa0-bd5e-d55b12a293e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310166821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
3310166821
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.256499548
Short name T1027
Test name
Test status
Simulation time 65560563 ps
CPU time 4.04 seconds
Started Jul 25 06:28:55 PM PDT 24
Finished Jul 25 06:28:59 PM PDT 24
Peak memory 215560 kb
Host smart-490007bc-5bef-41b8-9c66-b6d63af9c273
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256499548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.s
pi_device_same_csr_outstanding.256499548
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.467748089
Short name T93
Test name
Test status
Simulation time 103556053 ps
CPU time 1.81 seconds
Started Jul 25 06:28:52 PM PDT 24
Finished Jul 25 06:28:54 PM PDT 24
Peak memory 215516 kb
Host smart-a2afc437-35b3-4d32-8e76-8da6d2599851
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467748089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.467748089
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1763622477
Short name T88
Test name
Test status
Simulation time 3054322424 ps
CPU time 20.11 seconds
Started Jul 25 06:28:55 PM PDT 24
Finished Jul 25 06:29:15 PM PDT 24
Peak memory 215576 kb
Host smart-3c95befe-3721-46c0-aeef-b52e92560808
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763622477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.1763622477
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.2172246938
Short name T1122
Test name
Test status
Simulation time 87647951 ps
CPU time 1.94 seconds
Started Jul 25 06:28:52 PM PDT 24
Finished Jul 25 06:28:54 PM PDT 24
Peak memory 215636 kb
Host smart-0c97905e-a27c-417a-8992-76f57145f408
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172246938 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.2172246938
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2385288539
Short name T111
Test name
Test status
Simulation time 195149453 ps
CPU time 1.33 seconds
Started Jul 25 06:28:52 PM PDT 24
Finished Jul 25 06:28:53 PM PDT 24
Peak memory 207036 kb
Host smart-6e248253-4480-4f07-9440-726333579b70
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385288539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
2385288539
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3668099819
Short name T1029
Test name
Test status
Simulation time 13182201 ps
CPU time 0.74 seconds
Started Jul 25 06:28:52 PM PDT 24
Finished Jul 25 06:28:53 PM PDT 24
Peak memory 203988 kb
Host smart-1089c7a4-4d37-4ab4-918c-3842f050a613
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668099819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
3668099819
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3371860492
Short name T1058
Test name
Test status
Simulation time 573066644 ps
CPU time 3.97 seconds
Started Jul 25 06:28:52 PM PDT 24
Finished Jul 25 06:28:56 PM PDT 24
Peak memory 215460 kb
Host smart-75112b80-cfc7-47f5-96f0-476540a94369
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371860492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.3371860492
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.470324721
Short name T1076
Test name
Test status
Simulation time 51084623 ps
CPU time 1.65 seconds
Started Jul 25 06:28:50 PM PDT 24
Finished Jul 25 06:28:52 PM PDT 24
Peak memory 215700 kb
Host smart-13bdcfde-c6d7-49d5-b3dd-fb6bb4abd22c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470324721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.470324721
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.2484292421
Short name T102
Test name
Test status
Simulation time 205263541 ps
CPU time 1.97 seconds
Started Jul 25 06:28:51 PM PDT 24
Finished Jul 25 06:28:53 PM PDT 24
Peak memory 215556 kb
Host smart-e02203f9-f40a-411b-a3f5-d3a3b4b70001
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484292421 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.2484292421
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.2958202206
Short name T1024
Test name
Test status
Simulation time 66233975 ps
CPU time 1.99 seconds
Started Jul 25 06:28:48 PM PDT 24
Finished Jul 25 06:28:50 PM PDT 24
Peak memory 207356 kb
Host smart-2b9a0404-49a5-4895-9add-fd6f2998bdab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958202206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
2958202206
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.1574236539
Short name T1060
Test name
Test status
Simulation time 13827163 ps
CPU time 0.8 seconds
Started Jul 25 06:28:59 PM PDT 24
Finished Jul 25 06:29:00 PM PDT 24
Peak memory 203996 kb
Host smart-66f5a95e-7140-4ede-8306-ca309dc66dee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574236539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
1574236539
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.311979821
Short name T1038
Test name
Test status
Simulation time 224650687 ps
CPU time 5.03 seconds
Started Jul 25 06:28:59 PM PDT 24
Finished Jul 25 06:29:04 PM PDT 24
Peak memory 215580 kb
Host smart-bd06fec4-63cf-4bb7-bbeb-220f8a2361db
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311979821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.s
pi_device_same_csr_outstanding.311979821
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.1673077420
Short name T1101
Test name
Test status
Simulation time 139363584 ps
CPU time 3.56 seconds
Started Jul 25 06:28:54 PM PDT 24
Finished Jul 25 06:28:58 PM PDT 24
Peak memory 215572 kb
Host smart-4abba9b6-b36c-4694-b827-c7c594d4763f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673077420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
1673077420
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.391927745
Short name T61
Test name
Test status
Simulation time 553059168 ps
CPU time 13.37 seconds
Started Jul 25 06:28:51 PM PDT 24
Finished Jul 25 06:29:05 PM PDT 24
Peak memory 215592 kb
Host smart-b15dea2a-2075-44b4-9ee1-e5449d2fb1cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391927745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device
_tl_intg_err.391927745
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2539353812
Short name T1061
Test name
Test status
Simulation time 141838895 ps
CPU time 2.93 seconds
Started Jul 25 06:28:58 PM PDT 24
Finished Jul 25 06:29:01 PM PDT 24
Peak memory 217004 kb
Host smart-03454e86-926e-4770-a91d-4ea557aaf168
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539353812 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.2539353812
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.443547438
Short name T1118
Test name
Test status
Simulation time 70229871 ps
CPU time 2.28 seconds
Started Jul 25 06:28:58 PM PDT 24
Finished Jul 25 06:29:01 PM PDT 24
Peak memory 215528 kb
Host smart-7af4bad5-09f1-4c97-85b0-5dae1fb09acb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443547438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.443547438
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1160726143
Short name T1021
Test name
Test status
Simulation time 13261727 ps
CPU time 0.74 seconds
Started Jul 25 06:28:52 PM PDT 24
Finished Jul 25 06:28:53 PM PDT 24
Peak memory 203992 kb
Host smart-fbf9b468-bba8-489e-a27c-86599b1e9438
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160726143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
1160726143
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.780779545
Short name T1040
Test name
Test status
Simulation time 214928107 ps
CPU time 3.09 seconds
Started Jul 25 06:28:52 PM PDT 24
Finished Jul 25 06:28:55 PM PDT 24
Peak memory 215348 kb
Host smart-b14a00b1-9096-4f23-904f-5b26550161c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780779545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.s
pi_device_same_csr_outstanding.780779545
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1800161803
Short name T1130
Test name
Test status
Simulation time 222114884 ps
CPU time 4.7 seconds
Started Jul 25 06:28:54 PM PDT 24
Finished Jul 25 06:28:58 PM PDT 24
Peak memory 215572 kb
Host smart-a3b7083b-b712-4a33-a2b2-4ae7634b46b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800161803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
1800161803
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.346959125
Short name T163
Test name
Test status
Simulation time 628635924 ps
CPU time 14.85 seconds
Started Jul 25 06:29:02 PM PDT 24
Finished Jul 25 06:29:17 PM PDT 24
Peak memory 215580 kb
Host smart-f0827d9c-31c1-4302-9375-bb8cd8ec5f61
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346959125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device
_tl_intg_err.346959125
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3623641172
Short name T1106
Test name
Test status
Simulation time 184216155 ps
CPU time 2.82 seconds
Started Jul 25 06:28:51 PM PDT 24
Finished Jul 25 06:28:54 PM PDT 24
Peak memory 216704 kb
Host smart-a5e71a4b-4c29-4835-bef8-8ea1e7aba467
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623641172 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.3623641172
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.246050284
Short name T1080
Test name
Test status
Simulation time 29433710 ps
CPU time 2.09 seconds
Started Jul 25 06:28:58 PM PDT 24
Finished Jul 25 06:29:00 PM PDT 24
Peak memory 207228 kb
Host smart-1e7100f8-739a-4af3-b042-e21571119c0c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246050284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.246050284
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2920116806
Short name T1077
Test name
Test status
Simulation time 43635999 ps
CPU time 0.8 seconds
Started Jul 25 06:28:52 PM PDT 24
Finished Jul 25 06:28:53 PM PDT 24
Peak memory 204304 kb
Host smart-21d73a26-e18f-499c-8c8c-963a015be0cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920116806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
2920116806
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1468958167
Short name T122
Test name
Test status
Simulation time 29070860 ps
CPU time 1.79 seconds
Started Jul 25 06:28:51 PM PDT 24
Finished Jul 25 06:28:53 PM PDT 24
Peak memory 207260 kb
Host smart-d4f03587-0d0b-4919-8c9a-bb657b655831
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468958167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.1468958167
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2201919189
Short name T1078
Test name
Test status
Simulation time 322636306 ps
CPU time 3.55 seconds
Started Jul 25 06:28:53 PM PDT 24
Finished Jul 25 06:28:56 PM PDT 24
Peak memory 216620 kb
Host smart-4d8112c1-c4a7-4fdd-b199-936cf5639346
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201919189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
2201919189
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1911539002
Short name T161
Test name
Test status
Simulation time 1205229991 ps
CPU time 18.91 seconds
Started Jul 25 06:28:50 PM PDT 24
Finished Jul 25 06:29:09 PM PDT 24
Peak memory 215716 kb
Host smart-1457c3bc-3c87-46b4-8472-8e146dc41700
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911539002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.1911539002
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.1231619946
Short name T112
Test name
Test status
Simulation time 1314652434 ps
CPU time 13.71 seconds
Started Jul 25 06:28:34 PM PDT 24
Finished Jul 25 06:28:48 PM PDT 24
Peak memory 216564 kb
Host smart-4e549e9b-563e-4d06-b0bd-8160098557a6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231619946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.1231619946
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.72682420
Short name T114
Test name
Test status
Simulation time 1802680054 ps
CPU time 37.95 seconds
Started Jul 25 06:28:31 PM PDT 24
Finished Jul 25 06:29:09 PM PDT 24
Peak memory 207356 kb
Host smart-ef4475c9-bb8e-41c1-98d7-fc0304e7df24
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72682420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_
bit_bash.72682420
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2632754866
Short name T79
Test name
Test status
Simulation time 25877226 ps
CPU time 0.98 seconds
Started Jul 25 06:28:32 PM PDT 24
Finished Jul 25 06:28:33 PM PDT 24
Peak memory 207140 kb
Host smart-ef0415a8-406e-468a-9d07-48c62b4096ea
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632754866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.2632754866
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3371171614
Short name T1062
Test name
Test status
Simulation time 101215285 ps
CPU time 2.71 seconds
Started Jul 25 06:28:32 PM PDT 24
Finished Jul 25 06:28:35 PM PDT 24
Peak memory 217868 kb
Host smart-37c6828f-8083-45e3-99bc-096b0b10e6b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371171614 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.3371171614
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2039247165
Short name T104
Test name
Test status
Simulation time 58326721 ps
CPU time 1.85 seconds
Started Jul 25 06:28:33 PM PDT 24
Finished Jul 25 06:28:35 PM PDT 24
Peak memory 215576 kb
Host smart-495691bf-bb12-473c-8354-f030535731a7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039247165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.2
039247165
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.3310207552
Short name T1048
Test name
Test status
Simulation time 153006602 ps
CPU time 0.75 seconds
Started Jul 25 06:28:31 PM PDT 24
Finished Jul 25 06:28:32 PM PDT 24
Peak memory 203992 kb
Host smart-b0b9293d-c5ec-4aca-be13-92d1b0e8b041
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310207552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.3
310207552
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.1679659251
Short name T1112
Test name
Test status
Simulation time 59501570 ps
CPU time 2.14 seconds
Started Jul 25 06:28:34 PM PDT 24
Finished Jul 25 06:28:36 PM PDT 24
Peak memory 215440 kb
Host smart-97d4987c-2670-4140-93bd-7e5650cdd58e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679659251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.1679659251
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.2856893065
Short name T1016
Test name
Test status
Simulation time 27077113 ps
CPU time 0.68 seconds
Started Jul 25 06:28:32 PM PDT 24
Finished Jul 25 06:28:33 PM PDT 24
Peak memory 203912 kb
Host smart-6483a6be-6aef-4369-8675-b67ff8473a5c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856893065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.2856893065
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3717022249
Short name T1054
Test name
Test status
Simulation time 145894774 ps
CPU time 3.15 seconds
Started Jul 25 06:28:32 PM PDT 24
Finished Jul 25 06:28:35 PM PDT 24
Peak memory 215484 kb
Host smart-b71e4257-1f8b-4be5-bb99-876dafc74c12
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717022249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.3717022249
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3943617961
Short name T89
Test name
Test status
Simulation time 297402116 ps
CPU time 3.8 seconds
Started Jul 25 06:28:32 PM PDT 24
Finished Jul 25 06:28:36 PM PDT 24
Peak memory 215628 kb
Host smart-acf39c60-7c38-4638-9e6f-e26d521dd0d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943617961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.3
943617961
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.645092825
Short name T158
Test name
Test status
Simulation time 2405946302 ps
CPU time 7.75 seconds
Started Jul 25 06:28:29 PM PDT 24
Finished Jul 25 06:28:36 PM PDT 24
Peak memory 215640 kb
Host smart-0c895e23-7c87-46a0-9de3-3c8156ce6b02
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645092825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_
tl_intg_err.645092825
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.3104339184
Short name T1023
Test name
Test status
Simulation time 36566769 ps
CPU time 0.79 seconds
Started Jul 25 06:28:50 PM PDT 24
Finished Jul 25 06:28:51 PM PDT 24
Peak memory 204000 kb
Host smart-b6eb23b6-70dc-4134-954b-a5400e409a2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104339184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
3104339184
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.615716703
Short name T1018
Test name
Test status
Simulation time 18581658 ps
CPU time 0.77 seconds
Started Jul 25 06:28:53 PM PDT 24
Finished Jul 25 06:28:54 PM PDT 24
Peak memory 203996 kb
Host smart-11396a7c-fd34-41bf-9214-aa69fd3a844a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615716703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.615716703
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.2958967292
Short name T1012
Test name
Test status
Simulation time 21208603 ps
CPU time 0.74 seconds
Started Jul 25 06:28:51 PM PDT 24
Finished Jul 25 06:28:52 PM PDT 24
Peak memory 203964 kb
Host smart-2d655dc3-93ca-40c2-a61c-a107160c37bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958967292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
2958967292
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.1607835706
Short name T1025
Test name
Test status
Simulation time 10850051 ps
CPU time 0.71 seconds
Started Jul 25 06:29:00 PM PDT 24
Finished Jul 25 06:29:01 PM PDT 24
Peak memory 203956 kb
Host smart-1a0ea308-19be-4788-b178-57114118cf1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607835706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
1607835706
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.800169368
Short name T1090
Test name
Test status
Simulation time 45615870 ps
CPU time 0.73 seconds
Started Jul 25 06:29:02 PM PDT 24
Finished Jul 25 06:29:03 PM PDT 24
Peak memory 204008 kb
Host smart-97a95391-0368-4838-a1f1-5d1af0446df8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800169368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.800169368
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.2328956600
Short name T1066
Test name
Test status
Simulation time 26759825 ps
CPU time 0.75 seconds
Started Jul 25 06:28:59 PM PDT 24
Finished Jul 25 06:29:00 PM PDT 24
Peak memory 203992 kb
Host smart-005a7631-9774-48a4-9dab-a731411259de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328956600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
2328956600
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.3391090123
Short name T1013
Test name
Test status
Simulation time 19601511 ps
CPU time 0.78 seconds
Started Jul 25 06:29:01 PM PDT 24
Finished Jul 25 06:29:02 PM PDT 24
Peak memory 204012 kb
Host smart-1a41bbca-9104-48cd-9603-b49df3f99c3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391090123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
3391090123
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.2268518812
Short name T1083
Test name
Test status
Simulation time 36137553 ps
CPU time 0.74 seconds
Started Jul 25 06:29:02 PM PDT 24
Finished Jul 25 06:29:03 PM PDT 24
Peak memory 204312 kb
Host smart-1d9693b1-ce24-4e9d-ad71-af8b9889e885
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268518812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
2268518812
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.1856725116
Short name T1087
Test name
Test status
Simulation time 23173585 ps
CPU time 0.73 seconds
Started Jul 25 06:29:02 PM PDT 24
Finished Jul 25 06:29:03 PM PDT 24
Peak memory 204320 kb
Host smart-7b2de34b-231f-4362-a4b2-3d2e14836afa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856725116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
1856725116
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.3493246862
Short name T1120
Test name
Test status
Simulation time 14889663 ps
CPU time 0.76 seconds
Started Jul 25 06:29:00 PM PDT 24
Finished Jul 25 06:29:00 PM PDT 24
Peak memory 204036 kb
Host smart-3be4dce3-9f67-4e00-896c-193d24a44a55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493246862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
3493246862
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.124402281
Short name T106
Test name
Test status
Simulation time 2245740791 ps
CPU time 15.71 seconds
Started Jul 25 06:28:32 PM PDT 24
Finished Jul 25 06:28:48 PM PDT 24
Peak memory 207348 kb
Host smart-de881e02-45d0-4578-8554-a0a6c0413402
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124402281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_aliasing.124402281
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.724474469
Short name T1045
Test name
Test status
Simulation time 749491044 ps
CPU time 12.77 seconds
Started Jul 25 06:28:40 PM PDT 24
Finished Jul 25 06:28:52 PM PDT 24
Peak memory 207264 kb
Host smart-7729b92d-f52c-455d-987f-c3aee3d08370
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724474469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_bit_bash.724474469
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1807817896
Short name T78
Test name
Test status
Simulation time 65828570 ps
CPU time 1.16 seconds
Started Jul 25 06:28:38 PM PDT 24
Finished Jul 25 06:28:40 PM PDT 24
Peak memory 215456 kb
Host smart-24ef888d-2b4a-452d-925e-9d875cd9ff5f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807817896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.1807817896
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2433684277
Short name T1123
Test name
Test status
Simulation time 84736349 ps
CPU time 2.47 seconds
Started Jul 25 06:28:38 PM PDT 24
Finished Jul 25 06:28:41 PM PDT 24
Peak memory 216808 kb
Host smart-17169a9b-c8f3-4bc7-b590-1d3332bfb784
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433684277 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.2433684277
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.4234088087
Short name T1116
Test name
Test status
Simulation time 213701212 ps
CPU time 2.55 seconds
Started Jul 25 06:28:35 PM PDT 24
Finished Jul 25 06:28:38 PM PDT 24
Peak memory 207268 kb
Host smart-3aa877cc-1c27-44ba-bebb-f6ec698a4e83
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234088087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.4
234088087
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.807464986
Short name T1064
Test name
Test status
Simulation time 17736908 ps
CPU time 0.75 seconds
Started Jul 25 06:28:39 PM PDT 24
Finished Jul 25 06:28:40 PM PDT 24
Peak memory 203952 kb
Host smart-a7740632-d9fa-4258-952c-f61925c3190b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807464986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.807464986
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2618888581
Short name T1110
Test name
Test status
Simulation time 16972820 ps
CPU time 1.2 seconds
Started Jul 25 06:28:40 PM PDT 24
Finished Jul 25 06:28:41 PM PDT 24
Peak memory 215420 kb
Host smart-54f3a05b-3ebc-4ac0-8cd3-e5cf72d4df48
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618888581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.2618888581
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.3057859282
Short name T1103
Test name
Test status
Simulation time 35131414 ps
CPU time 0.69 seconds
Started Jul 25 06:28:29 PM PDT 24
Finished Jul 25 06:28:30 PM PDT 24
Peak memory 204240 kb
Host smart-ee6882fc-51ac-4d94-860b-e7440c850c43
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057859282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.3057859282
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2823453557
Short name T1093
Test name
Test status
Simulation time 91645270 ps
CPU time 2.06 seconds
Started Jul 25 06:28:40 PM PDT 24
Finished Jul 25 06:28:42 PM PDT 24
Peak memory 215552 kb
Host smart-bb4d29a7-5a42-4eb4-80bb-e1acfd9d7eaa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823453557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.2823453557
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.4196482507
Short name T1091
Test name
Test status
Simulation time 3683746276 ps
CPU time 20.29 seconds
Started Jul 25 06:28:39 PM PDT 24
Finished Jul 25 06:29:00 PM PDT 24
Peak memory 216532 kb
Host smart-bce8c43b-cc73-483b-abd9-bb082e7553d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196482507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.4196482507
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2201705073
Short name T1059
Test name
Test status
Simulation time 43527004 ps
CPU time 0.71 seconds
Started Jul 25 06:29:01 PM PDT 24
Finished Jul 25 06:29:02 PM PDT 24
Peak memory 203972 kb
Host smart-c9c3d41e-e276-4072-8990-4e418e1977ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201705073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
2201705073
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.3758911969
Short name T1082
Test name
Test status
Simulation time 34332196 ps
CPU time 0.76 seconds
Started Jul 25 06:28:59 PM PDT 24
Finished Jul 25 06:29:00 PM PDT 24
Peak memory 204304 kb
Host smart-1bb68add-d087-4bd0-b776-fb580f296c0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758911969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
3758911969
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.2476455439
Short name T1105
Test name
Test status
Simulation time 12711603 ps
CPU time 0.79 seconds
Started Jul 25 06:29:01 PM PDT 24
Finished Jul 25 06:29:02 PM PDT 24
Peak memory 204308 kb
Host smart-62a4030f-0e0f-4b09-9412-71b1304325a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476455439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
2476455439
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.1699611202
Short name T1089
Test name
Test status
Simulation time 17470906 ps
CPU time 0.7 seconds
Started Jul 25 06:29:00 PM PDT 24
Finished Jul 25 06:29:01 PM PDT 24
Peak memory 203992 kb
Host smart-88dc0586-3a88-4a8d-97d8-d36045f430fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699611202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
1699611202
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1277303416
Short name T1100
Test name
Test status
Simulation time 55758231 ps
CPU time 0.75 seconds
Started Jul 25 06:28:57 PM PDT 24
Finished Jul 25 06:28:58 PM PDT 24
Peak memory 204004 kb
Host smart-9aaa9671-cb66-461a-aae9-1228e1c73ceb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277303416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
1277303416
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.4060344954
Short name T1114
Test name
Test status
Simulation time 45580522 ps
CPU time 0.72 seconds
Started Jul 25 06:29:03 PM PDT 24
Finished Jul 25 06:29:04 PM PDT 24
Peak memory 204004 kb
Host smart-4df291cb-c193-47cb-b656-620298410d4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060344954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
4060344954
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.2018271355
Short name T1041
Test name
Test status
Simulation time 45814335 ps
CPU time 0.82 seconds
Started Jul 25 06:29:02 PM PDT 24
Finished Jul 25 06:29:03 PM PDT 24
Peak memory 204300 kb
Host smart-889defa3-236a-49b1-a6c4-1704ace1ac26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018271355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
2018271355
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.2469165216
Short name T1010
Test name
Test status
Simulation time 48947701 ps
CPU time 0.73 seconds
Started Jul 25 06:29:01 PM PDT 24
Finished Jul 25 06:29:02 PM PDT 24
Peak memory 203972 kb
Host smart-8112ec9b-cd72-481b-b367-630a7174b797
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469165216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
2469165216
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.4015239343
Short name T1068
Test name
Test status
Simulation time 35747378 ps
CPU time 0.7 seconds
Started Jul 25 06:29:04 PM PDT 24
Finished Jul 25 06:29:05 PM PDT 24
Peak memory 204324 kb
Host smart-1fcf015c-76d8-4f85-8e2b-b1478b6767c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015239343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
4015239343
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1029287380
Short name T1094
Test name
Test status
Simulation time 13718159 ps
CPU time 0.73 seconds
Started Jul 25 06:28:59 PM PDT 24
Finished Jul 25 06:29:00 PM PDT 24
Peak memory 203992 kb
Host smart-fad213f2-6607-4227-8a6f-1069fefaa2a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029287380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
1029287380
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.2387085706
Short name T1075
Test name
Test status
Simulation time 3598137299 ps
CPU time 23.84 seconds
Started Jul 25 06:28:43 PM PDT 24
Finished Jul 25 06:29:07 PM PDT 24
Peak memory 215564 kb
Host smart-1510d5d2-5709-4d58-8854-c9153dcce9b5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387085706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.2387085706
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.1797650397
Short name T1035
Test name
Test status
Simulation time 4528837597 ps
CPU time 36.67 seconds
Started Jul 25 06:28:45 PM PDT 24
Finished Jul 25 06:29:22 PM PDT 24
Peak memory 207348 kb
Host smart-24975466-038a-4e26-8b9d-446a2d5086dc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797650397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.1797650397
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.1698853722
Short name T108
Test name
Test status
Simulation time 72287757 ps
CPU time 0.97 seconds
Started Jul 25 06:28:40 PM PDT 24
Finished Jul 25 06:28:41 PM PDT 24
Peak memory 207136 kb
Host smart-e121d835-1894-443a-b730-41b7a3465476
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698853722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.1698853722
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.2202553656
Short name T60
Test name
Test status
Simulation time 251866917 ps
CPU time 1.72 seconds
Started Jul 25 06:28:42 PM PDT 24
Finished Jul 25 06:28:44 PM PDT 24
Peak memory 216524 kb
Host smart-288c2f84-f3a2-495a-9a45-98a578ceb622
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202553656 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.2202553656
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1963445415
Short name T1072
Test name
Test status
Simulation time 154014544 ps
CPU time 2.4 seconds
Started Jul 25 06:28:45 PM PDT 24
Finished Jul 25 06:28:48 PM PDT 24
Peak memory 215556 kb
Host smart-bd44848a-bae6-4437-9c9a-e5d5deb04562
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963445415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.1
963445415
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.603206434
Short name T1115
Test name
Test status
Simulation time 54564673 ps
CPU time 0.73 seconds
Started Jul 25 06:28:47 PM PDT 24
Finished Jul 25 06:28:48 PM PDT 24
Peak memory 204116 kb
Host smart-2090f75c-e510-4321-b963-2b349019b21c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603206434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.603206434
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1512273151
Short name T1047
Test name
Test status
Simulation time 26752936 ps
CPU time 1.83 seconds
Started Jul 25 06:28:42 PM PDT 24
Finished Jul 25 06:28:44 PM PDT 24
Peak memory 215508 kb
Host smart-b81bcb6d-6e50-4e4c-93fa-57a9a3cd26bc
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512273151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.1512273151
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1288096991
Short name T1036
Test name
Test status
Simulation time 23172516 ps
CPU time 0.7 seconds
Started Jul 25 06:28:40 PM PDT 24
Finished Jul 25 06:28:40 PM PDT 24
Peak memory 203904 kb
Host smart-6f88b437-d94e-4c05-a277-db960bb1f091
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288096991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.1288096991
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2627313514
Short name T1032
Test name
Test status
Simulation time 298119107 ps
CPU time 1.79 seconds
Started Jul 25 06:28:47 PM PDT 24
Finished Jul 25 06:28:49 PM PDT 24
Peak memory 215320 kb
Host smart-e571a5ac-ba3e-4bb2-aebb-05349821ad3a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627313514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.2627313514
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.3342063275
Short name T1104
Test name
Test status
Simulation time 89421205 ps
CPU time 2.01 seconds
Started Jul 25 06:28:32 PM PDT 24
Finished Jul 25 06:28:34 PM PDT 24
Peak memory 215580 kb
Host smart-461e3add-8953-41bf-b6fe-b51cdcc3c097
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342063275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.3
342063275
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.540222946
Short name T135
Test name
Test status
Simulation time 2824771565 ps
CPU time 14.99 seconds
Started Jul 25 06:28:31 PM PDT 24
Finished Jul 25 06:28:46 PM PDT 24
Peak memory 217120 kb
Host smart-77e881d7-dc2b-4385-a0c6-19cc3c0b2b64
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540222946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_
tl_intg_err.540222946
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.322263195
Short name T1069
Test name
Test status
Simulation time 12838169 ps
CPU time 0.72 seconds
Started Jul 25 06:28:59 PM PDT 24
Finished Jul 25 06:29:00 PM PDT 24
Peak memory 203980 kb
Host smart-599fbf67-5995-420d-82bb-536e1bec795f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322263195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.322263195
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.3191757270
Short name T1085
Test name
Test status
Simulation time 32302239 ps
CPU time 0.71 seconds
Started Jul 25 06:29:02 PM PDT 24
Finished Jul 25 06:29:03 PM PDT 24
Peak memory 204000 kb
Host smart-9a2cb3dc-774f-4577-ad6e-cc09682aa18b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191757270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
3191757270
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.2251478577
Short name T1049
Test name
Test status
Simulation time 38690556 ps
CPU time 0.74 seconds
Started Jul 25 06:29:01 PM PDT 24
Finished Jul 25 06:29:02 PM PDT 24
Peak memory 203972 kb
Host smart-1803d3bd-b1b9-4872-a40c-6e2da3eff860
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251478577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
2251478577
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2620364015
Short name T1009
Test name
Test status
Simulation time 42025963 ps
CPU time 0.72 seconds
Started Jul 25 06:29:04 PM PDT 24
Finished Jul 25 06:29:05 PM PDT 24
Peak memory 204012 kb
Host smart-ce1b97fa-a13c-4aed-aaf1-8873ea5f3a7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620364015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
2620364015
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.813925445
Short name T1079
Test name
Test status
Simulation time 38740394 ps
CPU time 0.71 seconds
Started Jul 25 06:29:02 PM PDT 24
Finished Jul 25 06:29:03 PM PDT 24
Peak memory 204280 kb
Host smart-4acbd8fd-4e11-4718-9367-09f381840ac8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813925445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.813925445
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3668590377
Short name T1043
Test name
Test status
Simulation time 15328517 ps
CPU time 0.75 seconds
Started Jul 25 06:29:01 PM PDT 24
Finished Jul 25 06:29:02 PM PDT 24
Peak memory 204296 kb
Host smart-7fccdaf6-2459-4f04-8141-05db993d7485
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668590377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
3668590377
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.385734960
Short name T1129
Test name
Test status
Simulation time 62227496 ps
CPU time 0.74 seconds
Started Jul 25 06:29:02 PM PDT 24
Finished Jul 25 06:29:03 PM PDT 24
Peak memory 204348 kb
Host smart-545c4f73-2fbf-4111-9828-8042a82e0e8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385734960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.385734960
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.3689688984
Short name T1019
Test name
Test status
Simulation time 11976224 ps
CPU time 0.74 seconds
Started Jul 25 06:29:01 PM PDT 24
Finished Jul 25 06:29:02 PM PDT 24
Peak memory 204344 kb
Host smart-b32810b4-ad54-4f75-b890-ce91a4ddf093
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689688984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
3689688984
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.3830049478
Short name T1017
Test name
Test status
Simulation time 17250464 ps
CPU time 0.75 seconds
Started Jul 25 06:28:59 PM PDT 24
Finished Jul 25 06:29:00 PM PDT 24
Peak memory 204292 kb
Host smart-6e0727e3-8e61-44dc-86b2-cdf94951281a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830049478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
3830049478
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.241450250
Short name T1117
Test name
Test status
Simulation time 40463112 ps
CPU time 0.7 seconds
Started Jul 25 06:29:02 PM PDT 24
Finished Jul 25 06:29:03 PM PDT 24
Peak memory 203972 kb
Host smart-a680d385-5905-4184-80f4-279cdbbeaf37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241450250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.241450250
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.2885983628
Short name T1111
Test name
Test status
Simulation time 273241084 ps
CPU time 1.6 seconds
Started Jul 25 06:28:47 PM PDT 24
Finished Jul 25 06:28:49 PM PDT 24
Peak memory 215496 kb
Host smart-69434c6c-8460-43d4-9b2c-1c03f26a4018
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885983628 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.2885983628
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.1718018276
Short name T1070
Test name
Test status
Simulation time 472710831 ps
CPU time 2.89 seconds
Started Jul 25 06:28:42 PM PDT 24
Finished Jul 25 06:28:45 PM PDT 24
Peak memory 215460 kb
Host smart-9b097244-0e8f-42a7-b219-3bc034eb38da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718018276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.1
718018276
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.4086820943
Short name T1126
Test name
Test status
Simulation time 30580009 ps
CPU time 0.75 seconds
Started Jul 25 06:28:42 PM PDT 24
Finished Jul 25 06:28:43 PM PDT 24
Peak memory 204004 kb
Host smart-33c719a2-2692-415a-84aa-198c4c248ca1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086820943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.4
086820943
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.296566268
Short name T1014
Test name
Test status
Simulation time 740791667 ps
CPU time 3.78 seconds
Started Jul 25 06:28:43 PM PDT 24
Finished Jul 25 06:28:47 PM PDT 24
Peak memory 215448 kb
Host smart-101e7133-9a14-4fc2-a6cf-e72d6804b851
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296566268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sp
i_device_same_csr_outstanding.296566268
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.3256286260
Short name T94
Test name
Test status
Simulation time 74120772 ps
CPU time 2.38 seconds
Started Jul 25 06:28:47 PM PDT 24
Finished Jul 25 06:28:50 PM PDT 24
Peak memory 215720 kb
Host smart-6f2e348e-5233-4b6f-a08d-49a41a679947
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256286260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.3
256286260
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.583412276
Short name T103
Test name
Test status
Simulation time 1482831573 ps
CPU time 8.64 seconds
Started Jul 25 06:28:40 PM PDT 24
Finished Jul 25 06:28:49 PM PDT 24
Peak memory 215844 kb
Host smart-6b4c6628-17d6-462a-b9e4-34f8a806cf69
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583412276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_
tl_intg_err.583412276
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3768775771
Short name T1108
Test name
Test status
Simulation time 224264536 ps
CPU time 4.11 seconds
Started Jul 25 06:28:39 PM PDT 24
Finished Jul 25 06:28:44 PM PDT 24
Peak memory 217604 kb
Host smart-5ba7146b-6e56-425d-99ed-d25156765e72
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768775771 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.3768775771
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.3391049347
Short name T1097
Test name
Test status
Simulation time 400585849 ps
CPU time 2.53 seconds
Started Jul 25 06:28:42 PM PDT 24
Finished Jul 25 06:28:45 PM PDT 24
Peak memory 215548 kb
Host smart-8fd8dcf0-224a-4ee9-a30f-40891386f4aa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391049347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.3
391049347
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2056811728
Short name T1084
Test name
Test status
Simulation time 37232040 ps
CPU time 0.74 seconds
Started Jul 25 06:28:44 PM PDT 24
Finished Jul 25 06:28:45 PM PDT 24
Peak memory 203996 kb
Host smart-481ec9a6-303c-4796-981d-390b52b49263
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056811728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.2
056811728
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3144505107
Short name T1124
Test name
Test status
Simulation time 170684866 ps
CPU time 2.97 seconds
Started Jul 25 06:28:42 PM PDT 24
Finished Jul 25 06:28:45 PM PDT 24
Peak memory 215504 kb
Host smart-f844da35-2642-421d-81ee-6bd2c3d033ab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144505107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.3144505107
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.3706667242
Short name T157
Test name
Test status
Simulation time 187079713 ps
CPU time 3.48 seconds
Started Jul 25 06:28:42 PM PDT 24
Finished Jul 25 06:28:46 PM PDT 24
Peak memory 216612 kb
Host smart-890afac7-9a2a-490d-9f3d-00d04a21831c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706667242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.3
706667242
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3766355950
Short name T1128
Test name
Test status
Simulation time 172575543 ps
CPU time 2.59 seconds
Started Jul 25 06:28:41 PM PDT 24
Finished Jul 25 06:28:44 PM PDT 24
Peak memory 216856 kb
Host smart-0431998b-9dda-49b8-9460-20839bddb1f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766355950 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.3766355950
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1881091314
Short name T1015
Test name
Test status
Simulation time 158721338 ps
CPU time 2.2 seconds
Started Jul 25 06:28:45 PM PDT 24
Finished Jul 25 06:28:47 PM PDT 24
Peak memory 215500 kb
Host smart-eff230d8-4e52-4c3d-87ed-fa23b0a04ccb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881091314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.1
881091314
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.3950245579
Short name T1109
Test name
Test status
Simulation time 50297484 ps
CPU time 0.73 seconds
Started Jul 25 06:28:43 PM PDT 24
Finished Jul 25 06:28:44 PM PDT 24
Peak memory 203984 kb
Host smart-76b57953-9f18-4a2c-a9d1-ce0e6a7bdde2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950245579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.3
950245579
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3541356526
Short name T1042
Test name
Test status
Simulation time 347739129 ps
CPU time 3.8 seconds
Started Jul 25 06:28:40 PM PDT 24
Finished Jul 25 06:28:44 PM PDT 24
Peak memory 215540 kb
Host smart-3921e923-af0e-48b8-8027-8f29f903941a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541356526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.3541356526
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.3864629780
Short name T1095
Test name
Test status
Simulation time 67714928 ps
CPU time 4.51 seconds
Started Jul 25 06:28:42 PM PDT 24
Finished Jul 25 06:28:47 PM PDT 24
Peak memory 215600 kb
Host smart-a66c0b45-aa39-4e6e-b850-e7192cc7f963
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864629780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.3
864629780
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.3762816795
Short name T134
Test name
Test status
Simulation time 981733814 ps
CPU time 22.09 seconds
Started Jul 25 06:28:47 PM PDT 24
Finished Jul 25 06:29:10 PM PDT 24
Peak memory 215484 kb
Host smart-7331be50-4189-4dd3-ae26-b651601665a0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762816795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.3762816795
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3495062915
Short name T87
Test name
Test status
Simulation time 100965239 ps
CPU time 3.91 seconds
Started Jul 25 06:28:44 PM PDT 24
Finished Jul 25 06:28:48 PM PDT 24
Peak memory 217712 kb
Host smart-ff54f629-9a14-4a85-8032-be5e7e424848
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495062915 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.3495062915
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.2365143714
Short name T117
Test name
Test status
Simulation time 61824252 ps
CPU time 2.37 seconds
Started Jul 25 06:28:42 PM PDT 24
Finished Jul 25 06:28:44 PM PDT 24
Peak memory 215536 kb
Host smart-60687a5e-3cd8-4231-b6ae-e1d53ac7e0cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365143714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.2
365143714
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.852379912
Short name T1074
Test name
Test status
Simulation time 15826480 ps
CPU time 0.77 seconds
Started Jul 25 06:28:40 PM PDT 24
Finished Jul 25 06:28:41 PM PDT 24
Peak memory 203936 kb
Host smart-71e4c5e3-0444-42ed-b822-e2ce420f281e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852379912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.852379912
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.58047642
Short name T1033
Test name
Test status
Simulation time 426759772 ps
CPU time 2.81 seconds
Started Jul 25 06:28:41 PM PDT 24
Finished Jul 25 06:28:44 PM PDT 24
Peak memory 215520 kb
Host smart-80e89630-784a-450f-8e73-622f3d3bd642
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58047642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi
_device_same_csr_outstanding.58047642
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.976542104
Short name T1086
Test name
Test status
Simulation time 886344359 ps
CPU time 3.7 seconds
Started Jul 25 06:28:40 PM PDT 24
Finished Jul 25 06:28:44 PM PDT 24
Peak memory 215620 kb
Host smart-8ea4c084-7bcf-4190-9135-686a2843b664
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976542104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.976542104
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.4217107819
Short name T1050
Test name
Test status
Simulation time 1462068035 ps
CPU time 7.97 seconds
Started Jul 25 06:28:42 PM PDT 24
Finished Jul 25 06:28:51 PM PDT 24
Peak memory 215712 kb
Host smart-90dc8c75-f501-4a02-bfdd-ae501e855a47
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217107819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.4217107819
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.4269192713
Short name T1055
Test name
Test status
Simulation time 120394803 ps
CPU time 3.6 seconds
Started Jul 25 06:28:40 PM PDT 24
Finished Jul 25 06:28:44 PM PDT 24
Peak memory 217072 kb
Host smart-fd56f9bc-625b-47b6-960a-205f28b82e40
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269192713 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.4269192713
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.1499913367
Short name T1037
Test name
Test status
Simulation time 72943045 ps
CPU time 2.13 seconds
Started Jul 25 06:28:44 PM PDT 24
Finished Jul 25 06:28:47 PM PDT 24
Peak memory 215488 kb
Host smart-d5332652-81ab-4324-8747-35c42825a688
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499913367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.1
499913367
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3470972439
Short name T1092
Test name
Test status
Simulation time 85542631 ps
CPU time 0.74 seconds
Started Jul 25 06:28:45 PM PDT 24
Finished Jul 25 06:28:46 PM PDT 24
Peak memory 204004 kb
Host smart-bb783bdd-c58c-40ff-b7c2-10ebc6a1d9b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470972439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.3
470972439
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.54766697
Short name T1063
Test name
Test status
Simulation time 151293702 ps
CPU time 3.9 seconds
Started Jul 25 06:28:41 PM PDT 24
Finished Jul 25 06:28:45 PM PDT 24
Peak memory 215580 kb
Host smart-f0357b7d-71c6-43e9-9bc7-2bebd4fcd3ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54766697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi
_device_same_csr_outstanding.54766697
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.76619300
Short name T97
Test name
Test status
Simulation time 189160378 ps
CPU time 1.91 seconds
Started Jul 25 06:28:42 PM PDT 24
Finished Jul 25 06:28:45 PM PDT 24
Peak memory 215624 kb
Host smart-eedc6d52-dd4e-4061-9adf-e71f0a874701
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76619300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.76619300
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2258243424
Short name T159
Test name
Test status
Simulation time 324112591 ps
CPU time 12.81 seconds
Started Jul 25 06:28:42 PM PDT 24
Finished Jul 25 06:28:55 PM PDT 24
Peak memory 215568 kb
Host smart-98e5f2b0-6ec5-47d4-b2c0-55737880182a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258243424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.2258243424
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.2072503028
Short name T540
Test name
Test status
Simulation time 81793952 ps
CPU time 0.73 seconds
Started Jul 25 06:36:29 PM PDT 24
Finished Jul 25 06:36:30 PM PDT 24
Peak memory 205644 kb
Host smart-7dfc68cf-d645-4c1b-a726-25045fe54f1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072503028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.2
072503028
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.436859048
Short name T333
Test name
Test status
Simulation time 744980771 ps
CPU time 3.38 seconds
Started Jul 25 06:36:20 PM PDT 24
Finished Jul 25 06:36:23 PM PDT 24
Peak memory 232900 kb
Host smart-100b464b-23b2-4bcd-9af3-afdf3a3ab23b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436859048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.436859048
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.935931892
Short name T309
Test name
Test status
Simulation time 74773951 ps
CPU time 0.79 seconds
Started Jul 25 06:36:28 PM PDT 24
Finished Jul 25 06:36:29 PM PDT 24
Peak memory 206696 kb
Host smart-89319e5c-3ec5-44b0-a425-6b979be92e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935931892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.935931892
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.11709944
Short name T235
Test name
Test status
Simulation time 223360482720 ps
CPU time 70.9 seconds
Started Jul 25 06:36:20 PM PDT 24
Finished Jul 25 06:37:31 PM PDT 24
Peak memory 224744 kb
Host smart-9fdcaf2c-922f-4f55-aff3-13a6b702be66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11709944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.11709944
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.379696188
Short name T423
Test name
Test status
Simulation time 12778165283 ps
CPU time 62.46 seconds
Started Jul 25 06:36:16 PM PDT 24
Finished Jul 25 06:37:19 PM PDT 24
Peak memory 249444 kb
Host smart-1b035889-85c2-461a-af47-394efc0ede89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379696188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.379696188
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.3262635352
Short name T2
Test name
Test status
Simulation time 9467691655 ps
CPU time 45.35 seconds
Started Jul 25 06:36:29 PM PDT 24
Finished Jul 25 06:37:14 PM PDT 24
Peak memory 217952 kb
Host smart-58097fd1-36cb-424e-87b1-dd239586c386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262635352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.3262635352
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.2708079779
Short name T509
Test name
Test status
Simulation time 359051347 ps
CPU time 4.04 seconds
Started Jul 25 06:36:28 PM PDT 24
Finished Jul 25 06:36:32 PM PDT 24
Peak memory 231464 kb
Host smart-2ac43ab8-2c3a-4638-bc80-918318070ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708079779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.2708079779
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.2081678977
Short name T202
Test name
Test status
Simulation time 168510649936 ps
CPU time 274.02 seconds
Started Jul 25 06:36:20 PM PDT 24
Finished Jul 25 06:40:54 PM PDT 24
Peak memory 256796 kb
Host smart-63701069-265d-4991-abab-ae963e196a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081678977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds
.2081678977
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.3678526644
Short name T664
Test name
Test status
Simulation time 868825900 ps
CPU time 6.47 seconds
Started Jul 25 06:36:20 PM PDT 24
Finished Jul 25 06:36:27 PM PDT 24
Peak memory 232932 kb
Host smart-69b00d47-2867-42fb-afb3-acf077d365ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678526644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.3678526644
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.1049515205
Short name T245
Test name
Test status
Simulation time 2546093357 ps
CPU time 6.21 seconds
Started Jul 25 06:36:26 PM PDT 24
Finished Jul 25 06:36:32 PM PDT 24
Peak memory 232876 kb
Host smart-a95f4aec-a443-4605-b890-80d1d0d622f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049515205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.1049515205
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.2541003276
Short name T876
Test name
Test status
Simulation time 3067796813 ps
CPU time 5.76 seconds
Started Jul 25 06:36:21 PM PDT 24
Finished Jul 25 06:36:27 PM PDT 24
Peak memory 224716 kb
Host smart-b0b56625-51ae-4ef9-a4f9-cb2543f02195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541003276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.2541003276
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.1490018605
Short name T526
Test name
Test status
Simulation time 259748504 ps
CPU time 4.01 seconds
Started Jul 25 06:36:21 PM PDT 24
Finished Jul 25 06:36:26 PM PDT 24
Peak memory 223324 kb
Host smart-0e2ceddc-bea8-4213-ae2f-8badff98d3ea
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1490018605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.1490018605
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.2681030779
Short name T119
Test name
Test status
Simulation time 177999518724 ps
CPU time 458.23 seconds
Started Jul 25 06:36:31 PM PDT 24
Finished Jul 25 06:44:10 PM PDT 24
Peak memory 282756 kb
Host smart-9843bbba-dc2d-4b92-bdf0-9b077cbc192e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681030779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.2681030779
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.3920743959
Short name T607
Test name
Test status
Simulation time 2455604079 ps
CPU time 27.43 seconds
Started Jul 25 06:36:19 PM PDT 24
Finished Jul 25 06:36:47 PM PDT 24
Peak memory 216420 kb
Host smart-e37c2b3a-ed62-4195-b974-5775bdaf4966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920743959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.3920743959
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.2564277642
Short name T451
Test name
Test status
Simulation time 446148365 ps
CPU time 3.03 seconds
Started Jul 25 06:36:28 PM PDT 24
Finished Jul 25 06:36:31 PM PDT 24
Peak memory 216440 kb
Host smart-590bf4d3-7328-4766-9931-9ecc5aab6079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564277642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.2564277642
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.1178379928
Short name T416
Test name
Test status
Simulation time 61013890 ps
CPU time 0.92 seconds
Started Jul 25 06:36:28 PM PDT 24
Finished Jul 25 06:36:29 PM PDT 24
Peak memory 206132 kb
Host smart-05e6723c-7b4d-4b99-ba44-2014a9f7a4b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178379928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.1178379928
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.3418635527
Short name T772
Test name
Test status
Simulation time 461503441 ps
CPU time 3.57 seconds
Started Jul 25 06:36:28 PM PDT 24
Finished Jul 25 06:36:32 PM PDT 24
Peak memory 217184 kb
Host smart-92e07351-e57e-4a71-8a25-c30457c824da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418635527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.3418635527
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.1171300000
Short name T480
Test name
Test status
Simulation time 12153883 ps
CPU time 0.75 seconds
Started Jul 25 06:36:32 PM PDT 24
Finished Jul 25 06:36:33 PM PDT 24
Peak memory 205048 kb
Host smart-5714c88f-169b-4ff8-94f6-ced70e4fa807
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171300000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.1
171300000
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.1877058704
Short name T49
Test name
Test status
Simulation time 65732127 ps
CPU time 2.32 seconds
Started Jul 25 06:36:32 PM PDT 24
Finished Jul 25 06:36:34 PM PDT 24
Peak memory 232588 kb
Host smart-17e7acf0-23cb-4131-a215-bb3e16f603a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877058704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.1877058704
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.1293499236
Short name T445
Test name
Test status
Simulation time 113663793 ps
CPU time 0.82 seconds
Started Jul 25 06:36:40 PM PDT 24
Finished Jul 25 06:36:41 PM PDT 24
Peak memory 206744 kb
Host smart-aaec0671-319e-4de9-bbbf-611a468ce8d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293499236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.1293499236
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.2749807734
Short name T241
Test name
Test status
Simulation time 19377515833 ps
CPU time 40.9 seconds
Started Jul 25 06:36:31 PM PDT 24
Finished Jul 25 06:37:13 PM PDT 24
Peak memory 239596 kb
Host smart-b0759cca-785e-4eac-9caf-a2b8f2f7d873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749807734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.2749807734
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.1488361069
Short name T535
Test name
Test status
Simulation time 8926036416 ps
CPU time 139.1 seconds
Started Jul 25 06:36:38 PM PDT 24
Finished Jul 25 06:38:57 PM PDT 24
Peak memory 255588 kb
Host smart-1354560c-f29f-453b-9aa6-d21be86cdff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488361069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.1488361069
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.1940841614
Short name T432
Test name
Test status
Simulation time 2351710306 ps
CPU time 7.58 seconds
Started Jul 25 06:36:34 PM PDT 24
Finished Jul 25 06:36:42 PM PDT 24
Peak memory 232968 kb
Host smart-b5f0b3ab-b84f-4607-a7cd-a52772317bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940841614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.1940841614
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.1567421822
Short name T617
Test name
Test status
Simulation time 1986186888 ps
CPU time 34.98 seconds
Started Jul 25 06:36:38 PM PDT 24
Finished Jul 25 06:37:13 PM PDT 24
Peak memory 249300 kb
Host smart-d8d4b549-af75-438b-839a-971211c35c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567421822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds
.1567421822
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_intercept.881771908
Short name T567
Test name
Test status
Simulation time 9469209354 ps
CPU time 16.78 seconds
Started Jul 25 06:36:34 PM PDT 24
Finished Jul 25 06:36:51 PM PDT 24
Peak memory 224708 kb
Host smart-971c0d69-4b13-4ab2-9208-756a73a8bd59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881771908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.881771908
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.3580526974
Short name T531
Test name
Test status
Simulation time 2508625158 ps
CPU time 26.57 seconds
Started Jul 25 06:36:33 PM PDT 24
Finished Jul 25 06:37:00 PM PDT 24
Peak memory 235620 kb
Host smart-b60dd520-0650-4e7c-9338-5123caa5f628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580526974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.3580526974
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.4294039169
Short name T219
Test name
Test status
Simulation time 50504155378 ps
CPU time 13.21 seconds
Started Jul 25 06:36:34 PM PDT 24
Finished Jul 25 06:36:47 PM PDT 24
Peak memory 232856 kb
Host smart-799170b2-f6ee-4e96-886d-f95ca53ce080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294039169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.4294039169
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.1680779794
Short name T852
Test name
Test status
Simulation time 9266793882 ps
CPU time 15.62 seconds
Started Jul 25 06:36:23 PM PDT 24
Finished Jul 25 06:36:39 PM PDT 24
Peak memory 224732 kb
Host smart-b0c31e24-66f6-45cb-92fb-26914fe353cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680779794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.1680779794
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.3115900477
Short name T447
Test name
Test status
Simulation time 2633873889 ps
CPU time 13.43 seconds
Started Jul 25 06:36:32 PM PDT 24
Finished Jul 25 06:36:46 PM PDT 24
Peak memory 220400 kb
Host smart-2bfda5ba-691f-40b5-8762-1745dd65ef31
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3115900477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.3115900477
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.1373654480
Short name T65
Test name
Test status
Simulation time 452955084 ps
CPU time 0.96 seconds
Started Jul 25 06:36:31 PM PDT 24
Finished Jul 25 06:36:32 PM PDT 24
Peak memory 236500 kb
Host smart-bacb2755-49a9-45d6-b776-4b9d5dd9cca1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373654480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.1373654480
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.3735283601
Short name T616
Test name
Test status
Simulation time 2104552511 ps
CPU time 17.7 seconds
Started Jul 25 06:36:40 PM PDT 24
Finished Jul 25 06:36:58 PM PDT 24
Peak memory 216836 kb
Host smart-29c50086-ab6b-4b80-bd5f-77e349c9778d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735283601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.3735283601
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.2365563158
Short name T581
Test name
Test status
Simulation time 513366832 ps
CPU time 1.01 seconds
Started Jul 25 06:36:39 PM PDT 24
Finished Jul 25 06:36:40 PM PDT 24
Peak memory 206264 kb
Host smart-f730781d-96fc-4529-a016-651296834cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365563158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.2365563158
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.3381514498
Short name T303
Test name
Test status
Simulation time 282573103 ps
CPU time 6.52 seconds
Started Jul 25 06:36:43 PM PDT 24
Finished Jul 25 06:36:49 PM PDT 24
Peak memory 216444 kb
Host smart-c1c3cbc4-30a1-4e22-bd2a-1a6834972c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381514498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.3381514498
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.3407658648
Short name T817
Test name
Test status
Simulation time 47805130 ps
CPU time 0.74 seconds
Started Jul 25 06:36:31 PM PDT 24
Finished Jul 25 06:36:31 PM PDT 24
Peak memory 206136 kb
Host smart-6d52c2f7-677e-45af-8512-9c9994a2948a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407658648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.3407658648
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.2178239937
Short name T195
Test name
Test status
Simulation time 3343648755 ps
CPU time 13.22 seconds
Started Jul 25 06:36:33 PM PDT 24
Finished Jul 25 06:36:46 PM PDT 24
Peak memory 241108 kb
Host smart-16beb515-e706-4a6c-84e5-583556f3040c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178239937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.2178239937
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.2442248459
Short name T517
Test name
Test status
Simulation time 14182376 ps
CPU time 0.72 seconds
Started Jul 25 06:36:56 PM PDT 24
Finished Jul 25 06:36:57 PM PDT 24
Peak memory 205028 kb
Host smart-259ed410-bb47-42fc-b6ff-e59ac6a9c1c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442248459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
2442248459
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.3629728485
Short name T590
Test name
Test status
Simulation time 307066490 ps
CPU time 2.8 seconds
Started Jul 25 06:36:57 PM PDT 24
Finished Jul 25 06:37:00 PM PDT 24
Peak memory 232912 kb
Host smart-7a17f3e7-ae92-4032-82ce-cbba94c9d4a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629728485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.3629728485
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.3254387264
Short name T819
Test name
Test status
Simulation time 52145657 ps
CPU time 0.73 seconds
Started Jul 25 06:36:45 PM PDT 24
Finished Jul 25 06:36:46 PM PDT 24
Peak memory 206732 kb
Host smart-b29bee26-28d6-49fc-9ee9-ceb4dd2b926b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254387264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.3254387264
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.1987333188
Short name T283
Test name
Test status
Simulation time 135620506332 ps
CPU time 267.21 seconds
Started Jul 25 06:36:58 PM PDT 24
Finished Jul 25 06:41:26 PM PDT 24
Peak memory 264820 kb
Host smart-343469bf-83aa-427e-b4c6-1c346f3e5277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987333188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.1987333188
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.1270058026
Short name T661
Test name
Test status
Simulation time 112674977250 ps
CPU time 244.19 seconds
Started Jul 25 06:37:13 PM PDT 24
Finished Jul 25 06:41:18 PM PDT 24
Peak memory 254444 kb
Host smart-8b0a0778-c5a5-4959-8eb4-b5cb2fcaf1d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270058026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.1270058026
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.2674431936
Short name T30
Test name
Test status
Simulation time 36331511857 ps
CPU time 359.78 seconds
Started Jul 25 06:36:59 PM PDT 24
Finished Jul 25 06:42:59 PM PDT 24
Peak memory 267212 kb
Host smart-2672187b-bd69-4a98-ac10-5b5355c905dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674431936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.2674431936
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.1142822403
Short name T515
Test name
Test status
Simulation time 3001417080 ps
CPU time 14.01 seconds
Started Jul 25 06:37:01 PM PDT 24
Finished Jul 25 06:37:15 PM PDT 24
Peak memory 241072 kb
Host smart-e7562c47-f102-404c-918a-e504f7c79380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142822403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.1142822403
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.1732157038
Short name T242
Test name
Test status
Simulation time 63594112125 ps
CPU time 221.33 seconds
Started Jul 25 06:36:59 PM PDT 24
Finished Jul 25 06:40:41 PM PDT 24
Peak memory 254924 kb
Host smart-86694e62-4bcb-46ae-84b5-e52c1a3f600a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732157038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmd
s.1732157038
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_intercept.2919793515
Short name T984
Test name
Test status
Simulation time 428639389 ps
CPU time 6.55 seconds
Started Jul 25 06:36:50 PM PDT 24
Finished Jul 25 06:36:57 PM PDT 24
Peak memory 232884 kb
Host smart-fee6b99c-2a85-4f0c-a8e7-b529ad61e6f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919793515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.2919793515
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.2738107127
Short name T232
Test name
Test status
Simulation time 1581698115 ps
CPU time 10.2 seconds
Started Jul 25 06:36:49 PM PDT 24
Finished Jul 25 06:37:00 PM PDT 24
Peak memory 232888 kb
Host smart-33c63f47-676c-4d30-b72a-567194945d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738107127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.2738107127
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.2376201336
Short name T968
Test name
Test status
Simulation time 91207932 ps
CPU time 2.13 seconds
Started Jul 25 06:36:55 PM PDT 24
Finished Jul 25 06:36:58 PM PDT 24
Peak memory 224292 kb
Host smart-2a8c312e-e19e-4223-99cd-8dda933393d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376201336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.2376201336
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.587417584
Short name T774
Test name
Test status
Simulation time 5400166405 ps
CPU time 14.94 seconds
Started Jul 25 06:36:47 PM PDT 24
Finished Jul 25 06:37:02 PM PDT 24
Peak memory 241044 kb
Host smart-0d05e051-0d4e-4ccc-88fe-24ed68860f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587417584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.587417584
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.2641188955
Short name T360
Test name
Test status
Simulation time 545513355 ps
CPU time 7.19 seconds
Started Jul 25 06:37:12 PM PDT 24
Finished Jul 25 06:37:19 PM PDT 24
Peak memory 219520 kb
Host smart-93bdf0b8-4383-4133-a38d-4c2d32c6f5ef
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2641188955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.2641188955
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.1763551120
Short name T429
Test name
Test status
Simulation time 22643525387 ps
CPU time 21.4 seconds
Started Jul 25 06:36:57 PM PDT 24
Finished Jul 25 06:37:19 PM PDT 24
Peak memory 220860 kb
Host smart-d322b629-bfc7-4ead-a385-007757e495ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763551120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.1763551120
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.419613102
Short name T477
Test name
Test status
Simulation time 9614160776 ps
CPU time 15.74 seconds
Started Jul 25 06:36:48 PM PDT 24
Finished Jul 25 06:37:04 PM PDT 24
Peak memory 216436 kb
Host smart-c0d6800b-12ae-4e90-87b0-7968877a525f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419613102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.419613102
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.2652085935
Short name T824
Test name
Test status
Simulation time 15715201 ps
CPU time 0.98 seconds
Started Jul 25 06:36:48 PM PDT 24
Finished Jul 25 06:36:49 PM PDT 24
Peak memory 207144 kb
Host smart-f9ae6dee-e153-428f-89b2-a820a83cc67e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652085935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.2652085935
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.2725163378
Short name T322
Test name
Test status
Simulation time 78677192 ps
CPU time 0.9 seconds
Started Jul 25 06:36:49 PM PDT 24
Finished Jul 25 06:36:50 PM PDT 24
Peak memory 207112 kb
Host smart-bc399c14-a923-4548-88af-b85f63b86bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725163378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.2725163378
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.1394964991
Short name T4
Test name
Test status
Simulation time 1219108262 ps
CPU time 5.25 seconds
Started Jul 25 06:37:02 PM PDT 24
Finished Jul 25 06:37:08 PM PDT 24
Peak memory 232880 kb
Host smart-45e582ce-2ae1-4741-bbb7-09bdc53296b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394964991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.1394964991
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.1383808824
Short name T810
Test name
Test status
Simulation time 128723952 ps
CPU time 2.8 seconds
Started Jul 25 06:37:01 PM PDT 24
Finished Jul 25 06:37:04 PM PDT 24
Peak memory 232832 kb
Host smart-52b87e56-1ce9-4fb0-8451-0ac18ab08bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383808824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.1383808824
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.2948326833
Short name T454
Test name
Test status
Simulation time 15879906 ps
CPU time 0.77 seconds
Started Jul 25 06:36:58 PM PDT 24
Finished Jul 25 06:36:59 PM PDT 24
Peak memory 206056 kb
Host smart-3192091e-9362-4f4f-970d-d41fa4731f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948326833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.2948326833
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.1412008098
Short name T912
Test name
Test status
Simulation time 13040656836 ps
CPU time 32.47 seconds
Started Jul 25 06:37:13 PM PDT 24
Finished Jul 25 06:37:45 PM PDT 24
Peak memory 224772 kb
Host smart-0609aa2c-f6f9-43b9-8d00-da714d4925c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412008098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.1412008098
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.2799784998
Short name T415
Test name
Test status
Simulation time 56596721449 ps
CPU time 259.43 seconds
Started Jul 25 06:36:58 PM PDT 24
Finished Jul 25 06:41:17 PM PDT 24
Peak memory 249392 kb
Host smart-9731f969-4b3f-480c-ac38-1f14fedb6774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799784998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.2799784998
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.2210581493
Short name T957
Test name
Test status
Simulation time 244268722 ps
CPU time 3.46 seconds
Started Jul 25 06:37:14 PM PDT 24
Finished Jul 25 06:37:18 PM PDT 24
Peak memory 232876 kb
Host smart-7c348ac5-7f68-499e-a28a-38207c49745e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210581493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.2210581493
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.1715591556
Short name T747
Test name
Test status
Simulation time 27248443992 ps
CPU time 94.32 seconds
Started Jul 25 06:37:01 PM PDT 24
Finished Jul 25 06:38:35 PM PDT 24
Peak memory 249288 kb
Host smart-7ed787c2-d25a-4116-aacc-198ae62a520d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715591556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmd
s.1715591556
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_intercept.773633939
Short name T488
Test name
Test status
Simulation time 34149463 ps
CPU time 2.57 seconds
Started Jul 25 06:37:17 PM PDT 24
Finished Jul 25 06:37:19 PM PDT 24
Peak memory 232908 kb
Host smart-224de55f-139d-4b18-9e0f-1ff5c6b09d50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773633939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.773633939
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.3902507578
Short name T248
Test name
Test status
Simulation time 13859571455 ps
CPU time 39.25 seconds
Started Jul 25 06:36:58 PM PDT 24
Finished Jul 25 06:37:38 PM PDT 24
Peak memory 239380 kb
Host smart-6f79af59-8f10-4a2e-9c45-a5149989d979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902507578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.3902507578
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.731196052
Short name T225
Test name
Test status
Simulation time 9206786795 ps
CPU time 17.38 seconds
Started Jul 25 06:36:57 PM PDT 24
Finished Jul 25 06:37:14 PM PDT 24
Peak memory 239300 kb
Host smart-b6d766bf-ea32-4b34-a9d4-9a85f09131cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731196052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.731196052
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.1241280654
Short name T427
Test name
Test status
Simulation time 3654635397 ps
CPU time 10.85 seconds
Started Jul 25 06:37:10 PM PDT 24
Finished Jul 25 06:37:22 PM PDT 24
Peak memory 221040 kb
Host smart-f16207cc-05d4-4cd7-97fb-8ebdbb844426
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1241280654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.1241280654
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.2689183194
Short name T827
Test name
Test status
Simulation time 2632769156 ps
CPU time 31.52 seconds
Started Jul 25 06:36:58 PM PDT 24
Finished Jul 25 06:37:30 PM PDT 24
Peak memory 233004 kb
Host smart-eb1cc472-7fad-4e5e-965d-742a1ce10807
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689183194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.2689183194
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.1460373808
Short name T644
Test name
Test status
Simulation time 1246518657 ps
CPU time 19.95 seconds
Started Jul 25 06:37:11 PM PDT 24
Finished Jul 25 06:37:31 PM PDT 24
Peak memory 216688 kb
Host smart-fc11e2f5-2e5b-400e-b280-b86b96fd6c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460373808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.1460373808
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.614066920
Short name T341
Test name
Test status
Simulation time 1304124390 ps
CPU time 4.17 seconds
Started Jul 25 06:37:01 PM PDT 24
Finished Jul 25 06:37:05 PM PDT 24
Peak memory 216444 kb
Host smart-f77f2dd3-1cb0-4f34-8cdf-2bc569a68f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614066920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.614066920
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.3823639764
Short name T546
Test name
Test status
Simulation time 20763397 ps
CPU time 1.34 seconds
Started Jul 25 06:36:58 PM PDT 24
Finished Jul 25 06:36:59 PM PDT 24
Peak memory 216460 kb
Host smart-8924eacb-c66c-43f6-a50a-86fa40c5906f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823639764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.3823639764
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.836095855
Short name T453
Test name
Test status
Simulation time 77396357 ps
CPU time 0.96 seconds
Started Jul 25 06:36:59 PM PDT 24
Finished Jul 25 06:37:00 PM PDT 24
Peak memory 206132 kb
Host smart-d8a60d56-94e1-488c-93ac-1f0f7306f95a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836095855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.836095855
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.2834288780
Short name T583
Test name
Test status
Simulation time 198745978 ps
CPU time 2.85 seconds
Started Jul 25 06:37:11 PM PDT 24
Finished Jul 25 06:37:14 PM PDT 24
Peak memory 232916 kb
Host smart-ac09d895-6a98-4212-8cfa-23e763f7bede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834288780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.2834288780
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.1954371427
Short name T474
Test name
Test status
Simulation time 45258601 ps
CPU time 0.74 seconds
Started Jul 25 06:37:20 PM PDT 24
Finished Jul 25 06:37:21 PM PDT 24
Peak memory 205596 kb
Host smart-28e8235d-d622-4ab1-94d7-fb97538025cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954371427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
1954371427
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.4129003797
Short name T170
Test name
Test status
Simulation time 138970931 ps
CPU time 3 seconds
Started Jul 25 06:37:03 PM PDT 24
Finished Jul 25 06:37:06 PM PDT 24
Peak memory 224696 kb
Host smart-9ef93761-6749-4fb3-b57e-7295f187d011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129003797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.4129003797
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.3594511264
Short name T1005
Test name
Test status
Simulation time 75184228 ps
CPU time 0.84 seconds
Started Jul 25 06:36:57 PM PDT 24
Finished Jul 25 06:36:58 PM PDT 24
Peak memory 206748 kb
Host smart-689886e0-35e0-46f4-9217-dce889708e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594511264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.3594511264
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.982735197
Short name T306
Test name
Test status
Simulation time 8245618744 ps
CPU time 45.01 seconds
Started Jul 25 06:37:14 PM PDT 24
Finished Jul 25 06:37:59 PM PDT 24
Peak memory 234208 kb
Host smart-1367723a-ea0b-42ea-a6da-7b3ff10fabe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982735197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.982735197
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.1043661299
Short name T601
Test name
Test status
Simulation time 166851670 ps
CPU time 3.45 seconds
Started Jul 25 06:37:04 PM PDT 24
Finished Jul 25 06:37:07 PM PDT 24
Peak memory 233932 kb
Host smart-1bee3875-c607-424d-95d6-19b93528ca84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043661299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.1043661299
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.3447284460
Short name T270
Test name
Test status
Simulation time 61793330895 ps
CPU time 113.73 seconds
Started Jul 25 06:37:04 PM PDT 24
Finished Jul 25 06:38:58 PM PDT 24
Peak memory 251664 kb
Host smart-6fcb1433-2a2f-4722-b7db-86bab304a5d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447284460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmd
s.3447284460
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_intercept.3616129139
Short name T81
Test name
Test status
Simulation time 65221097 ps
CPU time 2.74 seconds
Started Jul 25 06:37:03 PM PDT 24
Finished Jul 25 06:37:06 PM PDT 24
Peak memory 232868 kb
Host smart-3d07b739-9b98-4d0d-bbb7-c4b6536bcc12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616129139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.3616129139
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.2924302686
Short name T510
Test name
Test status
Simulation time 1111399603 ps
CPU time 8.46 seconds
Started Jul 25 06:37:15 PM PDT 24
Finished Jul 25 06:37:24 PM PDT 24
Peak memory 224700 kb
Host smart-cd2c20ed-bb59-4a85-a90d-c5deea30070e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924302686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.2924302686
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.603717849
Short name T986
Test name
Test status
Simulation time 471370636 ps
CPU time 2.59 seconds
Started Jul 25 06:37:04 PM PDT 24
Finished Jul 25 06:37:06 PM PDT 24
Peak memory 224632 kb
Host smart-e7eb2350-5beb-406b-8768-5c6a3b84d587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603717849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swap
.603717849
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.102828930
Short name T716
Test name
Test status
Simulation time 108095659 ps
CPU time 2.48 seconds
Started Jul 25 06:37:01 PM PDT 24
Finished Jul 25 06:37:03 PM PDT 24
Peak memory 232560 kb
Host smart-4bf6b872-ad08-4cfa-aa8a-2ccda484433c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102828930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.102828930
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.902252708
Short name T910
Test name
Test status
Simulation time 119722918 ps
CPU time 4.31 seconds
Started Jul 25 06:37:11 PM PDT 24
Finished Jul 25 06:37:16 PM PDT 24
Peak memory 220140 kb
Host smart-f1844b01-57e4-4a43-8d56-b5c8f8527755
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=902252708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dire
ct.902252708
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.3666073606
Short name T931
Test name
Test status
Simulation time 31905091127 ps
CPU time 364.05 seconds
Started Jul 25 06:37:16 PM PDT 24
Finished Jul 25 06:43:20 PM PDT 24
Peak memory 272972 kb
Host smart-81d00f7d-f894-4b1d-a3c2-6c2e5c643445
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666073606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.3666073606
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.1849051584
Short name T74
Test name
Test status
Simulation time 4005194414 ps
CPU time 27.81 seconds
Started Jul 25 06:37:16 PM PDT 24
Finished Jul 25 06:37:44 PM PDT 24
Peak memory 216528 kb
Host smart-1a25cfd1-dc04-4974-b269-a3e49b50f0e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849051584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.1849051584
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.3276737357
Short name T939
Test name
Test status
Simulation time 10204399103 ps
CPU time 6.5 seconds
Started Jul 25 06:37:12 PM PDT 24
Finished Jul 25 06:37:19 PM PDT 24
Peak memory 216432 kb
Host smart-133ab243-71f6-4b49-9127-448a44d95adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276737357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.3276737357
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.510395107
Short name T712
Test name
Test status
Simulation time 190028255 ps
CPU time 1.65 seconds
Started Jul 25 06:37:17 PM PDT 24
Finished Jul 25 06:37:19 PM PDT 24
Peak memory 216464 kb
Host smart-5ddfd9ec-ce70-426e-ba34-ac5d3db0e0ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510395107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.510395107
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.2578171897
Short name T421
Test name
Test status
Simulation time 69724121 ps
CPU time 0.77 seconds
Started Jul 25 06:37:17 PM PDT 24
Finished Jul 25 06:37:18 PM PDT 24
Peak memory 206152 kb
Host smart-e3182c68-b9a1-46c7-b42b-c38c92f18fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578171897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.2578171897
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.2565371694
Short name T228
Test name
Test status
Simulation time 5691941800 ps
CPU time 13.67 seconds
Started Jul 25 06:37:04 PM PDT 24
Finished Jul 25 06:37:18 PM PDT 24
Peak memory 232896 kb
Host smart-fd590f09-135a-4502-a289-43541e4dffe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565371694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.2565371694
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.2777028483
Short name T313
Test name
Test status
Simulation time 35840935 ps
CPU time 0.72 seconds
Started Jul 25 06:37:12 PM PDT 24
Finished Jul 25 06:37:13 PM PDT 24
Peak memory 205632 kb
Host smart-33d85dce-5012-478b-9961-57342cbac785
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777028483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
2777028483
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.2522447059
Short name T982
Test name
Test status
Simulation time 633229048 ps
CPU time 6.46 seconds
Started Jul 25 06:37:20 PM PDT 24
Finished Jul 25 06:37:27 PM PDT 24
Peak memory 232912 kb
Host smart-34f4cdc4-5c41-4559-84de-515ac52d714f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522447059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.2522447059
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.3565384557
Short name T633
Test name
Test status
Simulation time 39179534 ps
CPU time 0.82 seconds
Started Jul 25 06:37:04 PM PDT 24
Finished Jul 25 06:37:05 PM PDT 24
Peak memory 206728 kb
Host smart-89e0e07e-05cf-48a4-8467-fd82a9bdd9e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565384557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.3565384557
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.489137487
Short name T484
Test name
Test status
Simulation time 15949474720 ps
CPU time 118.16 seconds
Started Jul 25 06:37:16 PM PDT 24
Finished Jul 25 06:39:14 PM PDT 24
Peak memory 257252 kb
Host smart-3bd2717d-6928-46bf-88db-72f6f3ded9d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489137487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.489137487
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.1087186303
Short name T784
Test name
Test status
Simulation time 8072114061 ps
CPU time 68.5 seconds
Started Jul 25 06:37:10 PM PDT 24
Finished Jul 25 06:38:19 PM PDT 24
Peak memory 224780 kb
Host smart-c840f6a6-195e-4faf-b482-6e4e3759fa7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087186303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.1087186303
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.1297205914
Short name T521
Test name
Test status
Simulation time 81669050 ps
CPU time 3.39 seconds
Started Jul 25 06:37:19 PM PDT 24
Finished Jul 25 06:37:22 PM PDT 24
Peak memory 233748 kb
Host smart-1f327538-abb4-4c22-ba92-40007a9e83b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297205914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.1297205914
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_intercept.316353246
Short name T226
Test name
Test status
Simulation time 599228440 ps
CPU time 6.85 seconds
Started Jul 25 06:37:24 PM PDT 24
Finished Jul 25 06:37:31 PM PDT 24
Peak memory 219088 kb
Host smart-72829093-0e41-436d-b03b-ccffe1abf577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316353246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.316353246
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.1874039222
Short name T763
Test name
Test status
Simulation time 9577067349 ps
CPU time 93.02 seconds
Started Jul 25 06:37:16 PM PDT 24
Finished Jul 25 06:38:49 PM PDT 24
Peak memory 249512 kb
Host smart-22a42bda-e29c-4423-8e65-da7def9ba0b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874039222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.1874039222
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.3983092025
Short name T382
Test name
Test status
Simulation time 1120660399 ps
CPU time 2.48 seconds
Started Jul 25 06:37:23 PM PDT 24
Finished Jul 25 06:37:26 PM PDT 24
Peak memory 224600 kb
Host smart-5883a4bb-1822-4e5d-911f-8e8fdb3ca535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983092025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.3983092025
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.94893023
Short name T257
Test name
Test status
Simulation time 1272902770 ps
CPU time 4.78 seconds
Started Jul 25 06:37:03 PM PDT 24
Finished Jul 25 06:37:08 PM PDT 24
Peak memory 232868 kb
Host smart-21da7ec9-8af7-4053-99de-6adb4a802588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94893023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.94893023
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.2049393110
Short name T353
Test name
Test status
Simulation time 4604729862 ps
CPU time 7.82 seconds
Started Jul 25 06:37:25 PM PDT 24
Finished Jul 25 06:37:33 PM PDT 24
Peak memory 222940 kb
Host smart-1363c5f7-d748-41d2-8229-be25d4a1bc1c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2049393110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.2049393110
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.37051464
Short name T491
Test name
Test status
Simulation time 4189763732 ps
CPU time 90.16 seconds
Started Jul 25 06:37:18 PM PDT 24
Finished Jul 25 06:38:48 PM PDT 24
Peak memory 249444 kb
Host smart-10539599-9bbd-4ee6-858c-a90e2bff0e4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37051464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stress
_all.37051464
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.2258774356
Short name T946
Test name
Test status
Simulation time 5102991615 ps
CPU time 8.03 seconds
Started Jul 25 06:37:12 PM PDT 24
Finished Jul 25 06:37:20 PM PDT 24
Peak memory 216448 kb
Host smart-e76a4103-0c3b-429e-823e-fadfd29328f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258774356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.2258774356
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.696750846
Short name T385
Test name
Test status
Simulation time 6808883518 ps
CPU time 4.39 seconds
Started Jul 25 06:37:03 PM PDT 24
Finished Jul 25 06:37:08 PM PDT 24
Peak memory 216512 kb
Host smart-843a09a9-19ef-4c73-b6e3-24b3dba39394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696750846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.696750846
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.3175738664
Short name T938
Test name
Test status
Simulation time 105944164 ps
CPU time 1.79 seconds
Started Jul 25 06:37:14 PM PDT 24
Finished Jul 25 06:37:16 PM PDT 24
Peak memory 216456 kb
Host smart-e0408b6e-f329-4a13-9761-8216a59f6098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175738664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.3175738664
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.275601999
Short name T344
Test name
Test status
Simulation time 30045201 ps
CPU time 0.82 seconds
Started Jul 25 06:37:08 PM PDT 24
Finished Jul 25 06:37:09 PM PDT 24
Peak memory 206092 kb
Host smart-c79c628e-7c6c-4fad-aeb0-e6734be43376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275601999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.275601999
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.2487474
Short name T904
Test name
Test status
Simulation time 9277711619 ps
CPU time 10.23 seconds
Started Jul 25 06:37:15 PM PDT 24
Finished Jul 25 06:37:25 PM PDT 24
Peak memory 232872 kb
Host smart-49131572-07b7-4c2c-bb24-69ecf77d294e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.2487474
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.2317175277
Short name T870
Test name
Test status
Simulation time 22578383 ps
CPU time 0.73 seconds
Started Jul 25 06:37:15 PM PDT 24
Finished Jul 25 06:37:16 PM PDT 24
Peak memory 205044 kb
Host smart-2acf272c-8319-4fb3-b3b0-16dbd4b7fc6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317175277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
2317175277
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.3281284807
Short name T169
Test name
Test status
Simulation time 103685400 ps
CPU time 3.53 seconds
Started Jul 25 06:37:32 PM PDT 24
Finished Jul 25 06:37:36 PM PDT 24
Peak memory 224704 kb
Host smart-60bbc3e4-86f5-4fc1-a672-19282204ec7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281284807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.3281284807
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.3876864116
Short name T697
Test name
Test status
Simulation time 36993123 ps
CPU time 0.74 seconds
Started Jul 25 06:37:25 PM PDT 24
Finished Jul 25 06:37:26 PM PDT 24
Peak memory 205724 kb
Host smart-b5dd089b-aae1-4df5-8904-963d06f78349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876864116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.3876864116
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.3630629322
Short name T967
Test name
Test status
Simulation time 38942056785 ps
CPU time 162.15 seconds
Started Jul 25 06:37:14 PM PDT 24
Finished Jul 25 06:39:56 PM PDT 24
Peak memory 249224 kb
Host smart-7598cd17-95e1-4b2b-b7ea-289172f6b411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630629322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.3630629322
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.1784204870
Short name T214
Test name
Test status
Simulation time 8950446050 ps
CPU time 78.82 seconds
Started Jul 25 06:37:16 PM PDT 24
Finished Jul 25 06:38:35 PM PDT 24
Peak memory 251872 kb
Host smart-0543a647-d31c-4161-b9da-ed6459044960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784204870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.1784204870
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.2838760631
Short name T201
Test name
Test status
Simulation time 3703694966 ps
CPU time 92.37 seconds
Started Jul 25 06:37:15 PM PDT 24
Finished Jul 25 06:38:47 PM PDT 24
Peak memory 256888 kb
Host smart-9cea2ddc-35fe-4005-a747-8bc59c97d19d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838760631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.2838760631
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.1376612182
Short name T506
Test name
Test status
Simulation time 113462214611 ps
CPU time 206.18 seconds
Started Jul 25 06:37:17 PM PDT 24
Finished Jul 25 06:40:44 PM PDT 24
Peak memory 255964 kb
Host smart-e96d194b-32ae-4cdd-b875-6181f4f83e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376612182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmd
s.1376612182
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_intercept.3598960763
Short name T335
Test name
Test status
Simulation time 393594336 ps
CPU time 4.66 seconds
Started Jul 25 06:37:12 PM PDT 24
Finished Jul 25 06:37:17 PM PDT 24
Peak memory 232812 kb
Host smart-add720f8-2881-47b5-badc-2eaab60eaa5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598960763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.3598960763
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.1002950761
Short name T215
Test name
Test status
Simulation time 924977227 ps
CPU time 16.52 seconds
Started Jul 25 06:37:11 PM PDT 24
Finished Jul 25 06:37:27 PM PDT 24
Peak memory 249292 kb
Host smart-3ec52465-6f5e-474a-a673-5847158d6100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002950761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.1002950761
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.3412119948
Short name T981
Test name
Test status
Simulation time 31615057 ps
CPU time 2 seconds
Started Jul 25 06:37:14 PM PDT 24
Finished Jul 25 06:37:16 PM PDT 24
Peak memory 224360 kb
Host smart-1f0795a0-8d74-4f03-91d6-59d381636043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412119948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.3412119948
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.1609460353
Short name T588
Test name
Test status
Simulation time 478122275 ps
CPU time 3.28 seconds
Started Jul 25 06:37:20 PM PDT 24
Finished Jul 25 06:37:24 PM PDT 24
Peak memory 232888 kb
Host smart-34548c08-4e09-4dc7-afc0-bf5b0b46e449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609460353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.1609460353
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.4252087023
Short name T680
Test name
Test status
Simulation time 460951616 ps
CPU time 3.52 seconds
Started Jul 25 06:37:19 PM PDT 24
Finished Jul 25 06:37:23 PM PDT 24
Peak memory 219316 kb
Host smart-70b8f7cf-4c4e-44dd-845e-846f4b12e5c8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4252087023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.4252087023
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.3932141853
Short name T879
Test name
Test status
Simulation time 3766997832 ps
CPU time 29.07 seconds
Started Jul 25 06:37:09 PM PDT 24
Finished Jul 25 06:37:38 PM PDT 24
Peak memory 216620 kb
Host smart-39e4bc21-646d-46bc-9592-e136ae26a440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932141853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.3932141853
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.1826810661
Short name T859
Test name
Test status
Simulation time 395443341 ps
CPU time 1.79 seconds
Started Jul 25 06:37:10 PM PDT 24
Finished Jul 25 06:37:12 PM PDT 24
Peak memory 208076 kb
Host smart-51449ae0-7fd4-48e7-8871-647abd0ab37e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826810661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.1826810661
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.365770879
Short name T782
Test name
Test status
Simulation time 184292566 ps
CPU time 2.29 seconds
Started Jul 25 06:37:18 PM PDT 24
Finished Jul 25 06:37:20 PM PDT 24
Peak memory 216436 kb
Host smart-80860090-1d45-41af-a0e0-503d3265fc8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365770879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.365770879
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.167093188
Short name T497
Test name
Test status
Simulation time 52891970 ps
CPU time 0.7 seconds
Started Jul 25 06:37:12 PM PDT 24
Finished Jul 25 06:37:13 PM PDT 24
Peak memory 205752 kb
Host smart-f7dbcb4f-f311-4067-9363-7140d2ea82af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167093188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.167093188
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.48407033
Short name T483
Test name
Test status
Simulation time 19257672367 ps
CPU time 15.67 seconds
Started Jul 25 06:37:12 PM PDT 24
Finished Jul 25 06:37:28 PM PDT 24
Peak memory 224752 kb
Host smart-7e8f4b90-f46e-4edb-b8ca-2bf23c255f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48407033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.48407033
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.1913685437
Short name T57
Test name
Test status
Simulation time 15492270 ps
CPU time 0.78 seconds
Started Jul 25 06:37:25 PM PDT 24
Finished Jul 25 06:37:26 PM PDT 24
Peak memory 205076 kb
Host smart-ca05acbf-9018-4cf3-9759-d063b4a2c4d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913685437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
1913685437
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.1766692576
Short name T230
Test name
Test status
Simulation time 34137076 ps
CPU time 2.22 seconds
Started Jul 25 06:37:14 PM PDT 24
Finished Jul 25 06:37:16 PM PDT 24
Peak memory 232756 kb
Host smart-564c0e7d-c3a0-4e19-8313-7a447ae9b49a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766692576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.1766692576
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.2784694246
Short name T544
Test name
Test status
Simulation time 68263022 ps
CPU time 0.78 seconds
Started Jul 25 06:37:14 PM PDT 24
Finished Jul 25 06:37:15 PM PDT 24
Peak memory 206760 kb
Host smart-25c456e5-fffb-4c81-94f1-3fcec7ef3d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784694246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.2784694246
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.4095230516
Short name T120
Test name
Test status
Simulation time 49949699583 ps
CPU time 446.76 seconds
Started Jul 25 06:37:21 PM PDT 24
Finished Jul 25 06:44:48 PM PDT 24
Peak memory 266080 kb
Host smart-65ed5d0d-3eac-4467-bdc0-f6130adf3fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095230516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.4095230516
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.3475338506
Short name T676
Test name
Test status
Simulation time 30335836933 ps
CPU time 104.53 seconds
Started Jul 25 06:37:13 PM PDT 24
Finished Jul 25 06:38:57 PM PDT 24
Peak memory 257592 kb
Host smart-890906b9-0d3a-4260-b4b8-839217875255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475338506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.3475338506
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.376224662
Short name T525
Test name
Test status
Simulation time 138239568 ps
CPU time 4.29 seconds
Started Jul 25 06:37:15 PM PDT 24
Finished Jul 25 06:37:19 PM PDT 24
Peak memory 224712 kb
Host smart-6ea9346a-b958-4cd0-ab98-e313a89e909c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376224662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.376224662
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.1393809148
Short name T267
Test name
Test status
Simulation time 5532371446 ps
CPU time 64.48 seconds
Started Jul 25 06:37:19 PM PDT 24
Finished Jul 25 06:38:24 PM PDT 24
Peak memory 254104 kb
Host smart-c372c0ac-2c76-4d4b-b1fc-098c95b94ad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393809148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmd
s.1393809148
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_intercept.2417092123
Short name T656
Test name
Test status
Simulation time 1144174924 ps
CPU time 6.13 seconds
Started Jul 25 06:37:19 PM PDT 24
Finished Jul 25 06:37:25 PM PDT 24
Peak memory 232900 kb
Host smart-cf163fa5-8c8b-4e68-8408-98d0c2614a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417092123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.2417092123
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.427810628
Short name T958
Test name
Test status
Simulation time 1575400611 ps
CPU time 20.84 seconds
Started Jul 25 06:37:17 PM PDT 24
Finished Jul 25 06:37:38 PM PDT 24
Peak memory 232916 kb
Host smart-835e228b-3ffb-4ac2-aedb-8966a266a41b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427810628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.427810628
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.1965973372
Short name T533
Test name
Test status
Simulation time 4526935874 ps
CPU time 5.57 seconds
Started Jul 25 06:37:15 PM PDT 24
Finished Jul 25 06:37:21 PM PDT 24
Peak memory 232944 kb
Host smart-4616c47b-4722-4f56-9be9-89ad21900562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965973372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.1965973372
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.715758435
Short name T692
Test name
Test status
Simulation time 60869884 ps
CPU time 2.98 seconds
Started Jul 25 06:37:14 PM PDT 24
Finished Jul 25 06:37:18 PM PDT 24
Peak memory 232784 kb
Host smart-1d56260b-36f4-4e1a-8a17-6307bbc5b568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715758435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.715758435
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.4037737145
Short name T395
Test name
Test status
Simulation time 1038589495 ps
CPU time 6.3 seconds
Started Jul 25 06:37:12 PM PDT 24
Finished Jul 25 06:37:18 PM PDT 24
Peak memory 223152 kb
Host smart-4d4affa8-d4d9-4c97-ba74-a41c539b1d1d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4037737145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.4037737145
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.1289395690
Short name T734
Test name
Test status
Simulation time 250120079 ps
CPU time 1.1 seconds
Started Jul 25 06:37:20 PM PDT 24
Finished Jul 25 06:37:22 PM PDT 24
Peak memory 207964 kb
Host smart-b689ebe2-20e4-42c0-97b8-7ee04e8bbd7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289395690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.1289395690
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.478527188
Short name T663
Test name
Test status
Simulation time 16093642088 ps
CPU time 27.17 seconds
Started Jul 25 06:37:20 PM PDT 24
Finished Jul 25 06:37:47 PM PDT 24
Peak memory 216484 kb
Host smart-01d92583-afc0-4899-994c-e067eefaa64e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478527188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.478527188
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.3764886847
Short name T318
Test name
Test status
Simulation time 1245350890 ps
CPU time 6.71 seconds
Started Jul 25 06:37:13 PM PDT 24
Finished Jul 25 06:37:20 PM PDT 24
Peak memory 216400 kb
Host smart-c4b15a39-123c-4dc3-8ff6-f7e69d2b2ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764886847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.3764886847
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.1255982551
Short name T543
Test name
Test status
Simulation time 1919987999 ps
CPU time 3.64 seconds
Started Jul 25 06:37:15 PM PDT 24
Finished Jul 25 06:37:19 PM PDT 24
Peak memory 216420 kb
Host smart-3acc9a5c-8d97-4995-985b-bab502d738e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255982551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.1255982551
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.1625558854
Short name T728
Test name
Test status
Simulation time 343430677 ps
CPU time 0.86 seconds
Started Jul 25 06:37:16 PM PDT 24
Finished Jul 25 06:37:17 PM PDT 24
Peak memory 206116 kb
Host smart-04909e88-a947-4454-af2c-ebb44b2a46de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625558854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.1625558854
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.3146235317
Short name T690
Test name
Test status
Simulation time 7186259939 ps
CPU time 11.42 seconds
Started Jul 25 06:37:17 PM PDT 24
Finished Jul 25 06:37:29 PM PDT 24
Peak memory 240888 kb
Host smart-469b1314-ce6c-4c93-b125-6a685c63070d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146235317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.3146235317
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.1234849903
Short name T442
Test name
Test status
Simulation time 32366460 ps
CPU time 0.71 seconds
Started Jul 25 06:37:18 PM PDT 24
Finished Jul 25 06:37:19 PM PDT 24
Peak memory 205028 kb
Host smart-6ab10ed2-8b16-4b9d-a720-e9a4be64214d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234849903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
1234849903
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.3957998921
Short name T885
Test name
Test status
Simulation time 35929446 ps
CPU time 2.77 seconds
Started Jul 25 06:37:22 PM PDT 24
Finished Jul 25 06:37:25 PM PDT 24
Peak memory 232800 kb
Host smart-f8762d09-a26a-49fa-af1e-1bd90dd5a3e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957998921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.3957998921
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.2262505262
Short name T570
Test name
Test status
Simulation time 21859833 ps
CPU time 0.84 seconds
Started Jul 25 06:37:19 PM PDT 24
Finished Jul 25 06:37:20 PM PDT 24
Peak memory 206744 kb
Host smart-c12170ac-3ed3-4dea-b113-9c89aef35141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262505262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.2262505262
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.2464659280
Short name T877
Test name
Test status
Simulation time 1981777454 ps
CPU time 43.71 seconds
Started Jul 25 06:37:22 PM PDT 24
Finished Jul 25 06:38:06 PM PDT 24
Peak memory 250832 kb
Host smart-b3150239-3f24-4bb3-9da4-cd6fb333ae52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464659280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.2464659280
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.3063248633
Short name T721
Test name
Test status
Simulation time 99521412297 ps
CPU time 269.19 seconds
Started Jul 25 06:37:23 PM PDT 24
Finished Jul 25 06:41:52 PM PDT 24
Peak memory 256084 kb
Host smart-3fa48f1a-3c70-42b4-9515-ec07dc0af461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063248633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.3063248633
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.2136095163
Short name T411
Test name
Test status
Simulation time 103600250580 ps
CPU time 181.19 seconds
Started Jul 25 06:37:20 PM PDT 24
Finished Jul 25 06:40:21 PM PDT 24
Peak memory 249332 kb
Host smart-e087abc8-1ce8-4727-ac4d-84a82afdeaef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136095163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.2136095163
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.2443144828
Short name T837
Test name
Test status
Simulation time 2173822229 ps
CPU time 6.16 seconds
Started Jul 25 06:37:26 PM PDT 24
Finished Jul 25 06:37:33 PM PDT 24
Peak memory 239844 kb
Host smart-89ce77c9-e51e-4399-8141-82988674e7ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443144828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.2443144828
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_intercept.181563839
Short name T179
Test name
Test status
Simulation time 6700520090 ps
CPU time 21.52 seconds
Started Jul 25 06:37:25 PM PDT 24
Finished Jul 25 06:37:47 PM PDT 24
Peak memory 232924 kb
Host smart-144c43e8-ce70-4289-a724-7c25ff0e2e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181563839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.181563839
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.3120166179
Short name T916
Test name
Test status
Simulation time 12610691642 ps
CPU time 113.07 seconds
Started Jul 25 06:37:23 PM PDT 24
Finished Jul 25 06:39:17 PM PDT 24
Peak memory 241016 kb
Host smart-d89a7b98-bcdd-4793-9fda-7787915e60a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120166179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.3120166179
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.3955308104
Short name T965
Test name
Test status
Simulation time 732281355 ps
CPU time 8.98 seconds
Started Jul 25 06:37:18 PM PDT 24
Finished Jul 25 06:37:27 PM PDT 24
Peak memory 232784 kb
Host smart-6142e297-758b-49eb-b651-55effafb857a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955308104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.3955308104
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.141506720
Short name T221
Test name
Test status
Simulation time 1681807973 ps
CPU time 5.41 seconds
Started Jul 25 06:37:26 PM PDT 24
Finished Jul 25 06:37:32 PM PDT 24
Peak memory 232944 kb
Host smart-87668673-6c90-4c8e-99d1-e1e14346445e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141506720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.141506720
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.3290736546
Short name T783
Test name
Test status
Simulation time 751732146 ps
CPU time 6.02 seconds
Started Jul 25 06:37:18 PM PDT 24
Finished Jul 25 06:37:24 PM PDT 24
Peak memory 219464 kb
Host smart-d7ef255b-ae1a-432b-ac7a-45dfc3de9c82
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3290736546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.3290736546
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.2305001373
Short name T547
Test name
Test status
Simulation time 10511097705 ps
CPU time 24.25 seconds
Started Jul 25 06:37:17 PM PDT 24
Finished Jul 25 06:37:42 PM PDT 24
Peak memory 216472 kb
Host smart-30a6245b-a7a7-460d-8cdc-347227b21d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305001373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.2305001373
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.1937536431
Short name T71
Test name
Test status
Simulation time 40246844 ps
CPU time 0.71 seconds
Started Jul 25 06:37:23 PM PDT 24
Finished Jul 25 06:37:24 PM PDT 24
Peak memory 205824 kb
Host smart-ab8fad93-823c-4403-95c3-d7d6fbf4cf3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937536431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.1937536431
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.2476390002
Short name T758
Test name
Test status
Simulation time 26028916 ps
CPU time 0.69 seconds
Started Jul 25 06:37:21 PM PDT 24
Finished Jul 25 06:37:22 PM PDT 24
Peak memory 205816 kb
Host smart-8a6e6d64-249b-4e47-b1c3-85e66d348c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476390002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.2476390002
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.96556240
Short name T348
Test name
Test status
Simulation time 43113562 ps
CPU time 0.82 seconds
Started Jul 25 06:37:17 PM PDT 24
Finished Jul 25 06:37:18 PM PDT 24
Peak memory 206088 kb
Host smart-993447f6-0026-4356-9374-5a8766f6b87b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96556240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.96556240
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.4219368844
Short name T541
Test name
Test status
Simulation time 1471373915 ps
CPU time 4.76 seconds
Started Jul 25 06:37:20 PM PDT 24
Finished Jul 25 06:37:25 PM PDT 24
Peak memory 224640 kb
Host smart-aca22d1f-cada-47b2-b728-201a1206363f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219368844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.4219368844
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.83049409
Short name T504
Test name
Test status
Simulation time 18254869 ps
CPU time 0.7 seconds
Started Jul 25 06:37:17 PM PDT 24
Finished Jul 25 06:37:18 PM PDT 24
Peak memory 205604 kb
Host smart-107f2269-ff00-4ff9-b760-53206cb681e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83049409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.83049409
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.2073031079
Short name T532
Test name
Test status
Simulation time 634119426 ps
CPU time 7.85 seconds
Started Jul 25 06:37:23 PM PDT 24
Finished Jul 25 06:37:31 PM PDT 24
Peak memory 232808 kb
Host smart-86e65860-6611-4464-a5e3-1b016c899fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073031079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.2073031079
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.69495087
Short name T992
Test name
Test status
Simulation time 13703071 ps
CPU time 0.77 seconds
Started Jul 25 06:37:16 PM PDT 24
Finished Jul 25 06:37:17 PM PDT 24
Peak memory 207072 kb
Host smart-19642a1c-521d-4aad-9bb4-bf11ca988dbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69495087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.69495087
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.563380386
Short name T278
Test name
Test status
Simulation time 3246194304 ps
CPU time 28.16 seconds
Started Jul 25 06:37:17 PM PDT 24
Finished Jul 25 06:37:45 PM PDT 24
Peak memory 249352 kb
Host smart-7a95fb26-869d-4ad9-ae13-e830ab3f983a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563380386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.563380386
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.3606070029
Short name T573
Test name
Test status
Simulation time 53419375655 ps
CPU time 116.22 seconds
Started Jul 25 06:37:21 PM PDT 24
Finished Jul 25 06:39:18 PM PDT 24
Peak memory 249412 kb
Host smart-c164b650-2166-445b-8330-5232926fe911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606070029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.3606070029
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.144080656
Short name T672
Test name
Test status
Simulation time 110056497719 ps
CPU time 61 seconds
Started Jul 25 06:37:18 PM PDT 24
Finished Jul 25 06:38:20 PM PDT 24
Peak memory 240064 kb
Host smart-21f08337-4650-4215-ab50-fdc41535b6b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144080656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idle
.144080656
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.1739475650
Short name T125
Test name
Test status
Simulation time 807297886 ps
CPU time 4.89 seconds
Started Jul 25 06:37:25 PM PDT 24
Finished Jul 25 06:37:31 PM PDT 24
Peak memory 232780 kb
Host smart-dad221f7-ea80-4a44-a18d-ef993b6878fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739475650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.1739475650
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.2458123194
Short name T455
Test name
Test status
Simulation time 15153486 ps
CPU time 0.77 seconds
Started Jul 25 06:37:25 PM PDT 24
Finished Jul 25 06:37:27 PM PDT 24
Peak memory 215932 kb
Host smart-fffc72d2-46bc-4f78-bedb-64bd010279b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458123194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmd
s.2458123194
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_intercept.2441988076
Short name T188
Test name
Test status
Simulation time 1350319406 ps
CPU time 15.1 seconds
Started Jul 25 06:37:17 PM PDT 24
Finished Jul 25 06:37:32 PM PDT 24
Peak memory 232872 kb
Host smart-31744188-5dab-43fb-80cf-7072fcb28719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441988076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.2441988076
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.1416751259
Short name T640
Test name
Test status
Simulation time 1690651673 ps
CPU time 5.42 seconds
Started Jul 25 06:37:16 PM PDT 24
Finished Jul 25 06:37:22 PM PDT 24
Peak memory 224704 kb
Host smart-c900b906-b3e8-4f79-bad4-7df5a0d01ede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416751259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.1416751259
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.3889853798
Short name T261
Test name
Test status
Simulation time 2256295240 ps
CPU time 5.79 seconds
Started Jul 25 06:37:22 PM PDT 24
Finished Jul 25 06:37:28 PM PDT 24
Peak memory 224684 kb
Host smart-b4cb328b-12e0-4758-8223-311479b439b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889853798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.3889853798
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.1787653548
Short name T490
Test name
Test status
Simulation time 15996989740 ps
CPU time 8.47 seconds
Started Jul 25 06:37:17 PM PDT 24
Finished Jul 25 06:37:26 PM PDT 24
Peak memory 224780 kb
Host smart-cc3992d7-36e6-4b70-8b2c-d07c484e6635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787653548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.1787653548
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.3967059516
Short name T951
Test name
Test status
Simulation time 3650172673 ps
CPU time 5.34 seconds
Started Jul 25 06:37:26 PM PDT 24
Finished Jul 25 06:37:32 PM PDT 24
Peak memory 223488 kb
Host smart-6ae5d806-c987-4b58-b809-5c575c9805b3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3967059516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.3967059516
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.1898765613
Short name T410
Test name
Test status
Simulation time 1709696532 ps
CPU time 27.86 seconds
Started Jul 25 06:37:17 PM PDT 24
Finished Jul 25 06:37:45 PM PDT 24
Peak memory 216772 kb
Host smart-95d5e7c2-6804-40ee-93f5-6bdd8ef15200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898765613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.1898765613
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.3774044017
Short name T374
Test name
Test status
Simulation time 1938662202 ps
CPU time 3.67 seconds
Started Jul 25 06:37:22 PM PDT 24
Finished Jul 25 06:37:26 PM PDT 24
Peak memory 216332 kb
Host smart-3a5ff753-0773-4759-b299-080a7aa23c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774044017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.3774044017
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.506660714
Short name T28
Test name
Test status
Simulation time 92660237 ps
CPU time 0.97 seconds
Started Jul 25 06:37:25 PM PDT 24
Finished Jul 25 06:37:26 PM PDT 24
Peak memory 207096 kb
Host smart-cba9689c-d004-47e2-b339-55d923ce5e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506660714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.506660714
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.4262206876
Short name T814
Test name
Test status
Simulation time 110057378 ps
CPU time 1.12 seconds
Started Jul 25 06:37:18 PM PDT 24
Finished Jul 25 06:37:19 PM PDT 24
Peak memory 206124 kb
Host smart-18193c70-c406-4dca-bd65-3a58c35aed91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262206876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.4262206876
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.152277043
Short name T152
Test name
Test status
Simulation time 682688834 ps
CPU time 3.02 seconds
Started Jul 25 06:37:18 PM PDT 24
Finished Jul 25 06:37:22 PM PDT 24
Peak memory 228240 kb
Host smart-007f0eb4-89a3-4be5-9965-582589a656ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152277043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.152277043
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.1377048151
Short name T433
Test name
Test status
Simulation time 32855714 ps
CPU time 0.7 seconds
Started Jul 25 06:37:26 PM PDT 24
Finished Jul 25 06:37:28 PM PDT 24
Peak memory 205052 kb
Host smart-52cff069-b738-4458-95c9-42fbfa0d22c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377048151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
1377048151
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.4047444456
Short name T549
Test name
Test status
Simulation time 243671366 ps
CPU time 3.39 seconds
Started Jul 25 06:37:26 PM PDT 24
Finished Jul 25 06:37:30 PM PDT 24
Peak memory 232888 kb
Host smart-92019a46-7f06-4cfb-ab64-1c202788f670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047444456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.4047444456
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.1836913428
Short name T614
Test name
Test status
Simulation time 44551593 ps
CPU time 0.76 seconds
Started Jul 25 06:37:26 PM PDT 24
Finished Jul 25 06:37:27 PM PDT 24
Peak memory 206092 kb
Host smart-75d76cf8-6d5e-4d19-82c0-1d64db52202c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836913428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.1836913428
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.1493738547
Short name T177
Test name
Test status
Simulation time 35584413673 ps
CPU time 109.1 seconds
Started Jul 25 06:37:25 PM PDT 24
Finished Jul 25 06:39:14 PM PDT 24
Peak memory 256748 kb
Host smart-9930eaca-d473-40d2-b637-23a801267fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493738547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.1493738547
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.1783288284
Short name T247
Test name
Test status
Simulation time 11685070539 ps
CPU time 125.27 seconds
Started Jul 25 06:37:23 PM PDT 24
Finished Jul 25 06:39:29 PM PDT 24
Peak memory 249704 kb
Host smart-fa2fd4da-f060-4353-a7dd-c0ae2177b70a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783288284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.1783288284
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.2288039623
Short name T47
Test name
Test status
Simulation time 9416010695 ps
CPU time 49.56 seconds
Started Jul 25 06:37:24 PM PDT 24
Finished Jul 25 06:38:14 PM PDT 24
Peak memory 250760 kb
Host smart-1e44824e-d34e-4d17-b0d8-1334176f6844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288039623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.2288039623
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.1565383789
Short name T48
Test name
Test status
Simulation time 669713875 ps
CPU time 4.3 seconds
Started Jul 25 06:37:25 PM PDT 24
Finished Jul 25 06:37:30 PM PDT 24
Peak memory 240176 kb
Host smart-50cb9636-2df5-44ea-8553-5f2a1ecd6fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565383789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.1565383789
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.1148053915
Short name T271
Test name
Test status
Simulation time 12445463884 ps
CPU time 90.69 seconds
Started Jul 25 06:37:31 PM PDT 24
Finished Jul 25 06:39:03 PM PDT 24
Peak memory 251116 kb
Host smart-7adf3651-0e12-4e49-8852-3af78dd58e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148053915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmd
s.1148053915
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/18.spi_device_intercept.3041114412
Short name T223
Test name
Test status
Simulation time 2119046874 ps
CPU time 17.55 seconds
Started Jul 25 06:37:25 PM PDT 24
Finished Jul 25 06:37:44 PM PDT 24
Peak memory 232900 kb
Host smart-4d5c6895-d356-4893-8360-ce48c212a8de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041114412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.3041114412
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.387819913
Short name T216
Test name
Test status
Simulation time 12846717837 ps
CPU time 8.12 seconds
Started Jul 25 06:37:25 PM PDT 24
Finished Jul 25 06:37:34 PM PDT 24
Peak memory 224724 kb
Host smart-a9fafc28-8fc8-4d2f-a60b-d276d18294e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387819913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swap
.387819913
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.2216247411
Short name T258
Test name
Test status
Simulation time 2233908832 ps
CPU time 8.06 seconds
Started Jul 25 06:37:26 PM PDT 24
Finished Jul 25 06:37:34 PM PDT 24
Peak memory 224708 kb
Host smart-ae69966c-0fe0-4084-996f-16148c894afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216247411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.2216247411
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.1243206967
Short name T990
Test name
Test status
Simulation time 2752047007 ps
CPU time 17.37 seconds
Started Jul 25 06:37:31 PM PDT 24
Finished Jul 25 06:37:48 PM PDT 24
Peak memory 221040 kb
Host smart-72de16df-e5e7-4dbb-9afe-2e81a92d5415
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1243206967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.1243206967
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.1107812846
Short name T279
Test name
Test status
Simulation time 41955308359 ps
CPU time 78.57 seconds
Started Jul 25 06:37:23 PM PDT 24
Finished Jul 25 06:38:42 PM PDT 24
Peak memory 254136 kb
Host smart-37a6bdd9-219a-4785-869d-af9cd88dbbbe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107812846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.1107812846
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.42096749
Short name T765
Test name
Test status
Simulation time 957744422 ps
CPU time 7.26 seconds
Started Jul 25 06:37:26 PM PDT 24
Finished Jul 25 06:37:34 PM PDT 24
Peak memory 216436 kb
Host smart-ecd1ee17-4ab4-4a7a-9f71-31cc7ee3d1e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42096749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.42096749
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.1318020057
Short name T565
Test name
Test status
Simulation time 2277383962 ps
CPU time 2.37 seconds
Started Jul 25 06:37:18 PM PDT 24
Finished Jul 25 06:37:21 PM PDT 24
Peak memory 208048 kb
Host smart-244528c6-b603-4b50-bd1c-4e1c223436a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318020057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.1318020057
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.2196184387
Short name T482
Test name
Test status
Simulation time 313262247 ps
CPU time 2.56 seconds
Started Jul 25 06:37:28 PM PDT 24
Finished Jul 25 06:37:31 PM PDT 24
Peak memory 216428 kb
Host smart-41380fbb-defd-4e75-af94-a170f05b2b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196184387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.2196184387
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.1480776108
Short name T648
Test name
Test status
Simulation time 31508549 ps
CPU time 0.82 seconds
Started Jul 25 06:37:24 PM PDT 24
Finished Jul 25 06:37:25 PM PDT 24
Peak memory 206124 kb
Host smart-c0605038-7395-4232-a90d-521c2840c271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480776108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.1480776108
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.34757619
Short name T722
Test name
Test status
Simulation time 2532401944 ps
CPU time 14.85 seconds
Started Jul 25 06:37:23 PM PDT 24
Finished Jul 25 06:37:38 PM PDT 24
Peak memory 232828 kb
Host smart-102e1271-cd88-45aa-87e6-aa39a09b0e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34757619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.34757619
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.1636848875
Short name T495
Test name
Test status
Simulation time 41731381 ps
CPU time 0.77 seconds
Started Jul 25 06:37:24 PM PDT 24
Finished Jul 25 06:37:25 PM PDT 24
Peak memory 205924 kb
Host smart-aafd64a6-35eb-4ea3-8ce2-120e1b8bd1bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636848875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
1636848875
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.3015141071
Short name T307
Test name
Test status
Simulation time 425955243 ps
CPU time 3.09 seconds
Started Jul 25 06:37:24 PM PDT 24
Finished Jul 25 06:37:27 PM PDT 24
Peak memory 224580 kb
Host smart-69695aec-eee9-459f-88a8-0abada63668c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015141071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.3015141071
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.3599970891
Short name T466
Test name
Test status
Simulation time 56791529 ps
CPU time 0.77 seconds
Started Jul 25 06:37:26 PM PDT 24
Finished Jul 25 06:37:28 PM PDT 24
Peak memory 205788 kb
Host smart-8ab75d57-375f-424e-ba44-17ec27b8ec00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599970891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.3599970891
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.2100010185
Short name T244
Test name
Test status
Simulation time 24480073184 ps
CPU time 103.39 seconds
Started Jul 25 06:37:31 PM PDT 24
Finished Jul 25 06:39:15 PM PDT 24
Peak memory 269348 kb
Host smart-a3066f78-7d8a-424a-a255-f55d9f78d94d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100010185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.2100010185
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.552884031
Short name T740
Test name
Test status
Simulation time 91393251340 ps
CPU time 230.02 seconds
Started Jul 25 06:37:25 PM PDT 24
Finished Jul 25 06:41:16 PM PDT 24
Peak memory 254376 kb
Host smart-3d0cc0aa-33f3-4997-9866-56e676dfbed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552884031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idle
.552884031
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.521877255
Short name T808
Test name
Test status
Simulation time 1493268798 ps
CPU time 5.64 seconds
Started Jul 25 06:37:31 PM PDT 24
Finished Jul 25 06:37:37 PM PDT 24
Peak memory 232876 kb
Host smart-5c454309-88fe-4165-8899-b6ac96f4a133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521877255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.521877255
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.733425675
Short name T45
Test name
Test status
Simulation time 9011948987 ps
CPU time 21.49 seconds
Started Jul 25 06:37:25 PM PDT 24
Finished Jul 25 06:37:47 PM PDT 24
Peak memory 232988 kb
Host smart-4cda84ca-ee05-4962-a16b-45d1a4846253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733425675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmds
.733425675
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_intercept.877986314
Short name T646
Test name
Test status
Simulation time 46333451055 ps
CPU time 26.03 seconds
Started Jul 25 06:37:24 PM PDT 24
Finished Jul 25 06:37:51 PM PDT 24
Peak memory 232980 kb
Host smart-68252ca2-988e-462e-854e-0ce52a9c39e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877986314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.877986314
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.521600951
Short name T408
Test name
Test status
Simulation time 115372873 ps
CPU time 3.14 seconds
Started Jul 25 06:37:26 PM PDT 24
Finished Jul 25 06:37:29 PM PDT 24
Peak memory 232932 kb
Host smart-f654610f-5296-44f5-816f-da6a246a0f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521600951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.521600951
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.3930800761
Short name T178
Test name
Test status
Simulation time 5609570358 ps
CPU time 15.91 seconds
Started Jul 25 06:37:26 PM PDT 24
Finished Jul 25 06:37:43 PM PDT 24
Peak memory 232920 kb
Host smart-3fc8dd23-f718-48ca-b416-79a544d7b862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930800761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.3930800761
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.705535024
Short name T710
Test name
Test status
Simulation time 15992592147 ps
CPU time 19 seconds
Started Jul 25 06:37:28 PM PDT 24
Finished Jul 25 06:37:47 PM PDT 24
Peak memory 241144 kb
Host smart-d88246c6-dffe-4011-9550-19291704ddb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705535024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.705535024
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.4277731216
Short name T657
Test name
Test status
Simulation time 295073713 ps
CPU time 4.99 seconds
Started Jul 25 06:37:25 PM PDT 24
Finished Jul 25 06:37:30 PM PDT 24
Peak memory 223256 kb
Host smart-7d202b64-b8ca-4167-9158-98db6369b5e8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4277731216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.4277731216
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.3181739506
Short name T305
Test name
Test status
Simulation time 2426328816 ps
CPU time 14.78 seconds
Started Jul 25 06:37:31 PM PDT 24
Finished Jul 25 06:37:46 PM PDT 24
Peak memory 220052 kb
Host smart-4466031e-fae6-47a1-b79f-fd2ef41b8384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181739506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.3181739506
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.1011490128
Short name T377
Test name
Test status
Simulation time 275159281 ps
CPU time 1.28 seconds
Started Jul 25 06:37:25 PM PDT 24
Finished Jul 25 06:37:27 PM PDT 24
Peak memory 208040 kb
Host smart-8d20a550-44d9-4522-a84a-19d1e7f87457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011490128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.1011490128
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.450467592
Short name T461
Test name
Test status
Simulation time 56512809 ps
CPU time 0.78 seconds
Started Jul 25 06:37:30 PM PDT 24
Finished Jul 25 06:37:31 PM PDT 24
Peak memory 206688 kb
Host smart-ae634940-6cec-49fc-a72a-dad2b9961007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450467592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.450467592
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.1277046724
Short name T603
Test name
Test status
Simulation time 14341726 ps
CPU time 0.72 seconds
Started Jul 25 06:37:27 PM PDT 24
Finished Jul 25 06:37:28 PM PDT 24
Peak memory 206136 kb
Host smart-2247f019-be5c-4d42-b242-2f1ed7a29f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277046724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.1277046724
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.2641882852
Short name T776
Test name
Test status
Simulation time 224171057 ps
CPU time 2.22 seconds
Started Jul 25 06:37:30 PM PDT 24
Finished Jul 25 06:37:32 PM PDT 24
Peak memory 224364 kb
Host smart-ba0a8227-3927-4717-a5f7-09c5ab973573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641882852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.2641882852
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.1326365812
Short name T864
Test name
Test status
Simulation time 15521574 ps
CPU time 0.71 seconds
Started Jul 25 06:36:35 PM PDT 24
Finished Jul 25 06:36:36 PM PDT 24
Peak memory 205872 kb
Host smart-49fe06c2-5a56-4069-b876-bc0e380a6b1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326365812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.1
326365812
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.832097127
Short name T962
Test name
Test status
Simulation time 277868468 ps
CPU time 4.01 seconds
Started Jul 25 06:36:29 PM PDT 24
Finished Jul 25 06:36:33 PM PDT 24
Peak memory 224720 kb
Host smart-5ea9b7e8-543d-4fa9-8409-615e8729515d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832097127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.832097127
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.2313849242
Short name T638
Test name
Test status
Simulation time 13722067 ps
CPU time 0.74 seconds
Started Jul 25 06:36:33 PM PDT 24
Finished Jul 25 06:36:34 PM PDT 24
Peak memory 206760 kb
Host smart-7ae9cf1b-0aa4-48a0-a936-8d4ea25adee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313849242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.2313849242
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.1512743439
Short name T893
Test name
Test status
Simulation time 19276681746 ps
CPU time 42.07 seconds
Started Jul 25 06:36:35 PM PDT 24
Finished Jul 25 06:37:18 PM PDT 24
Peak memory 249372 kb
Host smart-9ba7c2b7-a23c-408f-b911-c126eac1aac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512743439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.1512743439
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.577358127
Short name T507
Test name
Test status
Simulation time 17157576779 ps
CPU time 155.33 seconds
Started Jul 25 06:37:08 PM PDT 24
Finished Jul 25 06:39:43 PM PDT 24
Peak memory 267084 kb
Host smart-3ff164c7-7cbc-4088-9d0f-fff48af80aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577358127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.577358127
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.2597814529
Short name T465
Test name
Test status
Simulation time 37289601502 ps
CPU time 88.25 seconds
Started Jul 25 06:36:43 PM PDT 24
Finished Jul 25 06:38:11 PM PDT 24
Peak memory 249360 kb
Host smart-b0d9f309-3168-4393-bbf5-2276fdd06956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597814529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.2597814529
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.1063617942
Short name T75
Test name
Test status
Simulation time 395762267 ps
CPU time 10.06 seconds
Started Jul 25 06:36:36 PM PDT 24
Finished Jul 25 06:36:46 PM PDT 24
Peak memory 224676 kb
Host smart-1ab05d33-4beb-46e3-8ee9-460da00fdcd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063617942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.1063617942
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.723037423
Short name T485
Test name
Test status
Simulation time 4530148653 ps
CPU time 31.75 seconds
Started Jul 25 06:36:36 PM PDT 24
Finished Jul 25 06:37:08 PM PDT 24
Peak memory 254768 kb
Host smart-3821e54f-7351-4873-963c-7127c257b64e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723037423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds.
723037423
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_intercept.2824117746
Short name T701
Test name
Test status
Simulation time 2086161683 ps
CPU time 12.7 seconds
Started Jul 25 06:36:32 PM PDT 24
Finished Jul 25 06:36:45 PM PDT 24
Peak memory 232836 kb
Host smart-fd851984-65b7-4b15-9eac-12693c8244fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824117746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.2824117746
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.4024281144
Short name T823
Test name
Test status
Simulation time 208729939 ps
CPU time 3.95 seconds
Started Jul 25 06:36:31 PM PDT 24
Finished Jul 25 06:36:35 PM PDT 24
Peak memory 224712 kb
Host smart-1e9cfe05-23db-4b45-96d7-04c63059f66d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024281144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.4024281144
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.1096272829
Short name T674
Test name
Test status
Simulation time 479843380 ps
CPU time 5.25 seconds
Started Jul 25 06:36:40 PM PDT 24
Finished Jul 25 06:36:45 PM PDT 24
Peak memory 224688 kb
Host smart-934792b2-6545-4597-9cb9-bf203a1ee066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096272829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.1096272829
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.2091968872
Short name T471
Test name
Test status
Simulation time 20772943886 ps
CPU time 17.89 seconds
Started Jul 25 06:36:40 PM PDT 24
Finished Jul 25 06:36:59 PM PDT 24
Peak memory 239320 kb
Host smart-f2e51e8c-a511-4de4-936d-6f63c008f99e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091968872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.2091968872
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.1002207449
Short name T1007
Test name
Test status
Simulation time 915930397 ps
CPU time 5.23 seconds
Started Jul 25 06:36:28 PM PDT 24
Finished Jul 25 06:36:34 PM PDT 24
Peak memory 223352 kb
Host smart-4ed1afaf-75ee-4eb6-bbf5-914e61e25168
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1002207449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.1002207449
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.1652252766
Short name T66
Test name
Test status
Simulation time 80854980 ps
CPU time 1.16 seconds
Started Jul 25 06:36:40 PM PDT 24
Finished Jul 25 06:36:41 PM PDT 24
Peak memory 236488 kb
Host smart-2b712d4f-087c-44d4-a30d-4f5b444f6b89
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652252766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.1652252766
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.3603907957
Short name T233
Test name
Test status
Simulation time 16427967305 ps
CPU time 87.59 seconds
Started Jul 25 06:36:32 PM PDT 24
Finished Jul 25 06:38:00 PM PDT 24
Peak memory 256780 kb
Host smart-fb92abbe-6a82-44b5-81c3-e18cad2f2d52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603907957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.3603907957
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.4078834742
Short name T724
Test name
Test status
Simulation time 1282446709 ps
CPU time 5.25 seconds
Started Jul 25 06:36:32 PM PDT 24
Finished Jul 25 06:36:38 PM PDT 24
Peak memory 216444 kb
Host smart-b86c2e14-5f27-4447-b938-ddddd6b4f26b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078834742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.4078834742
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.4066217078
Short name T545
Test name
Test status
Simulation time 4495571995 ps
CPU time 7.95 seconds
Started Jul 25 06:36:38 PM PDT 24
Finished Jul 25 06:36:46 PM PDT 24
Peak memory 216488 kb
Host smart-f4fd9ecd-81e7-422f-af2c-9c7788dd30cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066217078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.4066217078
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.789179435
Short name T302
Test name
Test status
Simulation time 116041362 ps
CPU time 3.96 seconds
Started Jul 25 06:36:31 PM PDT 24
Finished Jul 25 06:36:35 PM PDT 24
Peak memory 216488 kb
Host smart-5484f499-0b0a-4471-9a92-f25aeefd0859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789179435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.789179435
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.3088598467
Short name T707
Test name
Test status
Simulation time 12699070 ps
CPU time 0.71 seconds
Started Jul 25 06:36:33 PM PDT 24
Finished Jul 25 06:36:34 PM PDT 24
Peak memory 205720 kb
Host smart-c37f6161-7432-4006-9d55-6cd9147c8175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088598467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.3088598467
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.2250325122
Short name T873
Test name
Test status
Simulation time 23743513767 ps
CPU time 14.13 seconds
Started Jul 25 06:36:32 PM PDT 24
Finished Jul 25 06:36:46 PM PDT 24
Peak memory 237312 kb
Host smart-22b4b66c-5040-4797-b097-de5246815857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250325122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.2250325122
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.3369715619
Short name T730
Test name
Test status
Simulation time 32732543 ps
CPU time 0.7 seconds
Started Jul 25 06:37:32 PM PDT 24
Finished Jul 25 06:37:33 PM PDT 24
Peak memory 205028 kb
Host smart-25ff85af-cc78-4d60-91f7-c7e04720b396
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369715619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
3369715619
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.587666233
Short name T930
Test name
Test status
Simulation time 187820855 ps
CPU time 2.31 seconds
Started Jul 25 06:37:37 PM PDT 24
Finished Jul 25 06:37:40 PM PDT 24
Peak memory 224672 kb
Host smart-4cf5ae4a-0331-4e7e-9470-b461f68ba140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587666233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.587666233
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.3225323050
Short name T971
Test name
Test status
Simulation time 35279041 ps
CPU time 0.77 seconds
Started Jul 25 06:37:31 PM PDT 24
Finished Jul 25 06:37:33 PM PDT 24
Peak memory 205732 kb
Host smart-9881086f-7178-43c2-8524-d5720513af03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225323050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.3225323050
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.3363273327
Short name T181
Test name
Test status
Simulation time 54986435711 ps
CPU time 418.99 seconds
Started Jul 25 06:37:30 PM PDT 24
Finished Jul 25 06:44:29 PM PDT 24
Peak memory 261056 kb
Host smart-ab776237-105f-4b98-a5e7-8c2218cc6ba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363273327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.3363273327
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.2053751515
Short name T437
Test name
Test status
Simulation time 38582283258 ps
CPU time 277.66 seconds
Started Jul 25 06:37:34 PM PDT 24
Finished Jul 25 06:42:12 PM PDT 24
Peak memory 255144 kb
Host smart-1df996ed-4c87-4a4d-92da-9d62214b7ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053751515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.2053751515
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.872550968
Short name T213
Test name
Test status
Simulation time 91780973987 ps
CPU time 208.06 seconds
Started Jul 25 06:37:31 PM PDT 24
Finished Jul 25 06:40:59 PM PDT 24
Peak memory 257112 kb
Host smart-825dad1f-f17f-4b65-a885-963a151004d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872550968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idle
.872550968
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.3079866566
Short name T496
Test name
Test status
Simulation time 583886812 ps
CPU time 5.28 seconds
Started Jul 25 06:37:33 PM PDT 24
Finished Jul 25 06:37:38 PM PDT 24
Peak memory 241012 kb
Host smart-e42cdece-3606-4cff-bcd7-e75ecde7d758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079866566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.3079866566
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.2182551217
Short name T578
Test name
Test status
Simulation time 9050818521 ps
CPU time 66.2 seconds
Started Jul 25 06:37:35 PM PDT 24
Finished Jul 25 06:38:41 PM PDT 24
Peak memory 249316 kb
Host smart-777438e2-d925-4caa-9bac-80be09456f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182551217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmd
s.2182551217
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_intercept.3190823276
Short name T207
Test name
Test status
Simulation time 1077279320 ps
CPU time 3.69 seconds
Started Jul 25 06:37:31 PM PDT 24
Finished Jul 25 06:37:35 PM PDT 24
Peak memory 224704 kb
Host smart-9b8326f0-c854-415e-99ff-c9f19354fbdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190823276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.3190823276
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.1797458969
Short name T807
Test name
Test status
Simulation time 3957896587 ps
CPU time 7.42 seconds
Started Jul 25 06:37:35 PM PDT 24
Finished Jul 25 06:37:42 PM PDT 24
Peak memory 224704 kb
Host smart-cfea4b1f-dbcc-43c6-9b6b-aab50e473827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797458969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.1797458969
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.3272542004
Short name T665
Test name
Test status
Simulation time 1495634315 ps
CPU time 3.08 seconds
Started Jul 25 06:37:24 PM PDT 24
Finished Jul 25 06:37:27 PM PDT 24
Peak memory 224600 kb
Host smart-844581e9-eec5-411a-bd42-8ad2e1dc2061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272542004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.3272542004
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.2069226244
Short name T197
Test name
Test status
Simulation time 11218152425 ps
CPU time 19.79 seconds
Started Jul 25 06:37:23 PM PDT 24
Finished Jul 25 06:37:43 PM PDT 24
Peak memory 232900 kb
Host smart-017b0028-39b2-4e9b-a5b4-64af2913d10e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069226244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.2069226244
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.915683125
Short name T413
Test name
Test status
Simulation time 1590586239 ps
CPU time 14.5 seconds
Started Jul 25 06:37:34 PM PDT 24
Finished Jul 25 06:37:49 PM PDT 24
Peak memory 222700 kb
Host smart-bfee97ac-97d8-4e09-8f82-2d68e5a7a61a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=915683125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dire
ct.915683125
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.2379653039
Short name T121
Test name
Test status
Simulation time 6283713919 ps
CPU time 103.58 seconds
Started Jul 25 06:37:32 PM PDT 24
Finished Jul 25 06:39:16 PM PDT 24
Peak memory 257604 kb
Host smart-663e8863-34a9-4248-b8a1-3507fb6ac2ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379653039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.2379653039
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.3047153178
Short name T439
Test name
Test status
Simulation time 5377133849 ps
CPU time 33.8 seconds
Started Jul 25 06:37:26 PM PDT 24
Finished Jul 25 06:38:00 PM PDT 24
Peak memory 216528 kb
Host smart-f4544023-42dc-4141-9946-acd5a6573ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047153178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.3047153178
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.1031167562
Short name T863
Test name
Test status
Simulation time 573761578 ps
CPU time 3.01 seconds
Started Jul 25 06:37:21 PM PDT 24
Finished Jul 25 06:37:24 PM PDT 24
Peak memory 216420 kb
Host smart-a9d3d59d-d27a-47ef-8a3b-095abae8e05d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031167562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.1031167562
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.2213236057
Short name T775
Test name
Test status
Simulation time 352869483 ps
CPU time 1.27 seconds
Started Jul 25 06:37:26 PM PDT 24
Finished Jul 25 06:37:28 PM PDT 24
Peak memory 208052 kb
Host smart-a1b1efa9-ebc5-4d10-a46b-74e156566f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213236057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.2213236057
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.2989152537
Short name T554
Test name
Test status
Simulation time 19889533 ps
CPU time 0.8 seconds
Started Jul 25 06:37:23 PM PDT 24
Finished Jul 25 06:37:24 PM PDT 24
Peak memory 206092 kb
Host smart-0f269075-9629-423b-aba2-2596823a7e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989152537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.2989152537
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.2251587369
Short name T749
Test name
Test status
Simulation time 7795819391 ps
CPU time 7.37 seconds
Started Jul 25 06:37:35 PM PDT 24
Finished Jul 25 06:37:42 PM PDT 24
Peak memory 224668 kb
Host smart-f686cfef-72c5-46dc-8f11-2d3c0f862862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251587369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.2251587369
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.3742701934
Short name T937
Test name
Test status
Simulation time 18195549 ps
CPU time 0.75 seconds
Started Jul 25 06:37:34 PM PDT 24
Finished Jul 25 06:37:35 PM PDT 24
Peak memory 205600 kb
Host smart-6047ffd8-f64e-4d48-a8fc-b24557e9d851
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742701934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
3742701934
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.2528965404
Short name T231
Test name
Test status
Simulation time 544030070 ps
CPU time 3.76 seconds
Started Jul 25 06:37:32 PM PDT 24
Finished Jul 25 06:37:36 PM PDT 24
Peak memory 224664 kb
Host smart-3f44a7a4-7a0c-4650-b514-cf6a44cc30c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528965404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.2528965404
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.4283073403
Short name T380
Test name
Test status
Simulation time 30295894 ps
CPU time 0.83 seconds
Started Jul 25 06:37:32 PM PDT 24
Finished Jul 25 06:37:33 PM PDT 24
Peak memory 206036 kb
Host smart-d7ba104f-80e4-4224-a4e3-27d21b55cf0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283073403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.4283073403
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.2083702949
Short name T751
Test name
Test status
Simulation time 2273395776 ps
CPU time 16.69 seconds
Started Jul 25 06:37:31 PM PDT 24
Finished Jul 25 06:37:48 PM PDT 24
Peak memory 241140 kb
Host smart-bd09c500-ce34-4927-aa0a-bf834e9842b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083702949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.2083702949
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.1682122049
Short name T908
Test name
Test status
Simulation time 35733253007 ps
CPU time 97.23 seconds
Started Jul 25 06:37:32 PM PDT 24
Finished Jul 25 06:39:10 PM PDT 24
Peak memory 257568 kb
Host smart-8186d259-61bf-433a-a6d0-cd9cfc023f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682122049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.1682122049
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.3449398399
Short name T199
Test name
Test status
Simulation time 1030383730 ps
CPU time 19.13 seconds
Started Jul 25 06:37:36 PM PDT 24
Finished Jul 25 06:37:55 PM PDT 24
Peak memory 232976 kb
Host smart-2b63c7b6-178f-4d48-8153-9ed770b8c861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449398399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.3449398399
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.3624896969
Short name T975
Test name
Test status
Simulation time 6679776958 ps
CPU time 53.28 seconds
Started Jul 25 06:37:34 PM PDT 24
Finished Jul 25 06:38:27 PM PDT 24
Peak memory 254640 kb
Host smart-0de17fac-b7ae-49e8-a8ab-8aab08aec519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624896969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmd
s.3624896969
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_intercept.1720984830
Short name T566
Test name
Test status
Simulation time 496640352 ps
CPU time 4.17 seconds
Started Jul 25 06:37:33 PM PDT 24
Finished Jul 25 06:37:38 PM PDT 24
Peak memory 224704 kb
Host smart-8b5f0c0d-697e-4ca6-819b-e174166b1049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720984830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.1720984830
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.2858270506
Short name T390
Test name
Test status
Simulation time 12163868469 ps
CPU time 33.01 seconds
Started Jul 25 06:37:35 PM PDT 24
Finished Jul 25 06:38:08 PM PDT 24
Peak memory 232968 kb
Host smart-b5be6b31-4a85-4497-a6ab-898372da534c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858270506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.2858270506
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.3471157195
Short name T636
Test name
Test status
Simulation time 606694970 ps
CPU time 3.41 seconds
Started Jul 25 06:37:31 PM PDT 24
Finished Jul 25 06:37:35 PM PDT 24
Peak memory 224660 kb
Host smart-ee8fd065-361c-43c5-960f-5659bdd987af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471157195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.3471157195
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.462040176
Short name T1001
Test name
Test status
Simulation time 3839512781 ps
CPU time 13.18 seconds
Started Jul 25 06:37:33 PM PDT 24
Finished Jul 25 06:37:47 PM PDT 24
Peak memory 237512 kb
Host smart-50a4e495-f911-4995-97ff-27d4806f4280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462040176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.462040176
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.833841826
Short name T623
Test name
Test status
Simulation time 585623493 ps
CPU time 7.46 seconds
Started Jul 25 06:37:35 PM PDT 24
Finished Jul 25 06:37:43 PM PDT 24
Peak memory 219052 kb
Host smart-0e85a8ea-b3f0-462c-9737-e0d0a180d8cf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=833841826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dire
ct.833841826
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.3832814662
Short name T140
Test name
Test status
Simulation time 15295916517 ps
CPU time 109.93 seconds
Started Jul 25 06:37:36 PM PDT 24
Finished Jul 25 06:39:27 PM PDT 24
Peak memory 252292 kb
Host smart-ec0a1de8-d08d-46c4-a980-fecc0be3be45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832814662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.3832814662
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.1962846812
Short name T851
Test name
Test status
Simulation time 8726841213 ps
CPU time 14.07 seconds
Started Jul 25 06:37:34 PM PDT 24
Finished Jul 25 06:37:49 PM PDT 24
Peak memory 216552 kb
Host smart-ede29708-0a1d-4a48-81ff-7a68005c1f74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962846812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.1962846812
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.989870377
Short name T822
Test name
Test status
Simulation time 771381422 ps
CPU time 2.49 seconds
Started Jul 25 06:37:33 PM PDT 24
Finished Jul 25 06:37:36 PM PDT 24
Peak memory 216400 kb
Host smart-772948d5-b58f-457b-adb4-0d8e540b1fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989870377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.989870377
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.1251723308
Short name T356
Test name
Test status
Simulation time 616948324 ps
CPU time 9.38 seconds
Started Jul 25 06:37:34 PM PDT 24
Finished Jul 25 06:37:43 PM PDT 24
Peak memory 216452 kb
Host smart-dbc0286a-1159-41a8-8bcd-6281181c0362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251723308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.1251723308
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.3898336015
Short name T771
Test name
Test status
Simulation time 27981350 ps
CPU time 0.75 seconds
Started Jul 25 06:37:36 PM PDT 24
Finished Jul 25 06:37:37 PM PDT 24
Peak memory 206084 kb
Host smart-642aed4d-ec63-4648-bf2e-85f6aae7b77d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898336015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.3898336015
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.3623973460
Short name T979
Test name
Test status
Simulation time 859040999 ps
CPU time 5 seconds
Started Jul 25 06:37:33 PM PDT 24
Finished Jul 25 06:37:38 PM PDT 24
Peak memory 232856 kb
Host smart-a55105f9-6813-4c91-8206-cf8ae92a2ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623973460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.3623973460
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.2491982694
Short name T592
Test name
Test status
Simulation time 13990517 ps
CPU time 0.75 seconds
Started Jul 25 06:37:42 PM PDT 24
Finished Jul 25 06:37:43 PM PDT 24
Peak memory 205572 kb
Host smart-adaa0fa9-a398-4ee5-b549-830914b965f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491982694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
2491982694
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.770487642
Short name T359
Test name
Test status
Simulation time 756930462 ps
CPU time 4.9 seconds
Started Jul 25 06:37:32 PM PDT 24
Finished Jul 25 06:37:37 PM PDT 24
Peak memory 224720 kb
Host smart-8ed4f499-0761-40bb-a9eb-b2b13d8c3947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770487642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.770487642
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.2376172723
Short name T13
Test name
Test status
Simulation time 72583171 ps
CPU time 0.85 seconds
Started Jul 25 06:37:34 PM PDT 24
Finished Jul 25 06:37:35 PM PDT 24
Peak memory 206536 kb
Host smart-1c6bc2c9-498a-45d9-82ed-d336df2329ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376172723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.2376172723
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.3208509424
Short name T798
Test name
Test status
Simulation time 85681515095 ps
CPU time 184.85 seconds
Started Jul 25 06:37:31 PM PDT 24
Finished Jul 25 06:40:36 PM PDT 24
Peak memory 256076 kb
Host smart-73d44490-f474-4114-8606-0f3b0a19fb4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208509424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.3208509424
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.2708721542
Short name T182
Test name
Test status
Simulation time 31052157104 ps
CPU time 90.71 seconds
Started Jul 25 06:37:32 PM PDT 24
Finished Jul 25 06:39:03 PM PDT 24
Peak memory 256600 kb
Host smart-cde26948-0c0f-4489-84e9-afef8d64e0bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708721542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.2708721542
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.1448737871
Short name T174
Test name
Test status
Simulation time 52346737150 ps
CPU time 247.17 seconds
Started Jul 25 06:37:38 PM PDT 24
Finished Jul 25 06:41:45 PM PDT 24
Peak memory 254068 kb
Host smart-51942542-5116-4eef-b2b6-7507ae04a883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448737871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.1448737871
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.3436063724
Short name T456
Test name
Test status
Simulation time 4000632635 ps
CPU time 10.78 seconds
Started Jul 25 06:37:35 PM PDT 24
Finished Jul 25 06:37:46 PM PDT 24
Peak memory 239668 kb
Host smart-a7b2164b-0aab-4a18-980a-a933969fe5dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436063724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.3436063724
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.3858193637
Short name T683
Test name
Test status
Simulation time 74088868 ps
CPU time 0.91 seconds
Started Jul 25 06:37:36 PM PDT 24
Finished Jul 25 06:37:37 PM PDT 24
Peak memory 216112 kb
Host smart-c4cf5fc4-8421-4e17-9a6f-23c1445d9cec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858193637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmd
s.3858193637
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_intercept.2119307021
Short name T608
Test name
Test status
Simulation time 260698294 ps
CPU time 3.4 seconds
Started Jul 25 06:37:34 PM PDT 24
Finished Jul 25 06:37:38 PM PDT 24
Peak memory 224636 kb
Host smart-a3e90653-f6b0-4c69-b487-d5b20b037eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119307021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.2119307021
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.3233506229
Short name T256
Test name
Test status
Simulation time 16517912983 ps
CPU time 51.12 seconds
Started Jul 25 06:37:34 PM PDT 24
Finished Jul 25 06:38:25 PM PDT 24
Peak memory 232856 kb
Host smart-9002e592-afcb-43b6-84d1-71f5db7bcd99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233506229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.3233506229
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.3655859732
Short name T915
Test name
Test status
Simulation time 598124854 ps
CPU time 4.31 seconds
Started Jul 25 06:37:33 PM PDT 24
Finished Jul 25 06:37:38 PM PDT 24
Peak memory 224604 kb
Host smart-294abd97-16fe-41b5-b069-0e8d80ad06b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655859732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.3655859732
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.1029649724
Short name T669
Test name
Test status
Simulation time 17970050360 ps
CPU time 10.83 seconds
Started Jul 25 06:37:34 PM PDT 24
Finished Jul 25 06:37:45 PM PDT 24
Peak memory 224764 kb
Host smart-5a7f8a71-5472-4d91-baf4-744063a35cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029649724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.1029649724
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.2534313493
Short name T609
Test name
Test status
Simulation time 110873041 ps
CPU time 3.35 seconds
Started Jul 25 06:37:31 PM PDT 24
Finished Jul 25 06:37:35 PM PDT 24
Peak memory 223184 kb
Host smart-8fb1051e-a84e-4199-a828-f7c365019d94
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2534313493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.2534313493
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.3123722439
Short name T141
Test name
Test status
Simulation time 17081446663 ps
CPU time 164.98 seconds
Started Jul 25 06:37:39 PM PDT 24
Finished Jul 25 06:40:24 PM PDT 24
Peak memory 270352 kb
Host smart-50d6bd7c-8b80-437b-aa2a-4edf91137f2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123722439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.3123722439
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.3493451424
Short name T606
Test name
Test status
Simulation time 1454942980 ps
CPU time 8.74 seconds
Started Jul 25 06:37:33 PM PDT 24
Finished Jul 25 06:37:42 PM PDT 24
Peak memory 216440 kb
Host smart-49542921-ddca-49d3-a401-98f9943f1543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493451424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.3493451424
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.3159061750
Short name T717
Test name
Test status
Simulation time 11076201 ps
CPU time 0.72 seconds
Started Jul 25 06:37:33 PM PDT 24
Finished Jul 25 06:37:34 PM PDT 24
Peak memory 205824 kb
Host smart-39b71b59-f5cf-481e-816d-2f3ada37361f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159061750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.3159061750
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.2431738549
Short name T383
Test name
Test status
Simulation time 110501279 ps
CPU time 6.5 seconds
Started Jul 25 06:37:34 PM PDT 24
Finished Jul 25 06:37:40 PM PDT 24
Peak memory 216384 kb
Host smart-bb9d9013-dd99-4290-bb67-65288ab48289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431738549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.2431738549
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.1475698330
Short name T831
Test name
Test status
Simulation time 74032781 ps
CPU time 0.99 seconds
Started Jul 25 06:37:34 PM PDT 24
Finished Jul 25 06:37:35 PM PDT 24
Peak memory 206080 kb
Host smart-8329d43c-f636-49f4-b1a5-52eacb9e2564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475698330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.1475698330
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.624574478
Short name T731
Test name
Test status
Simulation time 78704296 ps
CPU time 2.54 seconds
Started Jul 25 06:37:33 PM PDT 24
Finished Jul 25 06:37:36 PM PDT 24
Peak memory 232916 kb
Host smart-602b8147-fc00-4e98-b17d-702cfb62502b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624574478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.624574478
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.27020902
Short name T539
Test name
Test status
Simulation time 13237419 ps
CPU time 0.75 seconds
Started Jul 25 06:37:45 PM PDT 24
Finished Jul 25 06:37:46 PM PDT 24
Peak memory 205008 kb
Host smart-cecb973a-1e6a-478d-ac4e-8ea201599511
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27020902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.27020902
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.2359506046
Short name T229
Test name
Test status
Simulation time 50258131 ps
CPU time 2.4 seconds
Started Jul 25 06:37:39 PM PDT 24
Finished Jul 25 06:37:41 PM PDT 24
Peak memory 224648 kb
Host smart-f429c21c-28d9-474f-ac60-d201083be74f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359506046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.2359506046
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.2301707033
Short name T446
Test name
Test status
Simulation time 24417846 ps
CPU time 0.8 seconds
Started Jul 25 06:37:40 PM PDT 24
Finished Jul 25 06:37:41 PM PDT 24
Peak memory 206744 kb
Host smart-4331901e-cd96-4138-bcda-640a72bf6cd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301707033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.2301707033
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.2425141401
Short name T397
Test name
Test status
Simulation time 1787611013 ps
CPU time 11.02 seconds
Started Jul 25 06:37:40 PM PDT 24
Finished Jul 25 06:37:52 PM PDT 24
Peak memory 224652 kb
Host smart-57556fad-20ed-4df9-a660-973af475e0b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425141401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.2425141401
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.1163706854
Short name T15
Test name
Test status
Simulation time 7397258781 ps
CPU time 68.34 seconds
Started Jul 25 06:37:38 PM PDT 24
Finished Jul 25 06:38:46 PM PDT 24
Peak memory 249104 kb
Host smart-7d709b5b-6fe4-4c32-9850-55ad9b612ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163706854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.1163706854
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.3217634173
Short name T518
Test name
Test status
Simulation time 2222092317 ps
CPU time 39.72 seconds
Started Jul 25 06:37:41 PM PDT 24
Finished Jul 25 06:38:21 PM PDT 24
Peak memory 241180 kb
Host smart-1591dcff-86f2-41a9-90d8-50fb97289ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217634173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.3217634173
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.446510440
Short name T995
Test name
Test status
Simulation time 2825784951 ps
CPU time 41.07 seconds
Started Jul 25 06:37:38 PM PDT 24
Finished Jul 25 06:38:19 PM PDT 24
Peak memory 232960 kb
Host smart-b726b8b5-0bcc-459c-af60-65b72ca85076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446510440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.446510440
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.845095943
Short name T220
Test name
Test status
Simulation time 19422139023 ps
CPU time 105.77 seconds
Started Jul 25 06:37:40 PM PDT 24
Finished Jul 25 06:39:25 PM PDT 24
Peak memory 249360 kb
Host smart-42c719eb-23a1-4c26-b2c2-4ab86952ede7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845095943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmds
.845095943
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_intercept.4037904256
Short name T528
Test name
Test status
Simulation time 358930889 ps
CPU time 4.59 seconds
Started Jul 25 06:37:40 PM PDT 24
Finished Jul 25 06:37:45 PM PDT 24
Peak memory 232916 kb
Host smart-df7f37dd-2106-4708-b861-e7f535b8aa3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037904256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.4037904256
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.1204129295
Short name T745
Test name
Test status
Simulation time 740856346 ps
CPU time 2.55 seconds
Started Jul 25 06:37:41 PM PDT 24
Finished Jul 25 06:37:43 PM PDT 24
Peak memory 224696 kb
Host smart-30502472-ff82-4752-b53a-7b19ca4851be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204129295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.1204129295
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.2963267384
Short name T682
Test name
Test status
Simulation time 434238147 ps
CPU time 4.1 seconds
Started Jul 25 06:37:40 PM PDT 24
Finished Jul 25 06:37:44 PM PDT 24
Peak memory 232948 kb
Host smart-e398dcc4-8d82-4a56-8419-620fb670c17c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963267384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.2963267384
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.4164048986
Short name T571
Test name
Test status
Simulation time 6912297389 ps
CPU time 10.87 seconds
Started Jul 25 06:37:40 PM PDT 24
Finished Jul 25 06:37:51 PM PDT 24
Peak memory 240784 kb
Host smart-09f03ee8-d7d9-4b5a-9197-0272a8e342e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164048986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.4164048986
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.3801398707
Short name T478
Test name
Test status
Simulation time 1444483637 ps
CPU time 15.52 seconds
Started Jul 25 06:37:42 PM PDT 24
Finished Jul 25 06:37:57 PM PDT 24
Peak memory 222304 kb
Host smart-abe051e2-bafc-4e25-a463-a63c49e33b7a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3801398707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.3801398707
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.1756067461
Short name T1000
Test name
Test status
Simulation time 556118608 ps
CPU time 9.43 seconds
Started Jul 25 06:37:39 PM PDT 24
Finished Jul 25 06:37:49 PM PDT 24
Peak memory 219100 kb
Host smart-4a92de65-9427-4f9b-b84d-3136d53da5ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756067461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.1756067461
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.2290607848
Short name T941
Test name
Test status
Simulation time 1087831599 ps
CPU time 3.89 seconds
Started Jul 25 06:37:42 PM PDT 24
Finished Jul 25 06:37:46 PM PDT 24
Peak memory 216416 kb
Host smart-a2ce8993-0e36-4870-830c-c18491e0ab86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290607848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.2290607848
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.1211671301
Short name T899
Test name
Test status
Simulation time 143655631 ps
CPU time 1.84 seconds
Started Jul 25 06:37:44 PM PDT 24
Finished Jul 25 06:37:46 PM PDT 24
Peak memory 216408 kb
Host smart-6bd44f46-911f-4ebf-8ec9-21887c8cdbcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211671301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.1211671301
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.599646003
Short name T604
Test name
Test status
Simulation time 82986832 ps
CPU time 0.86 seconds
Started Jul 25 06:37:40 PM PDT 24
Finished Jul 25 06:37:41 PM PDT 24
Peak memory 206112 kb
Host smart-ee9c1490-08cb-4e03-b6a3-9e3a6c3ffe86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599646003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.599646003
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.3348645381
Short name T430
Test name
Test status
Simulation time 199299755 ps
CPU time 2.53 seconds
Started Jul 25 06:37:41 PM PDT 24
Finished Jul 25 06:37:44 PM PDT 24
Peak memory 232916 kb
Host smart-738c026c-eed9-4087-8a6f-edd95e4d198e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348645381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.3348645381
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.20171780
Short name T653
Test name
Test status
Simulation time 28156579 ps
CPU time 0.78 seconds
Started Jul 25 06:37:43 PM PDT 24
Finished Jul 25 06:37:44 PM PDT 24
Peak memory 205052 kb
Host smart-ea41b739-bd2c-4280-911a-7b9504796b58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20171780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.20171780
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.2916630426
Short name T251
Test name
Test status
Simulation time 983694693 ps
CPU time 9.87 seconds
Started Jul 25 06:37:38 PM PDT 24
Finished Jul 25 06:37:48 PM PDT 24
Peak memory 224688 kb
Host smart-0d512d42-148f-4db9-ba4c-a9da2d14417a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916630426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.2916630426
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.2345484863
Short name T523
Test name
Test status
Simulation time 27874375 ps
CPU time 0.74 seconds
Started Jul 25 06:37:39 PM PDT 24
Finished Jul 25 06:37:40 PM PDT 24
Peak memory 207060 kb
Host smart-7fb8b301-d073-4827-a2ad-773e447ee6fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345484863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.2345484863
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.3844708485
Short name T240
Test name
Test status
Simulation time 51246444628 ps
CPU time 111.35 seconds
Started Jul 25 06:37:41 PM PDT 24
Finished Jul 25 06:39:32 PM PDT 24
Peak memory 253612 kb
Host smart-d60b9846-0c7a-4dbb-8255-b5bde2851c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844708485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.3844708485
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.2038616253
Short name T282
Test name
Test status
Simulation time 29785166187 ps
CPU time 278.76 seconds
Started Jul 25 06:37:43 PM PDT 24
Finished Jul 25 06:42:22 PM PDT 24
Peak memory 250876 kb
Host smart-7b6dedad-5640-4c8c-98cc-4e069d2c8cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038616253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.2038616253
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.2518209297
Short name T613
Test name
Test status
Simulation time 8428437145 ps
CPU time 64.61 seconds
Started Jul 25 06:37:42 PM PDT 24
Finished Jul 25 06:38:47 PM PDT 24
Peak memory 257596 kb
Host smart-ca7de661-4a79-4b26-9498-b15e0a4e09d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518209297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.2518209297
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.3575409353
Short name T903
Test name
Test status
Simulation time 977174887 ps
CPU time 21.55 seconds
Started Jul 25 06:37:39 PM PDT 24
Finished Jul 25 06:38:01 PM PDT 24
Peak memory 241044 kb
Host smart-13370175-9088-4e3e-a8a9-7476be97ff1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575409353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.3575409353
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.1022129232
Short name T935
Test name
Test status
Simulation time 1404350307 ps
CPU time 23.2 seconds
Started Jul 25 06:37:40 PM PDT 24
Finished Jul 25 06:38:04 PM PDT 24
Peak memory 241048 kb
Host smart-8afaf0e2-b3d1-49cb-bd33-0e67948faf12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022129232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmd
s.1022129232
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/24.spi_device_intercept.2102632035
Short name T833
Test name
Test status
Simulation time 31954315 ps
CPU time 2.03 seconds
Started Jul 25 06:37:43 PM PDT 24
Finished Jul 25 06:37:45 PM PDT 24
Peak memory 223348 kb
Host smart-ba1cb5c7-21a1-4923-aacd-0b39be25e447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102632035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.2102632035
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.1080754503
Short name T378
Test name
Test status
Simulation time 25114835865 ps
CPU time 100.52 seconds
Started Jul 25 06:37:44 PM PDT 24
Finished Jul 25 06:39:24 PM PDT 24
Peak memory 232968 kb
Host smart-544ebec5-d68e-4fe2-801d-d08db323e9e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080754503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.1080754503
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.1936278700
Short name T869
Test name
Test status
Simulation time 103866171 ps
CPU time 2.79 seconds
Started Jul 25 06:37:41 PM PDT 24
Finished Jul 25 06:37:44 PM PDT 24
Peak memory 232892 kb
Host smart-cce3a0a0-cf1c-42f8-8462-970ed9a2d6dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936278700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.1936278700
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.1671346362
Short name T845
Test name
Test status
Simulation time 489987031 ps
CPU time 4.85 seconds
Started Jul 25 06:37:41 PM PDT 24
Finished Jul 25 06:37:46 PM PDT 24
Peak memory 224672 kb
Host smart-7cf7d723-b7d4-425e-b3ec-7bcf7277d219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671346362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.1671346362
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.3132337123
Short name T574
Test name
Test status
Simulation time 3411509168 ps
CPU time 9.83 seconds
Started Jul 25 06:37:40 PM PDT 24
Finished Jul 25 06:37:50 PM PDT 24
Peak memory 222864 kb
Host smart-2a70c0c1-d5a6-4e2f-b46d-935954b5a6ea
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3132337123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.3132337123
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.3080616805
Short name T143
Test name
Test status
Simulation time 159346865 ps
CPU time 0.91 seconds
Started Jul 25 06:37:39 PM PDT 24
Finished Jul 25 06:37:40 PM PDT 24
Peak memory 205784 kb
Host smart-a9950afe-7ca8-48d8-8ebb-9b48a293fe10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080616805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.3080616805
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.1819421367
Short name T593
Test name
Test status
Simulation time 733310501 ps
CPU time 5.79 seconds
Started Jul 25 06:37:40 PM PDT 24
Finished Jul 25 06:37:46 PM PDT 24
Peak memory 216688 kb
Host smart-3cfba660-ed89-43fc-9315-0594409c75e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819421367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.1819421367
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.592465943
Short name T597
Test name
Test status
Simulation time 27023555854 ps
CPU time 16.67 seconds
Started Jul 25 06:37:40 PM PDT 24
Finished Jul 25 06:37:57 PM PDT 24
Peak memory 217500 kb
Host smart-bc36be90-eba8-47b6-967b-05d67bbf6178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592465943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.592465943
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.3021969694
Short name T315
Test name
Test status
Simulation time 295956397 ps
CPU time 1.74 seconds
Started Jul 25 06:37:40 PM PDT 24
Finished Jul 25 06:37:42 PM PDT 24
Peak memory 216388 kb
Host smart-c97fc6b0-688b-4478-bfaa-8de79ef61f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021969694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.3021969694
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.960555854
Short name T550
Test name
Test status
Simulation time 13317517 ps
CPU time 0.72 seconds
Started Jul 25 06:37:38 PM PDT 24
Finished Jul 25 06:37:39 PM PDT 24
Peak memory 205748 kb
Host smart-b92f6970-dcc5-4815-821f-2c85a32d5df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960555854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.960555854
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.995702779
Short name T254
Test name
Test status
Simulation time 2835013976 ps
CPU time 9.04 seconds
Started Jul 25 06:37:37 PM PDT 24
Finished Jul 25 06:37:46 PM PDT 24
Peak memory 224712 kb
Host smart-0cdfec02-8bf2-4ba1-a5d5-a5176a241031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995702779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.995702779
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.3165550342
Short name T659
Test name
Test status
Simulation time 20972382 ps
CPU time 0.74 seconds
Started Jul 25 06:37:49 PM PDT 24
Finished Jul 25 06:37:50 PM PDT 24
Peak memory 205508 kb
Host smart-1034b89b-4a7e-45f0-b703-c517b5adc2e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165550342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
3165550342
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.1487140799
Short name T727
Test name
Test status
Simulation time 3548952951 ps
CPU time 11.6 seconds
Started Jul 25 06:37:47 PM PDT 24
Finished Jul 25 06:37:58 PM PDT 24
Peak memory 232968 kb
Host smart-93ee4aa3-26a0-4e6c-927b-d60c9250520e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487140799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.1487140799
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.3479335746
Short name T913
Test name
Test status
Simulation time 13694740 ps
CPU time 0.81 seconds
Started Jul 25 06:37:48 PM PDT 24
Finished Jul 25 06:37:49 PM PDT 24
Peak memory 206736 kb
Host smart-a234cbdc-ecd2-441a-89f7-ba0e160932e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479335746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.3479335746
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.3869241096
Short name T264
Test name
Test status
Simulation time 36066672992 ps
CPU time 297.36 seconds
Started Jul 25 06:37:49 PM PDT 24
Finished Jul 25 06:42:46 PM PDT 24
Peak memory 271268 kb
Host smart-f66b5f85-5d63-463f-bd42-e232648ff47f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869241096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.3869241096
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.2906374345
Short name T585
Test name
Test status
Simulation time 5010745908 ps
CPU time 63.76 seconds
Started Jul 25 06:37:46 PM PDT 24
Finished Jul 25 06:38:50 PM PDT 24
Peak memory 252656 kb
Host smart-fdc4b06e-7114-4bfe-b4e5-b42bb224dc0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906374345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.2906374345
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.2448932980
Short name T25
Test name
Test status
Simulation time 458510559 ps
CPU time 5.56 seconds
Started Jul 25 06:37:45 PM PDT 24
Finished Jul 25 06:37:51 PM PDT 24
Peak memory 219940 kb
Host smart-0915661b-b561-49a1-a406-1f75171bd597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448932980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.2448932980
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.4198871916
Short name T277
Test name
Test status
Simulation time 16843803994 ps
CPU time 108.13 seconds
Started Jul 25 06:37:49 PM PDT 24
Finished Jul 25 06:39:37 PM PDT 24
Peak memory 257540 kb
Host smart-9831a653-65ab-429f-a08a-662438d6b912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198871916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmd
s.4198871916
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_intercept.2657996026
Short name T184
Test name
Test status
Simulation time 2115105856 ps
CPU time 19.98 seconds
Started Jul 25 06:37:48 PM PDT 24
Finished Jul 25 06:38:08 PM PDT 24
Peak memory 224716 kb
Host smart-b79eaf40-0cc8-46c6-98d1-b5f6a1047dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657996026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.2657996026
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.290802023
Short name T561
Test name
Test status
Simulation time 112228543 ps
CPU time 2.44 seconds
Started Jul 25 06:37:45 PM PDT 24
Finished Jul 25 06:37:48 PM PDT 24
Peak memory 232536 kb
Host smart-0a42223e-8e29-45ae-a44f-024159f71795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290802023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.290802023
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.3369270817
Short name T943
Test name
Test status
Simulation time 172326101288 ps
CPU time 41.33 seconds
Started Jul 25 06:37:49 PM PDT 24
Finished Jul 25 06:38:30 PM PDT 24
Peak memory 232976 kb
Host smart-e8ba11f2-5ec0-4353-a481-eff624e06a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369270817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.3369270817
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.3051574327
Short name T470
Test name
Test status
Simulation time 2577572693 ps
CPU time 7.65 seconds
Started Jul 25 06:37:49 PM PDT 24
Finished Jul 25 06:37:57 PM PDT 24
Peak memory 224764 kb
Host smart-00225e92-7829-4ee8-acba-52ea1f2be451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051574327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.3051574327
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.2028793347
Short name T821
Test name
Test status
Simulation time 155502245 ps
CPU time 3.39 seconds
Started Jul 25 06:37:45 PM PDT 24
Finished Jul 25 06:37:48 PM PDT 24
Peak memory 223244 kb
Host smart-b467b474-4ee7-4f2c-8acc-a1a1d8d7d09d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2028793347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.2028793347
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.4199363269
Short name T142
Test name
Test status
Simulation time 192527404 ps
CPU time 0.98 seconds
Started Jul 25 06:37:45 PM PDT 24
Finished Jul 25 06:37:46 PM PDT 24
Peak memory 206736 kb
Host smart-e14ba4e6-c582-4fb4-8884-89e15bbeb788
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199363269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.4199363269
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.1951296992
Short name T558
Test name
Test status
Simulation time 4541165656 ps
CPU time 23.62 seconds
Started Jul 25 06:37:49 PM PDT 24
Finished Jul 25 06:38:12 PM PDT 24
Peak memory 216468 kb
Host smart-7c29c067-a641-47ea-9fcb-2b9a13659f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951296992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.1951296992
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.2988832425
Short name T972
Test name
Test status
Simulation time 38968029 ps
CPU time 0.71 seconds
Started Jul 25 06:37:47 PM PDT 24
Finished Jul 25 06:37:48 PM PDT 24
Peak memory 205832 kb
Host smart-94ee3333-bde0-4a65-9d6c-86d492c7ed13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988832425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.2988832425
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.4035951482
Short name T489
Test name
Test status
Simulation time 13990159 ps
CPU time 0.78 seconds
Started Jul 25 06:37:47 PM PDT 24
Finished Jul 25 06:37:48 PM PDT 24
Peak memory 207124 kb
Host smart-5bc1f9dc-326a-4852-982f-fcb4450d7644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035951482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.4035951482
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.3472101466
Short name T880
Test name
Test status
Simulation time 37683789 ps
CPU time 0.8 seconds
Started Jul 25 06:37:46 PM PDT 24
Finished Jul 25 06:37:47 PM PDT 24
Peak memory 206092 kb
Host smart-3ffb78a4-c96e-4ccd-a500-943ee9c69ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472101466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.3472101466
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.4196840884
Short name T514
Test name
Test status
Simulation time 472942890 ps
CPU time 2.37 seconds
Started Jul 25 06:37:45 PM PDT 24
Finished Jul 25 06:37:48 PM PDT 24
Peak memory 224392 kb
Host smart-99d2fa3c-d1df-458f-86ac-c4983d5e0b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196840884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.4196840884
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.2515397661
Short name T320
Test name
Test status
Simulation time 12629615 ps
CPU time 0.73 seconds
Started Jul 25 06:37:58 PM PDT 24
Finished Jul 25 06:37:59 PM PDT 24
Peak memory 205032 kb
Host smart-5c7fde58-24fe-4904-9515-b3511df628a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515397661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
2515397661
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.1966867380
Short name T387
Test name
Test status
Simulation time 613276153 ps
CPU time 6.09 seconds
Started Jul 25 06:38:01 PM PDT 24
Finished Jul 25 06:38:07 PM PDT 24
Peak memory 224624 kb
Host smart-b1628773-569b-4401-b37a-b79b699ca38f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966867380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.1966867380
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.3342101289
Short name T743
Test name
Test status
Simulation time 71249983 ps
CPU time 0.76 seconds
Started Jul 25 06:37:46 PM PDT 24
Finished Jul 25 06:37:47 PM PDT 24
Peak memory 205728 kb
Host smart-b4fe550d-94cb-4147-9502-47d827378c3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342101289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.3342101289
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.3534752698
Short name T757
Test name
Test status
Simulation time 4516255772 ps
CPU time 44.88 seconds
Started Jul 25 06:37:55 PM PDT 24
Finished Jul 25 06:38:40 PM PDT 24
Peak memory 257536 kb
Host smart-d28c912d-b958-43a7-b1c0-5b86ce29d710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534752698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.3534752698
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.3151636101
Short name T961
Test name
Test status
Simulation time 35449020540 ps
CPU time 315.2 seconds
Started Jul 25 06:37:57 PM PDT 24
Finished Jul 25 06:43:12 PM PDT 24
Peak memory 257640 kb
Host smart-f384278b-a629-4bb0-ab6e-2cc204379023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151636101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.3151636101
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.2600094282
Short name T806
Test name
Test status
Simulation time 7463984976 ps
CPU time 123.33 seconds
Started Jul 25 06:37:58 PM PDT 24
Finished Jul 25 06:40:01 PM PDT 24
Peak memory 257600 kb
Host smart-1074e5bc-5576-44c7-b1bb-f77c069865c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600094282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.2600094282
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.3676815968
Short name T291
Test name
Test status
Simulation time 192014082 ps
CPU time 4.94 seconds
Started Jul 25 06:37:57 PM PDT 24
Finished Jul 25 06:38:02 PM PDT 24
Peak memory 241108 kb
Host smart-a4a9b148-1f7a-4921-9071-f8a036636775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676815968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.3676815968
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.95529418
Short name T805
Test name
Test status
Simulation time 2195012747 ps
CPU time 10.98 seconds
Started Jul 25 06:37:56 PM PDT 24
Finished Jul 25 06:38:08 PM PDT 24
Peak memory 234216 kb
Host smart-863922ba-2b21-40e5-a3d4-8a81e9b85670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95529418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmds.95529418
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_intercept.3487667600
Short name T709
Test name
Test status
Simulation time 200896687 ps
CPU time 5.37 seconds
Started Jul 25 06:37:49 PM PDT 24
Finished Jul 25 06:37:54 PM PDT 24
Peak memory 232856 kb
Host smart-e3ce209c-b805-4606-a3a5-d6379c0ef581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487667600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.3487667600
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.2029892951
Short name T711
Test name
Test status
Simulation time 754807160 ps
CPU time 5.45 seconds
Started Jul 25 06:37:56 PM PDT 24
Finished Jul 25 06:38:02 PM PDT 24
Peak memory 232912 kb
Host smart-2a5ab029-3c96-4307-aa09-6b20389d5978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029892951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.2029892951
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.3700670108
Short name T761
Test name
Test status
Simulation time 1479944766 ps
CPU time 5.67 seconds
Started Jul 25 06:37:48 PM PDT 24
Finished Jul 25 06:37:54 PM PDT 24
Peak memory 232912 kb
Host smart-33fa712f-2b04-4e6a-b491-872454f81b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700670108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.3700670108
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.2303199445
Short name T86
Test name
Test status
Simulation time 8680597533 ps
CPU time 27.09 seconds
Started Jul 25 06:37:45 PM PDT 24
Finished Jul 25 06:38:12 PM PDT 24
Peak memory 232916 kb
Host smart-288e8c53-e639-4d9e-943b-77c892f0982e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303199445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.2303199445
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.141528449
Short name T794
Test name
Test status
Simulation time 2373328052 ps
CPU time 14.39 seconds
Started Jul 25 06:37:58 PM PDT 24
Finished Jul 25 06:38:12 PM PDT 24
Peak memory 220664 kb
Host smart-eb25d3e9-d32f-4a48-9ebe-87f7bc5614f1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=141528449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dire
ct.141528449
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.2662669489
Short name T708
Test name
Test status
Simulation time 55684046 ps
CPU time 1.03 seconds
Started Jul 25 06:37:54 PM PDT 24
Finished Jul 25 06:37:55 PM PDT 24
Peak memory 208012 kb
Host smart-51e2661d-c5d4-4c0e-ac89-29821a58f7a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662669489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.2662669489
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.4289907095
Short name T389
Test name
Test status
Simulation time 734302435 ps
CPU time 2.47 seconds
Started Jul 25 06:37:46 PM PDT 24
Finished Jul 25 06:37:48 PM PDT 24
Peak memory 216456 kb
Host smart-c2fffad9-5d2f-4f19-910d-933caec214f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289907095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.4289907095
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.165187949
Short name T848
Test name
Test status
Simulation time 601459883 ps
CPU time 2.19 seconds
Started Jul 25 06:37:49 PM PDT 24
Finished Jul 25 06:37:51 PM PDT 24
Peak memory 208028 kb
Host smart-66aed5b6-99d1-4c9f-91a0-b8bb51a1221c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165187949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.165187949
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.3995183216
Short name T54
Test name
Test status
Simulation time 111359894 ps
CPU time 1.94 seconds
Started Jul 25 06:37:46 PM PDT 24
Finished Jul 25 06:37:48 PM PDT 24
Peak memory 208236 kb
Host smart-c7e1bc93-971b-46e9-ab6e-d59a08ec979f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995183216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.3995183216
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.2209866677
Short name T944
Test name
Test status
Simulation time 146205652 ps
CPU time 0.94 seconds
Started Jul 25 06:37:47 PM PDT 24
Finished Jul 25 06:37:48 PM PDT 24
Peak memory 206656 kb
Host smart-eb1e73df-f1ee-4646-bdf0-0cfa21a0a0cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209866677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.2209866677
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.1089576888
Short name T630
Test name
Test status
Simulation time 92804242122 ps
CPU time 18.67 seconds
Started Jul 25 06:37:55 PM PDT 24
Finished Jul 25 06:38:14 PM PDT 24
Peak memory 250868 kb
Host smart-2e089fa0-09b2-479c-bfbb-661e9a671ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089576888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.1089576888
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.1875015976
Short name T312
Test name
Test status
Simulation time 12425905 ps
CPU time 0.72 seconds
Started Jul 25 06:37:57 PM PDT 24
Finished Jul 25 06:37:58 PM PDT 24
Peak memory 204972 kb
Host smart-6fe4d1fc-92a7-4ad6-b5b6-e37a8f7023f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875015976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
1875015976
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.2916039608
Short name T953
Test name
Test status
Simulation time 1474242976 ps
CPU time 9.21 seconds
Started Jul 25 06:37:57 PM PDT 24
Finished Jul 25 06:38:06 PM PDT 24
Peak memory 224644 kb
Host smart-e01938ae-899b-4c26-8955-c8be117f9c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916039608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.2916039608
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.584421122
Short name T675
Test name
Test status
Simulation time 87845933 ps
CPU time 0.76 seconds
Started Jul 25 06:37:57 PM PDT 24
Finished Jul 25 06:37:58 PM PDT 24
Peak memory 205748 kb
Host smart-7bd594b7-b959-48a2-adbb-f696a995ab1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584421122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.584421122
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.2866539146
Short name T872
Test name
Test status
Simulation time 12668499183 ps
CPU time 80.79 seconds
Started Jul 25 06:37:57 PM PDT 24
Finished Jul 25 06:39:18 PM PDT 24
Peak memory 263676 kb
Host smart-c43bb64f-8c3d-43fe-8c50-a65d1f0ef04c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866539146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.2866539146
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.614925962
Short name T647
Test name
Test status
Simulation time 40412730055 ps
CPU time 155.09 seconds
Started Jul 25 06:37:55 PM PDT 24
Finished Jul 25 06:40:31 PM PDT 24
Peak memory 254604 kb
Host smart-2a85bb53-b27c-45f3-962c-a9eb24a205a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614925962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idle
.614925962
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.2291101381
Short name T420
Test name
Test status
Simulation time 124696024 ps
CPU time 3.41 seconds
Started Jul 25 06:38:00 PM PDT 24
Finished Jul 25 06:38:03 PM PDT 24
Peak memory 224708 kb
Host smart-e6bc3389-fb7d-459c-aeda-947fb288f673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291101381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.2291101381
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.3149248594
Short name T82
Test name
Test status
Simulation time 21143626268 ps
CPU time 31.3 seconds
Started Jul 25 06:37:57 PM PDT 24
Finished Jul 25 06:38:28 PM PDT 24
Peak memory 249284 kb
Host smart-4926b048-ee42-47b2-a78d-b9e19d8789a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149248594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmd
s.3149248594
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_intercept.1953100087
Short name T564
Test name
Test status
Simulation time 1164702127 ps
CPU time 13.99 seconds
Started Jul 25 06:37:57 PM PDT 24
Finished Jul 25 06:38:11 PM PDT 24
Peak memory 232864 kb
Host smart-39e207db-b5cb-4f7b-8330-dd2505681690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953100087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.1953100087
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.5122474
Short name T394
Test name
Test status
Simulation time 278204185 ps
CPU time 7.33 seconds
Started Jul 25 06:37:57 PM PDT 24
Finished Jul 25 06:38:04 PM PDT 24
Peak memory 241084 kb
Host smart-b8723a5c-750f-4704-a3cd-280174e8436a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5122474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.5122474
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.715566079
Short name T238
Test name
Test status
Simulation time 1074095003 ps
CPU time 6.35 seconds
Started Jul 25 06:37:58 PM PDT 24
Finished Jul 25 06:38:05 PM PDT 24
Peak memory 224720 kb
Host smart-0cf80301-3111-4381-8126-f32b045a8234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715566079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swap
.715566079
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.1203076734
Short name T704
Test name
Test status
Simulation time 734011404 ps
CPU time 5.22 seconds
Started Jul 25 06:37:59 PM PDT 24
Finished Jul 25 06:38:05 PM PDT 24
Peak memory 224720 kb
Host smart-809fb859-4bb2-40bf-93ca-2d36e8acbf35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203076734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.1203076734
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.2410483804
Short name T44
Test name
Test status
Simulation time 3608578183 ps
CPU time 10.26 seconds
Started Jul 25 06:37:58 PM PDT 24
Finished Jul 25 06:38:08 PM PDT 24
Peak memory 219112 kb
Host smart-ed998f82-cd65-4325-81eb-7fef302e6196
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2410483804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.2410483804
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.3993458423
Short name T63
Test name
Test status
Simulation time 160798994 ps
CPU time 0.97 seconds
Started Jul 25 06:37:57 PM PDT 24
Finished Jul 25 06:37:58 PM PDT 24
Peak memory 206888 kb
Host smart-23184b7d-df16-4781-afaa-b8e43ed0732c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993458423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.3993458423
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.1170029998
Short name T976
Test name
Test status
Simulation time 1816062485 ps
CPU time 13.93 seconds
Started Jul 25 06:37:56 PM PDT 24
Finished Jul 25 06:38:10 PM PDT 24
Peak memory 219436 kb
Host smart-c98417c5-03c7-4210-b8a2-a1d9bc771354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170029998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.1170029998
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.4100371934
Short name T652
Test name
Test status
Simulation time 26140313761 ps
CPU time 14.4 seconds
Started Jul 25 06:37:56 PM PDT 24
Finished Jul 25 06:38:11 PM PDT 24
Peak memory 216456 kb
Host smart-d335f442-5904-4ec9-abb1-475ac26b9734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100371934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.4100371934
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.369206825
Short name T332
Test name
Test status
Simulation time 203569289 ps
CPU time 1.14 seconds
Started Jul 25 06:37:57 PM PDT 24
Finished Jul 25 06:37:58 PM PDT 24
Peak memory 207960 kb
Host smart-137a5b57-d05a-48d6-b0a4-360a8d7fa068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369206825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.369206825
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.2909806423
Short name T586
Test name
Test status
Simulation time 58105641 ps
CPU time 0.77 seconds
Started Jul 25 06:37:58 PM PDT 24
Finished Jul 25 06:37:59 PM PDT 24
Peak memory 206076 kb
Host smart-437aad19-0a10-476b-a3b6-45582b85341c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909806423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.2909806423
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.1495751402
Short name T862
Test name
Test status
Simulation time 37423742644 ps
CPU time 17.4 seconds
Started Jul 25 06:37:56 PM PDT 24
Finished Jul 25 06:38:13 PM PDT 24
Peak memory 232968 kb
Host smart-615ad9e1-60ee-4cb2-914e-86d1ae65486a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495751402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.1495751402
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.1427323124
Short name T386
Test name
Test status
Simulation time 42206193 ps
CPU time 0.73 seconds
Started Jul 25 06:38:03 PM PDT 24
Finished Jul 25 06:38:04 PM PDT 24
Peak memory 205536 kb
Host smart-4d3217ee-c270-415f-b5e3-25dba89f8081
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427323124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
1427323124
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.1297747476
Short name T621
Test name
Test status
Simulation time 7542582671 ps
CPU time 19.26 seconds
Started Jul 25 06:38:02 PM PDT 24
Finished Jul 25 06:38:22 PM PDT 24
Peak memory 224708 kb
Host smart-88039bf9-dd69-4df0-b5c7-b65817105c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297747476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.1297747476
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.2596040144
Short name T637
Test name
Test status
Simulation time 20570780 ps
CPU time 0.81 seconds
Started Jul 25 06:38:02 PM PDT 24
Finished Jul 25 06:38:03 PM PDT 24
Peak memory 206736 kb
Host smart-33067b31-497d-426e-8e85-1ade446e586f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596040144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.2596040144
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.1424582278
Short name T373
Test name
Test status
Simulation time 2775588163 ps
CPU time 8.33 seconds
Started Jul 25 06:38:02 PM PDT 24
Finished Jul 25 06:38:10 PM PDT 24
Peak memory 234000 kb
Host smart-a7a5c792-3d83-4c0b-8ae7-4f96a202dbd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424582278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.1424582278
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.170906955
Short name T919
Test name
Test status
Simulation time 17353872010 ps
CPU time 194.96 seconds
Started Jul 25 06:38:04 PM PDT 24
Finished Jul 25 06:41:19 PM PDT 24
Peak memory 251204 kb
Host smart-76d9b9ba-7778-42f3-8390-10ff171fbd51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170906955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.170906955
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.2190769351
Short name T70
Test name
Test status
Simulation time 10895497336 ps
CPU time 10.51 seconds
Started Jul 25 06:38:04 PM PDT 24
Finished Jul 25 06:38:15 PM PDT 24
Peak memory 217576 kb
Host smart-31de86c6-d910-4069-b316-291517c680ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190769351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.2190769351
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.120246692
Short name T741
Test name
Test status
Simulation time 391668588 ps
CPU time 9.47 seconds
Started Jul 25 06:38:01 PM PDT 24
Finished Jul 25 06:38:11 PM PDT 24
Peak memory 232908 kb
Host smart-efe64cc6-fcd2-4d12-bf0b-512de469b351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120246692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.120246692
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.1412456382
Short name T190
Test name
Test status
Simulation time 16693210120 ps
CPU time 54.79 seconds
Started Jul 25 06:38:01 PM PDT 24
Finished Jul 25 06:38:56 PM PDT 24
Peak memory 252724 kb
Host smart-504cd814-3d5e-4869-85ec-c8fc4cc060ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412456382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmd
s.1412456382
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.3672552285
Short name T84
Test name
Test status
Simulation time 299126159 ps
CPU time 5.49 seconds
Started Jul 25 06:38:03 PM PDT 24
Finished Jul 25 06:38:09 PM PDT 24
Peak memory 224684 kb
Host smart-ff3fdc63-ec74-4dbe-aae6-74d65314fbc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672552285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.3672552285
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.408162032
Short name T209
Test name
Test status
Simulation time 3156164238 ps
CPU time 15.33 seconds
Started Jul 25 06:38:02 PM PDT 24
Finished Jul 25 06:38:17 PM PDT 24
Peak memory 235596 kb
Host smart-2ffeb525-b325-48e0-a1c1-154801bdaa0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408162032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.408162032
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.3010427224
Short name T650
Test name
Test status
Simulation time 550466936 ps
CPU time 6.38 seconds
Started Jul 25 06:38:02 PM PDT 24
Finished Jul 25 06:38:08 PM PDT 24
Peak memory 232892 kb
Host smart-218eae73-186a-4bb0-b569-6b3416ceae80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010427224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.3010427224
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.563247402
Short name T500
Test name
Test status
Simulation time 117145921230 ps
CPU time 18.67 seconds
Started Jul 25 06:38:00 PM PDT 24
Finished Jul 25 06:38:18 PM PDT 24
Peak memory 239804 kb
Host smart-e821faaa-e39d-4661-a3b9-d0f7d7956fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563247402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.563247402
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.2289719269
Short name T529
Test name
Test status
Simulation time 8502046939 ps
CPU time 14.27 seconds
Started Jul 25 06:38:01 PM PDT 24
Finished Jul 25 06:38:15 PM PDT 24
Peak memory 222340 kb
Host smart-61803499-b74f-4f57-b859-90f86616397a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2289719269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.2289719269
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.2811344458
Short name T881
Test name
Test status
Simulation time 218022199 ps
CPU time 1.06 seconds
Started Jul 25 06:38:04 PM PDT 24
Finished Jul 25 06:38:06 PM PDT 24
Peak memory 206392 kb
Host smart-f794e753-2e9f-4ae0-942e-f985884f790a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811344458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.2811344458
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.4212467478
Short name T27
Test name
Test status
Simulation time 13229745665 ps
CPU time 41.86 seconds
Started Jul 25 06:38:04 PM PDT 24
Finished Jul 25 06:38:46 PM PDT 24
Peak memory 216468 kb
Host smart-0b63a047-a28f-43ce-9923-abb4a1d78a61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212467478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.4212467478
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.193497865
Short name T718
Test name
Test status
Simulation time 30493792 ps
CPU time 0.74 seconds
Started Jul 25 06:38:04 PM PDT 24
Finished Jul 25 06:38:05 PM PDT 24
Peak memory 205836 kb
Host smart-522079fa-a0f9-4b9f-b9cc-24f7e1ff8723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193497865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.193497865
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.666528387
Short name T767
Test name
Test status
Simulation time 261361712 ps
CPU time 1.29 seconds
Started Jul 25 06:38:03 PM PDT 24
Finished Jul 25 06:38:04 PM PDT 24
Peak memory 216228 kb
Host smart-5369b60f-e25b-4b3a-981c-8474fc141571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666528387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.666528387
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.2068613551
Short name T582
Test name
Test status
Simulation time 285586659 ps
CPU time 0.93 seconds
Started Jul 25 06:38:01 PM PDT 24
Finished Jul 25 06:38:02 PM PDT 24
Peak memory 206120 kb
Host smart-9280777c-30a9-40c2-ab43-d28814b970ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068613551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.2068613551
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.4222411066
Short name T997
Test name
Test status
Simulation time 2061768462 ps
CPU time 5.2 seconds
Started Jul 25 06:38:02 PM PDT 24
Finished Jul 25 06:38:07 PM PDT 24
Peak memory 224604 kb
Host smart-54f2c83f-75f0-49ed-9ca9-9c692c4ff6f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222411066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.4222411066
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.3360004317
Short name T59
Test name
Test status
Simulation time 17089531 ps
CPU time 0.78 seconds
Started Jul 25 06:38:00 PM PDT 24
Finished Jul 25 06:38:01 PM PDT 24
Peak memory 205608 kb
Host smart-b8d62460-05cf-451a-bb66-01d03e4c9fea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360004317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
3360004317
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.768025447
Short name T673
Test name
Test status
Simulation time 922982989 ps
CPU time 6.6 seconds
Started Jul 25 06:38:04 PM PDT 24
Finished Jul 25 06:38:11 PM PDT 24
Peak memory 232832 kb
Host smart-7b603e6c-ec08-4613-9d27-d5baf99e7c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768025447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.768025447
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.3346881638
Short name T883
Test name
Test status
Simulation time 15153031 ps
CPU time 0.74 seconds
Started Jul 25 06:38:00 PM PDT 24
Finished Jul 25 06:38:01 PM PDT 24
Peak memory 206064 kb
Host smart-b4bb60d1-9427-43d2-99e9-52b76861b655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346881638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.3346881638
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.1168139895
Short name T149
Test name
Test status
Simulation time 4048148149 ps
CPU time 30.24 seconds
Started Jul 25 06:38:02 PM PDT 24
Finished Jul 25 06:38:33 PM PDT 24
Peak memory 218844 kb
Host smart-02249774-c489-4c20-941f-5ca3681c0407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168139895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.1168139895
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.3385589974
Short name T301
Test name
Test status
Simulation time 12726463885 ps
CPU time 65.31 seconds
Started Jul 25 06:38:01 PM PDT 24
Finished Jul 25 06:39:07 PM PDT 24
Peak memory 218852 kb
Host smart-370871c3-3037-4624-a2a8-64b20c0a894f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385589974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.3385589974
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.2403683490
Short name T969
Test name
Test status
Simulation time 54117598826 ps
CPU time 53.64 seconds
Started Jul 25 06:38:04 PM PDT 24
Finished Jul 25 06:38:57 PM PDT 24
Peak memory 229768 kb
Host smart-98f689bf-2071-4f8a-8772-64139ace5140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403683490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.2403683490
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.228015554
Short name T926
Test name
Test status
Simulation time 3160133212 ps
CPU time 10.94 seconds
Started Jul 25 06:38:04 PM PDT 24
Finished Jul 25 06:38:15 PM PDT 24
Peak memory 224572 kb
Host smart-3eb36f06-101c-4519-8b43-157768a730ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228015554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.228015554
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.2320047018
Short name T165
Test name
Test status
Simulation time 9847596482 ps
CPU time 54.86 seconds
Started Jul 25 06:38:01 PM PDT 24
Finished Jul 25 06:38:56 PM PDT 24
Peak memory 249400 kb
Host smart-e2477840-d4e6-48bf-bb98-53bcd8478bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320047018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmd
s.2320047018
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_intercept.1204694836
Short name T666
Test name
Test status
Simulation time 11924122533 ps
CPU time 31.56 seconds
Started Jul 25 06:38:01 PM PDT 24
Finished Jul 25 06:38:32 PM PDT 24
Peak memory 224760 kb
Host smart-49c9be4a-aba2-4576-9de5-362f972d27c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204694836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.1204694836
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.3513722288
Short name T698
Test name
Test status
Simulation time 1032564423 ps
CPU time 17.56 seconds
Started Jul 25 06:38:01 PM PDT 24
Finished Jul 25 06:38:18 PM PDT 24
Peak memory 232848 kb
Host smart-4c8dbcb4-5071-4751-8cfc-ca038700ddeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513722288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.3513722288
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.1209030943
Short name T72
Test name
Test status
Simulation time 177398628 ps
CPU time 2.75 seconds
Started Jul 25 06:37:59 PM PDT 24
Finished Jul 25 06:38:02 PM PDT 24
Peak memory 224652 kb
Host smart-f69c1de8-a567-4b0f-bffb-7162d4abbcd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209030943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.1209030943
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.1773858647
Short name T426
Test name
Test status
Simulation time 2533264982 ps
CPU time 5.95 seconds
Started Jul 25 06:38:05 PM PDT 24
Finished Jul 25 06:38:11 PM PDT 24
Peak memory 224704 kb
Host smart-f7f273ec-2374-4a9c-89bb-6bc95f48ff42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773858647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.1773858647
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.388443434
Short name T952
Test name
Test status
Simulation time 1109050506 ps
CPU time 12.12 seconds
Started Jul 25 06:38:01 PM PDT 24
Finished Jul 25 06:38:13 PM PDT 24
Peak memory 219252 kb
Host smart-c83f0031-2f12-4fce-9161-774ff23e532b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=388443434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dire
ct.388443434
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.4007093109
Short name T19
Test name
Test status
Simulation time 5955946735 ps
CPU time 45.04 seconds
Started Jul 25 06:38:03 PM PDT 24
Finished Jul 25 06:38:48 PM PDT 24
Peak memory 241152 kb
Host smart-42d1ba58-1129-4356-9332-ca4da90c908b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007093109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.4007093109
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.621091102
Short name T304
Test name
Test status
Simulation time 32837637088 ps
CPU time 42.13 seconds
Started Jul 25 06:38:05 PM PDT 24
Finished Jul 25 06:38:47 PM PDT 24
Peak memory 216536 kb
Host smart-efe604a2-4cef-4177-aac6-aa31c8f880f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621091102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.621091102
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.2803333675
Short name T922
Test name
Test status
Simulation time 2257740386 ps
CPU time 2.15 seconds
Started Jul 25 06:38:05 PM PDT 24
Finished Jul 25 06:38:08 PM PDT 24
Peak memory 208076 kb
Host smart-5dce8470-fa35-43a9-a5f7-047cf364ec1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803333675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.2803333675
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.1094322323
Short name T412
Test name
Test status
Simulation time 145540371 ps
CPU time 1.9 seconds
Started Jul 25 06:38:05 PM PDT 24
Finished Jul 25 06:38:07 PM PDT 24
Peak memory 216376 kb
Host smart-d0c64987-b130-455d-9653-31b34196b205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094322323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.1094322323
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.1850997826
Short name T338
Test name
Test status
Simulation time 147977931 ps
CPU time 0.9 seconds
Started Jul 25 06:38:00 PM PDT 24
Finished Jul 25 06:38:01 PM PDT 24
Peak memory 206076 kb
Host smart-22d37b7e-75b9-4991-8818-fe06b41d715f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850997826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.1850997826
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.3687205226
Short name T670
Test name
Test status
Simulation time 551062047 ps
CPU time 3.73 seconds
Started Jul 25 06:38:04 PM PDT 24
Finished Jul 25 06:38:08 PM PDT 24
Peak memory 224724 kb
Host smart-6666a4ac-a41a-4c3c-911f-d4846bcca83f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687205226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.3687205226
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.2283741368
Short name T358
Test name
Test status
Simulation time 14802286 ps
CPU time 0.77 seconds
Started Jul 25 06:36:32 PM PDT 24
Finished Jul 25 06:36:33 PM PDT 24
Peak memory 205948 kb
Host smart-950957dd-dde3-4798-93bd-c8477e284413
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283741368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.2
283741368
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.2111961407
Short name T467
Test name
Test status
Simulation time 116207438 ps
CPU time 2.9 seconds
Started Jul 25 06:36:36 PM PDT 24
Finished Jul 25 06:36:39 PM PDT 24
Peak memory 224736 kb
Host smart-cce569db-8a2c-4209-bee2-b2eda411d348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111961407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.2111961407
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.2492618020
Short name T310
Test name
Test status
Simulation time 38376757 ps
CPU time 0.74 seconds
Started Jul 25 06:36:34 PM PDT 24
Finished Jul 25 06:36:35 PM PDT 24
Peak memory 205672 kb
Host smart-2ab652ba-c25a-4a57-9cd2-77d8c18b8664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492618020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.2492618020
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.3205710714
Short name T76
Test name
Test status
Simulation time 19781666675 ps
CPU time 63.57 seconds
Started Jul 25 06:36:52 PM PDT 24
Finished Jul 25 06:37:56 PM PDT 24
Peak memory 257468 kb
Host smart-efd8bd97-4076-4a0e-bb60-8c142c667a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205710714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.3205710714
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.1676593826
Short name T612
Test name
Test status
Simulation time 44585161123 ps
CPU time 76.33 seconds
Started Jul 25 06:36:36 PM PDT 24
Finished Jul 25 06:37:52 PM PDT 24
Peak memory 256784 kb
Host smart-49e7a915-69ce-4a72-915d-0e97d323786a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676593826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.1676593826
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.3008308888
Short name T746
Test name
Test status
Simulation time 155606987 ps
CPU time 3.46 seconds
Started Jul 25 06:36:34 PM PDT 24
Finished Jul 25 06:36:37 PM PDT 24
Peak memory 232860 kb
Host smart-1f684620-583d-4560-a420-a00721a4ecf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008308888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.3008308888
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.1982074384
Short name T475
Test name
Test status
Simulation time 33094219227 ps
CPU time 61.39 seconds
Started Jul 25 06:36:35 PM PDT 24
Finished Jul 25 06:37:37 PM PDT 24
Peak memory 241096 kb
Host smart-e1ba2d10-1dc1-4683-9d26-7f29db274c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982074384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds
.1982074384
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_intercept.2059514285
Short name T24
Test name
Test status
Simulation time 33767771 ps
CPU time 2.52 seconds
Started Jul 25 06:36:37 PM PDT 24
Finished Jul 25 06:36:39 PM PDT 24
Peak memory 232856 kb
Host smart-f2b7c100-79d1-4644-8032-dbbb8a3ff0ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059514285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.2059514285
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.3024059551
Short name T888
Test name
Test status
Simulation time 25056764476 ps
CPU time 68.24 seconds
Started Jul 25 06:36:32 PM PDT 24
Finished Jul 25 06:37:40 PM PDT 24
Peak memory 249140 kb
Host smart-96783d74-5039-4405-a7be-d18fc65e8f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024059551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.3024059551
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.1643044997
Short name T865
Test name
Test status
Simulation time 1656143594 ps
CPU time 7.19 seconds
Started Jul 25 06:36:41 PM PDT 24
Finished Jul 25 06:36:49 PM PDT 24
Peak memory 232860 kb
Host smart-af2f3d23-d24a-4f21-b579-111366c4ce89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643044997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.1643044997
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.557891238
Short name T849
Test name
Test status
Simulation time 1611751560 ps
CPU time 7.25 seconds
Started Jul 25 06:36:38 PM PDT 24
Finished Jul 25 06:36:45 PM PDT 24
Peak memory 224632 kb
Host smart-4989a277-981b-4b15-b3a9-b98f6f428e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557891238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.557891238
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.3544212875
Short name T847
Test name
Test status
Simulation time 6788476561 ps
CPU time 6.98 seconds
Started Jul 25 06:36:32 PM PDT 24
Finished Jul 25 06:36:40 PM PDT 24
Peak memory 219088 kb
Host smart-83e5f889-9122-4136-8347-a33849f74015
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3544212875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.3544212875
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.1863673804
Short name T67
Test name
Test status
Simulation time 1155038514 ps
CPU time 1.14 seconds
Started Jul 25 06:36:34 PM PDT 24
Finished Jul 25 06:36:35 PM PDT 24
Peak memory 235824 kb
Host smart-2c8e75af-8b21-4bea-aa76-200b3d96fe27
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863673804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.1863673804
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.1848600551
Short name T20
Test name
Test status
Simulation time 142950093 ps
CPU time 0.96 seconds
Started Jul 25 06:36:38 PM PDT 24
Finished Jul 25 06:36:39 PM PDT 24
Peak memory 207068 kb
Host smart-b44c5110-0725-4470-966b-9da455fcb93a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848600551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.1848600551
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.1669856116
Short name T723
Test name
Test status
Simulation time 4282004144 ps
CPU time 23.95 seconds
Started Jul 25 06:36:35 PM PDT 24
Finished Jul 25 06:36:59 PM PDT 24
Peak memory 216468 kb
Host smart-e5dca4ac-2398-4f8d-8404-a3bfcb9dc44a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669856116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.1669856116
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.1547766901
Short name T842
Test name
Test status
Simulation time 1777210599 ps
CPU time 10.03 seconds
Started Jul 25 06:36:38 PM PDT 24
Finished Jul 25 06:36:48 PM PDT 24
Peak memory 216416 kb
Host smart-4b645eea-4fbc-45a6-868a-34ed0417a6d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547766901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.1547766901
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.2064050192
Short name T762
Test name
Test status
Simulation time 49580540 ps
CPU time 0.7 seconds
Started Jul 25 06:36:34 PM PDT 24
Finished Jul 25 06:36:35 PM PDT 24
Peak memory 205716 kb
Host smart-31aa3572-5260-4dcd-9ad5-014c165c97e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064050192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.2064050192
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.3318487587
Short name T492
Test name
Test status
Simulation time 32914073 ps
CPU time 0.73 seconds
Started Jul 25 06:36:32 PM PDT 24
Finished Jul 25 06:36:33 PM PDT 24
Peak memory 206124 kb
Host smart-68197d92-9068-4e7e-b681-ee7631cf9fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318487587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.3318487587
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.732354305
Short name T780
Test name
Test status
Simulation time 2078011284 ps
CPU time 4.01 seconds
Started Jul 25 06:36:38 PM PDT 24
Finished Jul 25 06:36:43 PM PDT 24
Peak memory 224672 kb
Host smart-ed9de269-fd0f-4e06-87a2-866764fc7270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732354305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.732354305
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.4002028818
Short name T627
Test name
Test status
Simulation time 13662147 ps
CPU time 0.74 seconds
Started Jul 25 06:38:10 PM PDT 24
Finished Jul 25 06:38:11 PM PDT 24
Peak memory 205908 kb
Host smart-8437af3f-d79f-49aa-95c8-c48287c8c8e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002028818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
4002028818
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.88386368
Short name T354
Test name
Test status
Simulation time 203659593 ps
CPU time 3.63 seconds
Started Jul 25 06:38:01 PM PDT 24
Finished Jul 25 06:38:05 PM PDT 24
Peak memory 232932 kb
Host smart-72c92180-31b4-4f35-bb66-d2851a546276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88386368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.88386368
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.1917650065
Short name T148
Test name
Test status
Simulation time 16645384 ps
CPU time 0.8 seconds
Started Jul 25 06:38:05 PM PDT 24
Finished Jul 25 06:38:06 PM PDT 24
Peak memory 206744 kb
Host smart-81fba8d9-f8cf-4847-9116-2405cc67a545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917650065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.1917650065
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.4054965359
Short name T502
Test name
Test status
Simulation time 99181817439 ps
CPU time 183.88 seconds
Started Jul 25 06:38:13 PM PDT 24
Finished Jul 25 06:41:17 PM PDT 24
Peak memory 249356 kb
Host smart-73196aa5-8090-4d92-995e-0f8276f756a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054965359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.4054965359
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.3499305086
Short name T210
Test name
Test status
Simulation time 16529949621 ps
CPU time 65.44 seconds
Started Jul 25 06:38:08 PM PDT 24
Finished Jul 25 06:39:14 PM PDT 24
Peak memory 224776 kb
Host smart-4c783939-72e5-4932-965f-c43ba65bb2de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499305086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.3499305086
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.385961592
Short name T51
Test name
Test status
Simulation time 6206502434 ps
CPU time 66.51 seconds
Started Jul 25 06:38:12 PM PDT 24
Finished Jul 25 06:39:18 PM PDT 24
Peak memory 249436 kb
Host smart-1e895c7c-4c80-4ff2-96e5-41fae38fa45b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385961592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idle
.385961592
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.3697704495
Short name T493
Test name
Test status
Simulation time 490309383 ps
CPU time 7.35 seconds
Started Jul 25 06:38:03 PM PDT 24
Finished Jul 25 06:38:10 PM PDT 24
Peak memory 232856 kb
Host smart-12a11450-abb2-4849-a5a9-35184d8b9314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697704495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.3697704495
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.1979208254
Short name T274
Test name
Test status
Simulation time 56787779337 ps
CPU time 165.37 seconds
Started Jul 25 06:38:09 PM PDT 24
Finished Jul 25 06:40:55 PM PDT 24
Peak memory 254016 kb
Host smart-eb7ce6cb-eec7-44bd-8172-019b9e014976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979208254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmd
s.1979208254
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/30.spi_device_intercept.2394224281
Short name T196
Test name
Test status
Simulation time 5205877529 ps
CPU time 18.89 seconds
Started Jul 25 06:38:06 PM PDT 24
Finished Jul 25 06:38:25 PM PDT 24
Peak memory 232900 kb
Host smart-2f8d7cb0-c8b6-4489-9d67-15f2959216c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394224281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.2394224281
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.1212140019
Short name T839
Test name
Test status
Simulation time 17486155516 ps
CPU time 33.49 seconds
Started Jul 25 06:38:05 PM PDT 24
Finished Jul 25 06:38:38 PM PDT 24
Peak memory 224768 kb
Host smart-526688e1-22fa-4e50-bb43-9343978d5c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212140019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.1212140019
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.1220384022
Short name T438
Test name
Test status
Simulation time 128120049 ps
CPU time 2.71 seconds
Started Jul 25 06:38:07 PM PDT 24
Finished Jul 25 06:38:09 PM PDT 24
Peak memory 232844 kb
Host smart-a7ae39e5-e55e-4f51-b3eb-2f0e6abe6e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220384022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.1220384022
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.1142552676
Short name T398
Test name
Test status
Simulation time 2248590765 ps
CPU time 11.33 seconds
Started Jul 25 06:38:02 PM PDT 24
Finished Jul 25 06:38:13 PM PDT 24
Peak memory 249288 kb
Host smart-c5651a1e-23db-473d-a6df-2066862ef023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142552676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.1142552676
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.4094107880
Short name T625
Test name
Test status
Simulation time 891515456 ps
CPU time 5.14 seconds
Started Jul 25 06:38:12 PM PDT 24
Finished Jul 25 06:38:17 PM PDT 24
Peak memory 220756 kb
Host smart-67935938-b2f4-474e-bf88-538d3c89e8ee
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4094107880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.4094107880
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.1198519310
Short name T147
Test name
Test status
Simulation time 26960796566 ps
CPU time 171.17 seconds
Started Jul 25 06:38:09 PM PDT 24
Finished Jul 25 06:41:00 PM PDT 24
Peak memory 265648 kb
Host smart-8c5be223-aecd-4db1-8c91-be9605135d9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198519310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.1198519310
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.2128328819
Short name T552
Test name
Test status
Simulation time 5262218676 ps
CPU time 14.87 seconds
Started Jul 25 06:38:07 PM PDT 24
Finished Jul 25 06:38:22 PM PDT 24
Peak memory 216392 kb
Host smart-a18fd4a4-7488-41d2-a5b4-f94bdb3710be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128328819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.2128328819
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.721701103
Short name T735
Test name
Test status
Simulation time 784217402 ps
CPU time 5.77 seconds
Started Jul 25 06:38:06 PM PDT 24
Finished Jul 25 06:38:11 PM PDT 24
Peak memory 216456 kb
Host smart-2e90f876-9172-468f-83aa-04eea0ee924f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721701103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.721701103
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.878889861
Short name T150
Test name
Test status
Simulation time 222202628 ps
CPU time 3.59 seconds
Started Jul 25 06:38:05 PM PDT 24
Finished Jul 25 06:38:08 PM PDT 24
Peak memory 216464 kb
Host smart-d18369b1-4d29-4442-b074-f64680e059c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878889861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.878889861
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.530028392
Short name T460
Test name
Test status
Simulation time 159072932 ps
CPU time 0.96 seconds
Started Jul 25 06:38:07 PM PDT 24
Finished Jul 25 06:38:08 PM PDT 24
Peak memory 206080 kb
Host smart-47a15a19-9e22-4b57-829c-aaf2f003643c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530028392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.530028392
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.1033155544
Short name T419
Test name
Test status
Simulation time 4141776214 ps
CPU time 9.31 seconds
Started Jul 25 06:38:04 PM PDT 24
Finished Jul 25 06:38:14 PM PDT 24
Peak memory 248700 kb
Host smart-f609c8fa-6150-4710-8dc9-536959a15559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033155544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.1033155544
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.996670599
Short name T809
Test name
Test status
Simulation time 25338881 ps
CPU time 0.73 seconds
Started Jul 25 06:38:09 PM PDT 24
Finished Jul 25 06:38:10 PM PDT 24
Peak memory 205028 kb
Host smart-3826fd07-8124-4a6c-91c3-6e8d98874368
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996670599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.996670599
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.353586773
Short name T324
Test name
Test status
Simulation time 120020658 ps
CPU time 3.35 seconds
Started Jul 25 06:38:11 PM PDT 24
Finished Jul 25 06:38:14 PM PDT 24
Peak memory 232868 kb
Host smart-b20f4a27-1830-499b-89c0-0c79562b819e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353586773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.353586773
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.4115076490
Short name T337
Test name
Test status
Simulation time 42363192 ps
CPU time 0.77 seconds
Started Jul 25 06:38:09 PM PDT 24
Finished Jul 25 06:38:10 PM PDT 24
Peak memory 207076 kb
Host smart-34092b97-e137-45fb-bbf9-a624f97ceecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115076490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.4115076490
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.668347777
Short name T949
Test name
Test status
Simulation time 39460963934 ps
CPU time 161.14 seconds
Started Jul 25 06:38:12 PM PDT 24
Finished Jul 25 06:40:53 PM PDT 24
Peak memory 257032 kb
Host smart-03b1d55c-ab44-43d0-912e-a386c6ba4ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668347777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.668347777
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.1715777126
Short name T171
Test name
Test status
Simulation time 138173516742 ps
CPU time 166.9 seconds
Started Jul 25 06:38:11 PM PDT 24
Finished Jul 25 06:40:58 PM PDT 24
Peak memory 257104 kb
Host smart-ac0fdb5c-3094-4cdc-ab17-2c560b124659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715777126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.1715777126
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.1186556050
Short name T186
Test name
Test status
Simulation time 37466800948 ps
CPU time 153.55 seconds
Started Jul 25 06:38:12 PM PDT 24
Finished Jul 25 06:40:46 PM PDT 24
Peak memory 249408 kb
Host smart-375b444f-04b7-4d81-a105-1ce33c9c19b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186556050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.1186556050
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.3863663354
Short name T297
Test name
Test status
Simulation time 11844845585 ps
CPU time 14.98 seconds
Started Jul 25 06:38:08 PM PDT 24
Finished Jul 25 06:38:24 PM PDT 24
Peak memory 234100 kb
Host smart-90ae4abf-5bc8-4a32-82a1-5db7f86eaf7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863663354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.3863663354
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.3724284496
Short name T286
Test name
Test status
Simulation time 12279097434 ps
CPU time 157.38 seconds
Started Jul 25 06:38:13 PM PDT 24
Finished Jul 25 06:40:50 PM PDT 24
Peak memory 257540 kb
Host smart-a2bc2b9a-c37d-4f83-be1c-272ff47fd55a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724284496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmd
s.3724284496
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/31.spi_device_intercept.514201365
Short name T700
Test name
Test status
Simulation time 100428359 ps
CPU time 2.84 seconds
Started Jul 25 06:38:13 PM PDT 24
Finished Jul 25 06:38:16 PM PDT 24
Peak memory 232920 kb
Host smart-f3466c5b-d5e1-4925-b75e-ef846c3d9e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514201365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.514201365
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.932019341
Short name T999
Test name
Test status
Simulation time 38396012379 ps
CPU time 66.99 seconds
Started Jul 25 06:38:15 PM PDT 24
Finished Jul 25 06:39:22 PM PDT 24
Peak memory 236136 kb
Host smart-6a426561-a83b-4218-a809-dc05fa7c8015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932019341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.932019341
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.25538047
Short name T649
Test name
Test status
Simulation time 119700109 ps
CPU time 4.04 seconds
Started Jul 25 06:38:09 PM PDT 24
Finished Jul 25 06:38:13 PM PDT 24
Peak memory 232860 kb
Host smart-f311e1fd-a7a1-44d5-a0ec-4e299bd79f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25538047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swap.25538047
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.2715211624
Short name T956
Test name
Test status
Simulation time 4944385452 ps
CPU time 10.6 seconds
Started Jul 25 06:38:08 PM PDT 24
Finished Jul 25 06:38:19 PM PDT 24
Peak memory 239328 kb
Host smart-5acc352d-b05d-4974-8671-512f603a0626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715211624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.2715211624
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.2889716401
Short name T813
Test name
Test status
Simulation time 470458221 ps
CPU time 6.87 seconds
Started Jul 25 06:38:15 PM PDT 24
Finished Jul 25 06:38:22 PM PDT 24
Peak memory 219064 kb
Host smart-a2ab94eb-7baf-4a13-a980-9a7d4db466fb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2889716401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.2889716401
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.3480800836
Short name T725
Test name
Test status
Simulation time 832725876 ps
CPU time 5.06 seconds
Started Jul 25 06:38:15 PM PDT 24
Finished Jul 25 06:38:20 PM PDT 24
Peak memory 216456 kb
Host smart-011f10d1-c806-4916-93c1-d6861e39aed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480800836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.3480800836
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.1721660514
Short name T966
Test name
Test status
Simulation time 840571813 ps
CPU time 2.59 seconds
Started Jul 25 06:38:22 PM PDT 24
Finished Jul 25 06:38:24 PM PDT 24
Peak memory 216392 kb
Host smart-9054bfb2-0e17-4744-ab7d-7fee4f38eee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721660514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.1721660514
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.1667782865
Short name T414
Test name
Test status
Simulation time 23436122 ps
CPU time 0.69 seconds
Started Jul 25 06:38:10 PM PDT 24
Finished Jul 25 06:38:11 PM PDT 24
Peak memory 205836 kb
Host smart-e1264457-91c1-4b36-80e9-37c54206e791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667782865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.1667782865
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.1782936448
Short name T146
Test name
Test status
Simulation time 382117138 ps
CPU time 0.96 seconds
Started Jul 25 06:38:08 PM PDT 24
Finished Jul 25 06:38:09 PM PDT 24
Peak memory 206120 kb
Host smart-e9791b3c-92aa-4b02-97b8-44b53c95b563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782936448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.1782936448
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.789658326
Short name T349
Test name
Test status
Simulation time 393158179 ps
CPU time 3.89 seconds
Started Jul 25 06:38:10 PM PDT 24
Finished Jul 25 06:38:14 PM PDT 24
Peak memory 224668 kb
Host smart-b0a0288a-194d-4fc1-ac77-af31d26bbfd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789658326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.789658326
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.3831712234
Short name T417
Test name
Test status
Simulation time 23078371 ps
CPU time 0.7 seconds
Started Jul 25 06:38:10 PM PDT 24
Finished Jul 25 06:38:11 PM PDT 24
Peak memory 205872 kb
Host smart-7bd0d9ee-2058-424e-9b07-95f1c7ddf7e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831712234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
3831712234
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.1594115668
Short name T742
Test name
Test status
Simulation time 104567615 ps
CPU time 2.36 seconds
Started Jul 25 06:38:15 PM PDT 24
Finished Jul 25 06:38:17 PM PDT 24
Peak memory 224700 kb
Host smart-081dd516-5ddf-4e55-8778-c29cca6b1451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594115668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.1594115668
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.1350335670
Short name T980
Test name
Test status
Simulation time 24567944 ps
CPU time 0.73 seconds
Started Jul 25 06:38:09 PM PDT 24
Finished Jul 25 06:38:10 PM PDT 24
Peak memory 205728 kb
Host smart-2d8ee4f3-4a82-4abc-ba44-6be1bd625393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350335670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.1350335670
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.2559022848
Short name T189
Test name
Test status
Simulation time 15056694571 ps
CPU time 118.74 seconds
Started Jul 25 06:38:09 PM PDT 24
Finished Jul 25 06:40:08 PM PDT 24
Peak memory 241116 kb
Host smart-f0bc14b4-9bff-450b-8b2f-96767e0d9b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559022848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.2559022848
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.310592038
Short name T194
Test name
Test status
Simulation time 13714782850 ps
CPU time 105.18 seconds
Started Jul 25 06:38:15 PM PDT 24
Finished Jul 25 06:40:01 PM PDT 24
Peak memory 233012 kb
Host smart-f801b953-5352-4d5c-9d37-5d136da811e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310592038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.310592038
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.1568558939
Short name T854
Test name
Test status
Simulation time 68984492941 ps
CPU time 326.6 seconds
Started Jul 25 06:38:12 PM PDT 24
Finished Jul 25 06:43:39 PM PDT 24
Peak memory 249404 kb
Host smart-981e8988-5898-4d6e-b8e2-67df313a4424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568558939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.1568558939
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.865292801
Short name T350
Test name
Test status
Simulation time 6351729691 ps
CPU time 23.34 seconds
Started Jul 25 06:38:12 PM PDT 24
Finished Jul 25 06:38:35 PM PDT 24
Peak memory 224768 kb
Host smart-0a5f66b8-794e-4dd5-a5e9-d83848bd7599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865292801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.865292801
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.2703723221
Short name T934
Test name
Test status
Simulation time 47628257750 ps
CPU time 317.87 seconds
Started Jul 25 06:38:10 PM PDT 24
Finished Jul 25 06:43:28 PM PDT 24
Peak memory 254140 kb
Host smart-16991de6-85db-4117-bf7d-529e9be414b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703723221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmd
s.2703723221
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_intercept.2471484557
Short name T985
Test name
Test status
Simulation time 971684102 ps
CPU time 10.85 seconds
Started Jul 25 06:38:13 PM PDT 24
Finished Jul 25 06:38:24 PM PDT 24
Peak memory 232924 kb
Host smart-62d37e22-b84e-464b-9b17-a5610e0db0d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471484557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.2471484557
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.3720992548
Short name T250
Test name
Test status
Simulation time 50385568851 ps
CPU time 36.81 seconds
Started Jul 25 06:38:09 PM PDT 24
Finished Jul 25 06:38:46 PM PDT 24
Peak memory 232920 kb
Host smart-64c893b5-b11b-4048-8655-ec8cfba8ffc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720992548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.3720992548
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.79953946
Short name T892
Test name
Test status
Simulation time 132265587 ps
CPU time 2.29 seconds
Started Jul 25 06:38:15 PM PDT 24
Finished Jul 25 06:38:17 PM PDT 24
Peak memory 224696 kb
Host smart-49fd65f0-7a22-4daf-9c18-fdad1e9765b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79953946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swap.79953946
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.1613137208
Short name T655
Test name
Test status
Simulation time 6477010218 ps
CPU time 4.97 seconds
Started Jul 25 06:38:11 PM PDT 24
Finished Jul 25 06:38:16 PM PDT 24
Peak memory 224776 kb
Host smart-3b55912b-0fdf-4d19-a56a-9e0075630cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613137208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.1613137208
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.1622229443
Short name T622
Test name
Test status
Simulation time 5178427175 ps
CPU time 15.82 seconds
Started Jul 25 06:38:12 PM PDT 24
Finished Jul 25 06:38:27 PM PDT 24
Peak memory 222276 kb
Host smart-007d929b-203e-4219-b094-c743b1dc6b11
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1622229443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.1622229443
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.3522896860
Short name T686
Test name
Test status
Simulation time 1575938046 ps
CPU time 2.91 seconds
Started Jul 25 06:38:13 PM PDT 24
Finished Jul 25 06:38:16 PM PDT 24
Peak memory 216432 kb
Host smart-6d247057-8b79-4ec1-8ea6-2116a4d5fcf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522896860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.3522896860
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.1544572801
Short name T542
Test name
Test status
Simulation time 3073228354 ps
CPU time 7.19 seconds
Started Jul 25 06:38:11 PM PDT 24
Finished Jul 25 06:38:18 PM PDT 24
Peak memory 216496 kb
Host smart-c11260e8-3267-4c3c-b1ca-c0e094ac37bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544572801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.1544572801
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.1341814451
Short name T804
Test name
Test status
Simulation time 132222814 ps
CPU time 0.95 seconds
Started Jul 25 06:38:08 PM PDT 24
Finished Jul 25 06:38:09 PM PDT 24
Peak memory 207368 kb
Host smart-7b8d1a0d-17ab-4da9-968f-ed1c0aee0188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341814451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.1341814451
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.1137286472
Short name T611
Test name
Test status
Simulation time 245883285 ps
CPU time 0.83 seconds
Started Jul 25 06:38:11 PM PDT 24
Finished Jul 25 06:38:12 PM PDT 24
Peak memory 206088 kb
Host smart-7f535fa7-d378-41d4-8ba3-1f49da16f3f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137286472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.1137286472
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.1608554105
Short name T321
Test name
Test status
Simulation time 225330054 ps
CPU time 2.5 seconds
Started Jul 25 06:38:11 PM PDT 24
Finished Jul 25 06:38:13 PM PDT 24
Peak memory 224756 kb
Host smart-08aa9bd1-50bb-4b69-9568-fdff2c8bd9b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608554105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.1608554105
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.2176988990
Short name T431
Test name
Test status
Simulation time 14504065 ps
CPU time 0.72 seconds
Started Jul 25 06:38:22 PM PDT 24
Finished Jul 25 06:38:22 PM PDT 24
Peak memory 205828 kb
Host smart-11dfc165-16e9-41b5-8655-93ac949dbadb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176988990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
2176988990
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.104969
Short name T719
Test name
Test status
Simulation time 924726871 ps
CPU time 2.88 seconds
Started Jul 25 06:38:16 PM PDT 24
Finished Jul 25 06:38:19 PM PDT 24
Peak memory 224696 kb
Host smart-ec4c37b6-7160-4678-9b45-91a8b3cb83ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.104969
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.1617337903
Short name T26
Test name
Test status
Simulation time 64068499 ps
CPU time 0.8 seconds
Started Jul 25 06:38:15 PM PDT 24
Finished Jul 25 06:38:16 PM PDT 24
Peak memory 207052 kb
Host smart-22e7b898-a6f1-4577-aa53-559bb87fc861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617337903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.1617337903
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.3800070290
Short name T319
Test name
Test status
Simulation time 44035411 ps
CPU time 0.75 seconds
Started Jul 25 06:38:17 PM PDT 24
Finished Jul 25 06:38:18 PM PDT 24
Peak memory 215908 kb
Host smart-9eb83df3-d855-45f1-9a64-7a97947c27ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800070290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.3800070290
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.1867285773
Short name T802
Test name
Test status
Simulation time 24035293209 ps
CPU time 145.49 seconds
Started Jul 25 06:38:18 PM PDT 24
Finished Jul 25 06:40:43 PM PDT 24
Peak memory 251240 kb
Host smart-22451a3c-208f-4577-9394-99e177d0adbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867285773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.1867285773
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.792866049
Short name T671
Test name
Test status
Simulation time 17696108910 ps
CPU time 125.37 seconds
Started Jul 25 06:38:19 PM PDT 24
Finished Jul 25 06:40:24 PM PDT 24
Peak memory 233068 kb
Host smart-cb1a4927-a950-488d-900b-fe4bce6dc87d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792866049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idle
.792866049
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.804388403
Short name T825
Test name
Test status
Simulation time 557747197 ps
CPU time 3.42 seconds
Started Jul 25 06:38:23 PM PDT 24
Finished Jul 25 06:38:27 PM PDT 24
Peak memory 224688 kb
Host smart-15c648ba-0e11-4751-b37b-244c4d29d384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804388403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.804388403
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.912880911
Short name T168
Test name
Test status
Simulation time 20664883758 ps
CPU time 85.89 seconds
Started Jul 25 06:38:19 PM PDT 24
Finished Jul 25 06:39:45 PM PDT 24
Peak memory 263136 kb
Host smart-9c6cfd68-c005-4c16-b70b-c29337da970b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912880911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmds
.912880911
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_intercept.1496586663
Short name T889
Test name
Test status
Simulation time 55649366 ps
CPU time 2.6 seconds
Started Jul 25 06:38:17 PM PDT 24
Finished Jul 25 06:38:20 PM PDT 24
Peak memory 232896 kb
Host smart-8b3aa333-69cd-422a-b061-511a9eb42ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496586663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.1496586663
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.730578024
Short name T511
Test name
Test status
Simulation time 12106291569 ps
CPU time 82.72 seconds
Started Jul 25 06:38:20 PM PDT 24
Finished Jul 25 06:39:43 PM PDT 24
Peak memory 249360 kb
Host smart-257ad569-fcd5-49c5-8ec9-91bf25ecebb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730578024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.730578024
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.1601459776
Short name T218
Test name
Test status
Simulation time 2520126824 ps
CPU time 11.54 seconds
Started Jul 25 06:38:19 PM PDT 24
Finished Jul 25 06:38:31 PM PDT 24
Peak memory 249340 kb
Host smart-d463be81-dbc7-47fd-903a-8a1709817761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601459776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.1601459776
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.1891253080
Short name T760
Test name
Test status
Simulation time 10181479504 ps
CPU time 29.09 seconds
Started Jul 25 06:38:19 PM PDT 24
Finished Jul 25 06:38:48 PM PDT 24
Peak memory 232932 kb
Host smart-540369dd-91e0-4844-951b-ec9ed7ee1b0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891253080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.1891253080
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.3616833442
Short name T403
Test name
Test status
Simulation time 625612391 ps
CPU time 4.12 seconds
Started Jul 25 06:38:22 PM PDT 24
Finished Jul 25 06:38:26 PM PDT 24
Peak memory 219376 kb
Host smart-ec4da725-2985-40f1-a8f9-d7edde015ff4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3616833442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.3616833442
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.3494107368
Short name T144
Test name
Test status
Simulation time 49004165 ps
CPU time 0.97 seconds
Started Jul 25 06:38:17 PM PDT 24
Finished Jul 25 06:38:19 PM PDT 24
Peak memory 207724 kb
Host smart-013580e5-0402-4338-afb7-9dc21cd837ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494107368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.3494107368
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.2989261620
Short name T577
Test name
Test status
Simulation time 3313249727 ps
CPU time 11.82 seconds
Started Jul 25 06:38:22 PM PDT 24
Finished Jul 25 06:38:34 PM PDT 24
Peak memory 216712 kb
Host smart-29050fad-c02c-4a26-b725-42ab783e9be3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989261620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.2989261620
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.2063206701
Short name T901
Test name
Test status
Simulation time 4632879523 ps
CPU time 3.4 seconds
Started Jul 25 06:38:14 PM PDT 24
Finished Jul 25 06:38:18 PM PDT 24
Peak memory 216508 kb
Host smart-20ac04a6-7b60-4bf3-9a98-1946c3f10987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063206701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.2063206701
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.1463874818
Short name T530
Test name
Test status
Simulation time 378737596 ps
CPU time 1.24 seconds
Started Jul 25 06:38:17 PM PDT 24
Finished Jul 25 06:38:19 PM PDT 24
Peak memory 216476 kb
Host smart-26b38f97-d71f-4e8d-8376-dc794e53c41e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463874818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.1463874818
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.1538927465
Short name T560
Test name
Test status
Simulation time 151436957 ps
CPU time 0.82 seconds
Started Jul 25 06:38:17 PM PDT 24
Finished Jul 25 06:38:18 PM PDT 24
Peak memory 206116 kb
Host smart-b0338a80-00c7-45f9-94a4-758f6ba379d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538927465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.1538927465
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.45800410
Short name T464
Test name
Test status
Simulation time 2768000511 ps
CPU time 6.87 seconds
Started Jul 25 06:38:19 PM PDT 24
Finished Jul 25 06:38:26 PM PDT 24
Peak memory 224708 kb
Host smart-c313626f-98d8-4cf4-9e13-f253db506ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45800410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.45800410
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.1129651303
Short name T329
Test name
Test status
Simulation time 55014115 ps
CPU time 0.72 seconds
Started Jul 25 06:38:22 PM PDT 24
Finished Jul 25 06:38:23 PM PDT 24
Peak memory 205520 kb
Host smart-d488c4c2-4366-48d3-a1cc-091e4ec94494
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129651303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
1129651303
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.34642091
Short name T970
Test name
Test status
Simulation time 482879232 ps
CPU time 6.72 seconds
Started Jul 25 06:38:18 PM PDT 24
Finished Jul 25 06:38:25 PM PDT 24
Peak memory 232880 kb
Host smart-2fb9aff2-11a7-4af7-a024-ab8ff4f6ad63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34642091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.34642091
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.2627566298
Short name T779
Test name
Test status
Simulation time 70792097 ps
CPU time 0.83 seconds
Started Jul 25 06:38:18 PM PDT 24
Finished Jul 25 06:38:19 PM PDT 24
Peak memory 206752 kb
Host smart-735778bf-9814-4b10-b4a8-bab59d44bdcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627566298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.2627566298
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.4172851621
Short name T167
Test name
Test status
Simulation time 10195447351 ps
CPU time 35 seconds
Started Jul 25 06:38:17 PM PDT 24
Finished Jul 25 06:38:52 PM PDT 24
Peak memory 241164 kb
Host smart-44f0485b-dc1d-4cdf-8569-f26c626d2da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172851621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.4172851621
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.2089260882
Short name T200
Test name
Test status
Simulation time 38092759774 ps
CPU time 339.72 seconds
Started Jul 25 06:38:18 PM PDT 24
Finished Jul 25 06:43:58 PM PDT 24
Peak memory 267556 kb
Host smart-17998beb-ba0f-476e-9cb9-fa13fe895192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089260882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.2089260882
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.1113869033
Short name T38
Test name
Test status
Simulation time 45462907735 ps
CPU time 386.17 seconds
Started Jul 25 06:38:19 PM PDT 24
Finished Jul 25 06:44:45 PM PDT 24
Peak memory 254748 kb
Host smart-4b8050a4-e636-4c1f-bb9e-226ef25f1cde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113869033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.1113869033
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.422843291
Short name T1
Test name
Test status
Simulation time 485937461 ps
CPU time 11.99 seconds
Started Jul 25 06:38:22 PM PDT 24
Finished Jul 25 06:38:35 PM PDT 24
Peak memory 240808 kb
Host smart-bb3b3d2f-076c-4d9f-bdc8-c590bb3c368e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422843291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.422843291
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.13102320
Short name T384
Test name
Test status
Simulation time 27565062791 ps
CPU time 54.84 seconds
Started Jul 25 06:38:18 PM PDT 24
Finished Jul 25 06:39:13 PM PDT 24
Peak memory 236936 kb
Host smart-d2e07d52-27ef-477f-8f6e-fbf2c6776c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13102320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmds.13102320
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/34.spi_device_intercept.4175023687
Short name T898
Test name
Test status
Simulation time 1010468070 ps
CPU time 12.19 seconds
Started Jul 25 06:38:22 PM PDT 24
Finished Jul 25 06:38:34 PM PDT 24
Peak memory 224668 kb
Host smart-589d7e40-9b53-402e-af38-d34a3207a130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175023687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.4175023687
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.2335530896
Short name T815
Test name
Test status
Simulation time 12428372262 ps
CPU time 34.58 seconds
Started Jul 25 06:38:21 PM PDT 24
Finished Jul 25 06:38:55 PM PDT 24
Peak memory 232940 kb
Host smart-e4e7b1d2-73ca-46cb-a026-2956f6a0aca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335530896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.2335530896
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.3979787718
Short name T641
Test name
Test status
Simulation time 5071669845 ps
CPU time 16.51 seconds
Started Jul 25 06:38:20 PM PDT 24
Finished Jul 25 06:38:37 PM PDT 24
Peak memory 232932 kb
Host smart-203dc539-52b2-4704-bdef-e4caa3f21992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979787718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.3979787718
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.2346881806
Short name T929
Test name
Test status
Simulation time 4966460379 ps
CPU time 11.04 seconds
Started Jul 25 06:38:18 PM PDT 24
Finished Jul 25 06:38:29 PM PDT 24
Peak memory 232844 kb
Host smart-4d729279-7b1e-44bd-9ce8-7bec2d4aa51c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346881806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.2346881806
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.1181875991
Short name T128
Test name
Test status
Simulation time 634149399 ps
CPU time 3.99 seconds
Started Jul 25 06:38:19 PM PDT 24
Finished Jul 25 06:38:23 PM PDT 24
Peak memory 223340 kb
Host smart-6a8c5292-59ea-464e-825c-5a1e4cd6529e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1181875991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.1181875991
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.4164231293
Short name T850
Test name
Test status
Simulation time 245895387 ps
CPU time 1.03 seconds
Started Jul 25 06:38:18 PM PDT 24
Finished Jul 25 06:38:19 PM PDT 24
Peak memory 207192 kb
Host smart-a478a0d5-f0db-48d9-b66a-855f6d3fd1fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164231293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.4164231293
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.184284324
Short name T923
Test name
Test status
Simulation time 22344462900 ps
CPU time 24.8 seconds
Started Jul 25 06:38:19 PM PDT 24
Finished Jul 25 06:38:44 PM PDT 24
Peak memory 220540 kb
Host smart-46d8a42d-7256-45f9-9430-3ef96464edc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184284324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.184284324
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.2139047408
Short name T954
Test name
Test status
Simulation time 1207300405 ps
CPU time 3.76 seconds
Started Jul 25 06:38:19 PM PDT 24
Finished Jul 25 06:38:23 PM PDT 24
Peak memory 216436 kb
Host smart-dbc92023-55eb-49af-b4b2-6f7adfcf9fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139047408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.2139047408
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.1218545450
Short name T5
Test name
Test status
Simulation time 371068372 ps
CPU time 6.05 seconds
Started Jul 25 06:38:18 PM PDT 24
Finished Jul 25 06:38:24 PM PDT 24
Peak memory 216384 kb
Host smart-bf19d0b2-5148-47cf-ac52-8091f489dc2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218545450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.1218545450
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.1126492305
Short name T785
Test name
Test status
Simulation time 84168194 ps
CPU time 0.79 seconds
Started Jul 25 06:38:21 PM PDT 24
Finished Jul 25 06:38:22 PM PDT 24
Peak memory 206120 kb
Host smart-59542ad7-ca52-4df0-a599-cff427c2c306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126492305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.1126492305
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.692284088
Short name T253
Test name
Test status
Simulation time 9744294113 ps
CPU time 31.43 seconds
Started Jul 25 06:38:19 PM PDT 24
Finished Jul 25 06:38:51 PM PDT 24
Peak memory 243664 kb
Host smart-823c5d68-291b-4451-9dc1-5c62b8ed2d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692284088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.692284088
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.106624524
Short name T681
Test name
Test status
Simulation time 75998988 ps
CPU time 0.73 seconds
Started Jul 25 06:38:30 PM PDT 24
Finished Jul 25 06:38:31 PM PDT 24
Peak memory 205032 kb
Host smart-85982f2c-e990-412b-bc31-a80cf50aa85c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106624524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.106624524
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.3749254214
Short name T706
Test name
Test status
Simulation time 305487103 ps
CPU time 4.89 seconds
Started Jul 25 06:38:26 PM PDT 24
Finished Jul 25 06:38:31 PM PDT 24
Peak memory 232824 kb
Host smart-c36897be-b273-42dc-8d39-0eecc8cd69b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749254214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.3749254214
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.1619468438
Short name T516
Test name
Test status
Simulation time 15121791 ps
CPU time 0.79 seconds
Started Jul 25 06:38:25 PM PDT 24
Finished Jul 25 06:38:26 PM PDT 24
Peak memory 205716 kb
Host smart-a481bf86-592a-4651-9901-e510a7fda08c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619468438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.1619468438
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.2270919901
Short name T838
Test name
Test status
Simulation time 24511463777 ps
CPU time 196.54 seconds
Started Jul 25 06:38:32 PM PDT 24
Finished Jul 25 06:41:49 PM PDT 24
Peak memory 254940 kb
Host smart-f3aa3ba9-99c3-41f5-8e7e-f03582341057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270919901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.2270919901
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.2204212882
Short name T292
Test name
Test status
Simulation time 121471620 ps
CPU time 5.29 seconds
Started Jul 25 06:38:29 PM PDT 24
Finished Jul 25 06:38:34 PM PDT 24
Peak memory 232920 kb
Host smart-4b2cb6bd-a36f-4ae2-bda0-c03005d85a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204212882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.2204212882
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.2058277416
Short name T534
Test name
Test status
Simulation time 4591934470 ps
CPU time 27.62 seconds
Started Jul 25 06:38:24 PM PDT 24
Finished Jul 25 06:38:52 PM PDT 24
Peak memory 249324 kb
Host smart-2fa0056c-72be-43e6-9cb2-9b8fb27a7ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058277416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmd
s.2058277416
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_intercept.545721312
Short name T557
Test name
Test status
Simulation time 184389237 ps
CPU time 4.78 seconds
Started Jul 25 06:38:33 PM PDT 24
Finished Jul 25 06:38:38 PM PDT 24
Peak memory 232216 kb
Host smart-a1342919-62f2-4175-a125-0ce99ed6024a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545721312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.545721312
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.1955868139
Short name T755
Test name
Test status
Simulation time 2469326936 ps
CPU time 17.99 seconds
Started Jul 25 06:38:25 PM PDT 24
Finished Jul 25 06:38:43 PM PDT 24
Peak memory 241172 kb
Host smart-9e56ecc5-f68c-450c-8374-ee0cbf35494e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955868139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.1955868139
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.3615610840
Short name T928
Test name
Test status
Simulation time 9294305751 ps
CPU time 16.07 seconds
Started Jul 25 06:38:33 PM PDT 24
Finished Jul 25 06:38:49 PM PDT 24
Peak memory 232980 kb
Host smart-405d82c5-a6f5-4001-916a-ae203d8447e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615610840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.3615610840
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.2947289632
Short name T563
Test name
Test status
Simulation time 16897790249 ps
CPU time 11.01 seconds
Started Jul 25 06:38:25 PM PDT 24
Finished Jul 25 06:38:37 PM PDT 24
Peak memory 232976 kb
Host smart-8f06f7d8-ac8b-4a0f-b5c9-e2ceea0e80d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947289632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.2947289632
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.1203381752
Short name T369
Test name
Test status
Simulation time 821637688 ps
CPU time 5.46 seconds
Started Jul 25 06:38:24 PM PDT 24
Finished Jul 25 06:38:30 PM PDT 24
Peak memory 222924 kb
Host smart-5f55bec2-cc5a-47c4-beb7-f49becb03cfd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1203381752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.1203381752
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.816091918
Short name T559
Test name
Test status
Simulation time 129300202186 ps
CPU time 307.42 seconds
Started Jul 25 06:38:25 PM PDT 24
Finished Jul 25 06:43:32 PM PDT 24
Peak memory 257584 kb
Host smart-637ee820-c41c-48ad-8f1d-f9d1b3493a3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816091918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stres
s_all.816091918
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.817273601
Short name T891
Test name
Test status
Simulation time 27543277887 ps
CPU time 39.2 seconds
Started Jul 25 06:38:18 PM PDT 24
Finished Jul 25 06:38:57 PM PDT 24
Peak memory 216632 kb
Host smart-041b0ddd-5269-46d0-b23d-0c5f9eee82f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817273601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.817273601
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.1282146492
Short name T921
Test name
Test status
Simulation time 4725108018 ps
CPU time 7.15 seconds
Started Jul 25 06:38:19 PM PDT 24
Finished Jul 25 06:38:26 PM PDT 24
Peak memory 216488 kb
Host smart-b8610d1c-a34f-43e6-9346-bcf2a04fca26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282146492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.1282146492
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.630054857
Short name T357
Test name
Test status
Simulation time 12764098 ps
CPU time 0.77 seconds
Started Jul 25 06:38:26 PM PDT 24
Finished Jul 25 06:38:27 PM PDT 24
Peak memory 206156 kb
Host smart-82b222b8-9216-4576-a323-2337d4c0c0ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630054857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.630054857
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.1842630813
Short name T355
Test name
Test status
Simulation time 76509296 ps
CPU time 0.82 seconds
Started Jul 25 06:38:18 PM PDT 24
Finished Jul 25 06:38:19 PM PDT 24
Peak memory 206136 kb
Host smart-2652383e-767e-4a9e-85b6-04c832c41de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842630813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.1842630813
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.2627226007
Short name T252
Test name
Test status
Simulation time 376970561 ps
CPU time 5.37 seconds
Started Jul 25 06:38:27 PM PDT 24
Finished Jul 25 06:38:33 PM PDT 24
Peak memory 232916 kb
Host smart-9e29cb69-2f6f-4d9f-bf13-5f63ee5f1030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627226007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.2627226007
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.3839162830
Short name T906
Test name
Test status
Simulation time 19972176 ps
CPU time 0.74 seconds
Started Jul 25 06:38:30 PM PDT 24
Finished Jul 25 06:38:31 PM PDT 24
Peak memory 205536 kb
Host smart-61e60047-f5ac-49ab-abc5-8b9538ae775d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839162830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
3839162830
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.386437429
Short name T834
Test name
Test status
Simulation time 386962422 ps
CPU time 4.18 seconds
Started Jul 25 06:38:27 PM PDT 24
Finished Jul 25 06:38:32 PM PDT 24
Peak memory 232916 kb
Host smart-ef138199-5680-42e5-85b1-ee6b46719e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386437429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.386437429
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.2886429333
Short name T795
Test name
Test status
Simulation time 34764476 ps
CPU time 0.79 seconds
Started Jul 25 06:38:28 PM PDT 24
Finished Jul 25 06:38:29 PM PDT 24
Peak memory 206756 kb
Host smart-f7359512-b251-4710-8e59-a1e50447a141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886429333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.2886429333
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.3521972464
Short name T155
Test name
Test status
Simulation time 3457955729 ps
CPU time 68.87 seconds
Started Jul 25 06:38:24 PM PDT 24
Finished Jul 25 06:39:33 PM PDT 24
Peak memory 257556 kb
Host smart-1b1e362b-6286-492a-b843-0cb8cd1097ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521972464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.3521972464
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.164334862
Short name T205
Test name
Test status
Simulation time 28050713579 ps
CPU time 110.81 seconds
Started Jul 25 06:38:26 PM PDT 24
Finished Jul 25 06:40:17 PM PDT 24
Peak memory 250344 kb
Host smart-f6884dd7-9fcc-475f-b1bb-2e8fe2abd73c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164334862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.164334862
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.2636138625
Short name T927
Test name
Test status
Simulation time 227306761 ps
CPU time 4.92 seconds
Started Jul 25 06:38:29 PM PDT 24
Finished Jul 25 06:38:34 PM PDT 24
Peak memory 239136 kb
Host smart-abad7f9e-205e-4369-81d7-40efd210f2bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636138625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.2636138625
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.399772850
Short name T6
Test name
Test status
Simulation time 9227440051 ps
CPU time 62.93 seconds
Started Jul 25 06:38:25 PM PDT 24
Finished Jul 25 06:39:28 PM PDT 24
Peak memory 249364 kb
Host smart-3fb364b0-9b49-4e02-80e1-7282aa43344a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399772850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmds
.399772850
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_intercept.3782841624
Short name T905
Test name
Test status
Simulation time 567056025 ps
CPU time 4.36 seconds
Started Jul 25 06:38:29 PM PDT 24
Finished Jul 25 06:38:33 PM PDT 24
Peak memory 232844 kb
Host smart-a8b7b926-5c02-4ede-bc42-5f417c68fe38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782841624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.3782841624
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.842785094
Short name T691
Test name
Test status
Simulation time 7813724599 ps
CPU time 37.81 seconds
Started Jul 25 06:38:42 PM PDT 24
Finished Jul 25 06:39:20 PM PDT 24
Peak memory 232976 kb
Host smart-29a59897-8207-44be-9209-75bbda2cd1e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842785094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.842785094
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.3592892053
Short name T269
Test name
Test status
Simulation time 514660230 ps
CPU time 7.42 seconds
Started Jul 25 06:38:26 PM PDT 24
Finished Jul 25 06:38:33 PM PDT 24
Peak memory 224652 kb
Host smart-cf21917d-b6d5-4a52-a70b-5fd8265d4511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592892053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.3592892053
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.901153668
Short name T918
Test name
Test status
Simulation time 1075208246 ps
CPU time 7.55 seconds
Started Jul 25 06:38:24 PM PDT 24
Finished Jul 25 06:38:32 PM PDT 24
Peak memory 224656 kb
Host smart-cf88b60a-c6c9-4323-b732-e4846c630700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901153668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.901153668
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.386276107
Short name T434
Test name
Test status
Simulation time 735428046 ps
CPU time 8.17 seconds
Started Jul 25 06:38:27 PM PDT 24
Finished Jul 25 06:38:35 PM PDT 24
Peak memory 223248 kb
Host smart-aaa429a9-39f9-472d-8abd-f562cc0766ee
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=386276107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dire
ct.386276107
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.1271841301
Short name T917
Test name
Test status
Simulation time 69026817844 ps
CPU time 241.34 seconds
Started Jul 25 06:38:27 PM PDT 24
Finished Jul 25 06:42:28 PM PDT 24
Peak memory 255964 kb
Host smart-71074e0e-dd1d-4d39-8501-8e95fd50e077
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271841301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.1271841301
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.37487889
Short name T739
Test name
Test status
Simulation time 20284895 ps
CPU time 0.74 seconds
Started Jul 25 06:38:26 PM PDT 24
Finished Jul 25 06:38:27 PM PDT 24
Peak memory 205844 kb
Host smart-915687f0-98cf-4fe3-a7cf-0d56c80e36d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37487889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.37487889
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.3286868234
Short name T668
Test name
Test status
Simulation time 9636247729 ps
CPU time 4.51 seconds
Started Jul 25 06:38:33 PM PDT 24
Finished Jul 25 06:38:38 PM PDT 24
Peak memory 216628 kb
Host smart-4180a4d8-1955-4b98-a7e0-82ad6e02c2d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286868234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.3286868234
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.520061178
Short name T7
Test name
Test status
Simulation time 311987240 ps
CPU time 7.23 seconds
Started Jul 25 06:38:30 PM PDT 24
Finished Jul 25 06:38:37 PM PDT 24
Peak memory 216488 kb
Host smart-49ecd134-5bc1-4564-ae4f-7a9f80a07f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520061178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.520061178
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.2509900143
Short name T364
Test name
Test status
Simulation time 357723722 ps
CPU time 0.94 seconds
Started Jul 25 06:38:27 PM PDT 24
Finished Jul 25 06:38:28 PM PDT 24
Peak memory 207128 kb
Host smart-2acf649f-7d62-4cab-9b7c-15bb3262c912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509900143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.2509900143
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.2154685580
Short name T330
Test name
Test status
Simulation time 8053500485 ps
CPU time 16.71 seconds
Started Jul 25 06:38:27 PM PDT 24
Finished Jul 25 06:38:44 PM PDT 24
Peak memory 239896 kb
Host smart-0fab76a9-84f1-400f-819f-8b8756556870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154685580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.2154685580
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.3878335627
Short name T452
Test name
Test status
Simulation time 72343993 ps
CPU time 0.77 seconds
Started Jul 25 06:38:27 PM PDT 24
Finished Jul 25 06:38:28 PM PDT 24
Peak memory 205556 kb
Host smart-09365c8a-8453-4f58-948f-d5934c01c4b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878335627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
3878335627
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.3073347632
Short name T632
Test name
Test status
Simulation time 6232462432 ps
CPU time 8.16 seconds
Started Jul 25 06:38:33 PM PDT 24
Finished Jul 25 06:38:42 PM PDT 24
Peak memory 224744 kb
Host smart-53aeaf90-7a63-4bc7-8f3b-0246ab1138f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073347632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.3073347632
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.1106879220
Short name T457
Test name
Test status
Simulation time 14734518 ps
CPU time 0.74 seconds
Started Jul 25 06:38:33 PM PDT 24
Finished Jul 25 06:38:34 PM PDT 24
Peak memory 205724 kb
Host smart-48f40ed7-1fea-4e53-b9f2-cd5513325fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106879220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.1106879220
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.697942241
Short name T243
Test name
Test status
Simulation time 15139365911 ps
CPU time 86.14 seconds
Started Jul 25 06:38:27 PM PDT 24
Finished Jul 25 06:39:53 PM PDT 24
Peak memory 257464 kb
Host smart-b86affd8-00cf-42b3-94b1-e3761c863dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697942241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.697942241
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.2498084683
Short name T737
Test name
Test status
Simulation time 12697837081 ps
CPU time 137.6 seconds
Started Jul 25 06:38:32 PM PDT 24
Finished Jul 25 06:40:49 PM PDT 24
Peak memory 237516 kb
Host smart-c6d55681-2a8d-4f04-8a32-aefa070c90b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498084683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.2498084683
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.1817168192
Short name T265
Test name
Test status
Simulation time 7922880568 ps
CPU time 134.83 seconds
Started Jul 25 06:38:28 PM PDT 24
Finished Jul 25 06:40:43 PM PDT 24
Peak memory 266500 kb
Host smart-00dc1127-b4a1-4ba7-a1be-c41570cd1c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817168192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.1817168192
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.2193575924
Short name T853
Test name
Test status
Simulation time 2171868507 ps
CPU time 36.22 seconds
Started Jul 25 06:38:28 PM PDT 24
Finished Jul 25 06:39:04 PM PDT 24
Peak memory 232980 kb
Host smart-8236692c-66ab-46e7-9295-a63d6398073a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193575924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.2193575924
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.1045850842
Short name T198
Test name
Test status
Simulation time 7873514618 ps
CPU time 73.07 seconds
Started Jul 25 06:38:24 PM PDT 24
Finished Jul 25 06:39:37 PM PDT 24
Peak memory 254516 kb
Host smart-ed7e01a3-8496-4c84-9093-45a0fa1ef4e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045850842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmd
s.1045850842
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_intercept.2669075582
Short name T481
Test name
Test status
Simulation time 3851487570 ps
CPU time 43.61 seconds
Started Jul 25 06:38:30 PM PDT 24
Finished Jul 25 06:39:14 PM PDT 24
Peak memory 224788 kb
Host smart-8b83e1dc-e9ba-4fc1-b149-6cfe003f959e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669075582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.2669075582
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.1315903992
Short name T836
Test name
Test status
Simulation time 3242121647 ps
CPU time 23.28 seconds
Started Jul 25 06:38:25 PM PDT 24
Finished Jul 25 06:38:48 PM PDT 24
Peak memory 249352 kb
Host smart-26f6efc1-5ac6-47e6-b6e3-b4fc3248b9c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315903992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.1315903992
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.861511820
Short name T818
Test name
Test status
Simulation time 31496951 ps
CPU time 2.61 seconds
Started Jul 25 06:38:31 PM PDT 24
Finished Jul 25 06:38:34 PM PDT 24
Peak memory 232552 kb
Host smart-51804e58-0864-4474-8680-f7bf24ac2b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861511820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swap
.861511820
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.3150585029
Short name T610
Test name
Test status
Simulation time 21770714173 ps
CPU time 20.21 seconds
Started Jul 25 06:38:30 PM PDT 24
Finished Jul 25 06:38:50 PM PDT 24
Peak memory 232924 kb
Host smart-2abe5f2d-c9e7-4573-a7c2-c5c9f5efb636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150585029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.3150585029
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.2606015325
Short name T351
Test name
Test status
Simulation time 1165020235 ps
CPU time 8.96 seconds
Started Jul 25 06:38:25 PM PDT 24
Finished Jul 25 06:38:34 PM PDT 24
Peak memory 223344 kb
Host smart-b3e648b0-dad0-4637-88b3-30b00365f2da
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2606015325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.2606015325
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.126628771
Short name T284
Test name
Test status
Simulation time 184823936266 ps
CPU time 200.01 seconds
Started Jul 25 06:38:32 PM PDT 24
Finished Jul 25 06:41:52 PM PDT 24
Peak memory 274020 kb
Host smart-f305d820-4f24-4485-bbf6-2168a1b5002a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126628771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stres
s_all.126628771
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.3910796524
Short name T720
Test name
Test status
Simulation time 3898935327 ps
CPU time 29.91 seconds
Started Jul 25 06:38:28 PM PDT 24
Finished Jul 25 06:38:58 PM PDT 24
Peak memory 216664 kb
Host smart-87d50a5e-737d-4088-9d7b-68a2a60a259c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910796524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.3910796524
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.2909347374
Short name T635
Test name
Test status
Simulation time 7342823139 ps
CPU time 5.2 seconds
Started Jul 25 06:38:27 PM PDT 24
Finished Jul 25 06:38:33 PM PDT 24
Peak memory 217456 kb
Host smart-8314c820-42c3-4c5a-9956-1e71e876a9ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909347374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.2909347374
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.19294887
Short name T826
Test name
Test status
Simulation time 413795392 ps
CPU time 2.01 seconds
Started Jul 25 06:38:28 PM PDT 24
Finished Jul 25 06:38:31 PM PDT 24
Peak memory 216256 kb
Host smart-487b7ebd-da49-424b-a1c9-267f30d0b804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19294887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.19294887
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.79978348
Short name T791
Test name
Test status
Simulation time 22534466 ps
CPU time 0.73 seconds
Started Jul 25 06:38:32 PM PDT 24
Finished Jul 25 06:38:33 PM PDT 24
Peak memory 206096 kb
Host smart-c98aa40d-b5fe-4e58-a3dd-3dc148c0c835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79978348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.79978348
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.3191917914
Short name T449
Test name
Test status
Simulation time 65427042 ps
CPU time 2.16 seconds
Started Jul 25 06:38:33 PM PDT 24
Finished Jul 25 06:38:36 PM PDT 24
Peak memory 223808 kb
Host smart-bd495eab-8969-4048-a102-c036e4986bd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191917914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.3191917914
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.1430382075
Short name T317
Test name
Test status
Simulation time 36740581 ps
CPU time 0.73 seconds
Started Jul 25 06:38:27 PM PDT 24
Finished Jul 25 06:38:28 PM PDT 24
Peak memory 205604 kb
Host smart-b1d39a74-176b-4947-868f-451f8d48fdcf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430382075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
1430382075
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.3800333615
Short name T933
Test name
Test status
Simulation time 312174563 ps
CPU time 2.62 seconds
Started Jul 25 06:38:32 PM PDT 24
Finished Jul 25 06:38:34 PM PDT 24
Peak memory 224644 kb
Host smart-a746e24f-6e3b-4d71-a107-b4533b9c8ec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800333615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.3800333615
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.2717086157
Short name T787
Test name
Test status
Simulation time 55282418 ps
CPU time 0.78 seconds
Started Jul 25 06:38:28 PM PDT 24
Finished Jul 25 06:38:29 PM PDT 24
Peak memory 206604 kb
Host smart-044c6c82-0955-4a03-90d1-eff5a07c711a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717086157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.2717086157
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.2960845612
Short name T263
Test name
Test status
Simulation time 202370531366 ps
CPU time 360.38 seconds
Started Jul 25 06:38:31 PM PDT 24
Finished Jul 25 06:44:32 PM PDT 24
Peak memory 264396 kb
Host smart-1d1a6723-1b3a-4a4f-ac01-9a027be04082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960845612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.2960845612
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.2006878687
Short name T204
Test name
Test status
Simulation time 80286555874 ps
CPU time 86.41 seconds
Started Jul 25 06:38:32 PM PDT 24
Finished Jul 25 06:39:59 PM PDT 24
Peak memory 256848 kb
Host smart-48b9dcc6-a627-4ea4-9efd-b10e9496d19c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006878687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.2006878687
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.2827135428
Short name T217
Test name
Test status
Simulation time 35537429894 ps
CPU time 93.56 seconds
Started Jul 25 06:38:28 PM PDT 24
Finished Jul 25 06:40:02 PM PDT 24
Peak memory 254356 kb
Host smart-bd63e865-071c-46ce-8528-4c3c678d322a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827135428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.2827135428
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.2664580471
Short name T629
Test name
Test status
Simulation time 155783978 ps
CPU time 3.65 seconds
Started Jul 25 06:38:30 PM PDT 24
Finished Jul 25 06:38:34 PM PDT 24
Peak memory 224660 kb
Host smart-294c6a6f-d474-4020-9b0d-19f2997a612d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664580471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.2664580471
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.494809041
Short name T85
Test name
Test status
Simulation time 16541460284 ps
CPU time 64.13 seconds
Started Jul 25 06:38:32 PM PDT 24
Finished Jul 25 06:39:36 PM PDT 24
Peak memory 254732 kb
Host smart-2960f143-5001-4171-86f8-3597770c20fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494809041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmds
.494809041
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_intercept.4116603387
Short name T392
Test name
Test status
Simulation time 21285990211 ps
CPU time 25.1 seconds
Started Jul 25 06:38:28 PM PDT 24
Finished Jul 25 06:38:54 PM PDT 24
Peak memory 224768 kb
Host smart-15d6d80b-9b48-458c-b78c-a62a83e7e974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116603387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.4116603387
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.1109676140
Short name T858
Test name
Test status
Simulation time 10726038528 ps
CPU time 51.16 seconds
Started Jul 25 06:38:40 PM PDT 24
Finished Jul 25 06:39:31 PM PDT 24
Peak memory 232984 kb
Host smart-dc0999e5-517d-4314-943e-dd2bf90f3766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109676140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.1109676140
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.1043944858
Short name T371
Test name
Test status
Simulation time 689348017 ps
CPU time 2.52 seconds
Started Jul 25 06:38:27 PM PDT 24
Finished Jul 25 06:38:30 PM PDT 24
Peak memory 224680 kb
Host smart-bc7e0dbd-3bde-4c9e-908a-336a7b69a83f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043944858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.1043944858
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.369390598
Short name T960
Test name
Test status
Simulation time 326479109 ps
CPU time 2.43 seconds
Started Jul 25 06:38:27 PM PDT 24
Finished Jul 25 06:38:30 PM PDT 24
Peak memory 232540 kb
Host smart-df781122-5d7c-4dac-ab36-c7672ad60f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369390598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.369390598
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.2304656223
Short name T391
Test name
Test status
Simulation time 281292785 ps
CPU time 4.32 seconds
Started Jul 25 06:38:27 PM PDT 24
Finished Jul 25 06:38:32 PM PDT 24
Peak memory 218760 kb
Host smart-cd13f849-b2f3-493b-93b1-bbd2a70b30ce
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2304656223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.2304656223
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.51170389
Short name T605
Test name
Test status
Simulation time 41320961230 ps
CPU time 29.61 seconds
Started Jul 25 06:38:27 PM PDT 24
Finished Jul 25 06:38:57 PM PDT 24
Peak memory 216416 kb
Host smart-f39b59e7-c2f2-4519-8130-50efc167f700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51170389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.51170389
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.3124079930
Short name T900
Test name
Test status
Simulation time 9147716672 ps
CPU time 13.75 seconds
Started Jul 25 06:38:33 PM PDT 24
Finished Jul 25 06:38:47 PM PDT 24
Peak memory 216496 kb
Host smart-5affab54-0ff6-4038-8e26-aa9877dbc30d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124079930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.3124079930
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.1160049972
Short name T407
Test name
Test status
Simulation time 108997259 ps
CPU time 1.1 seconds
Started Jul 25 06:38:28 PM PDT 24
Finished Jul 25 06:38:30 PM PDT 24
Peak memory 208024 kb
Host smart-3f725c1e-2c38-4670-b7b1-af78ef7c3d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160049972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.1160049972
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.787658907
Short name T658
Test name
Test status
Simulation time 231529159 ps
CPU time 0.86 seconds
Started Jul 25 06:38:28 PM PDT 24
Finished Jul 25 06:38:29 PM PDT 24
Peak memory 206080 kb
Host smart-eb1db880-0440-422f-abc2-0e7d3eb74a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787658907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.787658907
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.1499530372
Short name T978
Test name
Test status
Simulation time 14192069485 ps
CPU time 15.66 seconds
Started Jul 25 06:38:26 PM PDT 24
Finished Jul 25 06:38:42 PM PDT 24
Peak memory 241092 kb
Host smart-3d399a3c-e0a0-45ef-9f3d-7e04da8d1f23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499530372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.1499530372
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.1488065003
Short name T800
Test name
Test status
Simulation time 14594057 ps
CPU time 0.75 seconds
Started Jul 25 06:38:35 PM PDT 24
Finished Jul 25 06:38:36 PM PDT 24
Peak memory 205596 kb
Host smart-fd2c504e-b624-433c-8508-4f33aa42e3df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488065003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
1488065003
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.1450497405
Short name T3
Test name
Test status
Simulation time 104847653 ps
CPU time 3.51 seconds
Started Jul 25 06:38:36 PM PDT 24
Finished Jul 25 06:38:40 PM PDT 24
Peak memory 232876 kb
Host smart-19d3cc74-482a-48e8-9375-c382eb0c9994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450497405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.1450497405
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.358995495
Short name T327
Test name
Test status
Simulation time 21916166 ps
CPU time 0.77 seconds
Started Jul 25 06:38:40 PM PDT 24
Finished Jul 25 06:38:41 PM PDT 24
Peak memory 207076 kb
Host smart-6277bc80-14cb-44c2-ac0c-156713fd445b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358995495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.358995495
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.1118690147
Short name T366
Test name
Test status
Simulation time 51891665 ps
CPU time 0.97 seconds
Started Jul 25 06:38:35 PM PDT 24
Finished Jul 25 06:38:36 PM PDT 24
Peak memory 216152 kb
Host smart-86a01f11-1851-4ec6-abc4-484c73e9dfaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118690147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.1118690147
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.742250142
Short name T812
Test name
Test status
Simulation time 797606126930 ps
CPU time 370.99 seconds
Started Jul 25 06:38:35 PM PDT 24
Finished Jul 25 06:44:47 PM PDT 24
Peak memory 253516 kb
Host smart-d0de6cbe-754b-4b05-b096-26faa60d7aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742250142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.742250142
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.2026880522
Short name T799
Test name
Test status
Simulation time 1051549939 ps
CPU time 15.67 seconds
Started Jul 25 06:38:39 PM PDT 24
Finished Jul 25 06:38:55 PM PDT 24
Peak memory 217768 kb
Host smart-f3680ec5-7066-4d88-997b-96de81dddc59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026880522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.2026880522
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.1223283648
Short name T820
Test name
Test status
Simulation time 160929673 ps
CPU time 3.44 seconds
Started Jul 25 06:38:37 PM PDT 24
Finished Jul 25 06:38:40 PM PDT 24
Peak memory 224704 kb
Host smart-e7729a76-8ea7-4685-8c75-69ba8de18bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223283648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.1223283648
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.587206452
Short name T172
Test name
Test status
Simulation time 102364401223 ps
CPU time 176.69 seconds
Started Jul 25 06:38:34 PM PDT 24
Finished Jul 25 06:41:30 PM PDT 24
Peak memory 252728 kb
Host smart-4ffbef3d-9ca5-46a2-9d1b-0a41e1cef3cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587206452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmds
.587206452
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/39.spi_device_intercept.3044980988
Short name T368
Test name
Test status
Simulation time 214732052 ps
CPU time 4.96 seconds
Started Jul 25 06:38:43 PM PDT 24
Finished Jul 25 06:38:49 PM PDT 24
Peak memory 224724 kb
Host smart-23b75120-9eeb-4b20-85bd-c6f64cc158a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044980988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.3044980988
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.538215647
Short name T645
Test name
Test status
Simulation time 713526284 ps
CPU time 10.98 seconds
Started Jul 25 06:38:36 PM PDT 24
Finished Jul 25 06:38:47 PM PDT 24
Peak memory 224724 kb
Host smart-484eb168-df7f-44a1-8c5f-7cb69d01b50f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538215647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.538215647
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.3874416352
Short name T977
Test name
Test status
Simulation time 140460412 ps
CPU time 2.24 seconds
Started Jul 25 06:38:34 PM PDT 24
Finished Jul 25 06:38:37 PM PDT 24
Peak memory 224276 kb
Host smart-0507be60-e261-4f88-ad15-100b30fcd716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874416352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.3874416352
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.1572147702
Short name T436
Test name
Test status
Simulation time 13434872177 ps
CPU time 17.34 seconds
Started Jul 25 06:38:36 PM PDT 24
Finished Jul 25 06:38:53 PM PDT 24
Peak memory 232952 kb
Host smart-72149ad4-bd8c-4df4-b201-4d88a54a85ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572147702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.1572147702
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.972508048
Short name T126
Test name
Test status
Simulation time 2572624649 ps
CPU time 6.27 seconds
Started Jul 25 06:38:35 PM PDT 24
Finished Jul 25 06:38:42 PM PDT 24
Peak memory 223584 kb
Host smart-c9cc6442-a40e-4ff1-996e-bf284dfaa2b0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=972508048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dire
ct.972508048
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.70874432
Short name T618
Test name
Test status
Simulation time 38718086 ps
CPU time 1.01 seconds
Started Jul 25 06:38:36 PM PDT 24
Finished Jul 25 06:38:37 PM PDT 24
Peak memory 206956 kb
Host smart-7648f9cd-300a-47ff-ae7c-503e3d8235bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70874432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stress
_all.70874432
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.1195938383
Short name T964
Test name
Test status
Simulation time 13876845363 ps
CPU time 48.43 seconds
Started Jul 25 06:38:31 PM PDT 24
Finished Jul 25 06:39:19 PM PDT 24
Peak memory 220364 kb
Host smart-258ed75b-989f-4df4-aee3-f199645c8f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195938383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.1195938383
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.1190962733
Short name T325
Test name
Test status
Simulation time 913197268 ps
CPU time 5.15 seconds
Started Jul 25 06:38:34 PM PDT 24
Finished Jul 25 06:38:40 PM PDT 24
Peak memory 216436 kb
Host smart-a41f8ca8-99fa-4905-b512-bef6dde00041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190962733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.1190962733
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.290326989
Short name T538
Test name
Test status
Simulation time 144473207 ps
CPU time 1.25 seconds
Started Jul 25 06:38:36 PM PDT 24
Finished Jul 25 06:38:37 PM PDT 24
Peak memory 207996 kb
Host smart-3af8f9e2-76e4-4bb1-adcc-4092e093fc69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290326989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.290326989
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.597694988
Short name T699
Test name
Test status
Simulation time 50169107 ps
CPU time 0.85 seconds
Started Jul 25 06:38:42 PM PDT 24
Finished Jul 25 06:38:43 PM PDT 24
Peak memory 206120 kb
Host smart-6edb3fca-b2d3-46c0-a85b-c557652848bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597694988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.597694988
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.1387706283
Short name T756
Test name
Test status
Simulation time 129611151 ps
CPU time 2.88 seconds
Started Jul 25 06:38:43 PM PDT 24
Finished Jul 25 06:38:47 PM PDT 24
Peak memory 232928 kb
Host smart-db4ed3d3-b2bb-45ee-8702-7405c9d6789c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387706283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.1387706283
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.2454674008
Short name T58
Test name
Test status
Simulation time 23753598 ps
CPU time 0.72 seconds
Started Jul 25 06:36:38 PM PDT 24
Finished Jul 25 06:36:44 PM PDT 24
Peak memory 205580 kb
Host smart-c11f0bc2-6b7b-4ee6-8c06-936c7169123f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454674008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.2
454674008
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.2059429814
Short name T764
Test name
Test status
Simulation time 74059812 ps
CPU time 2.06 seconds
Started Jul 25 06:36:38 PM PDT 24
Finished Jul 25 06:36:41 PM PDT 24
Peak memory 224316 kb
Host smart-31d8f654-5b24-4c48-9823-dab2395609f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059429814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.2059429814
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.1662846907
Short name T884
Test name
Test status
Simulation time 32933963 ps
CPU time 0.8 seconds
Started Jul 25 06:36:52 PM PDT 24
Finished Jul 25 06:36:52 PM PDT 24
Peak memory 206692 kb
Host smart-e5af104c-c518-44d3-8f36-ad833661d108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662846907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.1662846907
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.2196829832
Short name T947
Test name
Test status
Simulation time 112120408863 ps
CPU time 404.61 seconds
Started Jul 25 06:36:34 PM PDT 24
Finished Jul 25 06:43:19 PM PDT 24
Peak memory 260692 kb
Host smart-9b184687-28a3-46f3-817a-06cf8d2f43ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196829832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.2196829832
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.2698905307
Short name T996
Test name
Test status
Simulation time 41863767403 ps
CPU time 109.95 seconds
Started Jul 25 06:36:35 PM PDT 24
Finished Jul 25 06:38:25 PM PDT 24
Peak memory 273940 kb
Host smart-f32bf303-8d5f-47e7-a3cf-356a4e09ab56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698905307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.2698905307
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.1926897159
Short name T703
Test name
Test status
Simulation time 64530824259 ps
CPU time 121.65 seconds
Started Jul 25 06:36:50 PM PDT 24
Finished Jul 25 06:38:51 PM PDT 24
Peak memory 251176 kb
Host smart-3d0f5d2b-1389-448c-a687-75311f2937d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926897159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.1926897159
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.2131744178
Short name T298
Test name
Test status
Simulation time 214503725 ps
CPU time 6.55 seconds
Started Jul 25 06:36:36 PM PDT 24
Finished Jul 25 06:36:43 PM PDT 24
Peak memory 232896 kb
Host smart-78a43782-e140-4a87-a87e-960d16d134e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131744178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.2131744178
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_intercept.2768910075
Short name T811
Test name
Test status
Simulation time 1095899853 ps
CPU time 9.87 seconds
Started Jul 25 06:36:33 PM PDT 24
Finished Jul 25 06:36:43 PM PDT 24
Peak memory 224724 kb
Host smart-a8e93e69-6e72-4db8-94b4-b5f1b66e16d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768910075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.2768910075
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.368831989
Short name T991
Test name
Test status
Simulation time 7367669188 ps
CPU time 56.16 seconds
Started Jul 25 06:36:33 PM PDT 24
Finished Jul 25 06:37:29 PM PDT 24
Peak memory 232916 kb
Host smart-be540dc4-2ffb-4c07-9cb5-f3ae9755d104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368831989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.368831989
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.889478389
Short name T239
Test name
Test status
Simulation time 317955497 ps
CPU time 3.42 seconds
Started Jul 25 06:36:36 PM PDT 24
Finished Jul 25 06:36:40 PM PDT 24
Peak memory 232908 kb
Host smart-9db0855a-b254-4468-a2c0-b69d0616e5fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889478389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap.
889478389
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.668911431
Short name T227
Test name
Test status
Simulation time 847441785 ps
CPU time 6.61 seconds
Started Jul 25 06:36:32 PM PDT 24
Finished Jul 25 06:36:39 PM PDT 24
Peak memory 237792 kb
Host smart-f2becf8c-1b7b-4936-b04a-f53977ab4c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668911431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.668911431
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.4007714451
Short name T713
Test name
Test status
Simulation time 2994445082 ps
CPU time 5.33 seconds
Started Jul 25 06:36:41 PM PDT 24
Finished Jul 25 06:36:47 PM PDT 24
Peak memory 219516 kb
Host smart-b9c9030a-cbc1-4af4-947e-8b6c5dd0612a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4007714451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.4007714451
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.3226179868
Short name T34
Test name
Test status
Simulation time 352410129 ps
CPU time 1.19 seconds
Started Jul 25 06:36:35 PM PDT 24
Finished Jul 25 06:36:36 PM PDT 24
Peak memory 236484 kb
Host smart-0f704703-4e8f-4468-b049-bed69b4ee685
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226179868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.3226179868
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.2258567912
Short name T830
Test name
Test status
Simulation time 318270072549 ps
CPU time 490.56 seconds
Started Jul 25 06:36:36 PM PDT 24
Finished Jul 25 06:44:47 PM PDT 24
Peak memory 256408 kb
Host smart-358cc1e0-7526-4dd5-a33f-66eae25e34ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258567912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.2258567912
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.3893561245
Short name T857
Test name
Test status
Simulation time 15029413988 ps
CPU time 21.03 seconds
Started Jul 25 06:36:49 PM PDT 24
Finished Jul 25 06:37:10 PM PDT 24
Peak memory 216592 kb
Host smart-8020a97f-af84-4055-9b34-94c73fb3739e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893561245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.3893561245
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.2427783724
Short name T631
Test name
Test status
Simulation time 33320914528 ps
CPU time 21.5 seconds
Started Jul 25 06:36:49 PM PDT 24
Finished Jul 25 06:37:10 PM PDT 24
Peak memory 216388 kb
Host smart-7df8c7d1-7174-4cf6-88b9-9516685698af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427783724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.2427783724
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.3597445578
Short name T729
Test name
Test status
Simulation time 121295743 ps
CPU time 1.23 seconds
Started Jul 25 06:36:41 PM PDT 24
Finished Jul 25 06:36:42 PM PDT 24
Peak memory 216428 kb
Host smart-7c578ea8-4a45-4433-8077-e0ccfc2287f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597445578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.3597445578
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.3053263496
Short name T963
Test name
Test status
Simulation time 215596593 ps
CPU time 0.9 seconds
Started Jul 25 06:36:47 PM PDT 24
Finished Jul 25 06:36:49 PM PDT 24
Peak memory 207072 kb
Host smart-39a0d939-673a-457c-8175-c3b4be25faa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053263496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.3053263496
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.99189156
Short name T1008
Test name
Test status
Simulation time 367573036 ps
CPU time 3.35 seconds
Started Jul 25 06:36:40 PM PDT 24
Finished Jul 25 06:36:44 PM PDT 24
Peak memory 224712 kb
Host smart-b88603f6-b9ee-4416-952e-adc1272969f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99189156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.99189156
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.2027788478
Short name T444
Test name
Test status
Simulation time 90431655 ps
CPU time 0.73 seconds
Started Jul 25 06:38:43 PM PDT 24
Finished Jul 25 06:38:44 PM PDT 24
Peak memory 205028 kb
Host smart-03364b24-4c98-47f2-84da-ff59f27cbe7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027788478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
2027788478
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.376017296
Short name T551
Test name
Test status
Simulation time 166806444 ps
CPU time 4.5 seconds
Started Jul 25 06:38:42 PM PDT 24
Finished Jul 25 06:38:46 PM PDT 24
Peak memory 232896 kb
Host smart-75d14afb-925c-4702-8e79-5087b2b84899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376017296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.376017296
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.1970756997
Short name T501
Test name
Test status
Simulation time 16966326 ps
CPU time 0.82 seconds
Started Jul 25 06:38:33 PM PDT 24
Finished Jul 25 06:38:34 PM PDT 24
Peak memory 206736 kb
Host smart-47ed182f-30c2-4a38-baa2-59cd9c335b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970756997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.1970756997
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.1933477296
Short name T118
Test name
Test status
Simulation time 15710134154 ps
CPU time 127.63 seconds
Started Jul 25 06:38:45 PM PDT 24
Finished Jul 25 06:40:53 PM PDT 24
Peak memory 263740 kb
Host smart-d691559f-44b0-46fa-bca4-1d783cd38614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933477296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.1933477296
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.4036202944
Short name T789
Test name
Test status
Simulation time 28067268682 ps
CPU time 202.45 seconds
Started Jul 25 06:38:46 PM PDT 24
Finished Jul 25 06:42:08 PM PDT 24
Peak memory 249712 kb
Host smart-5de992b1-87dc-4d72-965f-12818e78ec85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036202944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.4036202944
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.789351620
Short name T314
Test name
Test status
Simulation time 94363029 ps
CPU time 3.54 seconds
Started Jul 25 06:38:45 PM PDT 24
Finished Jul 25 06:38:48 PM PDT 24
Peak memory 232936 kb
Host smart-3b5cd532-6137-408e-82cb-02cfe36150c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789351620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.789351620
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_intercept.1024101808
Short name T55
Test name
Test status
Simulation time 1264183508 ps
CPU time 10.82 seconds
Started Jul 25 06:38:42 PM PDT 24
Finished Jul 25 06:38:53 PM PDT 24
Peak memory 224776 kb
Host smart-1f691a44-9f36-486b-9811-605217e0c47d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024101808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.1024101808
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.2719764436
Short name T896
Test name
Test status
Simulation time 658826681 ps
CPU time 9.52 seconds
Started Jul 25 06:38:46 PM PDT 24
Finished Jul 25 06:38:56 PM PDT 24
Peak memory 224656 kb
Host smart-a1d25a01-cab4-477a-b45a-197a340856dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719764436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.2719764436
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.2736720160
Short name T715
Test name
Test status
Simulation time 38661262918 ps
CPU time 34.89 seconds
Started Jul 25 06:38:43 PM PDT 24
Finished Jul 25 06:39:18 PM PDT 24
Peak memory 250364 kb
Host smart-0e81735d-a399-4d70-941e-58e6f52a6ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736720160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.2736720160
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.2144497479
Short name T866
Test name
Test status
Simulation time 6693713689 ps
CPU time 20.73 seconds
Started Jul 25 06:38:45 PM PDT 24
Finished Jul 25 06:39:06 PM PDT 24
Peak memory 232940 kb
Host smart-45994429-8f5d-4345-b87f-e585aabed878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144497479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.2144497479
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.3154578819
Short name T401
Test name
Test status
Simulation time 674047921 ps
CPU time 3.6 seconds
Started Jul 25 06:38:43 PM PDT 24
Finished Jul 25 06:38:47 PM PDT 24
Peak memory 224384 kb
Host smart-0196edef-04be-4886-8f31-84fd93c5a7b7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3154578819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.3154578819
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.520238969
Short name T268
Test name
Test status
Simulation time 6132782766 ps
CPU time 124.5 seconds
Started Jul 25 06:38:43 PM PDT 24
Finished Jul 25 06:40:48 PM PDT 24
Peak memory 249632 kb
Host smart-fa24052e-f4f3-4af8-9bf2-2fcd953835fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520238969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stres
s_all.520238969
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.3792023748
Short name T527
Test name
Test status
Simulation time 610703961 ps
CPU time 2.93 seconds
Started Jul 25 06:38:42 PM PDT 24
Finished Jul 25 06:38:45 PM PDT 24
Peak memory 216476 kb
Host smart-44e414c2-6d82-4bce-8e5f-c8d45077d7f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792023748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.3792023748
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.1616770572
Short name T35
Test name
Test status
Simulation time 2260509313 ps
CPU time 5.96 seconds
Started Jul 25 06:38:43 PM PDT 24
Finished Jul 25 06:38:49 PM PDT 24
Peak memory 216464 kb
Host smart-12ec915e-90e7-40cb-9860-6ca25398aa43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616770572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.1616770572
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.2997355243
Short name T867
Test name
Test status
Simulation time 66649513 ps
CPU time 1.59 seconds
Started Jul 25 06:38:46 PM PDT 24
Finished Jul 25 06:38:48 PM PDT 24
Peak memory 216472 kb
Host smart-6a1d15b0-4f0e-4f29-a97b-94c8541362a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997355243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.2997355243
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.650143552
Short name T375
Test name
Test status
Simulation time 161612316 ps
CPU time 0.71 seconds
Started Jul 25 06:38:41 PM PDT 24
Finished Jul 25 06:38:42 PM PDT 24
Peak memory 206148 kb
Host smart-e5fb8579-6979-4e54-9ea0-dc0d78287d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650143552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.650143552
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.824750738
Short name T861
Test name
Test status
Simulation time 3495644643 ps
CPU time 9.86 seconds
Started Jul 25 06:38:44 PM PDT 24
Finished Jul 25 06:38:55 PM PDT 24
Peak memory 233848 kb
Host smart-ea6d46f3-50e0-4708-93dd-63e159d7f652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824750738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.824750738
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.1639482499
Short name T462
Test name
Test status
Simulation time 18265909 ps
CPU time 0.77 seconds
Started Jul 25 06:38:52 PM PDT 24
Finished Jul 25 06:38:53 PM PDT 24
Peak memory 205592 kb
Host smart-1cde510b-b079-45a5-a645-09d899435d8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639482499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
1639482499
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.144397508
Short name T520
Test name
Test status
Simulation time 209836151 ps
CPU time 5.03 seconds
Started Jul 25 06:38:40 PM PDT 24
Finished Jul 25 06:38:45 PM PDT 24
Peak memory 232940 kb
Host smart-ef24d74e-935c-4e8f-88fd-9bce5fc45d50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144397508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.144397508
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.3919839086
Short name T801
Test name
Test status
Simulation time 12972255 ps
CPU time 0.78 seconds
Started Jul 25 06:38:44 PM PDT 24
Finished Jul 25 06:38:45 PM PDT 24
Peak memory 206036 kb
Host smart-6ca62c48-dbb6-4e9a-9853-50257f414a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919839086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.3919839086
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.121989061
Short name T871
Test name
Test status
Simulation time 6661054188 ps
CPU time 33.65 seconds
Started Jul 25 06:38:44 PM PDT 24
Finished Jul 25 06:39:18 PM PDT 24
Peak memory 251068 kb
Host smart-fcbac948-71e2-4b72-9d51-146ae898b552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121989061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.121989061
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.3259881362
Short name T897
Test name
Test status
Simulation time 11847341774 ps
CPU time 115.62 seconds
Started Jul 25 06:38:45 PM PDT 24
Finished Jul 25 06:40:41 PM PDT 24
Peak memory 249428 kb
Host smart-fd8bd366-3f3e-4406-881b-f28fa0d05781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259881362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.3259881362
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.1005443793
Short name T959
Test name
Test status
Simulation time 13035992100 ps
CPU time 59.77 seconds
Started Jul 25 06:38:45 PM PDT 24
Finished Jul 25 06:39:45 PM PDT 24
Peak memory 253996 kb
Host smart-edf25bf7-769c-47f0-9cc8-672b249232a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005443793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.1005443793
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.1996819679
Short name T598
Test name
Test status
Simulation time 514409258 ps
CPU time 3.48 seconds
Started Jul 25 06:38:46 PM PDT 24
Finished Jul 25 06:38:50 PM PDT 24
Peak memory 224700 kb
Host smart-0d95ce6d-0f30-4112-9fc9-a7eac1e1cc75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996819679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.1996819679
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.684552919
Short name T211
Test name
Test status
Simulation time 34543021734 ps
CPU time 152.76 seconds
Started Jul 25 06:38:44 PM PDT 24
Finished Jul 25 06:41:17 PM PDT 24
Peak memory 257108 kb
Host smart-0d245eab-3732-4500-a332-8238db1b096d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684552919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmds
.684552919
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.2445783175
Short name T983
Test name
Test status
Simulation time 2090679151 ps
CPU time 5.12 seconds
Started Jul 25 06:38:44 PM PDT 24
Finished Jul 25 06:38:50 PM PDT 24
Peak memory 224664 kb
Host smart-e324dd78-ad64-421f-8cb9-dcb8713037ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445783175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.2445783175
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.105998515
Short name T404
Test name
Test status
Simulation time 8328057376 ps
CPU time 14.55 seconds
Started Jul 25 06:38:43 PM PDT 24
Finished Jul 25 06:38:58 PM PDT 24
Peak memory 224776 kb
Host smart-a683d64e-99c4-4239-ae63-15c1f861b5f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105998515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.105998515
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.2197164919
Short name T311
Test name
Test status
Simulation time 65944140 ps
CPU time 2.84 seconds
Started Jul 25 06:38:42 PM PDT 24
Finished Jul 25 06:38:45 PM PDT 24
Peak memory 232604 kb
Host smart-bc58bc99-a1ba-4593-88fe-a56e01fa34f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197164919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.2197164919
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.806142297
Short name T748
Test name
Test status
Simulation time 26441339908 ps
CPU time 20.4 seconds
Started Jul 25 06:38:44 PM PDT 24
Finished Jul 25 06:39:05 PM PDT 24
Peak memory 238964 kb
Host smart-046adeb7-4753-4a44-820b-d91f763bdd10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806142297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.806142297
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.3685007174
Short name T42
Test name
Test status
Simulation time 4708762012 ps
CPU time 13.22 seconds
Started Jul 25 06:38:43 PM PDT 24
Finished Jul 25 06:38:57 PM PDT 24
Peak memory 221928 kb
Host smart-08806dff-904f-4aa9-9e93-39f4618516bc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3685007174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.3685007174
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.901589483
Short name T379
Test name
Test status
Simulation time 215720966 ps
CPU time 0.98 seconds
Started Jul 25 06:38:45 PM PDT 24
Finished Jul 25 06:38:46 PM PDT 24
Peak memory 206736 kb
Host smart-27c401f6-8373-47eb-9a10-0b6049cf072c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901589483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stres
s_all.901589483
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.3571346539
Short name T400
Test name
Test status
Simulation time 11457487671 ps
CPU time 31.74 seconds
Started Jul 25 06:38:46 PM PDT 24
Finished Jul 25 06:39:18 PM PDT 24
Peak memory 216720 kb
Host smart-b6d7b0bf-49d2-4056-9f1b-94adb1290a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571346539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.3571346539
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.2306456784
Short name T499
Test name
Test status
Simulation time 6333527110 ps
CPU time 5.87 seconds
Started Jul 25 06:38:45 PM PDT 24
Finished Jul 25 06:38:51 PM PDT 24
Peak memory 216520 kb
Host smart-391b99a6-e25d-46c2-bac9-31d504b9d0be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306456784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.2306456784
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.3553519788
Short name T998
Test name
Test status
Simulation time 17636493 ps
CPU time 0.83 seconds
Started Jul 25 06:38:43 PM PDT 24
Finished Jul 25 06:38:44 PM PDT 24
Peak memory 206120 kb
Host smart-050ec4bb-b839-4f7d-b68e-eac16349843a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553519788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.3553519788
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.784908319
Short name T508
Test name
Test status
Simulation time 39368646 ps
CPU time 0.79 seconds
Started Jul 25 06:38:44 PM PDT 24
Finished Jul 25 06:38:45 PM PDT 24
Peak memory 206112 kb
Host smart-0aaab2c2-ae41-4216-a3bc-af813398aefe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784908319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.784908319
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.405406211
Short name T222
Test name
Test status
Simulation time 12910278611 ps
CPU time 9.41 seconds
Started Jul 25 06:38:43 PM PDT 24
Finished Jul 25 06:38:52 PM PDT 24
Peak memory 224764 kb
Host smart-8294d8ec-ecd5-4656-bb6d-4925aa846bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405406211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.405406211
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.2728751112
Short name T679
Test name
Test status
Simulation time 16064283 ps
CPU time 0.72 seconds
Started Jul 25 06:38:55 PM PDT 24
Finished Jul 25 06:38:56 PM PDT 24
Peak memory 205920 kb
Host smart-17deee0a-f171-4202-ba5c-fda199857670
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728751112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
2728751112
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.3850098577
Short name T568
Test name
Test status
Simulation time 251912576 ps
CPU time 4.41 seconds
Started Jul 25 06:38:53 PM PDT 24
Finished Jul 25 06:38:58 PM PDT 24
Peak memory 224652 kb
Host smart-12bb8201-5edf-407e-9dd0-c11645dbe3e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850098577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.3850098577
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.4054105180
Short name T907
Test name
Test status
Simulation time 58369477 ps
CPU time 0.75 seconds
Started Jul 25 06:38:51 PM PDT 24
Finished Jul 25 06:38:52 PM PDT 24
Peak memory 205740 kb
Host smart-bc5f9734-9476-4d5d-9bd9-ed442d7c9a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054105180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.4054105180
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.3385114355
Short name T841
Test name
Test status
Simulation time 8894475087 ps
CPU time 133.48 seconds
Started Jul 25 06:38:53 PM PDT 24
Finished Jul 25 06:41:06 PM PDT 24
Peak memory 265740 kb
Host smart-b6035921-fd34-4b89-8ce4-10b22d2d9375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385114355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.3385114355
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.2212579026
Short name T29
Test name
Test status
Simulation time 24136467718 ps
CPU time 88.61 seconds
Started Jul 25 06:38:51 PM PDT 24
Finished Jul 25 06:40:19 PM PDT 24
Peak memory 257284 kb
Host smart-5d9a0b61-0f7c-4cae-b96a-ee29d1186351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212579026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.2212579026
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.778900386
Short name T295
Test name
Test status
Simulation time 4300164694 ps
CPU time 23.03 seconds
Started Jul 25 06:38:51 PM PDT 24
Finished Jul 25 06:39:14 PM PDT 24
Peak memory 224744 kb
Host smart-571b8178-4402-46b8-890a-360fe8e70355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778900386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.778900386
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.3027630574
Short name T367
Test name
Test status
Simulation time 28196699395 ps
CPU time 98.05 seconds
Started Jul 25 06:38:50 PM PDT 24
Finished Jul 25 06:40:28 PM PDT 24
Peak memory 239268 kb
Host smart-c954f721-c84a-4a21-ac72-32700a0d4600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027630574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmd
s.3027630574
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_intercept.3238801361
Short name T714
Test name
Test status
Simulation time 2360840724 ps
CPU time 15.32 seconds
Started Jul 25 06:38:52 PM PDT 24
Finished Jul 25 06:39:08 PM PDT 24
Peak memory 224756 kb
Host smart-8ac355cf-4a6c-4fc9-967b-77c8cefb5a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238801361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.3238801361
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.2815058442
Short name T503
Test name
Test status
Simulation time 1969877804 ps
CPU time 17.77 seconds
Started Jul 25 06:38:52 PM PDT 24
Finished Jul 25 06:39:10 PM PDT 24
Peak memory 232904 kb
Host smart-4f6e3134-eba6-40e4-8310-25dbee7bd569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815058442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.2815058442
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.1015870219
Short name T702
Test name
Test status
Simulation time 58769481 ps
CPU time 2.47 seconds
Started Jul 25 06:38:58 PM PDT 24
Finished Jul 25 06:39:00 PM PDT 24
Peak memory 232592 kb
Host smart-27114c93-8583-4ad4-947f-64b292a17cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015870219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.1015870219
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.2331005807
Short name T596
Test name
Test status
Simulation time 5635949521 ps
CPU time 10.42 seconds
Started Jul 25 06:38:51 PM PDT 24
Finished Jul 25 06:39:01 PM PDT 24
Peak memory 232864 kb
Host smart-dbce1c8b-7522-4f54-bf65-635a69b22298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331005807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.2331005807
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.2907153336
Short name T498
Test name
Test status
Simulation time 556634119 ps
CPU time 3.5 seconds
Started Jul 25 06:38:51 PM PDT 24
Finished Jul 25 06:38:55 PM PDT 24
Peak memory 220592 kb
Host smart-5fda710c-929f-4138-bc9c-b3c0f2153f1a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2907153336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.2907153336
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.631739429
Short name T31
Test name
Test status
Simulation time 186699165 ps
CPU time 1 seconds
Started Jul 25 06:38:52 PM PDT 24
Finished Jul 25 06:38:53 PM PDT 24
Peak memory 207712 kb
Host smart-073ba920-f3d3-489a-9759-3d3daf9ad872
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631739429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stres
s_all.631739429
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.3177309862
Short name T945
Test name
Test status
Simulation time 2745614704 ps
CPU time 14.59 seconds
Started Jul 25 06:38:55 PM PDT 24
Finished Jul 25 06:39:10 PM PDT 24
Peak memory 216532 kb
Host smart-3b4e0847-4df5-4baa-8aca-7652461e69a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177309862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.3177309862
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.974240763
Short name T365
Test name
Test status
Simulation time 784324114 ps
CPU time 4.62 seconds
Started Jul 25 06:38:51 PM PDT 24
Finished Jul 25 06:38:56 PM PDT 24
Peak memory 216468 kb
Host smart-9da434e6-e3b6-430c-9bae-67c2a38cd122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974240763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.974240763
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.3928591092
Short name T536
Test name
Test status
Simulation time 686228074 ps
CPU time 1.46 seconds
Started Jul 25 06:38:51 PM PDT 24
Finished Jul 25 06:38:53 PM PDT 24
Peak memory 216368 kb
Host smart-22328ff7-fa84-4481-a798-f09a09d056a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928591092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.3928591092
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.2262076816
Short name T920
Test name
Test status
Simulation time 242409740 ps
CPU time 0.87 seconds
Started Jul 25 06:38:52 PM PDT 24
Finished Jul 25 06:38:53 PM PDT 24
Peak memory 206116 kb
Host smart-c9fe1986-f5e4-4daf-a4fb-ecaf991dacd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262076816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.2262076816
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.1336778898
Short name T788
Test name
Test status
Simulation time 1346346225 ps
CPU time 9.19 seconds
Started Jul 25 06:38:52 PM PDT 24
Finished Jul 25 06:39:01 PM PDT 24
Peak memory 224668 kb
Host smart-28942baa-46a8-4ef2-bbe1-8d5e9a6bacdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336778898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.1336778898
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.3330977936
Short name T580
Test name
Test status
Simulation time 26088593 ps
CPU time 0.72 seconds
Started Jul 25 06:38:52 PM PDT 24
Finished Jul 25 06:38:53 PM PDT 24
Peak memory 205560 kb
Host smart-0db5aa84-569a-4e09-aa60-0fdb0c6de826
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330977936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
3330977936
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.1028068713
Short name T555
Test name
Test status
Simulation time 1381796229 ps
CPU time 5.76 seconds
Started Jul 25 06:38:53 PM PDT 24
Finished Jul 25 06:38:59 PM PDT 24
Peak memory 232896 kb
Host smart-36b8f168-ee12-440c-918f-4775d9d8e043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028068713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.1028068713
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.517345656
Short name T786
Test name
Test status
Simulation time 28118209 ps
CPU time 0.74 seconds
Started Jul 25 06:38:53 PM PDT 24
Finished Jul 25 06:38:54 PM PDT 24
Peak memory 206044 kb
Host smart-20774857-a522-4d3a-bbd4-5afc84548c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517345656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.517345656
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.409559008
Short name T459
Test name
Test status
Simulation time 197669821 ps
CPU time 4.72 seconds
Started Jul 25 06:38:54 PM PDT 24
Finished Jul 25 06:38:59 PM PDT 24
Peak memory 224644 kb
Host smart-ddb39376-a175-44fd-8874-4b3f6c9eb2bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409559008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.409559008
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.26050110
Short name T925
Test name
Test status
Simulation time 164865177130 ps
CPU time 268.38 seconds
Started Jul 25 06:38:55 PM PDT 24
Finished Jul 25 06:43:24 PM PDT 24
Peak memory 251476 kb
Host smart-b287dd52-f9c6-4ec5-bd78-b79af8e497a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26050110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.26050110
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.2212929647
Short name T486
Test name
Test status
Simulation time 2656986912 ps
CPU time 6.16 seconds
Started Jul 25 06:38:56 PM PDT 24
Finished Jul 25 06:39:02 PM PDT 24
Peak memory 217860 kb
Host smart-615d897c-5d0c-418f-8449-315ea9d0652f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212929647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.2212929647
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.967404108
Short name T733
Test name
Test status
Simulation time 1684150872 ps
CPU time 26.39 seconds
Started Jul 25 06:38:53 PM PDT 24
Finished Jul 25 06:39:20 PM PDT 24
Peak memory 241060 kb
Host smart-aa613a8c-cec6-4ca0-bb9b-60365a728ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967404108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.967404108
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.1987028042
Short name T151
Test name
Test status
Simulation time 24387172130 ps
CPU time 25.03 seconds
Started Jul 25 06:38:52 PM PDT 24
Finished Jul 25 06:39:17 PM PDT 24
Peak memory 249356 kb
Host smart-c4f18ab6-9c3e-4487-8fe5-f7b07f71e3ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987028042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmd
s.1987028042
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_intercept.572798042
Short name T619
Test name
Test status
Simulation time 2042939674 ps
CPU time 5.32 seconds
Started Jul 25 06:38:55 PM PDT 24
Finished Jul 25 06:39:01 PM PDT 24
Peak memory 220000 kb
Host smart-f55a2b55-68e9-4825-bf42-a877ee3089e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572798042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.572798042
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.592285200
Short name T336
Test name
Test status
Simulation time 4756325284 ps
CPU time 17.25 seconds
Started Jul 25 06:38:52 PM PDT 24
Finished Jul 25 06:39:10 PM PDT 24
Peak memory 240988 kb
Host smart-bca48c99-6f9b-4cfc-9d32-895b9a13a3b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592285200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.592285200
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.1630790124
Short name T388
Test name
Test status
Simulation time 711034050 ps
CPU time 8.55 seconds
Started Jul 25 06:38:51 PM PDT 24
Finished Jul 25 06:39:00 PM PDT 24
Peak memory 232892 kb
Host smart-7d779a04-da02-4f01-91c3-c84959abb7e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630790124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.1630790124
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.1357876732
Short name T234
Test name
Test status
Simulation time 1164038092 ps
CPU time 3.7 seconds
Started Jul 25 06:38:54 PM PDT 24
Finished Jul 25 06:38:58 PM PDT 24
Peak memory 224704 kb
Host smart-efe4116a-da59-476f-ab33-c69d16533577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357876732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.1357876732
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.2743849087
Short name T23
Test name
Test status
Simulation time 1668093300 ps
CPU time 5.65 seconds
Started Jul 25 06:38:53 PM PDT 24
Finished Jul 25 06:38:59 PM PDT 24
Peak memory 223436 kb
Host smart-e1a5f358-a0bb-445f-82b4-199e1b099694
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2743849087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.2743849087
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.2584443228
Short name T689
Test name
Test status
Simulation time 120366318 ps
CPU time 0.89 seconds
Started Jul 25 06:38:55 PM PDT 24
Finished Jul 25 06:38:56 PM PDT 24
Peak memory 206048 kb
Host smart-0024e8bb-1e92-4158-b44a-ca7fd8619c02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584443228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.2584443228
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.2832524311
Short name T589
Test name
Test status
Simulation time 7356363305 ps
CPU time 26.9 seconds
Started Jul 25 06:38:51 PM PDT 24
Finished Jul 25 06:39:18 PM PDT 24
Peak memory 216444 kb
Host smart-ebd50f6f-f71f-4d2f-afb8-2cc13a763d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832524311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.2832524311
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.3667988605
Short name T594
Test name
Test status
Simulation time 198458187 ps
CPU time 1.1 seconds
Started Jul 25 06:38:50 PM PDT 24
Finished Jul 25 06:38:52 PM PDT 24
Peak memory 208084 kb
Host smart-4f5cd90d-08f6-4fcf-af58-ed451d4c47a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667988605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.3667988605
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.1263450564
Short name T687
Test name
Test status
Simulation time 139368862 ps
CPU time 1.19 seconds
Started Jul 25 06:38:51 PM PDT 24
Finished Jul 25 06:38:53 PM PDT 24
Peak memory 216508 kb
Host smart-2392f2fc-911f-4f21-a06d-f63937ff0805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263450564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.1263450564
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.798580198
Short name T347
Test name
Test status
Simulation time 19136038 ps
CPU time 0.83 seconds
Started Jul 25 06:38:52 PM PDT 24
Finished Jul 25 06:38:53 PM PDT 24
Peak memory 206128 kb
Host smart-45c87593-9083-4d84-a7aa-e647f0677489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798580198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.798580198
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.3502916544
Short name T463
Test name
Test status
Simulation time 12871032836 ps
CPU time 36.47 seconds
Started Jul 25 06:38:53 PM PDT 24
Finished Jul 25 06:39:29 PM PDT 24
Peak memory 240764 kb
Host smart-8d982e72-5b6c-4fcd-b714-af527f85e7e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502916544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.3502916544
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.3679232483
Short name T695
Test name
Test status
Simulation time 89929696 ps
CPU time 0.73 seconds
Started Jul 25 06:38:58 PM PDT 24
Finished Jul 25 06:38:59 PM PDT 24
Peak memory 205584 kb
Host smart-5ae0acd3-f027-4475-abb4-a9f8c9524ffd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679232483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
3679232483
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.2634730153
Short name T667
Test name
Test status
Simulation time 5776989255 ps
CPU time 26.8 seconds
Started Jul 25 06:39:01 PM PDT 24
Finished Jul 25 06:39:28 PM PDT 24
Peak memory 232960 kb
Host smart-70ed83c5-5f23-462b-90e9-96e00a6b983a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634730153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.2634730153
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.4017712211
Short name T524
Test name
Test status
Simulation time 21356653 ps
CPU time 0.79 seconds
Started Jul 25 06:38:54 PM PDT 24
Finished Jul 25 06:38:55 PM PDT 24
Peak memory 205696 kb
Host smart-86e18b11-1022-43ed-abf0-baae7a0f20a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017712211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.4017712211
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.1048169622
Short name T342
Test name
Test status
Simulation time 50130844 ps
CPU time 0.77 seconds
Started Jul 25 06:39:01 PM PDT 24
Finished Jul 25 06:39:01 PM PDT 24
Peak memory 215932 kb
Host smart-6315f089-a0a9-4e06-b2e7-8296d20f0b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048169622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.1048169622
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.764938442
Short name T494
Test name
Test status
Simulation time 83677861145 ps
CPU time 391.44 seconds
Started Jul 25 06:39:07 PM PDT 24
Finished Jul 25 06:45:39 PM PDT 24
Peak memory 268196 kb
Host smart-8dcfd91d-40ae-4c0f-8c25-134616dcf091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764938442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.764938442
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.4057259964
Short name T932
Test name
Test status
Simulation time 607295415 ps
CPU time 6.51 seconds
Started Jul 25 06:39:22 PM PDT 24
Finished Jul 25 06:39:28 PM PDT 24
Peak memory 232908 kb
Host smart-c2e40d61-5cd6-4150-9596-eab349b1312a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057259964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.4057259964
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_intercept.2868681374
Short name T778
Test name
Test status
Simulation time 546166980 ps
CPU time 8.03 seconds
Started Jul 25 06:38:51 PM PDT 24
Finished Jul 25 06:39:00 PM PDT 24
Peak memory 232864 kb
Host smart-0423aee2-9a69-4202-80b1-6eece806dd19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868681374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.2868681374
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.695437867
Short name T678
Test name
Test status
Simulation time 18421260313 ps
CPU time 80.79 seconds
Started Jul 25 06:38:54 PM PDT 24
Finished Jul 25 06:40:15 PM PDT 24
Peak memory 232948 kb
Host smart-2760a7d7-fba2-46f9-90ae-d5456c00d7c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695437867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.695437867
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.790805829
Short name T835
Test name
Test status
Simulation time 644882782 ps
CPU time 2.67 seconds
Started Jul 25 06:38:56 PM PDT 24
Finished Jul 25 06:38:59 PM PDT 24
Peak memory 224608 kb
Host smart-0c89658b-d9cb-42b5-bdf8-74152e6967e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790805829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swap
.790805829
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.3343619968
Short name T584
Test name
Test status
Simulation time 1841537387 ps
CPU time 6.07 seconds
Started Jul 25 06:38:57 PM PDT 24
Finished Jul 25 06:39:04 PM PDT 24
Peak memory 224708 kb
Host smart-a996aaa4-e288-4a41-be78-8318293db0d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343619968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.3343619968
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.3955203482
Short name T428
Test name
Test status
Simulation time 7391625275 ps
CPU time 14.03 seconds
Started Jul 25 06:39:01 PM PDT 24
Finished Jul 25 06:39:15 PM PDT 24
Peak memory 219684 kb
Host smart-354f2d91-9abe-4103-abe6-e23db706931c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3955203482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.3955203482
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.244082456
Short name T137
Test name
Test status
Simulation time 32233112258 ps
CPU time 138.75 seconds
Started Jul 25 06:39:01 PM PDT 24
Finished Jul 25 06:41:19 PM PDT 24
Peak memory 241352 kb
Host smart-ec04c113-fae1-4b3f-a202-b26b4fb2fd30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244082456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stres
s_all.244082456
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.3377717861
Short name T628
Test name
Test status
Simulation time 2989638475 ps
CPU time 22.52 seconds
Started Jul 25 06:38:53 PM PDT 24
Finished Jul 25 06:39:16 PM PDT 24
Peak memory 220448 kb
Host smart-5eb748d9-1a5d-4138-8273-a52db89c7b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377717861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.3377717861
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.2718086369
Short name T886
Test name
Test status
Simulation time 5352512421 ps
CPU time 4.72 seconds
Started Jul 25 06:38:51 PM PDT 24
Finished Jul 25 06:38:56 PM PDT 24
Peak memory 216444 kb
Host smart-bea673f4-a98a-402f-a029-f64ad2a0c2a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718086369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.2718086369
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.1474018794
Short name T345
Test name
Test status
Simulation time 255899706 ps
CPU time 1.12 seconds
Started Jul 25 06:38:53 PM PDT 24
Finished Jul 25 06:38:54 PM PDT 24
Peak memory 216420 kb
Host smart-c13b7a36-8f09-49c1-a710-af6a9c781b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474018794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.1474018794
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.4167987287
Short name T642
Test name
Test status
Simulation time 81503749 ps
CPU time 0.81 seconds
Started Jul 25 06:38:57 PM PDT 24
Finished Jul 25 06:38:58 PM PDT 24
Peak memory 206140 kb
Host smart-399f73f2-aa50-4712-8e92-aee052210865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167987287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.4167987287
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.2715735193
Short name T476
Test name
Test status
Simulation time 212387253 ps
CPU time 2.42 seconds
Started Jul 25 06:39:04 PM PDT 24
Finished Jul 25 06:39:06 PM PDT 24
Peak memory 232588 kb
Host smart-b3f4bbc2-7803-4bee-af83-22e7bea42584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715735193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.2715735193
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.2279097793
Short name T587
Test name
Test status
Simulation time 14240319 ps
CPU time 0.74 seconds
Started Jul 25 06:39:02 PM PDT 24
Finished Jul 25 06:39:03 PM PDT 24
Peak memory 205616 kb
Host smart-9fdb7ec2-8af8-499b-b183-e9ec4a0bfd9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279097793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
2279097793
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.3459355421
Short name T372
Test name
Test status
Simulation time 1875870775 ps
CPU time 3.56 seconds
Started Jul 25 06:39:01 PM PDT 24
Finished Jul 25 06:39:05 PM PDT 24
Peak memory 232764 kb
Host smart-aea0d296-5f43-4b13-b78b-4c25d8a7125a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459355421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.3459355421
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.2134683141
Short name T677
Test name
Test status
Simulation time 19845988 ps
CPU time 0.79 seconds
Started Jul 25 06:39:01 PM PDT 24
Finished Jul 25 06:39:02 PM PDT 24
Peak memory 205732 kb
Host smart-b9ee364c-392d-43fe-b697-e1a03fa6b223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134683141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.2134683141
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.2876855377
Short name T744
Test name
Test status
Simulation time 3187352763 ps
CPU time 69.35 seconds
Started Jul 25 06:39:02 PM PDT 24
Finished Jul 25 06:40:11 PM PDT 24
Peak memory 255988 kb
Host smart-9a553707-785b-4d18-815a-dbe743063504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876855377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.2876855377
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.2661504887
Short name T381
Test name
Test status
Simulation time 12358107435 ps
CPU time 24.69 seconds
Started Jul 25 06:39:03 PM PDT 24
Finished Jul 25 06:39:29 PM PDT 24
Peak memory 232992 kb
Host smart-8431ce85-46f5-41a3-86d6-c461a293c245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661504887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.2661504887
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.552207586
Short name T911
Test name
Test status
Simulation time 175671547054 ps
CPU time 363.94 seconds
Started Jul 25 06:39:01 PM PDT 24
Finished Jul 25 06:45:05 PM PDT 24
Peak memory 249392 kb
Host smart-9ca6be36-27bd-470c-8024-349b03f2e532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552207586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idle
.552207586
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.2736139106
Short name T732
Test name
Test status
Simulation time 108537361 ps
CPU time 4.04 seconds
Started Jul 25 06:39:06 PM PDT 24
Finished Jul 25 06:39:10 PM PDT 24
Peak memory 237544 kb
Host smart-88627bd2-123f-4dad-b7d8-88c5b9e7a28e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736139106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.2736139106
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.2357151425
Short name T166
Test name
Test status
Simulation time 82257833450 ps
CPU time 169.77 seconds
Started Jul 25 06:39:03 PM PDT 24
Finished Jul 25 06:41:53 PM PDT 24
Peak memory 257108 kb
Host smart-23607e44-6e8a-44d6-8066-8fbf6ce67ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357151425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmd
s.2357151425
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_intercept.3963476727
Short name T602
Test name
Test status
Simulation time 1486879556 ps
CPU time 11.68 seconds
Started Jul 25 06:38:59 PM PDT 24
Finished Jul 25 06:39:11 PM PDT 24
Peak memory 224660 kb
Host smart-3958e078-3faa-46e8-a5fa-2bdde748a322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963476727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.3963476727
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.1807815178
Short name T473
Test name
Test status
Simulation time 15764360316 ps
CPU time 58.36 seconds
Started Jul 25 06:39:03 PM PDT 24
Finished Jul 25 06:40:01 PM PDT 24
Peak memory 240120 kb
Host smart-978d8809-8cc7-4b3e-86af-ba6a5fc15807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807815178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.1807815178
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.1646395692
Short name T553
Test name
Test status
Simulation time 3515222398 ps
CPU time 6.63 seconds
Started Jul 25 06:39:00 PM PDT 24
Finished Jul 25 06:39:06 PM PDT 24
Peak memory 232916 kb
Host smart-442c4947-e3f0-4d44-b2eb-3a116bb11aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646395692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.1646395692
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.893673377
Short name T832
Test name
Test status
Simulation time 144412963 ps
CPU time 3.01 seconds
Started Jul 25 06:39:01 PM PDT 24
Finished Jul 25 06:39:04 PM PDT 24
Peak memory 232844 kb
Host smart-57d572ee-68b8-4696-8a91-22af762b0cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893673377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.893673377
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.1934429798
Short name T651
Test name
Test status
Simulation time 6902238254 ps
CPU time 12.02 seconds
Started Jul 25 06:38:58 PM PDT 24
Finished Jul 25 06:39:10 PM PDT 24
Peak memory 223304 kb
Host smart-94565861-918d-478c-af7c-32b805cc2b13
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1934429798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.1934429798
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.2679059104
Short name T950
Test name
Test status
Simulation time 39096431416 ps
CPU time 43.61 seconds
Started Jul 25 06:38:59 PM PDT 24
Finished Jul 25 06:39:43 PM PDT 24
Peak memory 224668 kb
Host smart-06daf3c1-3af3-43b1-8025-601c48d14cd2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679059104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.2679059104
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.4138637586
Short name T993
Test name
Test status
Simulation time 666023407 ps
CPU time 10.63 seconds
Started Jul 25 06:38:59 PM PDT 24
Finished Jul 25 06:39:10 PM PDT 24
Peak memory 216380 kb
Host smart-07dab752-ca59-48d5-982a-a2847355d3cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138637586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.4138637586
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.335137256
Short name T844
Test name
Test status
Simulation time 933704769 ps
CPU time 2.88 seconds
Started Jul 25 06:39:03 PM PDT 24
Finished Jul 25 06:39:06 PM PDT 24
Peak memory 216272 kb
Host smart-c856ab23-9232-484a-9177-594fb14852ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335137256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.335137256
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.3363122375
Short name T406
Test name
Test status
Simulation time 126279024 ps
CPU time 1.18 seconds
Started Jul 25 06:39:00 PM PDT 24
Finished Jul 25 06:39:01 PM PDT 24
Peak memory 208068 kb
Host smart-2eb2957e-4fc8-4641-a0aa-e2fb7297ed9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363122375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.3363122375
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.2125324518
Short name T472
Test name
Test status
Simulation time 85320532 ps
CPU time 0.99 seconds
Started Jul 25 06:39:01 PM PDT 24
Finished Jul 25 06:39:02 PM PDT 24
Peak memory 206112 kb
Host smart-bcc95f9f-8642-48c1-a612-01a1e17fecb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125324518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.2125324518
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.1561828247
Short name T548
Test name
Test status
Simulation time 2432204290 ps
CPU time 5.98 seconds
Started Jul 25 06:39:02 PM PDT 24
Finished Jul 25 06:39:08 PM PDT 24
Peak memory 224784 kb
Host smart-13f529de-f138-4478-b0f0-5bb4bc083919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561828247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.1561828247
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.524235258
Short name T694
Test name
Test status
Simulation time 40701206 ps
CPU time 0.74 seconds
Started Jul 25 06:39:07 PM PDT 24
Finished Jul 25 06:39:08 PM PDT 24
Peak memory 205856 kb
Host smart-a0c8bbd1-3479-47a9-b466-261081e06fb4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524235258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.524235258
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.358025170
Short name T69
Test name
Test status
Simulation time 189123879 ps
CPU time 2.37 seconds
Started Jul 25 06:39:03 PM PDT 24
Finished Jul 25 06:39:06 PM PDT 24
Peak memory 224728 kb
Host smart-9144362f-d34b-4e04-a2f7-fb45deff34b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358025170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.358025170
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.969981621
Short name T443
Test name
Test status
Simulation time 48141827 ps
CPU time 0.77 seconds
Started Jul 25 06:39:03 PM PDT 24
Finished Jul 25 06:39:04 PM PDT 24
Peak memory 205732 kb
Host smart-b0e24593-5395-45c1-a46b-35db147675fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969981621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.969981621
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.959260267
Short name T773
Test name
Test status
Simulation time 14338377146 ps
CPU time 86.38 seconds
Started Jul 25 06:39:02 PM PDT 24
Finished Jul 25 06:40:29 PM PDT 24
Peak memory 267556 kb
Host smart-624be0c2-ef08-477b-9449-efa170d3fe0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959260267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.959260267
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.142528152
Short name T643
Test name
Test status
Simulation time 9927644439 ps
CPU time 60.27 seconds
Started Jul 25 06:39:02 PM PDT 24
Finished Jul 25 06:40:02 PM PDT 24
Peak memory 224836 kb
Host smart-d715e930-2bc1-43ab-881c-82a16a53da50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142528152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.142528152
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.1554194676
Short name T405
Test name
Test status
Simulation time 75460634293 ps
CPU time 309.28 seconds
Started Jul 25 06:38:59 PM PDT 24
Finished Jul 25 06:44:08 PM PDT 24
Peak memory 249388 kb
Host smart-63e2e2f2-457f-47c6-bf64-df5025ccf697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554194676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.1554194676
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.540367975
Short name T537
Test name
Test status
Simulation time 1413527222 ps
CPU time 13 seconds
Started Jul 25 06:39:02 PM PDT 24
Finished Jul 25 06:39:15 PM PDT 24
Peak memory 232924 kb
Host smart-790aa5e4-1159-455a-bd25-ea435989142f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540367975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.540367975
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.4014259677
Short name T846
Test name
Test status
Simulation time 4316754936 ps
CPU time 21.29 seconds
Started Jul 25 06:39:03 PM PDT 24
Finished Jul 25 06:39:25 PM PDT 24
Peak memory 241152 kb
Host smart-e1506e5c-f403-4212-9175-e291691673a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014259677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmd
s.4014259677
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.4149808134
Short name T425
Test name
Test status
Simulation time 1827332571 ps
CPU time 4.02 seconds
Started Jul 25 06:39:07 PM PDT 24
Finished Jul 25 06:39:12 PM PDT 24
Peak memory 232792 kb
Host smart-e4ae0230-a2ab-4717-8046-f2b86f7202de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149808134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.4149808134
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.4068956126
Short name T626
Test name
Test status
Simulation time 2584177268 ps
CPU time 19.35 seconds
Started Jul 25 06:39:00 PM PDT 24
Finished Jul 25 06:39:20 PM PDT 24
Peak memory 234012 kb
Host smart-de3a3916-efe9-4905-87db-ca13e0db92e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068956126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.4068956126
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.2595983415
Short name T458
Test name
Test status
Simulation time 3061489228 ps
CPU time 7.66 seconds
Started Jul 25 06:39:03 PM PDT 24
Finished Jul 25 06:39:11 PM PDT 24
Peak memory 239764 kb
Host smart-e632eccd-65bc-4470-b20d-89bbe3b94116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595983415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.2595983415
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.2089114096
Short name T187
Test name
Test status
Simulation time 241632605 ps
CPU time 3.16 seconds
Started Jul 25 06:39:04 PM PDT 24
Finished Jul 25 06:39:07 PM PDT 24
Peak memory 232900 kb
Host smart-4f2e6b0f-68a2-4a23-a631-aeaf72429b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089114096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.2089114096
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.2648336919
Short name T955
Test name
Test status
Simulation time 3527825615 ps
CPU time 16.19 seconds
Started Jul 25 06:39:02 PM PDT 24
Finished Jul 25 06:39:19 PM PDT 24
Peak memory 222468 kb
Host smart-85ae4e79-19ca-4bf2-9496-0ce25782cc94
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2648336919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.2648336919
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.1116534448
Short name T942
Test name
Test status
Simulation time 15579217267 ps
CPU time 136.25 seconds
Started Jul 25 06:39:07 PM PDT 24
Finished Jul 25 06:41:24 PM PDT 24
Peak memory 257576 kb
Host smart-bef5447a-5b5b-45fc-909d-3ec540382ffb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116534448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.1116534448
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.4128256969
Short name T940
Test name
Test status
Simulation time 38171966064 ps
CPU time 42.39 seconds
Started Jul 25 06:38:59 PM PDT 24
Finished Jul 25 06:39:42 PM PDT 24
Peak memory 216432 kb
Host smart-e84d29b0-83d5-4969-8196-fc9e93ba8434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128256969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.4128256969
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.2818303872
Short name T736
Test name
Test status
Simulation time 730896376 ps
CPU time 3.83 seconds
Started Jul 25 06:39:07 PM PDT 24
Finished Jul 25 06:39:11 PM PDT 24
Peak memory 216388 kb
Host smart-0fc53ce1-7a14-4928-a024-dc2e2efdb8b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818303872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.2818303872
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.2969774161
Short name T790
Test name
Test status
Simulation time 975533584 ps
CPU time 2.82 seconds
Started Jul 25 06:39:06 PM PDT 24
Finished Jul 25 06:39:09 PM PDT 24
Peak memory 216404 kb
Host smart-09256b41-f66a-4b72-aa0f-0cd7786e80b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969774161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.2969774161
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.2982961509
Short name T654
Test name
Test status
Simulation time 39956203 ps
CPU time 0.88 seconds
Started Jul 25 06:39:01 PM PDT 24
Finished Jul 25 06:39:02 PM PDT 24
Peak memory 206116 kb
Host smart-f5d0fb26-ea15-42e9-83a3-2ab3a99bf32a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982961509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.2982961509
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.4056771199
Short name T1006
Test name
Test status
Simulation time 7848628164 ps
CPU time 13.99 seconds
Started Jul 25 06:39:02 PM PDT 24
Finished Jul 25 06:39:17 PM PDT 24
Peak memory 224780 kb
Host smart-bbf10f1a-7bf2-4154-81e1-30e5647c3d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056771199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.4056771199
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.2970234418
Short name T639
Test name
Test status
Simulation time 17888495 ps
CPU time 0.75 seconds
Started Jul 25 06:39:15 PM PDT 24
Finished Jul 25 06:39:16 PM PDT 24
Peak memory 205868 kb
Host smart-6632645f-3477-41b3-81d7-ec56a804ff0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970234418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
2970234418
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.3886073024
Short name T759
Test name
Test status
Simulation time 845216806 ps
CPU time 11.03 seconds
Started Jul 25 06:39:13 PM PDT 24
Finished Jul 25 06:39:25 PM PDT 24
Peak memory 232940 kb
Host smart-b14b26bb-a82a-4cc2-8afd-b6cc0c3abab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886073024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.3886073024
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.970084691
Short name T153
Test name
Test status
Simulation time 53892925 ps
CPU time 0.78 seconds
Started Jul 25 06:39:09 PM PDT 24
Finished Jul 25 06:39:10 PM PDT 24
Peak memory 207064 kb
Host smart-502943c9-6f76-49e4-b8c1-aa5f5c5b6df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970084691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.970084691
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.2967112069
Short name T40
Test name
Test status
Simulation time 3755776833 ps
CPU time 42.78 seconds
Started Jul 25 06:39:08 PM PDT 24
Finished Jul 25 06:39:51 PM PDT 24
Peak memory 257532 kb
Host smart-89c9de03-a6b4-4117-b44b-23cca100a5a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967112069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.2967112069
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.223796291
Short name T203
Test name
Test status
Simulation time 4378490168 ps
CPU time 19.35 seconds
Started Jul 25 06:39:13 PM PDT 24
Finished Jul 25 06:39:32 PM PDT 24
Peak memory 241088 kb
Host smart-758f1f8b-738b-4b40-a58b-c3a88e7f95a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223796291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.223796291
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.371120278
Short name T249
Test name
Test status
Simulation time 109319822067 ps
CPU time 511.9 seconds
Started Jul 25 06:39:11 PM PDT 24
Finished Jul 25 06:47:43 PM PDT 24
Peak memory 269272 kb
Host smart-ade36549-411b-43ce-bcfd-ce8bc4ddace4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371120278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idle
.371120278
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.2781834108
Short name T293
Test name
Test status
Simulation time 12550331277 ps
CPU time 46.23 seconds
Started Jul 25 06:39:07 PM PDT 24
Finished Jul 25 06:39:54 PM PDT 24
Peak memory 241172 kb
Host smart-b46fcfa7-8a01-4bcb-a650-7b9380c74203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781834108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.2781834108
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.3672807341
Short name T936
Test name
Test status
Simulation time 3024389499 ps
CPU time 45.12 seconds
Started Jul 25 06:39:21 PM PDT 24
Finished Jul 25 06:40:06 PM PDT 24
Peak memory 249360 kb
Host smart-553f9656-0515-4b35-adcd-8e8f1b9c5ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672807341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmd
s.3672807341
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_intercept.2408283322
Short name T599
Test name
Test status
Simulation time 439489073 ps
CPU time 4.64 seconds
Started Jul 25 06:39:10 PM PDT 24
Finished Jul 25 06:39:15 PM PDT 24
Peak memory 224712 kb
Host smart-92eea4e5-eb43-41da-b60a-4554ecc1bb4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408283322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.2408283322
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.1878865282
Short name T448
Test name
Test status
Simulation time 39264994489 ps
CPU time 30.17 seconds
Started Jul 25 06:39:13 PM PDT 24
Finished Jul 25 06:39:44 PM PDT 24
Peak memory 232960 kb
Host smart-b7d95a6a-e14d-4096-b3f5-78b2e9a4a07d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878865282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.1878865282
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.937773755
Short name T753
Test name
Test status
Simulation time 1447693877 ps
CPU time 3.07 seconds
Started Jul 25 06:39:10 PM PDT 24
Finished Jul 25 06:39:14 PM PDT 24
Peak memory 224708 kb
Host smart-202c6cab-1486-42aa-903a-d731c6a29131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937773755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swap
.937773755
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.1344799352
Short name T620
Test name
Test status
Simulation time 290145233 ps
CPU time 3.07 seconds
Started Jul 25 06:39:10 PM PDT 24
Finished Jul 25 06:39:13 PM PDT 24
Peak memory 224652 kb
Host smart-3584501b-2d36-478e-8a34-4bc402463aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344799352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.1344799352
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.2113935783
Short name T684
Test name
Test status
Simulation time 3241378858 ps
CPU time 5.31 seconds
Started Jul 25 06:39:10 PM PDT 24
Finished Jul 25 06:39:15 PM PDT 24
Peak memory 223248 kb
Host smart-41487e2d-6586-495a-bc37-4002fc9b0f82
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2113935783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.2113935783
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.3796452179
Short name T874
Test name
Test status
Simulation time 7537298841 ps
CPU time 19.18 seconds
Started Jul 25 06:39:12 PM PDT 24
Finished Jul 25 06:39:31 PM PDT 24
Peak memory 216536 kb
Host smart-0080ec5b-e1f7-42c7-9bac-5ba642314421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796452179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.3796452179
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.3141072121
Short name T9
Test name
Test status
Simulation time 857362305 ps
CPU time 3.61 seconds
Started Jul 25 06:39:11 PM PDT 24
Finished Jul 25 06:39:15 PM PDT 24
Peak memory 216372 kb
Host smart-af2f0b26-d7c7-438d-a62c-707eb3d2a79d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141072121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.3141072121
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.2865435619
Short name T308
Test name
Test status
Simulation time 37028320 ps
CPU time 0.9 seconds
Started Jul 25 06:39:16 PM PDT 24
Finished Jul 25 06:39:17 PM PDT 24
Peak memory 207128 kb
Host smart-170eabd6-b18a-4371-9be6-629c843a3baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865435619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.2865435619
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.579174494
Short name T418
Test name
Test status
Simulation time 20628028 ps
CPU time 0.75 seconds
Started Jul 25 06:39:11 PM PDT 24
Finished Jul 25 06:39:12 PM PDT 24
Peak memory 205988 kb
Host smart-a9b51a57-cfbe-4fd2-b181-7a7dbe22e71b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579174494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.579174494
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.891262513
Short name T860
Test name
Test status
Simulation time 245819154 ps
CPU time 2.59 seconds
Started Jul 25 06:39:10 PM PDT 24
Finished Jul 25 06:39:12 PM PDT 24
Peak memory 224600 kb
Host smart-cd19fe96-41a0-4eec-b5b2-0d184335a552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891262513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.891262513
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.4293268064
Short name T781
Test name
Test status
Simulation time 14996279 ps
CPU time 0.7 seconds
Started Jul 25 06:39:09 PM PDT 24
Finished Jul 25 06:39:10 PM PDT 24
Peak memory 205588 kb
Host smart-f48ad931-091b-4e1c-ab6d-9e27a8bf865d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293268064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
4293268064
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.1863558342
Short name T868
Test name
Test status
Simulation time 557568998 ps
CPU time 7.68 seconds
Started Jul 25 06:39:09 PM PDT 24
Finished Jul 25 06:39:16 PM PDT 24
Peak memory 232904 kb
Host smart-a02154ed-0d3f-4d8f-ae0a-b373fbcc0d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863558342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.1863558342
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.773816903
Short name T362
Test name
Test status
Simulation time 249914831 ps
CPU time 0.76 seconds
Started Jul 25 06:39:09 PM PDT 24
Finished Jul 25 06:39:09 PM PDT 24
Peak memory 205740 kb
Host smart-ac89a996-3091-4603-870b-471b150ba7e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773816903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.773816903
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.1512072676
Short name T828
Test name
Test status
Simulation time 14705821764 ps
CPU time 39.43 seconds
Started Jul 25 06:39:14 PM PDT 24
Finished Jul 25 06:39:54 PM PDT 24
Peak memory 217832 kb
Host smart-00ec5f54-b9ae-4e30-b024-5dae0899209b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512072676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.1512072676
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.214373312
Short name T173
Test name
Test status
Simulation time 139529372039 ps
CPU time 212.06 seconds
Started Jul 25 06:39:14 PM PDT 24
Finished Jul 25 06:42:46 PM PDT 24
Peak memory 249372 kb
Host smart-48c3c7ce-bd70-4866-93a6-bc3506847635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214373312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idle
.214373312
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.1458471657
Short name T829
Test name
Test status
Simulation time 5950814466 ps
CPU time 63.77 seconds
Started Jul 25 06:39:14 PM PDT 24
Finished Jul 25 06:40:18 PM PDT 24
Peak memory 249592 kb
Host smart-943cfeab-485b-457e-b4a4-8b1f302ff479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458471657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmd
s.1458471657
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_intercept.912360118
Short name T768
Test name
Test status
Simulation time 1922335450 ps
CPU time 9.74 seconds
Started Jul 25 06:39:10 PM PDT 24
Finished Jul 25 06:39:20 PM PDT 24
Peak memory 232820 kb
Host smart-ea52ccf6-4234-4f17-9aa6-59e73ae3ef3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912360118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.912360118
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.828877942
Short name T705
Test name
Test status
Simulation time 2774366735 ps
CPU time 14.69 seconds
Started Jul 25 06:39:10 PM PDT 24
Finished Jul 25 06:39:25 PM PDT 24
Peak memory 232884 kb
Host smart-016a5664-c87c-497a-99be-0a333836e765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828877942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.828877942
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.971017052
Short name T53
Test name
Test status
Simulation time 790566626 ps
CPU time 6.26 seconds
Started Jul 25 06:39:09 PM PDT 24
Finished Jul 25 06:39:15 PM PDT 24
Peak memory 227644 kb
Host smart-59abca20-a952-4687-b5e2-1391f61e13e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971017052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swap
.971017052
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.3091845630
Short name T522
Test name
Test status
Simulation time 114775822 ps
CPU time 2.25 seconds
Started Jul 25 06:39:10 PM PDT 24
Finished Jul 25 06:39:12 PM PDT 24
Peak memory 232528 kb
Host smart-5f5cd969-fc65-42d0-aa83-425ccda4d7b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091845630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.3091845630
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.700993221
Short name T130
Test name
Test status
Simulation time 167454053 ps
CPU time 4.8 seconds
Started Jul 25 06:39:10 PM PDT 24
Finished Jul 25 06:39:15 PM PDT 24
Peak memory 222688 kb
Host smart-eec52da4-4ad4-49b2-92e1-72699a26f46f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=700993221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dire
ct.700993221
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.1271123481
Short name T287
Test name
Test status
Simulation time 118716002053 ps
CPU time 522.89 seconds
Started Jul 25 06:39:12 PM PDT 24
Finished Jul 25 06:47:55 PM PDT 24
Peak memory 282360 kb
Host smart-7cc51c4b-7d19-4f99-8f06-c90d61fb2ada
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271123481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.1271123481
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.3095518129
Short name T396
Test name
Test status
Simulation time 20818625084 ps
CPU time 25.91 seconds
Started Jul 25 06:39:09 PM PDT 24
Finished Jul 25 06:39:35 PM PDT 24
Peak memory 216696 kb
Host smart-e2a97b76-f167-4b16-868f-9608ecdcdcec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095518129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.3095518129
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.2311017007
Short name T882
Test name
Test status
Simulation time 2780611051 ps
CPU time 12.3 seconds
Started Jul 25 06:39:14 PM PDT 24
Finished Jul 25 06:39:27 PM PDT 24
Peak memory 216412 kb
Host smart-8fb60e64-b3ff-419b-8c74-106e19f77e12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311017007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.2311017007
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.3862564387
Short name T323
Test name
Test status
Simulation time 70294801 ps
CPU time 0.9 seconds
Started Jul 25 06:39:08 PM PDT 24
Finished Jul 25 06:39:09 PM PDT 24
Peak memory 207248 kb
Host smart-c3adcb21-b38b-42d9-b9d3-4874db3a6802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862564387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.3862564387
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.2471179718
Short name T343
Test name
Test status
Simulation time 43757964 ps
CPU time 0.8 seconds
Started Jul 25 06:39:08 PM PDT 24
Finished Jul 25 06:39:09 PM PDT 24
Peak memory 206108 kb
Host smart-c118f174-f65b-4624-9a08-96d88b5993d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471179718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.2471179718
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.1886034142
Short name T914
Test name
Test status
Simulation time 29394938021 ps
CPU time 23.24 seconds
Started Jul 25 06:39:10 PM PDT 24
Finished Jul 25 06:39:33 PM PDT 24
Peak memory 232888 kb
Host smart-068cf99d-96c0-4e9c-b25b-087fb496e3d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886034142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.1886034142
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.2699174802
Short name T339
Test name
Test status
Simulation time 11042207 ps
CPU time 0.73 seconds
Started Jul 25 06:39:17 PM PDT 24
Finished Jul 25 06:39:18 PM PDT 24
Peak memory 205044 kb
Host smart-64164221-3cc1-47b9-9add-3d7a61cd4d73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699174802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
2699174802
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.2879378432
Short name T572
Test name
Test status
Simulation time 341834125 ps
CPU time 3.05 seconds
Started Jul 25 06:39:18 PM PDT 24
Finished Jul 25 06:39:21 PM PDT 24
Peak memory 224732 kb
Host smart-0bf3c641-255b-4268-89ae-b72009d178fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879378432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.2879378432
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.3619175876
Short name T361
Test name
Test status
Simulation time 27952567 ps
CPU time 0.9 seconds
Started Jul 25 06:39:14 PM PDT 24
Finished Jul 25 06:39:15 PM PDT 24
Peak memory 206560 kb
Host smart-4fa5d2a7-d18b-4169-b320-7ce11eaa2112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619175876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.3619175876
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.1215275126
Short name T393
Test name
Test status
Simulation time 31964378810 ps
CPU time 65.55 seconds
Started Jul 25 06:39:15 PM PDT 24
Finished Jul 25 06:40:21 PM PDT 24
Peak memory 249332 kb
Host smart-7b6d8cf0-8e65-40c1-b6ad-1f1ac3645a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215275126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.1215275126
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.2784561560
Short name T275
Test name
Test status
Simulation time 44036038207 ps
CPU time 213.75 seconds
Started Jul 25 06:39:17 PM PDT 24
Finished Jul 25 06:42:51 PM PDT 24
Peak memory 250756 kb
Host smart-ec3ac6f6-129c-43fa-815e-daa2a14764c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784561560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.2784561560
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.2667176953
Short name T37
Test name
Test status
Simulation time 9432882978 ps
CPU time 44.52 seconds
Started Jul 25 06:39:16 PM PDT 24
Finished Jul 25 06:40:00 PM PDT 24
Peak memory 255228 kb
Host smart-eea707f6-a2b9-4f8a-acae-ab3b8d7317bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667176953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.2667176953
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.3737811607
Short name T43
Test name
Test status
Simulation time 800894479 ps
CPU time 4.51 seconds
Started Jul 25 06:39:17 PM PDT 24
Finished Jul 25 06:39:22 PM PDT 24
Peak memory 232936 kb
Host smart-010d21cd-b2bf-41b0-909b-f87d00595caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737811607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.3737811607
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.561093275
Short name T73
Test name
Test status
Simulation time 20681251130 ps
CPU time 63.89 seconds
Started Jul 25 06:39:23 PM PDT 24
Finished Jul 25 06:40:27 PM PDT 24
Peak memory 257172 kb
Host smart-c9a56300-a272-4edc-b698-cb747759d701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561093275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmds
.561093275
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_intercept.766114593
Short name T224
Test name
Test status
Simulation time 501855474 ps
CPU time 7.8 seconds
Started Jul 25 06:39:17 PM PDT 24
Finished Jul 25 06:39:25 PM PDT 24
Peak memory 232912 kb
Host smart-b968a2f9-5634-4aaf-a573-759d91e89993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766114593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.766114593
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.3148090381
Short name T519
Test name
Test status
Simulation time 10838454241 ps
CPU time 30.18 seconds
Started Jul 25 06:39:23 PM PDT 24
Finished Jul 25 06:39:53 PM PDT 24
Peak memory 233980 kb
Host smart-1353515c-41e7-4532-ba7e-1a9388b7e78c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148090381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.3148090381
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.2546838078
Short name T576
Test name
Test status
Simulation time 481711010 ps
CPU time 2.42 seconds
Started Jul 25 06:39:20 PM PDT 24
Finished Jul 25 06:39:22 PM PDT 24
Peak memory 232824 kb
Host smart-6f607d09-159d-41d3-a234-466488ef58f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546838078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.2546838078
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.3219793801
Short name T236
Test name
Test status
Simulation time 568244577 ps
CPU time 10.45 seconds
Started Jul 25 06:39:08 PM PDT 24
Finished Jul 25 06:39:19 PM PDT 24
Peak memory 249404 kb
Host smart-491d9a12-5c90-4509-bc01-c6eb016b2a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219793801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.3219793801
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.2341903561
Short name T399
Test name
Test status
Simulation time 525396447 ps
CPU time 5.09 seconds
Started Jul 25 06:39:15 PM PDT 24
Finished Jul 25 06:39:20 PM PDT 24
Peak memory 220720 kb
Host smart-168666ee-7f0a-4ede-a961-634628968978
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2341903561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.2341903561
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.1206252263
Short name T180
Test name
Test status
Simulation time 30476725892 ps
CPU time 280.59 seconds
Started Jul 25 06:39:16 PM PDT 24
Finished Jul 25 06:43:57 PM PDT 24
Peak memory 251396 kb
Host smart-11f21e47-0b9b-4eb3-a69c-ece9433f3047
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206252263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.1206252263
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.1109787265
Short name T402
Test name
Test status
Simulation time 3302283968 ps
CPU time 23.23 seconds
Started Jul 25 06:39:15 PM PDT 24
Finished Jul 25 06:39:38 PM PDT 24
Peak memory 216448 kb
Host smart-659a60ca-366a-4002-92c2-cbf701dbf465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109787265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.1109787265
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.3124542244
Short name T376
Test name
Test status
Simulation time 323430056 ps
CPU time 1.92 seconds
Started Jul 25 06:39:07 PM PDT 24
Finished Jul 25 06:39:10 PM PDT 24
Peak memory 216208 kb
Host smart-00c5fd02-d999-47cc-ba6c-bb947f37a5bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124542244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.3124542244
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.237818435
Short name T346
Test name
Test status
Simulation time 484268438 ps
CPU time 2.61 seconds
Started Jul 25 06:39:10 PM PDT 24
Finished Jul 25 06:39:13 PM PDT 24
Peak memory 216448 kb
Host smart-40e06e26-221a-45bc-882e-6f39cf7e1322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237818435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.237818435
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.1262591844
Short name T370
Test name
Test status
Simulation time 104058397 ps
CPU time 0.83 seconds
Started Jul 25 06:39:08 PM PDT 24
Finished Jul 25 06:39:09 PM PDT 24
Peak memory 206052 kb
Host smart-6305e30f-0f7e-4ce6-87c6-1aab6cb8f71c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262591844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.1262591844
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.2892195101
Short name T777
Test name
Test status
Simulation time 7395056428 ps
CPU time 8.94 seconds
Started Jul 25 06:39:17 PM PDT 24
Finished Jul 25 06:39:26 PM PDT 24
Peak memory 232960 kb
Host smart-fd5672e0-376f-4c1d-aa1a-92dc2934acf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892195101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.2892195101
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.559972462
Short name T145
Test name
Test status
Simulation time 55544340 ps
CPU time 0.74 seconds
Started Jul 25 06:36:40 PM PDT 24
Finished Jul 25 06:36:41 PM PDT 24
Peak memory 205924 kb
Host smart-9d4a6137-bf8c-4be2-92f6-2de418089e86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559972462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.559972462
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.3451857397
Short name T693
Test name
Test status
Simulation time 352490531 ps
CPU time 5.73 seconds
Started Jul 25 06:36:34 PM PDT 24
Finished Jul 25 06:36:39 PM PDT 24
Peak memory 232904 kb
Host smart-7558adeb-f893-4c26-b0d1-a372914abc60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451857397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.3451857397
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.3806329425
Short name T856
Test name
Test status
Simulation time 35630860 ps
CPU time 0.78 seconds
Started Jul 25 06:36:36 PM PDT 24
Finished Jul 25 06:36:37 PM PDT 24
Peak memory 206732 kb
Host smart-5ed3a453-b2ec-4360-8c38-cfd452db2cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806329425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.3806329425
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.4131762383
Short name T752
Test name
Test status
Simulation time 3134214225 ps
CPU time 61.36 seconds
Started Jul 25 06:36:34 PM PDT 24
Finished Jul 25 06:37:36 PM PDT 24
Peak memory 256252 kb
Host smart-e6234be9-614c-450a-bc81-b0e96bac482a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131762383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.4131762383
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.2750774632
Short name T875
Test name
Test status
Simulation time 2917054835 ps
CPU time 27.93 seconds
Started Jul 25 06:36:41 PM PDT 24
Finished Jul 25 06:37:09 PM PDT 24
Peak memory 249344 kb
Host smart-813e9d2f-85bf-4834-bf57-6fb1af878219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750774632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.2750774632
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.1853760149
Short name T409
Test name
Test status
Simulation time 12395559509 ps
CPU time 11.58 seconds
Started Jul 25 06:36:40 PM PDT 24
Finished Jul 25 06:36:52 PM PDT 24
Peak memory 217676 kb
Host smart-087bffa1-2cd9-4bc4-b39c-6470dbd777e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853760149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.1853760149
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.943946957
Short name T1003
Test name
Test status
Simulation time 628787474 ps
CPU time 3.34 seconds
Started Jul 25 06:36:34 PM PDT 24
Finished Jul 25 06:36:38 PM PDT 24
Peak memory 224720 kb
Host smart-06c7890e-257c-4789-8908-7eec5fda2c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943946957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.943946957
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.600912929
Short name T41
Test name
Test status
Simulation time 43787683417 ps
CPU time 300.29 seconds
Started Jul 25 06:36:42 PM PDT 24
Finished Jul 25 06:41:42 PM PDT 24
Peak memory 265740 kb
Host smart-0949b3e0-f29f-445d-9d2d-86fb85d9817a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600912929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds.
600912929
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_intercept.4213723093
Short name T591
Test name
Test status
Simulation time 216259068 ps
CPU time 4.82 seconds
Started Jul 25 06:36:34 PM PDT 24
Finished Jul 25 06:36:39 PM PDT 24
Peak memory 224672 kb
Host smart-51afb82e-f755-4960-a857-13e46529f142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213723093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.4213723093
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.3974999349
Short name T185
Test name
Test status
Simulation time 9440611744 ps
CPU time 83.06 seconds
Started Jul 25 06:36:42 PM PDT 24
Finished Jul 25 06:38:05 PM PDT 24
Peak memory 232960 kb
Host smart-9a27a1c0-a5ad-4aa4-adcd-c804896ce4f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974999349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.3974999349
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.3054030614
Short name T237
Test name
Test status
Simulation time 421729563 ps
CPU time 3.43 seconds
Started Jul 25 06:36:40 PM PDT 24
Finished Jul 25 06:36:43 PM PDT 24
Peak memory 232892 kb
Host smart-a9c2c6a4-4659-4604-9cdf-e3e4075a119c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054030614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.3054030614
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.54771372
Short name T948
Test name
Test status
Simulation time 8460505082 ps
CPU time 23.14 seconds
Started Jul 25 06:36:39 PM PDT 24
Finished Jul 25 06:37:02 PM PDT 24
Peak memory 232912 kb
Host smart-e699a756-e3f6-4b0b-95c4-45e98ae24178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54771372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.54771372
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.376722711
Short name T505
Test name
Test status
Simulation time 238891359 ps
CPU time 4.38 seconds
Started Jul 25 06:36:33 PM PDT 24
Finished Jul 25 06:36:38 PM PDT 24
Peak memory 223276 kb
Host smart-87a88167-9ac2-478e-b624-2f250f9998e8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=376722711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_direc
t.376722711
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.4166427002
Short name T139
Test name
Test status
Simulation time 107659521132 ps
CPU time 434.42 seconds
Started Jul 25 06:36:42 PM PDT 24
Finished Jul 25 06:43:56 PM PDT 24
Peak memory 257108 kb
Host smart-e0d574ce-aba6-44f7-9e22-fe947d382f75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166427002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.4166427002
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.508460743
Short name T300
Test name
Test status
Simulation time 78173565240 ps
CPU time 25.98 seconds
Started Jul 25 06:36:37 PM PDT 24
Finished Jul 25 06:37:03 PM PDT 24
Peak memory 216464 kb
Host smart-34903832-c6aa-4a42-94e7-c09032523148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508460743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.508460743
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.2503771776
Short name T556
Test name
Test status
Simulation time 1353367930 ps
CPU time 5.37 seconds
Started Jul 25 06:36:48 PM PDT 24
Finished Jul 25 06:36:53 PM PDT 24
Peak memory 216396 kb
Host smart-b9381191-ed8c-4f2e-a944-37080284f65d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503771776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.2503771776
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.3492743997
Short name T974
Test name
Test status
Simulation time 44851399 ps
CPU time 0.98 seconds
Started Jul 25 06:36:36 PM PDT 24
Finished Jul 25 06:36:37 PM PDT 24
Peak memory 207076 kb
Host smart-5876e377-9c08-442d-9aa3-3a06f29e4821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492743997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.3492743997
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.1818263107
Short name T562
Test name
Test status
Simulation time 21641619 ps
CPU time 0.86 seconds
Started Jul 25 06:36:32 PM PDT 24
Finished Jul 25 06:36:33 PM PDT 24
Peak memory 206084 kb
Host smart-87a7cbdc-3ff3-4df2-aa0c-7d33e230e9b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818263107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.1818263107
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.1815149827
Short name T469
Test name
Test status
Simulation time 14857660675 ps
CPU time 27.25 seconds
Started Jul 25 06:36:38 PM PDT 24
Finished Jul 25 06:37:06 PM PDT 24
Peak memory 241052 kb
Host smart-edd6a8e1-b4a0-412e-b926-2196c491d727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815149827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.1815149827
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.1951068847
Short name T363
Test name
Test status
Simulation time 48401939 ps
CPU time 0.74 seconds
Started Jul 25 06:36:37 PM PDT 24
Finished Jul 25 06:36:38 PM PDT 24
Peak memory 205060 kb
Host smart-63811f45-8bdf-45fb-a751-e39d68ccf01a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951068847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.1
951068847
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.1959109787
Short name T255
Test name
Test status
Simulation time 159006685 ps
CPU time 2.37 seconds
Started Jul 25 06:36:46 PM PDT 24
Finished Jul 25 06:36:48 PM PDT 24
Peak memory 224624 kb
Host smart-de4416a5-9801-41ef-9904-f0546a4a289b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959109787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.1959109787
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.2179444408
Short name T726
Test name
Test status
Simulation time 30749768 ps
CPU time 0.74 seconds
Started Jul 25 06:36:37 PM PDT 24
Finished Jul 25 06:36:38 PM PDT 24
Peak memory 206044 kb
Host smart-94ecc7ab-0830-4a74-b315-fa6e4b1223bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179444408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.2179444408
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.1981420979
Short name T816
Test name
Test status
Simulation time 800140919 ps
CPU time 9.09 seconds
Started Jul 25 06:36:41 PM PDT 24
Finished Jul 25 06:36:50 PM PDT 24
Peak memory 233904 kb
Host smart-2f29d47a-d559-4710-a582-933852c10fe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981420979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.1981420979
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.1773082769
Short name T479
Test name
Test status
Simulation time 7823354124 ps
CPU time 70.27 seconds
Started Jul 25 06:37:00 PM PDT 24
Finished Jul 25 06:38:11 PM PDT 24
Peak memory 249392 kb
Host smart-3061d105-9947-4630-8f2c-93d040231691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773082769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.1773082769
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.3909536607
Short name T440
Test name
Test status
Simulation time 7348585084 ps
CPU time 87.8 seconds
Started Jul 25 06:36:42 PM PDT 24
Finished Jul 25 06:38:11 PM PDT 24
Peak memory 241140 kb
Host smart-d9055f9d-92c5-44b7-8711-adfdfee4bc43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909536607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.3909536607
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.248237717
Short name T441
Test name
Test status
Simulation time 4231004783 ps
CPU time 14.56 seconds
Started Jul 25 06:36:44 PM PDT 24
Finished Jul 25 06:36:59 PM PDT 24
Peak memory 232912 kb
Host smart-f515c8d8-0de8-4a57-983d-68cf1f7a61e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248237717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.248237717
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.1496525548
Short name T288
Test name
Test status
Simulation time 11081654835 ps
CPU time 103.97 seconds
Started Jul 25 06:36:42 PM PDT 24
Finished Jul 25 06:38:27 PM PDT 24
Peak memory 256532 kb
Host smart-a75951d0-34d6-4ed5-9153-3e4116324bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496525548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds
.1496525548
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/6.spi_device_intercept.2691046514
Short name T662
Test name
Test status
Simulation time 354467967 ps
CPU time 3.6 seconds
Started Jul 25 06:36:41 PM PDT 24
Finished Jul 25 06:36:45 PM PDT 24
Peak memory 224684 kb
Host smart-97690d20-6430-443e-a6ea-1a184900eb41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691046514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.2691046514
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.1707072529
Short name T754
Test name
Test status
Simulation time 5416306117 ps
CPU time 18.44 seconds
Started Jul 25 06:36:44 PM PDT 24
Finished Jul 25 06:37:03 PM PDT 24
Peak memory 224756 kb
Host smart-f9aff3ac-cf88-4432-8e0a-3bde5236641d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707072529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.1707072529
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.3115512820
Short name T843
Test name
Test status
Simulation time 250039995 ps
CPU time 2.34 seconds
Started Jul 25 06:36:44 PM PDT 24
Finished Jul 25 06:36:47 PM PDT 24
Peak memory 223592 kb
Host smart-0d7f1205-2a62-4d0e-bebb-bb7bc7a9a72f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115512820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.3115512820
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.200535372
Short name T624
Test name
Test status
Simulation time 2753219883 ps
CPU time 9.9 seconds
Started Jul 25 06:36:45 PM PDT 24
Finished Jul 25 06:36:55 PM PDT 24
Peak memory 224764 kb
Host smart-943e1e92-704b-4033-888b-d6e3ee4730b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200535372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.200535372
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.3547777999
Short name T569
Test name
Test status
Simulation time 313198515 ps
CPU time 7.06 seconds
Started Jul 25 06:36:41 PM PDT 24
Finished Jul 25 06:36:48 PM PDT 24
Peak memory 220800 kb
Host smart-80bc568c-34b9-45b5-ba5b-86fadf8a3948
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3547777999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.3547777999
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.527537706
Short name T138
Test name
Test status
Simulation time 1387757935 ps
CPU time 25.77 seconds
Started Jul 25 06:36:47 PM PDT 24
Finished Jul 25 06:37:13 PM PDT 24
Peak memory 241136 kb
Host smart-1deff4b0-7cd9-454a-9528-8ef1ce12f606
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527537706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stress
_all.527537706
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.824261077
Short name T894
Test name
Test status
Simulation time 6773248668 ps
CPU time 14.99 seconds
Started Jul 25 06:36:42 PM PDT 24
Finished Jul 25 06:36:57 PM PDT 24
Peak memory 216452 kb
Host smart-55764ad5-866a-4f87-b8ff-df03348f56d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824261077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.824261077
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.1471866981
Short name T600
Test name
Test status
Simulation time 11823735 ps
CPU time 0.69 seconds
Started Jul 25 06:36:53 PM PDT 24
Finished Jul 25 06:36:53 PM PDT 24
Peak memory 205768 kb
Host smart-0e366b47-f527-431e-9ec6-8ac1869c2ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471866981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.1471866981
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.277444328
Short name T688
Test name
Test status
Simulation time 38731730 ps
CPU time 0.71 seconds
Started Jul 25 06:36:47 PM PDT 24
Finished Jul 25 06:36:48 PM PDT 24
Peak memory 205744 kb
Host smart-4d9f2dab-6f6f-4366-a709-1fd175f66807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277444328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.277444328
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.1172531203
Short name T769
Test name
Test status
Simulation time 25965174 ps
CPU time 0.71 seconds
Started Jul 25 06:36:49 PM PDT 24
Finished Jul 25 06:36:50 PM PDT 24
Peak memory 206072 kb
Host smart-1f4545a4-873d-4b59-8ae2-2604cdef77df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172531203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.1172531203
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.3714508126
Short name T973
Test name
Test status
Simulation time 78901937 ps
CPU time 2.62 seconds
Started Jul 25 06:36:40 PM PDT 24
Finished Jul 25 06:36:43 PM PDT 24
Peak memory 234280 kb
Host smart-17d99bf2-eddf-4fa2-a355-7514f77a7ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714508126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.3714508126
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.305294092
Short name T331
Test name
Test status
Simulation time 33875818 ps
CPU time 0.72 seconds
Started Jul 25 06:36:44 PM PDT 24
Finished Jul 25 06:36:45 PM PDT 24
Peak memory 205576 kb
Host smart-7ffe1d15-3ee4-481c-8c94-07aa9562e4e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305294092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.305294092
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.3894059705
Short name T83
Test name
Test status
Simulation time 837893054 ps
CPU time 8.34 seconds
Started Jul 25 06:36:48 PM PDT 24
Finished Jul 25 06:36:56 PM PDT 24
Peak memory 232888 kb
Host smart-1a31529e-2a80-4aec-8b72-5f675040c32b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894059705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.3894059705
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.3124445693
Short name T579
Test name
Test status
Simulation time 78549435 ps
CPU time 0.82 seconds
Started Jul 25 06:36:46 PM PDT 24
Finished Jul 25 06:36:47 PM PDT 24
Peak memory 207048 kb
Host smart-ebf8c2d8-ecb4-4b0c-b838-7ce221e30ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124445693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.3124445693
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.3051356550
Short name T276
Test name
Test status
Simulation time 7000866709 ps
CPU time 90.4 seconds
Started Jul 25 06:36:45 PM PDT 24
Finished Jul 25 06:38:16 PM PDT 24
Peak memory 253752 kb
Host smart-2732836e-8cff-4c8a-88d1-e4240eed82d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051356550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.3051356550
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.478835326
Short name T792
Test name
Test status
Simulation time 6541492629 ps
CPU time 82.89 seconds
Started Jul 25 06:36:39 PM PDT 24
Finished Jul 25 06:38:02 PM PDT 24
Peak memory 251816 kb
Host smart-ac1ca6f5-1527-4430-8e33-ed4a3c417098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478835326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.478835326
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.3380911029
Short name T487
Test name
Test status
Simulation time 10809210647 ps
CPU time 19.68 seconds
Started Jul 25 06:36:39 PM PDT 24
Finished Jul 25 06:36:59 PM PDT 24
Peak memory 217860 kb
Host smart-ef4cdab8-e51c-4170-862b-32217916783d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380911029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.3380911029
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.3144193902
Short name T299
Test name
Test status
Simulation time 6138954237 ps
CPU time 24.09 seconds
Started Jul 25 06:37:08 PM PDT 24
Finished Jul 25 06:37:32 PM PDT 24
Peak memory 240920 kb
Host smart-b210ba18-5869-4f22-a4b9-e65e57e7ce6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144193902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.3144193902
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.2968335818
Short name T575
Test name
Test status
Simulation time 17453690580 ps
CPU time 163.2 seconds
Started Jul 25 06:36:42 PM PDT 24
Finished Jul 25 06:39:25 PM PDT 24
Peak memory 257540 kb
Host smart-75a3c4fb-987e-4617-9163-e432824c50ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968335818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds
.2968335818
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.354166692
Short name T259
Test name
Test status
Simulation time 160688434 ps
CPU time 2.3 seconds
Started Jul 25 06:36:39 PM PDT 24
Finished Jul 25 06:36:42 PM PDT 24
Peak memory 224676 kb
Host smart-f76ea745-ff06-48a5-8757-db6dd494fb7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354166692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.354166692
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.1139185072
Short name T987
Test name
Test status
Simulation time 8215716240 ps
CPU time 64.13 seconds
Started Jul 25 06:36:42 PM PDT 24
Finished Jul 25 06:37:47 PM PDT 24
Peak memory 232904 kb
Host smart-111380a4-817d-4710-8df6-12f3ba9f8267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139185072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.1139185072
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.3866459720
Short name T890
Test name
Test status
Simulation time 15707524094 ps
CPU time 14.03 seconds
Started Jul 25 06:36:48 PM PDT 24
Finished Jul 25 06:37:02 PM PDT 24
Peak memory 232888 kb
Host smart-32ec7901-1ab3-4c66-a4c6-1a9587f83d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866459720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.3866459720
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.170781144
Short name T887
Test name
Test status
Simulation time 33572938697 ps
CPU time 28.22 seconds
Started Jul 25 06:36:42 PM PDT 24
Finished Jul 25 06:37:10 PM PDT 24
Peak memory 239520 kb
Host smart-f13cb26f-c16f-4c9c-aca6-346fc8817aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170781144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.170781144
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.203551937
Short name T424
Test name
Test status
Simulation time 613480464 ps
CPU time 8.61 seconds
Started Jul 25 06:36:41 PM PDT 24
Finished Jul 25 06:36:50 PM PDT 24
Peak memory 221704 kb
Host smart-1659ad60-2c7c-4661-a55f-272d64343af7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=203551937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_direc
t.203551937
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.1010979803
Short name T924
Test name
Test status
Simulation time 76515012634 ps
CPU time 288.79 seconds
Started Jul 25 06:36:44 PM PDT 24
Finished Jul 25 06:41:33 PM PDT 24
Peak memory 283764 kb
Host smart-2cedeff9-1edf-4c50-a002-cd945ac17247
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010979803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.1010979803
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.2635347055
Short name T634
Test name
Test status
Simulation time 6567897335 ps
CPU time 23.24 seconds
Started Jul 25 06:36:45 PM PDT 24
Finished Jul 25 06:37:08 PM PDT 24
Peak memory 216452 kb
Host smart-09fa2b0e-c745-4747-b1de-ea582489c290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635347055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.2635347055
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.1852419411
Short name T793
Test name
Test status
Simulation time 5836162907 ps
CPU time 5.57 seconds
Started Jul 25 06:36:39 PM PDT 24
Finished Jul 25 06:36:44 PM PDT 24
Peak memory 216584 kb
Host smart-d7ba12ff-cdef-4158-bfdc-1156a391bfd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852419411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.1852419411
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.1663542743
Short name T797
Test name
Test status
Simulation time 164152973 ps
CPU time 3.47 seconds
Started Jul 25 06:36:40 PM PDT 24
Finished Jul 25 06:36:44 PM PDT 24
Peak memory 216472 kb
Host smart-4732d5f4-ad09-4f0b-98a6-ed12bd9c3c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663542743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.1663542743
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.884146204
Short name T895
Test name
Test status
Simulation time 26082702 ps
CPU time 0.77 seconds
Started Jul 25 06:36:48 PM PDT 24
Finished Jul 25 06:36:49 PM PDT 24
Peak memory 206112 kb
Host smart-185be4f4-be56-4cab-9d78-19b83259cbc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884146204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.884146204
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.4058003000
Short name T840
Test name
Test status
Simulation time 546335935 ps
CPU time 2.39 seconds
Started Jul 25 06:36:43 PM PDT 24
Finished Jul 25 06:36:46 PM PDT 24
Peak memory 224388 kb
Host smart-649cbb07-95c2-46ac-802c-678e7576217e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058003000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.4058003000
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.2140669713
Short name T989
Test name
Test status
Simulation time 31706802 ps
CPU time 0.74 seconds
Started Jul 25 06:36:47 PM PDT 24
Finished Jul 25 06:36:48 PM PDT 24
Peak memory 205560 kb
Host smart-c8fc0439-4014-40fd-8fc9-f6e01fd77fa8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140669713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.2
140669713
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.1385560805
Short name T738
Test name
Test status
Simulation time 79206097 ps
CPU time 3.47 seconds
Started Jul 25 06:36:47 PM PDT 24
Finished Jul 25 06:36:51 PM PDT 24
Peak memory 232892 kb
Host smart-726b4637-8267-442b-aa19-d2895ccbbb59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385560805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.1385560805
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.1571251525
Short name T435
Test name
Test status
Simulation time 53891399 ps
CPU time 0.75 seconds
Started Jul 25 06:36:41 PM PDT 24
Finished Jul 25 06:36:42 PM PDT 24
Peak memory 205656 kb
Host smart-b13be845-a670-4c29-a61b-bbdbb74f7d50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571251525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.1571251525
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.4131249617
Short name T855
Test name
Test status
Simulation time 2849003868 ps
CPU time 55.26 seconds
Started Jul 25 06:36:46 PM PDT 24
Finished Jul 25 06:37:47 PM PDT 24
Peak memory 249416 kb
Host smart-0173f2cd-8744-40f3-b7ee-d323ba9517cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131249617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.4131249617
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.1307066750
Short name T468
Test name
Test status
Simulation time 39032438005 ps
CPU time 325.18 seconds
Started Jul 25 06:36:43 PM PDT 24
Finished Jul 25 06:42:09 PM PDT 24
Peak memory 252880 kb
Host smart-256db317-bc37-4a01-b1dc-3c6d439d0410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307066750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.1307066750
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.1162291315
Short name T272
Test name
Test status
Simulation time 210673532553 ps
CPU time 501.21 seconds
Started Jul 25 06:36:45 PM PDT 24
Finished Jul 25 06:45:07 PM PDT 24
Peak memory 253524 kb
Host smart-c014fe1a-583d-491a-9d96-aa423eb3edda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162291315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.1162291315
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.705959036
Short name T8
Test name
Test status
Simulation time 818505251 ps
CPU time 6.25 seconds
Started Jul 25 06:36:44 PM PDT 24
Finished Jul 25 06:36:50 PM PDT 24
Peak memory 232916 kb
Host smart-ea76fd5a-a83a-40a8-97ef-81d45007969b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705959036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.705959036
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.390004465
Short name T340
Test name
Test status
Simulation time 2332480377 ps
CPU time 8.54 seconds
Started Jul 25 06:36:47 PM PDT 24
Finished Jul 25 06:36:55 PM PDT 24
Peak memory 224764 kb
Host smart-6d22752f-8619-4b00-8dea-59f68d981780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390004465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds.
390004465
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/8.spi_device_intercept.3023415718
Short name T92
Test name
Test status
Simulation time 74299595 ps
CPU time 2.07 seconds
Started Jul 25 06:36:45 PM PDT 24
Finished Jul 25 06:36:47 PM PDT 24
Peak memory 224368 kb
Host smart-62487cb5-1a8a-40b9-9995-4d3114616e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023415718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.3023415718
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.3479697947
Short name T770
Test name
Test status
Simulation time 9858368446 ps
CPU time 30.75 seconds
Started Jul 25 06:36:43 PM PDT 24
Finished Jul 25 06:37:14 PM PDT 24
Peak memory 240884 kb
Host smart-9ad3a00f-77a8-4552-b2e0-99f171183439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479697947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.3479697947
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.1775540997
Short name T246
Test name
Test status
Simulation time 8906939025 ps
CPU time 11.77 seconds
Started Jul 25 06:36:43 PM PDT 24
Finished Jul 25 06:36:54 PM PDT 24
Peak memory 224820 kb
Host smart-c1c9044a-3b27-4928-82bc-fb3adf17926a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775540997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.1775540997
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.560023123
Short name T334
Test name
Test status
Simulation time 121486125 ps
CPU time 2.64 seconds
Started Jul 25 06:36:40 PM PDT 24
Finished Jul 25 06:36:43 PM PDT 24
Peak memory 232896 kb
Host smart-b19d278f-c198-456c-928d-959eb99784f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560023123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.560023123
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.4066374295
Short name T127
Test name
Test status
Simulation time 416057812 ps
CPU time 5.15 seconds
Started Jul 25 06:36:48 PM PDT 24
Finished Jul 25 06:36:53 PM PDT 24
Peak memory 223380 kb
Host smart-0d34e3ef-7511-446b-82e1-a7f93d943ae8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4066374295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.4066374295
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.2834497029
Short name T1004
Test name
Test status
Simulation time 196928561 ps
CPU time 1.16 seconds
Started Jul 25 06:36:47 PM PDT 24
Finished Jul 25 06:36:49 PM PDT 24
Peak memory 216088 kb
Host smart-30d81906-4bb0-4f02-8846-a8fc83c7e4e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834497029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.2834497029
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.3480290833
Short name T803
Test name
Test status
Simulation time 11696830 ps
CPU time 0.7 seconds
Started Jul 25 06:36:47 PM PDT 24
Finished Jul 25 06:36:48 PM PDT 24
Peak memory 205848 kb
Host smart-a53818b0-2259-44a8-bebe-c09c4c4b2f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480290833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.3480290833
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.2879265221
Short name T326
Test name
Test status
Simulation time 22265287975 ps
CPU time 16.38 seconds
Started Jul 25 06:36:50 PM PDT 24
Finished Jul 25 06:37:06 PM PDT 24
Peak memory 215980 kb
Host smart-362e9f53-0f84-4e51-9b09-e3c0e508d5d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879265221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.2879265221
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.4003843264
Short name T766
Test name
Test status
Simulation time 432321527 ps
CPU time 3.39 seconds
Started Jul 25 06:36:45 PM PDT 24
Finished Jul 25 06:36:49 PM PDT 24
Peak memory 216432 kb
Host smart-f6cfaab9-0314-4dc8-a133-c8743e085f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003843264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.4003843264
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.2886224718
Short name T595
Test name
Test status
Simulation time 396246806 ps
CPU time 0.87 seconds
Started Jul 25 06:36:43 PM PDT 24
Finished Jul 25 06:36:44 PM PDT 24
Peak memory 206108 kb
Host smart-a6e64d90-cb4b-470d-afcf-9ab99cf1a6ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886224718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.2886224718
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.2147820386
Short name T12
Test name
Test status
Simulation time 11176195747 ps
CPU time 19.07 seconds
Started Jul 25 06:36:45 PM PDT 24
Finished Jul 25 06:37:04 PM PDT 24
Peak memory 241156 kb
Host smart-eb1eb9af-3186-4203-9519-448006b1068e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147820386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.2147820386
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.2473689471
Short name T450
Test name
Test status
Simulation time 46473294 ps
CPU time 0.72 seconds
Started Jul 25 06:36:48 PM PDT 24
Finished Jul 25 06:36:49 PM PDT 24
Peak memory 205584 kb
Host smart-f4575acd-e03d-464d-8745-8918077f2d65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473689471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.2
473689471
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.239094016
Short name T878
Test name
Test status
Simulation time 894751414 ps
CPU time 4.4 seconds
Started Jul 25 06:37:02 PM PDT 24
Finished Jul 25 06:37:06 PM PDT 24
Peak memory 224712 kb
Host smart-7299a2cd-aabb-475a-9ff4-5bd366d53ef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239094016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.239094016
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.3361988529
Short name T422
Test name
Test status
Simulation time 75843846 ps
CPU time 0.77 seconds
Started Jul 25 06:36:55 PM PDT 24
Finished Jul 25 06:36:55 PM PDT 24
Peak memory 207056 kb
Host smart-5dee35c4-aaee-45cc-9785-d5b024cb2064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361988529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.3361988529
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.1588644935
Short name T615
Test name
Test status
Simulation time 304724785 ps
CPU time 5.44 seconds
Started Jul 25 06:36:47 PM PDT 24
Finished Jul 25 06:36:53 PM PDT 24
Peak memory 224600 kb
Host smart-142db37d-f67a-4b96-84c1-edb86c375cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588644935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.1588644935
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.784065802
Short name T289
Test name
Test status
Simulation time 50092173053 ps
CPU time 195.49 seconds
Started Jul 25 06:36:47 PM PDT 24
Finished Jul 25 06:40:03 PM PDT 24
Peak memory 252936 kb
Host smart-bd88f0cf-e5b8-4f60-b224-f190ea59397d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784065802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.784065802
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.4112786506
Short name T352
Test name
Test status
Simulation time 2858582084 ps
CPU time 59.2 seconds
Started Jul 25 06:36:47 PM PDT 24
Finished Jul 25 06:37:47 PM PDT 24
Peak memory 249544 kb
Host smart-739d7a62-25fa-4613-8398-49957dfa3aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112786506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.4112786506
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.1746443344
Short name T316
Test name
Test status
Simulation time 288800983 ps
CPU time 4.14 seconds
Started Jul 25 06:36:47 PM PDT 24
Finished Jul 25 06:36:51 PM PDT 24
Peak memory 232860 kb
Host smart-817cf1e8-bb90-429e-aeb2-38afd97b60be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746443344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.1746443344
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.58781587
Short name T193
Test name
Test status
Simulation time 36566166572 ps
CPU time 105.16 seconds
Started Jul 25 06:36:50 PM PDT 24
Finished Jul 25 06:38:36 PM PDT 24
Peak memory 249352 kb
Host smart-d27ef1e4-2a68-414d-9279-103f427d3978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58781587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds.58781587
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.3236451477
Short name T796
Test name
Test status
Simulation time 251079264 ps
CPU time 2.45 seconds
Started Jul 25 06:37:12 PM PDT 24
Finished Jul 25 06:37:15 PM PDT 24
Peak memory 224664 kb
Host smart-9d9299f2-e21a-4f53-9041-8f998812be0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236451477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.3236451477
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.3967053602
Short name T685
Test name
Test status
Simulation time 671760456 ps
CPU time 5.32 seconds
Started Jul 25 06:36:47 PM PDT 24
Finished Jul 25 06:36:52 PM PDT 24
Peak memory 232912 kb
Host smart-27fa38f1-1f18-4b1d-82f3-bd65f08a7b27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967053602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.3967053602
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.2146151357
Short name T512
Test name
Test status
Simulation time 546676239 ps
CPU time 5.55 seconds
Started Jul 25 06:37:01 PM PDT 24
Finished Jul 25 06:37:07 PM PDT 24
Peak memory 224644 kb
Host smart-21523f3a-8bed-4ad3-8bc0-ab9feeeb6e76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146151357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.2146151357
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.286502664
Short name T513
Test name
Test status
Simulation time 4618019651 ps
CPU time 5.35 seconds
Started Jul 25 06:36:46 PM PDT 24
Finished Jul 25 06:36:52 PM PDT 24
Peak memory 224712 kb
Host smart-5b17e106-c01c-42af-95e6-9e29ecbf57b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286502664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.286502664
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.3271914174
Short name T131
Test name
Test status
Simulation time 793935184 ps
CPU time 5.23 seconds
Started Jul 25 06:36:54 PM PDT 24
Finished Jul 25 06:37:00 PM PDT 24
Peak memory 219144 kb
Host smart-4d4cfc47-942e-4e51-9f8e-6563a2ece064
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3271914174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.3271914174
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.3290761512
Short name T750
Test name
Test status
Simulation time 12791563318 ps
CPU time 77.69 seconds
Started Jul 25 06:36:47 PM PDT 24
Finished Jul 25 06:38:04 PM PDT 24
Peak memory 249360 kb
Host smart-2f6bde89-c84d-4502-bfca-2bec243efa2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290761512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.3290761512
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.1010262835
Short name T696
Test name
Test status
Simulation time 3455072999 ps
CPU time 9.05 seconds
Started Jul 25 06:36:46 PM PDT 24
Finished Jul 25 06:36:56 PM PDT 24
Peak memory 216440 kb
Host smart-4de56fb1-4233-433e-ad72-054f74351c2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010262835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.1010262835
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.2221396962
Short name T56
Test name
Test status
Simulation time 1399677631 ps
CPU time 3.53 seconds
Started Jul 25 06:36:51 PM PDT 24
Finished Jul 25 06:36:55 PM PDT 24
Peak memory 216436 kb
Host smart-7b83c096-43e5-4215-8756-baae7fe46d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221396962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.2221396962
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.2740500019
Short name T994
Test name
Test status
Simulation time 510146654 ps
CPU time 4.18 seconds
Started Jul 25 06:36:48 PM PDT 24
Finished Jul 25 06:36:52 PM PDT 24
Peak memory 216448 kb
Host smart-5d59ea81-34ce-477e-9703-d11122812264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740500019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.2740500019
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.1020658307
Short name T909
Test name
Test status
Simulation time 68945256 ps
CPU time 0.78 seconds
Started Jul 25 06:36:48 PM PDT 24
Finished Jul 25 06:36:49 PM PDT 24
Peak memory 206084 kb
Host smart-dba1f413-8d9c-4b88-830f-2be58796ffa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020658307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.1020658307
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.3814295601
Short name T660
Test name
Test status
Simulation time 127769060 ps
CPU time 2.61 seconds
Started Jul 25 06:36:49 PM PDT 24
Finished Jul 25 06:36:51 PM PDT 24
Peak memory 224596 kb
Host smart-2293aa04-0093-4160-b841-1b403dab13c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814295601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.3814295601
Directory /workspace/9.spi_device_upload/latest
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