Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3150940	1			T1	1		T2	1		T3	50879
all_values[1]	3150940	1			T1	1		T2	1		T3	50879
all_values[2]	3150940	1			T1	1		T2	1		T3	50879
all_values[3]	3150940	1			T1	1		T2	1		T3	50879
all_values[4]	3150940	1			T1	1		T2	1		T3	50879
all_values[5]	3150940	1			T1	1		T2	1		T3	50879
all_values[6]	3150940	1			T1	1		T2	1		T3	50879
all_values[7]	3150940	1			T1	1		T2	1		T3	50879

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24039753

1

T1

8

T2

8

T3

407032

auto[1]

1167767

1

T14

250936

T15

111

T16

35

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25179925

1

T1

8

T2

8

T3

406595

auto[1]

27595

1

T3

437

T7

348

T8

105

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2978387	1			T1	1		T2	1		T3	50703
all_values[0]	auto[0]	auto[1]	12529	1			T3	176		T7	189		T8	80
all_values[0]	auto[1]	auto[0]	159129	1			T14	3		T15	14		T16	1
all_values[0]	auto[1]	auto[1]	895	1			T14	3		T15	5		T16	2
all_values[1]	auto[0]	auto[0]	3024976	1			T1	1		T2	1		T3	50727
all_values[1]	auto[0]	auto[1]	8083	1			T3	152		T7	111		T8	15
all_values[1]	auto[1]	auto[0]	117222	1			T14	50103		T15	5		T16	3
all_values[1]	auto[1]	auto[1]	659	1			T14	82		T15	3		T17	2
all_values[2]	auto[0]	auto[0]	2993373	1			T1	1		T2	1		T3	50770
all_values[2]	auto[0]	auto[1]	3132	1			T3	109		T7	48		T8	10
all_values[2]	auto[1]	auto[0]	153956	1			T14	5		T15	3		T16	6
all_values[2]	auto[1]	auto[1]	479	1			T14	6		T15	5		T17	1
all_values[3]	auto[0]	auto[0]	3024660	1			T1	1		T2	1		T3	50879
all_values[3]	auto[0]	auto[1]	195	1			T14	4		T15	10		T17	1
all_values[3]	auto[1]	auto[0]	125916	1			T14	4		T15	10		T16	5
all_values[3]	auto[1]	auto[1]	169	1			T14	3		T15	1		T16	2
all_values[4]	auto[0]	auto[0]	3008533	1			T1	1		T2	1		T3	50879
all_values[4]	auto[0]	auto[1]	183	1			T14	4		T15	6		T17	1
all_values[4]	auto[1]	auto[0]	142041	1			T14	50175		T15	14		T16	6
all_values[4]	auto[1]	auto[1]	183	1			T14	4		T15	4		T16	1
all_values[5]	auto[0]	auto[0]	2974530	1			T1	1		T2	1		T3	50879
all_values[5]	auto[0]	auto[1]	174	1			T14	3		T15	12		T16	1
all_values[5]	auto[1]	auto[0]	176061	1			T14	50180		T15	8		T16	1
all_values[5]	auto[1]	auto[1]	175	1			T14	4		T15	5		T16	1
all_values[6]	auto[0]	auto[0]	3030002	1			T1	1		T2	1		T3	50879
all_values[6]	auto[0]	auto[1]	185	1			T14	3		T15	5		T16	3
all_values[6]	auto[1]	auto[0]	120572	1			T14	50179		T15	10		T16	1
all_values[6]	auto[1]	auto[1]	181	1			T14	5		T15	7		T16	3
all_values[7]	auto[0]	auto[0]	2980625	1			T1	1		T2	1		T3	50879
all_values[7]	auto[0]	auto[1]	186	1			T14	6		T15	4		T16	4
all_values[7]	auto[1]	auto[0]	169942	1			T14	50173		T15	12		T16	2
all_values[7]	auto[1]	auto[1]	187	1			T14	7		T15	5		T16	1