Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	36927	1			T3	113		T7	93		T8	164
auto[SpiFlashAddrCfg]	7884	1			T3	44		T7	43		T8	40
auto[SpiFlashAddr3b]	9400	1			T3	65		T7	50		T8	57
auto[SpiFlashAddr4b]	8295	1			T3	43		T7	42		T8	68

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

35588

1

T3

132

T7

135

T8

192

auto[1]

26918

1

T3

133

T7

93

T8

137

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32788

1

T3

138

T7

137

T8

153

auto[1]

29718

1

T3

127

T7

91

T8

176

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	41744	1			T3	149		T7	126		T8	192
values[1]	1188	1			T3	7		T7	6		T8	5
values[2]	1507	1			T3	5		T7	7		T8	7
values[3]	1596	1			T3	15		T7	5		T8	12
values[4]	1573	1			T3	10		T7	7		T8	12
values[5]	1574	1			T3	12		T7	16		T8	9
values[6]	1541	1			T3	3		T7	12		T8	7
values[7]	1527	1			T3	12		T7	5		T8	9
values[8]	10256	1			T3	52		T7	44		T8	76

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32413

1

T3

128

T7

228

T8

329

auto[1]

30093

1

T3

137

T12

260

T14

499

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

58981

1

T3

246

T7

217

T8

307

write

3525

1

T3

19

T7

11

T8

22

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

19969

1

T3

116

T7

95

T8

132

valids[0x1]

42537

1

T3

149

T7

133

T8

197

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1636	1			T3	11		T7	9		T8	11
internal_process_ops[0x5a]	1645	1			T3	10		T7	8		T8	8
internal_process_ops[0x05]	22338	1			T3	37		T7	32		T8	77
internal_process_ops[0x35]	1593	1			T3	7		T7	8		T8	6
internal_process_ops[0x15]	1683	1			T3	14		T7	8		T8	13
internal_process_ops[0x03]	1103	1			T3	4		T7	10		T8	10
internal_process_ops[0x0b]	1101	1			T3	5		T7	13		T8	11
internal_process_ops[0x3b]	1060	1			T3	3		T7	3		T8	7
internal_process_ops[0x6b]	1131	1			T3	5		T7	9		T8	13
internal_process_ops[0xbb]	1036	1			T3	6		T7	5		T8	6
internal_process_ops[0xeb]	1104	1			T3	7		T7	9		T8	6

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

60761

1

T3

256

T7

219

T8

318

auto[1]

1745

1

T3

9

T7

9

T8

11

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

59985

1

T3

250

T7

217

T8

320

auto[1]

2521

1

T3

15

T7

11

T8

9

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

11084

1

T3

26

T7

63

T8

109

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6828

1

T3

17

T7

30

T8

49

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2115

1

T3

5

T7

25

T8

18

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1889

1

T3

20

T7

16

T8

17

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2464

1

T3

7

T7

24

T8

26

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2153

1

T3

20

T7

21

T8

26

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2265

1

T3

14

T7

16

T8

29

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1949

1

T3

10

T7

22

T8

33

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

143

1

T3

2

T8

1

T25

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

121

1

T27

2

T31

2

T15

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

94

1

T8

3

T25

2

T31

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

99

1

T8

2

T25

3

T27

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

143

1

T8

3

T15

3

T32

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

87

1

T7

1

T8

1

T25

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

89

1

T3

1

T7

1

T25

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

108

1

T8

1

T16

1

T34

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

127

1

T3

2

T8

3

T25

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

84

1

T3

1

T7

2

T25

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

85

1

T3

1

T25

1

T15

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

80

1

T7

3

T8

2

T15

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

127

1

T3

2

T7

1

T146

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

109

1

T7

3

T8

2

T15

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

80

1

T8

1

T31

2

T16

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

90

1

T8

3

T9

2

T25

2

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10738

1

T3

38

T12

76

T14

117

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7346

1

T3

30

T12

36

T14

105

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1482

1

T3

7

T12

21

T14

39

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1507

1

T3

10

T12

21

T14

33

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1959

1

T3

12

T12

15

T14

45

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1986

1

T3

14

T12

27

T14

47

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1620

1

T3

8

T12

25

T14

35

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1596

1

T3

8

T12

17

T14

38

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

108

1

T12

2

T14

4

T38

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

111

1

T12

1

T14

1

T71

5

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

127

1

T12

2

T38

5

T71

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

128

1

T38

2

T17

4

T72

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

96

1

T14

1

T71

1

T39

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

142

1

T3

1

T12

10

T14

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

102

1

T12

3

T14

1

T37

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

124

1

T14

10

T38

1

T17

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

115

1

T14

4

T38

2

T71

4

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

117

1

T3

6

T12

1

T14

6

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

106

1

T3

2

T12

1

T14

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

124

1

T14

1

T37

6

T71

5

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

107

1

T12

1

T14

1

T38

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

124

1

T3

1

T14

3

T37

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

131

1

T12

1

T14

1

T71

4

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

97

1

T14

5

T71

1

T72

1

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3881	1			T3	18		T7	39		T8	45
auto[0]	values[0]	valids[0x1]	16911	1			T3	43		T7	87		T8	147
auto[0]	values[1]	valids[0x1]	658	1			T3	2		T7	6		T8	5
auto[0]	values[2]	valids[0x0]	530	1			T7	1		T8	1		T25	4
auto[0]	values[2]	valids[0x1]	327	1			T7	6		T8	6		T25	1
auto[0]	values[3]	valids[0x0]	567	1			T3	6		T7	4		T8	6
auto[0]	values[3]	valids[0x1]	342	1			T3	2		T7	1		T8	6
auto[0]	values[4]	valids[0x0]	539	1			T3	1		T7	5		T8	5
auto[0]	values[4]	valids[0x1]	352	1			T3	5		T7	2		T8	7
auto[0]	values[5]	valids[0x0]	525	1			T3	4		T7	10		T8	7
auto[0]	values[5]	valids[0x1]	346	1			T7	6		T8	2		T25	4
auto[0]	values[6]	valids[0x0]	583	1			T3	3		T7	11		T8	4
auto[0]	values[6]	valids[0x1]	301	1			T7	1		T8	3		T27	1
auto[0]	values[7]	valids[0x0]	568	1			T3	6		T7	2		T8	7
auto[0]	values[7]	valids[0x1]	286	1			T3	5		T7	3		T8	2
auto[0]	values[8]	valids[0x0]	3573	1			T3	25		T7	23		T8	57
auto[0]	values[8]	valids[0x1]	2124	1			T3	8		T7	21		T8	19
auto[1]	values[0]	valids[0x0]	4159	1			T3	24		T12	54		T14	93
auto[1]	values[0]	valids[0x1]	16793	1			T3	64		T12	86		T14	200
auto[1]	values[1]	valids[0x1]	530	1			T3	5		T12	8		T14	11
auto[1]	values[2]	valids[0x0]	370	1			T3	2		T12	6		T14	11
auto[1]	values[2]	valids[0x1]	280	1			T3	3		T12	4		T14	12
auto[1]	values[3]	valids[0x0]	381	1			T3	5		T12	1		T14	12
auto[1]	values[3]	valids[0x1]	306	1			T3	2		T12	9		T14	9
auto[1]	values[4]	valids[0x0]	386	1			T3	3		T12	6		T14	2
auto[1]	values[4]	valids[0x1]	296	1			T3	1		T12	5		T14	4
auto[1]	values[5]	valids[0x0]	413	1			T3	7		T12	9		T14	3
auto[1]	values[5]	valids[0x1]	290	1			T3	1		T12	5		T14	1
auto[1]	values[6]	valids[0x0]	410	1			T12	5		T14	6		T37	2
auto[1]	values[6]	valids[0x1]	247	1			T12	1		T14	10		T37	2
auto[1]	values[7]	valids[0x0]	413	1			T3	1		T12	7		T14	11
auto[1]	values[7]	valids[0x1]	260	1			T12	1		T14	11		T39	1
auto[1]	values[8]	valids[0x0]	2671	1			T3	11		T12	38		T14	60
auto[1]	values[8]	valids[0x1]	1888	1			T3	8		T12	15		T14	43