Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3473719

1

T2

2675

T3

17857

T7

9920

auto[1]

27809

1

T3

25

T7

28

T8

69

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

904067

1

T2

2675

T3

72

T7

66

auto[1]

2597461

1

T3

17810

T7

9882

T8

27200

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	660905	1			T3	3011		T7	1171		T8	6871
auto[524288:1048575]	438453	1			T2	3		T3	819		T7	4258
auto[1048576:1572863]	395096	1			T3	5979		T7	3		T8	1
auto[1572864:2097151]	401480	1			T3	6131		T7	7		T8	796
auto[2097152:2621439]	431597	1			T3	334		T7	74		T8	4240
auto[2621440:3145727]	361461	1			T3	129		T7	9		T8	978
auto[3145728:3670015]	398979	1			T3	1209		T7	260		T8	3137
auto[3670016:4194303]	413557	1			T2	2672		T3	270		T7	4166

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2633086

1

T2

4

T3

17882

T7

9944

auto[1]

868442

1

T2

2671

T7

4

T8

2

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3059046

1

T2

2675

T3

10205

T7

9426

auto[1]

442482

1

T3

7677

T7

522

T8

6383

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	177757	1			T3	12		T7	10		T8	7
auto[0]	auto[0]	auto[0:524287]	auto[1]	419074	1			T3	999		T7	642		T8	3871
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	112593	1			T2	3		T3	2		T7	3
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	278863	1			T3	817		T7	4253		T8	8360
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	103720	1			T3	12		T7	2		T12	17
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	232940	1			T3	5282		T7	1		T12	215
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	85745	1			T3	12		T7	2		T8	5
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	251750	1			T3	1123		T7	1		T8	774
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	120739	1			T3	7		T7	7		T8	4
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	259756	1			T3	326		T7	65		T8	3978
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	77578	1			T3	1		T7	4		T12	23
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	232117	1			T3	128		T7	2		T8	672
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	90231	1			T3	2		T7	4		T8	4
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	229762	1			T3	1200		T7	256		T8	3133
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	121344	1			T2	2672		T3	4		T7	17
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	242212	1			T3	258		T7	4130		T8	1
auto[0]	auto[1]	auto[0:524287]	auto[0]	2948	1			T7	3		T8	1		T12	21
auto[0]	auto[1]	auto[0:524287]	auto[1]	57249	1			T3	1996		T7	512		T8	2990
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	2324	1			T8	2		T12	25		T14	2
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	40957	1			T7	2		T8	2279		T12	256
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	629	1			T8	1		T14	9		T37	2
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	54713	1			T3	684		T25	256		T14	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	744	1			T3	3		T7	2		T8	3
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	59761	1			T3	4986		T7	1		T8	3
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	595	1			T7	1		T8	2		T25	3
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	47578	1			T8	256		T25	1		T14	256
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	623	1			T8	2		T12	18		T27	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	47504	1			T8	304		T12	640		T14	1956
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	1882	1			T3	2		T12	8		T27	2
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	73408	1			T3	1		T27	1		T15	129
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	574	1			T8	9		T12	24		T25	2
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	46049	1			T8	519		T12	515		T27	1
auto[1]	auto[0]	auto[0:524287]	auto[0]	503	1			T3	3		T7	2		T8	1
auto[1]	auto[0]	auto[0:524287]	auto[1]	2926	1			T3	1		T7	2		T8	1
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	481	1			T8	2		T12	15		T25	1
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	2417	1			T8	35		T25	5		T14	2
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	355	1			T3	1		T12	4		T25	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2143	1			T12	41		T25	1		T37	2
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	396	1			T3	4		T8	1		T12	6
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	2329	1			T8	8		T25	4		T38	32
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	386	1			T3	1		T7	1		T27	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2179	1			T14	1		T38	13		T15	43
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	376	1			T7	2		T12	8		T14	2
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	2808	1			T7	1		T14	3		T38	20
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	400	1			T3	2		T12	4		T25	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	2648	1			T25	2		T14	1		T31	33
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	415	1			T3	2		T7	5		T8	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	2103	1			T3	6		T7	14		T8	8
auto[1]	auto[1]	auto[0:524287]	auto[0]	86	1			T14	1		T38	2		T71	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	362	1			T38	37		T71	7		T18	1
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	108	1			T8	1		T12	9		T14	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	710	1			T8	1		T71	2		T17	2
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	109	1			T14	1		T31	3		T16	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	487	1			T31	18		T16	1		T71	33
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	107	1			T3	1		T7	1		T8	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	648	1			T3	2		T8	1		T14	2
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	44	1			T25	1		T15	2		T160	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	320	1			T25	2		T15	5		T160	41
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	73	1			T14	5		T72	4		T74	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	382	1			T14	7		T72	41		T74	9
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	91	1			T3	1		T12	5		T27	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	557	1			T3	1		T12	28		T27	3
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	111	1			T8	2		T27	1		T14	2
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	749	1			T8	6		T14	2		T31	18

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	2173420	1			T2	4		T3	10185		T7	9398
auto[0]	auto[0]	auto[1]	862761	1			T2	2671		T7	1		T8	1
auto[0]	auto[1]	auto[0]	432555	1			T3	7672		T7	521		T8	6371
auto[0]	auto[1]	auto[1]	4983	1			T38	1		T31	1		T78	1044
auto[1]	auto[0]	auto[0]	22296	1			T3	20		T7	24		T8	56
auto[1]	auto[0]	auto[1]	569	1			T7	3		T8	1		T12	10
auto[1]	auto[1]	auto[0]	4815	1			T3	5		T7	1		T8	12
auto[1]	auto[1]	auto[1]	129	1			T12	1		T14	1		T38	1