Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	3150940	1			T1	1		T2	1		T3	50879
all_pins[1]	3150940	1			T1	1		T2	1		T3	50879
all_pins[2]	3150940	1			T1	1		T2	1		T3	50879
all_pins[3]	3150940	1			T1	1		T2	1		T3	50879
all_pins[4]	3150940	1			T1	1		T2	1		T3	50879
all_pins[5]	3150940	1			T1	1		T2	1		T3	50879
all_pins[6]	3150940	1			T1	1		T2	1		T3	50879
all_pins[7]	3150940	1			T1	1		T2	1		T3	50879

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	25082157	1			T1	8		T2	8		T3	407032
values[0x1]	125363	1			T14	50763		T15	35		T16	10
transitions[0x0=>0x1]	122708	1			T14	50261		T15	29		T16	10
transitions[0x1=>0x0]	122720	1			T14	50261		T15	29		T16	10

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	3149985	1			T1	1		T2	1		T3	50879
all_pins[0]	values[0x1]	955	1			T14	3		T15	5		T16	2
all_pins[0]	transitions[0x0=>0x1]	517	1			T14	1		T15	5		T16	2
all_pins[0]	transitions[0x1=>0x0]	261	1			T14	84		T15	3		T17	2
all_pins[1]	values[0x0]	3150241	1			T1	1		T2	1		T3	50879
all_pins[1]	values[0x1]	699	1			T14	86		T15	3		T17	2
all_pins[1]	transitions[0x0=>0x1]	454	1			T14	84		T15	1		T17	2
all_pins[1]	transitions[0x1=>0x0]	252	1			T14	4		T15	3		T17	1
all_pins[2]	values[0x0]	3150443	1			T1	1		T2	1		T3	50879
all_pins[2]	values[0x1]	497	1			T14	6		T15	5		T17	1
all_pins[2]	transitions[0x0=>0x1]	452	1			T14	3		T15	5		T18	2
all_pins[2]	transitions[0x1=>0x0]	124	1			T15	1		T16	2		T17	1
all_pins[3]	values[0x0]	3150771	1			T1	1		T2	1		T3	50879
all_pins[3]	values[0x1]	169	1			T14	3		T15	1		T16	2
all_pins[3]	transitions[0x0=>0x1]	128	1			T14	2		T15	1		T16	2
all_pins[3]	transitions[0x1=>0x0]	142	1			T14	3		T15	4		T16	1
all_pins[4]	values[0x0]	3150757	1			T1	1		T2	1		T3	50879
all_pins[4]	values[0x1]	183	1			T14	4		T15	4		T16	1
all_pins[4]	transitions[0x0=>0x1]	149	1			T14	3		T15	3		T16	1
all_pins[4]	transitions[0x1=>0x0]	2547	1			T14	491		T15	4		T16	1
all_pins[5]	values[0x0]	3148359	1			T1	1		T2	1		T3	50879
all_pins[5]	values[0x1]	2581	1			T14	492		T15	5		T16	1
all_pins[5]	transitions[0x0=>0x1]	836	1			T14	5		T15	5		T16	1
all_pins[5]	transitions[0x1=>0x0]	118347	1			T14	49675		T15	7		T16	3
all_pins[6]	values[0x0]	3030848	1			T1	1		T2	1		T3	50879
all_pins[6]	values[0x1]	120092	1			T14	50162		T15	7		T16	3
all_pins[6]	transitions[0x0=>0x1]	120044	1			T14	50158		T15	6		T16	3
all_pins[6]	transitions[0x1=>0x0]	139	1			T14	3		T15	4		T16	1
all_pins[7]	values[0x0]	3150753	1			T1	1		T2	1		T3	50879
all_pins[7]	values[0x1]	187	1			T14	7		T15	5		T16	1
all_pins[7]	transitions[0x0=>0x1]	128	1			T14	5		T15	3		T16	1
all_pins[7]	transitions[0x1=>0x0]	908	1			T14	1		T15	3		T16	2