Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18869

1

T3

59

T7

135

T8

192

auto[1]

13544

1

T3

69

T7

93

T8

137

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4734	1			T3	20		T7	52		T25	47
values[1]	3875	1			T3	20		T7	26		T8	76
values[2]	3717	1			T8	60		T9	4		T25	23
values[3]	3616	1			T3	24		T8	40		T25	23
values[4]	4361	1			T7	21		T8	53		T25	24
values[5]	4352	1			T7	88		T8	42		T25	22
values[6]	3989	1			T3	44		T8	20		T25	30
values[7]	3769	1			T3	20		T7	41		T8	38

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4449	1			T7	95		T11	6		T27	20
values[1]	3430	1			T8	58		T16	46		T34	28
values[2]	4137	1			T3	20		T7	40		T25	43
values[3]	4542	1			T7	51		T8	40		T25	26
values[4]	4217	1			T7	42		T8	20		T25	45
values[5]	3917	1			T3	64		T8	109		T9	4
values[6]	3891	1			T8	20		T25	30		T31	174
values[7]	3830	1			T3	44		T8	82		T25	45

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	300	1			T7	10		T160	27		T207	6
auto[0]	values[0]	values[1]	174	1			T16	5		T185	15		T20	14
auto[0]	values[0]	values[2]	467	1			T3	10		T18	13		T160	13
auto[0]	values[0]	values[3]	402	1			T7	12		T25	12		T32	9
auto[0]	values[0]	values[4]	326	1			T25	12		T185	14		T208	8
auto[0]	values[0]	values[5]	307	1			T16	21		T34	23		T20	6
auto[0]	values[0]	values[6]	394	1			T18	12		T166	18		T83	16
auto[0]	values[0]	values[7]	286	1			T84	10		T16	14		T34	11
auto[0]	values[1]	values[0]	388	1			T7	18		T11	6		T15	106
auto[0]	values[1]	values[1]	178	1			T85	10		T22	101		T145	6
auto[0]	values[1]	values[2]	248	1			T16	11		T34	18		T20	12
auto[0]	values[1]	values[3]	280	1			T31	10		T209	8		T183	9
auto[0]	values[1]	values[4]	287	1			T35	8		T159	11		T210	10
auto[0]	values[1]	values[5]	279	1			T3	12		T8	52		T159	9
auto[0]	values[1]	values[6]	283	1			T31	15		T16	12		T211	6
auto[0]	values[1]	values[7]	338	1			T27	15		T170	24		T22	12
auto[0]	values[2]	values[0]	328	1			T32	9		T212	16		T163	14
auto[0]	values[2]	values[1]	238	1			T8	13		T18	8		T81	16
auto[0]	values[2]	values[2]	96	1			T213	8		T83	9		T170	8
auto[0]	values[2]	values[3]	372	1			T34	12		T159	10		T166	10
auto[0]	values[2]	values[4]	334	1			T8	13		T18	21		T167	7
auto[0]	values[2]	values[5]	221	1			T78	4		T159	15		T181	4
auto[0]	values[2]	values[6]	318	1			T8	9		T146	20		T160	15
auto[0]	values[2]	values[7]	399	1			T25	18		T214	6		T163	12
auto[0]	values[3]	values[0]	325	1			T15	9		T159	13		T83	11
auto[0]	values[3]	values[1]	180	1			T34	19		T196	8		T83	12
auto[0]	values[3]	values[2]	237	1			T25	13		T85	13		T20	12
auto[0]	values[3]	values[3]	324	1			T8	11		T215	22		T216	2
auto[0]	values[3]	values[4]	112	1			T31	15		T140	11		T217	16
auto[0]	values[3]	values[5]	305	1			T15	10		T190	8		T34	9
auto[0]	values[3]	values[6]	439	1			T31	19		T20	14		T170	10
auto[0]	values[3]	values[7]	347	1			T3	10		T8	9		T183	11
auto[0]	values[4]	values[0]	244	1			T18	9		T163	9		T218	40
auto[0]	values[4]	values[1]	206	1			T170	42		T219	6		T220	6
auto[0]	values[4]	values[2]	354	1			T48	10		T34	40		T18	9
auto[0]	values[4]	values[3]	200	1			T221	8		T160	12		T166	13
auto[0]	values[4]	values[4]	323	1			T7	9		T25	9		T184	14
auto[0]	values[4]	values[5]	422	1			T8	10		T16	10		T20	11
auto[0]	values[4]	values[6]	299	1			T16	15		T20	10		T83	29
auto[0]	values[4]	values[7]	229	1			T8	9		T15	10		T160	9
auto[0]	values[5]	values[0]	215	1			T7	36		T160	11		T167	10
auto[0]	values[5]	values[1]	351	1			T164	16		T167	12		T179	36
auto[0]	values[5]	values[2]	238	1			T7	9		T15	7		T32	9
auto[0]	values[5]	values[3]	437	1			T203	8		T31	15		T20	14
auto[0]	values[5]	values[4]	444	1			T7	9		T15	16		T16	11
auto[0]	values[5]	values[5]	188	1			T16	11		T200	18		T194	11
auto[0]	values[5]	values[6]	210	1			T183	14		T188	8		T163	9
auto[0]	values[5]	values[7]	283	1			T8	23		T25	15		T15	7
auto[0]	values[6]	values[0]	332	1			T16	34		T34	11		T159	14
auto[0]	values[6]	values[1]	152	1			T166	20		T167	10		T222	11
auto[0]	values[6]	values[2]	516	1			T31	23		T15	5		T223	4
auto[0]	values[6]	values[3]	209	1			T8	14		T160	10		T159	12
auto[0]	values[6]	values[4]	305	1			T16	8		T22	16		T179	6
auto[0]	values[6]	values[5]	332	1			T3	12		T182	18		T176	12
auto[0]	values[6]	values[6]	252	1			T25	15		T31	58		T224	2
auto[0]	values[6]	values[7]	289	1			T3	7		T27	11		T31	9
auto[0]	values[7]	values[0]	287	1			T27	13		T32	15		T183	9
auto[0]	values[7]	values[1]	365	1			T8	29		T16	15		T20	10
auto[0]	values[7]	values[2]	333	1			T7	18		T25	15		T27	14
auto[0]	values[7]	values[3]	416	1			T7	14		T185	12		T80	10
auto[0]	values[7]	values[4]	316	1			T31	12		T15	11		T160	13
auto[0]	values[7]	values[5]	204	1			T3	8		T16	11		T18	13
auto[0]	values[7]	values[6]	180	1			T31	15		T160	13		T167	11
auto[0]	values[7]	values[7]	226	1			T225	4		T226	20		T83	11
auto[1]	values[0]	values[0]	374	1			T7	12		T160	16		T20	45
auto[1]	values[0]	values[1]	184	1			T16	18		T185	7		T20	7
auto[1]	values[0]	values[2]	343	1			T3	10		T18	8		T160	7
auto[1]	values[0]	values[3]	250	1			T7	18		T25	14		T32	11
auto[1]	values[0]	values[4]	219	1			T25	9		T185	6		T179	14
auto[1]	values[0]	values[5]	312	1			T16	22		T34	24		T20	14
auto[1]	values[0]	values[6]	256	1			T18	9		T166	6		T83	4
auto[1]	values[0]	values[7]	140	1			T16	6		T34	9		T18	11
auto[1]	values[1]	values[0]	174	1			T7	8		T227	16		T15	4
auto[1]	values[1]	values[1]	231	1			T85	10		T22	5		T145	14
auto[1]	values[1]	values[2]	148	1			T16	9		T34	22		T20	8
auto[1]	values[1]	values[3]	294	1			T31	10		T183	15		T228	8
auto[1]	values[1]	values[4]	256	1			T159	9		T179	15		T29	13
auto[1]	values[1]	values[5]	138	1			T3	8		T8	24		T13	4
auto[1]	values[1]	values[6]	112	1			T31	5		T16	13		T178	9
auto[1]	values[1]	values[7]	241	1			T27	7		T170	16		T22	8
auto[1]	values[2]	values[0]	289	1			T32	11		T163	6		T141	11
auto[1]	values[2]	values[1]	153	1			T8	7		T18	12		T83	7
auto[1]	values[2]	values[2]	111	1			T83	11		T170	18		T177	12
auto[1]	values[2]	values[3]	310	1			T34	22		T159	10		T166	10
auto[1]	values[2]	values[4]	127	1			T8	7		T18	11		T167	13
auto[1]	values[2]	values[5]	104	1			T9	4		T159	5		T167	9
auto[1]	values[2]	values[6]	217	1			T8	11		T160	8		T229	12
auto[1]	values[2]	values[7]	100	1			T25	5		T163	10		T30	7
auto[1]	values[3]	values[0]	367	1			T15	11		T159	7		T83	9
auto[1]	values[3]	values[1]	99	1			T34	9		T83	8		T183	4
auto[1]	values[3]	values[2]	217	1			T25	10		T85	7		T20	12
auto[1]	values[3]	values[3]	120	1			T8	9		T230	14		T179	6
auto[1]	values[3]	values[4]	107	1			T31	5		T140	11		T217	4
auto[1]	values[3]	values[5]	172	1			T15	10		T34	11		T18	17
auto[1]	values[3]	values[6]	117	1			T31	10		T231	4		T20	6
auto[1]	values[3]	values[7]	148	1			T3	14		T8	11		T183	9
auto[1]	values[4]	values[0]	289	1			T18	11		T163	14		T218	10
auto[1]	values[4]	values[1]	318	1			T170	20		T219	14		T220	45
auto[1]	values[4]	values[2]	129	1			T34	5		T18	13		T159	4
auto[1]	values[4]	values[3]	188	1			T160	8		T166	10		T83	5
auto[1]	values[4]	values[4]	263	1			T7	12		T25	15		T180	3
auto[1]	values[4]	values[5]	377	1			T8	23		T16	10		T20	9
auto[1]	values[4]	values[6]	217	1			T16	5		T20	13		T83	11
auto[1]	values[4]	values[7]	303	1			T8	11		T15	55		T160	78
auto[1]	values[5]	values[0]	182	1			T7	11		T160	72		T167	10
auto[1]	values[5]	values[1]	294	1			T191	16		T167	8		T179	13
auto[1]	values[5]	values[2]	184	1			T7	11		T15	13		T32	12
auto[1]	values[5]	values[3]	253	1			T31	5		T20	8		T230	5
auto[1]	values[5]	values[4]	430	1			T7	12		T15	91		T16	9
auto[1]	values[5]	values[5]	116	1			T16	10		T194	9		T232	9
auto[1]	values[5]	values[6]	290	1			T183	7		T163	11		T30	8
auto[1]	values[5]	values[7]	237	1			T8	19		T25	7		T15	26
auto[1]	values[6]	values[0]	211	1			T16	18		T34	9		T159	6
auto[1]	values[6]	values[1]	139	1			T166	6		T167	10		T222	18
auto[1]	values[6]	values[2]	262	1			T31	72		T15	15		T140	12
auto[1]	values[6]	values[3]	252	1			T8	6		T160	10		T159	8
auto[1]	values[6]	values[4]	145	1			T16	12		T22	9		T179	14
auto[1]	values[6]	values[5]	230	1			T3	12		T83	6		T222	9
auto[1]	values[6]	values[6]	163	1			T25	15		T31	27		T169	18
auto[1]	values[6]	values[7]	200	1			T3	13		T27	13		T31	11
auto[1]	values[7]	values[0]	144	1			T27	7		T32	6		T183	11
auto[1]	values[7]	values[1]	168	1			T8	9		T16	8		T20	10
auto[1]	values[7]	values[2]	254	1			T7	2		T25	5		T27	7
auto[1]	values[7]	values[3]	235	1			T7	7		T185	8		T139	12
auto[1]	values[7]	values[4]	223	1			T31	11		T15	9		T160	64
auto[1]	values[7]	values[5]	210	1			T3	12		T16	9		T18	7
auto[1]	values[7]	values[6]	144	1			T31	25		T160	7		T167	9
auto[1]	values[7]	values[7]	64	1			T83	9		T139	15		T233	15