Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	400	1			T3	1		T7	3		T8	7
auto[ReadAddrCrossIntoMailbox]	316	1			T3	4		T7	2		T8	7
auto[ReadAddrCrossOutOfMailbox]	324	1			T3	2		T7	3		T8	2
auto[ReadAddrCrossAllMailbox]	241	1			T3	3		T7	4		T8	1
auto[ReadAddrOutsideMailbox]	3554	1			T3	12		T7	37		T8	36

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2381

1

T3

7

T7

29

T8

31

auto[1]

2454

1

T3

15

T7

20

T8

22

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	801	1			T3	4		T7	10		T8	10
read_ops[0x0b]	823	1			T3	4		T7	13		T8	11
read_ops[0x3b]	793	1			T3	1		T7	3		T8	7
read_ops[0x6b]	829	1			T3	4		T7	9		T8	13
read_ops[0xbb]	778	1			T3	3		T7	5		T8	6
read_ops[0xeb]	811	1			T3	6		T7	9		T8	6

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	35	1			T8	1		T190	1		T209	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	37	1			T8	2		T15	1		T190	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	29	1			T8	1		T31	1		T16	2
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	21	1			T8	1		T15	2		T34	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	33	1			T25	3		T27	1		T190	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	26	1			T15	2		T32	1		T190	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	24	1			T190	1		T185	1		T234	2
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T7	1		T15	3		T16	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	283	1			T3	1		T7	6		T8	2
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	294	1			T3	3		T7	3		T8	3
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	25	1			T8	1		T27	1		T20	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	33	1			T83	1		T167	1		T163	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	19	1			T8	1		T27	1		T16	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	32	1			T7	1		T8	1		T16	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	20	1			T27	1		T15	1		T18	2
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	24	1			T31	1		T16	1		T167	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T160	1		T20	3		T235	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	21	1			T3	2		T7	1		T159	2
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	285	1			T7	4		T8	4		T13	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	348	1			T3	2		T7	7		T8	4
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	28	1			T7	1		T8	1		T15	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	40	1			T25	2		T31	3		T159	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	25	1			T8	1		T15	2		T16	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	38	1			T3	1		T8	2		T159	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	24	1			T8	1		T25	1		T34	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	26	1			T15	1		T18	2		T159	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	23	1			T25	1		T34	1		T160	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	21	1			T27	1		T31	1		T18	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	292	1			T7	2		T8	1		T11	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	276	1			T8	1		T11	1		T13	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	31	1			T7	1		T8	1		T225	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	50	1			T225	1		T16	1		T34	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	31	1			T3	1		T27	1		T31	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	21	1			T3	2		T16	1		T166	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	26	1			T7	2		T8	1		T25	4
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	40	1			T31	1		T15	1		T16	2
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	21	1			T7	1		T15	1		T16	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	18	1			T25	1		T31	2		T32	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	295	1			T3	1		T7	3		T8	10
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	296	1			T7	2		T8	1		T31	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	29	1			T7	1		T27	1		T31	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	29	1			T8	1		T25	1		T27	2
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	27	1			T25	1		T16	1		T167	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	19	1			T20	1		T83	1		T183	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	26	1			T7	1		T25	1		T207	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	28	1			T3	1		T31	2		T207	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T8	1		T85	1		T218	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T3	1		T15	2		T34	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	301	1			T3	1		T7	1		T8	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	286	1			T7	2		T8	3		T25	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	33	1			T31	1		T16	3		T18	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	30	1			T3	1		T15	1		T34	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	25	1			T7	1		T27	1		T15	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	29	1			T160	1		T159	1		T83	2
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	25	1			T3	1		T160	1		T85	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	26	1			T27	1		T170	1		T22	3
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	22	1			T7	1		T27	1		T16	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	23	1			T15	1		T34	1		T159	2
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	311	1			T3	2		T7	4		T8	3
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	287	1			T3	2		T7	3		T8	3