Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4176	1			T3	24		T8	70		T25	50
values[1]	4246	1			T3	24		T7	50		T27	45
values[2]	3874	1			T3	40		T7	44		T8	58
values[3]	3960	1			T7	20		T8	40		T9	4
values[4]	4191	1			T8	20		T11	6		T84	10
values[5]	4067	1			T3	20		T7	71		T8	40
values[6]	3673	1			T3	20		T7	22		T8	53
values[7]	4226	1			T7	21		T8	48		T25	22

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4418	1			T7	30		T8	88		T84	10
values[1]	3496	1			T3	24		T7	47		T25	120
values[2]	4055	1			T3	20		T8	20		T25	20
values[3]	4189	1			T7	66		T8	33		T9	4
values[4]	4325	1			T3	40		T7	41		T8	70
values[5]	3996	1			T3	24		T7	20		T11	6
values[6]	4397	1			T8	58		T31	95		T16	68
values[7]	3537	1			T3	20		T7	24		T8	60

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31635

1

T3

127

T7

219

T8

318

auto[1]

778

1

T3

1

T7

9

T8

11

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	663	1			T8	48		T31	20		T18	21
auto[0]	values[0]	values[1]	316	1			T25	30		T197	70		T83	20
auto[0]	values[0]	values[2]	608	1			T25	20		T32	20		T160	22
auto[0]	values[0]	values[3]	396	1			T31	34		T164	16		T236	20
auto[0]	values[0]	values[4]	502	1			T8	18		T27	17		T205	12
auto[0]	values[0]	values[5]	329	1			T3	24		T209	8		T34	45
auto[0]	values[0]	values[6]	864	1			T16	22		T160	40		T159	19
auto[0]	values[0]	values[7]	401	1			T80	10		T30	20		T173	17
auto[0]	values[1]	values[0]	813	1			T7	25		T31	39		T34	31
auto[0]	values[1]	values[1]	402	1			T3	24		T18	20		T160	87
auto[0]	values[1]	values[2]	665	1			T27	24		T31	22		T48	10
auto[0]	values[1]	values[3]	405	1			T225	4		T32	21		T16	19
auto[0]	values[1]	values[4]	449	1			T16	21		T221	8		T159	18
auto[0]	values[1]	values[5]	566	1			T7	20		T27	21		T31	20
auto[0]	values[1]	values[6]	415	1			T18	20		T166	23		T20	19
auto[0]	values[1]	values[7]	434	1			T15	63		T145	20		T218	27
auto[0]	values[2]	values[0]	597	1			T16	19		T78	4		T237	16
auto[0]	values[2]	values[1]	207	1			T185	21		T159	20		T170	18
auto[0]	values[2]	values[2]	680	1			T15	104		T160	82		T188	8
auto[0]	values[2]	values[3]	416	1			T7	42		T227	16		T18	20
auto[0]	values[2]	values[4]	699	1			T3	19		T8	20		T34	26
auto[0]	values[2]	values[5]	439	1			T15	20		T83	38		T238	6
auto[0]	values[2]	values[6]	392	1			T8	36		T16	25		T187	20
auto[0]	values[2]	values[7]	338	1			T3	20		T190	8		T34	20
auto[0]	values[3]	values[0]	557	1			T8	20		T15	19		T32	20
auto[0]	values[3]	values[1]	472	1			T25	22		T20	43		T145	23
auto[0]	values[3]	values[2]	351	1			T31	20		T183	21		T29	86
auto[0]	values[3]	values[3]	480	1			T9	2		T13	4		T20	23
auto[0]	values[3]	values[4]	441	1			T7	20		T32	21		T182	18
auto[0]	values[3]	values[5]	450	1			T146	20		T16	20		T34	18
auto[0]	values[3]	values[6]	727	1			T31	20		T239	73		T167	19
auto[0]	values[3]	values[7]	395	1			T8	20		T15	33		T83	20
auto[0]	values[4]	values[0]	497	1			T84	10		T27	20		T31	28
auto[0]	values[4]	values[1]	438	1			T34	28		T240	19		T241	4
auto[0]	values[4]	values[2]	497	1			T34	20		T185	20		T242	4
auto[0]	values[4]	values[3]	472	1			T31	20		T180	20		T160	77
auto[0]	values[4]	values[4]	489	1			T15	108		T213	8		T166	26
auto[0]	values[4]	values[5]	651	1			T11	6		T79	12		T83	18
auto[0]	values[4]	values[6]	588	1			T8	20		T201	75		T140	19
auto[0]	values[4]	values[7]	446	1			T15	23		T169	18		T34	20
auto[0]	values[5]	values[0]	274	1			T18	30		T160	20		T166	23
auto[0]	values[5]	values[1]	487	1			T7	46		T25	20		T31	16
auto[0]	values[5]	values[2]	456	1			T31	51		T16	19		T166	20
auto[0]	values[5]	values[3]	693	1			T20	18		T218	48		T141	27
auto[0]	values[5]	values[4]	507	1			T3	20		T25	25		T15	20
auto[0]	values[5]	values[5]	598	1			T81	16		T22	50		T230	20
auto[0]	values[5]	values[6]	362	1			T215	22		T200	18		T22	18
auto[0]	values[5]	values[7]	583	1			T7	24		T8	40		T16	20
auto[0]	values[6]	values[0]	474	1			T243	10		T20	56		T201	58
auto[0]	values[6]	values[1]	470	1			T25	21		T16	23		T18	20
auto[0]	values[6]	values[2]	340	1			T3	20		T8	18		T160	20
auto[0]	values[6]	values[3]	675	1			T7	22		T8	33		T25	20
auto[0]	values[6]	values[4]	532	1			T18	21		T207	6		T83	19
auto[0]	values[6]	values[5]	246	1			T16	19		T34	27		T83	20
auto[0]	values[6]	values[6]	503	1			T16	20		T34	20		T170	26
auto[0]	values[6]	values[7]	353	1			T15	20		T160	18		T210	10
auto[0]	values[7]	values[0]	444	1			T8	20		T15	20		T34	20
auto[0]	values[7]	values[1]	624	1			T25	22		T159	20		T83	20
auto[0]	values[7]	values[2]	380	1			T234	14		T218	20		T30	37
auto[0]	values[7]	values[3]	548	1			T203	8		T16	41		T167	19
auto[0]	values[7]	values[4]	592	1			T7	20		T8	25		T16	48
auto[0]	values[7]	values[5]	625	1			T216	2		T159	17		T179	20
auto[0]	values[7]	values[6]	431	1			T31	75		T185	20		T187	20
auto[0]	values[7]	values[7]	491	1			T35	8		T176	12		T29	20
auto[1]	values[0]	values[0]	18	1			T18	1		T85	4		T145	1
auto[1]	values[0]	values[1]	5	1			T167	1		T139	1		T244	1
auto[1]	values[0]	values[2]	12	1			T160	1		T170	2		T230	2
auto[1]	values[0]	values[3]	6	1			T43	6		-	-		-	-
auto[1]	values[0]	values[4]	15	1			T8	4		T27	3		T205	2
auto[1]	values[0]	values[5]	6	1			T245	3		T246	1		T247	2
auto[1]	values[0]	values[6]	21	1			T16	1		T159	1		T170	3
auto[1]	values[0]	values[7]	14	1			T173	3		T141	4		T236	1
auto[1]	values[1]	values[0]	18	1			T7	5		T31	1		T34	3
auto[1]	values[1]	values[1]	5	1			T219	2		T248	3		-	-
auto[1]	values[1]	values[2]	16	1			T31	1		T222	3		T249	2
auto[1]	values[1]	values[3]	7	1			T16	1		T191	2		T159	1
auto[1]	values[1]	values[4]	16	1			T159	2		T173	2		T219	2
auto[1]	values[1]	values[5]	11	1			T163	1		T145	1		T173	1
auto[1]	values[1]	values[6]	9	1			T166	1		T20	1		T250	2
auto[1]	values[1]	values[7]	15	1			T15	2		T177	1		T30	3
auto[1]	values[2]	values[0]	12	1			T16	2		T42	2		T244	3
auto[1]	values[2]	values[1]	6	1			T185	1		T170	2		T222	1
auto[1]	values[2]	values[2]	10	1			T15	3		T160	1		T235	1
auto[1]	values[2]	values[3]	11	1			T7	2		T18	1		T170	1
auto[1]	values[2]	values[4]	20	1			T3	1		T179	1		T251	1
auto[1]	values[2]	values[5]	14	1			T83	2		T178	2		T236	2
auto[1]	values[2]	values[6]	20	1			T8	2		T29	1		T163	5
auto[1]	values[2]	values[7]	13	1			T20	3		T252	4		T139	2
auto[1]	values[3]	values[0]	6	1			T15	1		T235	1		T253	2
auto[1]	values[3]	values[1]	12	1			T25	1		T20	1		T145	1
auto[1]	values[3]	values[2]	7	1			T183	1		T172	1		T222	1
auto[1]	values[3]	values[3]	8	1			T9	2		T139	2		T220	1
auto[1]	values[3]	values[4]	7	1			T249	2		T244	3		T254	2
auto[1]	values[3]	values[5]	15	1			T34	2		T170	2		T179	1
auto[1]	values[3]	values[6]	22	1			T167	1		T22	3		T235	1
auto[1]	values[3]	values[7]	10	1			T235	1		T141	1		T120	2
auto[1]	values[4]	values[0]	17	1			T27	2		T31	1		T20	2
auto[1]	values[4]	values[1]	9	1			T179	1		T229	2		T145	1
auto[1]	values[4]	values[2]	3	1			T236	3		-	-		-	-
auto[1]	values[4]	values[3]	15	1			T20	2		T163	1		T173	1
auto[1]	values[4]	values[4]	13	1			T15	2		T183	3		T179	1
auto[1]	values[4]	values[5]	18	1			T83	2		T163	3		T139	1
auto[1]	values[4]	values[6]	20	1			T201	4		T140	1		T220	3
auto[1]	values[4]	values[7]	18	1			T15	1		T83	2		T167	2
auto[1]	values[5]	values[0]	13	1			T18	2		T255	5		T256	2
auto[1]	values[5]	values[1]	21	1			T7	1		T25	1		T31	4
auto[1]	values[5]	values[2]	8	1			T16	1		T22	1		T222	1
auto[1]	values[5]	values[3]	30	1			T20	2		T218	2		T195	2
auto[1]	values[5]	values[4]	10	1			T25	1		T201	2		T257	2
auto[1]	values[5]	values[5]	8	1			T22	1		T140	2		T245	1
auto[1]	values[5]	values[6]	8	1			T22	3		T179	1		T258	2
auto[1]	values[5]	values[7]	9	1			T140	2		T259	5		T260	2
auto[1]	values[6]	values[0]	9	1			T20	1		T201	1		T140	1
auto[1]	values[6]	values[1]	8	1			T25	3		T29	1		T178	1
auto[1]	values[6]	values[2]	12	1			T8	2		T167	1		T168	2
auto[1]	values[6]	values[3]	15	1			T25	3		T222	3		T177	1
auto[1]	values[6]	values[4]	13	1			T83	1		T201	1		T245	1
auto[1]	values[6]	values[5]	6	1			T16	1		T143	1		T261	3
auto[1]	values[6]	values[6]	9	1			T262	2		T263	1		T264	1
auto[1]	values[6]	values[7]	8	1			T160	2		T170	1		T230	1
auto[1]	values[7]	values[0]	6	1			T20	1		T145	1		T265	2
auto[1]	values[7]	values[1]	14	1			T170	2		T167	5		T140	1
auto[1]	values[7]	values[2]	10	1			T30	4		T141	2		T253	2
auto[1]	values[7]	values[3]	12	1			T16	2		T167	1		T235	3
auto[1]	values[7]	values[4]	20	1			T7	1		T8	3		T16	3
auto[1]	values[7]	values[5]	14	1			T159	3		T249	1		T233	4
auto[1]	values[7]	values[6]	6	1			T139	2		T173	1		T232	2
auto[1]	values[7]	values[7]	9	1			T172	2		T30	2		T42	1