Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	792	1			T14	14		T15	24		T16	7
all_values[1]	792	1			T14	14		T15	24		T16	7
all_values[2]	792	1			T14	14		T15	24		T16	7
all_values[3]	792	1			T14	14		T15	24		T16	7
all_values[4]	792	1			T14	14		T15	24		T16	7
all_values[5]	792	1			T14	14		T15	24		T16	7
all_values[6]	792	1			T14	14		T15	24		T16	7
all_values[7]	792	1			T14	14		T15	24		T16	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3357

1

T14

49

T15

107

T16

27

auto[1]

2979

1

T14

63

T15

85

T16

29

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2494

1

T14

35

T15

89

T16

24

auto[1]

3842

1

T14

77

T15

103

T16

32

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3598

1

T14

60

T15

118

T16

32

auto[1]

2738

1

T14

52

T15

74

T16

24

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	153	1			T14	4		T15	8		T16	2
all_values[0]	auto[0]	auto[0]	auto[1]	76	1			T14	2		T17	1		T18	4
all_values[0]	auto[0]	auto[1]	auto[0]	144	1			T14	4		T15	8		T16	1
all_values[0]	auto[0]	auto[1]	auto[1]	73	1			T15	3		T16	1		T145	4
all_values[0]	auto[1]	auto[0]	auto[1]	186	1			T14	1		T15	1		T17	2
all_values[0]	auto[1]	auto[1]	auto[1]	160	1			T14	3		T15	4		T16	3
all_values[1]	auto[0]	auto[0]	auto[0]	151	1			T14	1		T15	8		T16	3
all_values[1]	auto[0]	auto[0]	auto[1]	80	1			T14	1		T15	3		T18	2
all_values[1]	auto[0]	auto[1]	auto[0]	114	1			T15	5		T16	2		T17	3
all_values[1]	auto[0]	auto[1]	auto[1]	97	1			T14	3		T17	1		T18	2
all_values[1]	auto[1]	auto[0]	auto[1]	208	1			T14	2		T15	3		T17	2
all_values[1]	auto[1]	auto[1]	auto[1]	142	1			T14	7		T15	5		T16	2
all_values[2]	auto[0]	auto[0]	auto[0]	143	1			T15	8		T17	1		T18	7
all_values[2]	auto[0]	auto[0]	auto[1]	102	1			T14	2		T15	4		T17	2
all_values[2]	auto[0]	auto[1]	auto[0]	132	1			T14	3		T15	2		T16	4
all_values[2]	auto[0]	auto[1]	auto[1]	77	1			T14	2		T15	1		T22	2
all_values[2]	auto[1]	auto[0]	auto[1]	183	1			T14	1		T15	5		T16	3
all_values[2]	auto[1]	auto[1]	auto[1]	155	1			T14	6		T15	4		T17	1
all_values[3]	auto[0]	auto[0]	auto[0]	175	1			T14	5		T15	5		T16	1
all_values[3]	auto[0]	auto[0]	auto[1]	76	1			T14	1		T15	3		T18	4
all_values[3]	auto[0]	auto[1]	auto[0]	140	1			T14	1		T15	6		T16	1
all_values[3]	auto[0]	auto[1]	auto[1]	80	1			T14	2		T15	1		T17	1
all_values[3]	auto[1]	auto[0]	auto[1]	169	1			T14	2		T15	9		T16	1
all_values[3]	auto[1]	auto[1]	auto[1]	152	1			T14	3		T16	4		T17	2
all_values[4]	auto[0]	auto[0]	auto[0]	163	1			T14	4		T15	4		T16	1
all_values[4]	auto[0]	auto[0]	auto[1]	80	1			T14	1		T15	3		T18	2
all_values[4]	auto[0]	auto[1]	auto[0]	146	1			T15	7		T16	3		T17	2
all_values[4]	auto[0]	auto[1]	auto[1]	59	1			T14	2		T15	1		T16	1
all_values[4]	auto[1]	auto[0]	auto[1]	177	1			T14	4		T15	4		T17	1
all_values[4]	auto[1]	auto[1]	auto[1]	167	1			T14	3		T15	5		T16	2
all_values[5]	auto[0]	auto[0]	auto[0]	231	1			T14	1		T15	3		T16	5
all_values[5]	auto[0]	auto[1]	auto[0]	212	1			T14	6		T15	4		T17	2
all_values[5]	auto[1]	auto[0]	auto[1]	179	1			T14	4		T15	12		T16	1
all_values[5]	auto[1]	auto[1]	auto[1]	170	1			T14	3		T15	5		T16	1
all_values[6]	auto[0]	auto[0]	auto[0]	157	1			T14	1		T15	4		T17	1
all_values[6]	auto[0]	auto[0]	auto[1]	68	1			T14	1		T15	3		T16	1
all_values[6]	auto[0]	auto[1]	auto[0]	142	1			T14	4		T15	5		T18	2
all_values[6]	auto[0]	auto[1]	auto[1]	76	1			T14	2		T15	3		T16	1
all_values[6]	auto[1]	auto[0]	auto[1]	188	1			T14	4		T15	3		T16	5
all_values[6]	auto[1]	auto[1]	auto[1]	161	1			T14	2		T15	6		T17	2
all_values[7]	auto[0]	auto[0]	auto[0]	146	1			T14	1		T15	8		T18	3
all_values[7]	auto[0]	auto[0]	auto[1]	75	1			T14	2		T15	1		T16	3
all_values[7]	auto[0]	auto[1]	auto[0]	145	1			T15	4		T16	1		T18	7
all_values[7]	auto[0]	auto[1]	auto[1]	85	1			T14	4		T15	3		T16	1
all_values[7]	auto[1]	auto[0]	auto[1]	191	1			T14	4		T15	5		T16	1
all_values[7]	auto[1]	auto[1]	auto[1]	150	1			T14	3		T15	3		T16	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal