Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1718

1

T1

1

T3

18

T6

15

auto[1]

1733

1

T3

13

T6

17

T7

11

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2049

1

T3

27

T7

18

T8

9

auto[1]

1402

1

T1

1

T3

4

T6

32

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2645

1

T1

1

T3

22

T6

32

auto[1]

806

1

T3

9

T7

6

T8

5

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	655	1			T1	1		T3	4		T6	4
valid[1]	720	1			T3	4		T6	6		T7	5
valid[2]	677	1			T3	5		T6	7		T7	5
valid[3]	702	1			T3	8		T6	6		T7	2
valid[4]	697	1			T3	10		T6	9		T7	6

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	117	1			T7	3		T25	1		T14	1
auto[0]	auto[0]	valid[0]	auto[1]	129	1			T1	1		T3	1		T6	4
auto[0]	auto[0]	valid[1]	auto[0]	107	1			T3	2		T7	1		T28	1
auto[0]	auto[0]	valid[1]	auto[1]	166	1			T6	3		T7	1		T24	3
auto[0]	auto[0]	valid[2]	auto[0]	114	1			T3	3		T8	2		T28	1
auto[0]	auto[0]	valid[2]	auto[1]	150	1			T6	4		T24	4		T290	1
auto[0]	auto[0]	valid[3]	auto[0]	117	1			T3	2		T7	2		T27	1
auto[0]	auto[0]	valid[3]	auto[1]	154	1			T6	3		T291	1		T292	2
auto[0]	auto[0]	valid[4]	auto[0]	137	1			T3	4		T8	1		T23	1
auto[0]	auto[0]	valid[4]	auto[1]	112	1			T3	2		T6	1		T7	1
auto[0]	auto[1]	valid[0]	auto[0]	129	1			T3	1		T25	2		T27	2
auto[0]	auto[1]	valid[0]	auto[1]	127	1			T7	1		T8	1		T24	2
auto[0]	auto[1]	valid[1]	auto[0]	133	1			T3	2		T7	1		T8	1
auto[0]	auto[1]	valid[1]	auto[1]	151	1			T6	3		T24	1		T25	1
auto[0]	auto[1]	valid[2]	auto[0]	134	1			T3	1		T7	2		T27	1
auto[0]	auto[1]	valid[2]	auto[1]	127	1			T6	3		T8	1		T24	1
auto[0]	auto[1]	valid[3]	auto[0]	119	1			T3	2		T28	1		T14	2
auto[0]	auto[1]	valid[3]	auto[1]	147	1			T6	3		T8	1		T24	4
auto[0]	auto[1]	valid[4]	auto[0]	136	1			T3	1		T7	3		T25	1
auto[0]	auto[1]	valid[4]	auto[1]	139	1			T3	1		T6	8		T7	1
auto[1]	auto[0]	valid[0]	auto[0]	78	1			T3	1		T8	1		T14	2
auto[1]	auto[0]	valid[1]	auto[0]	92	1			T7	2		T26	1		T27	1
auto[1]	auto[0]	valid[2]	auto[0]	90	1			T3	1		T7	1		T25	1
auto[1]	auto[0]	valid[3]	auto[0]	75	1			T3	1		T8	1		T23	1
auto[1]	auto[0]	valid[4]	auto[0]	80	1			T3	1		T27	1		T14	1
auto[1]	auto[1]	valid[0]	auto[0]	75	1			T3	1		T8	1		T26	1
auto[1]	auto[1]	valid[1]	auto[0]	71	1			T25	1		T14	1		T36	1
auto[1]	auto[1]	valid[2]	auto[0]	62	1			T7	2		T18	1		T186	2
auto[1]	auto[1]	valid[3]	auto[0]	90	1			T3	3		T8	2		T14	2
auto[1]	auto[1]	valid[4]	auto[0]	93	1			T3	1		T7	1		T27	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal