Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

51513

1

T3

731

T7

374

T8

180

auto[1]

16248

1

T1

1

T3

35

T6

420

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48834

1

T1

1

T3

508

T6

420

auto[1]

18927

1

T3

258

T7

150

T8

83

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	34710	1			T1	1		T3	379		T6	202
others[1]	5661	1			T3	61		T6	47		T7	41
others[2]	5783	1			T3	63		T6	32		T7	33
others[3]	6564	1			T3	62		T6	47		T7	42
interest[1]	3827	1			T3	48		T6	28		T7	35
interest[4]	22558	1			T1	1		T3	254		T6	139
interest[64]	11216	1			T3	153		T6	64		T7	70

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	16562	1			T3	225		T7	117		T8	43
auto[0]	auto[0]	others[1]	2737	1			T3	47		T7	18		T8	7
auto[0]	auto[0]	others[2]	2844	1			T3	33		T7	16		T8	12
auto[0]	auto[0]	others[3]	3181	1			T3	32		T7	25		T8	17
auto[0]	auto[0]	interest[1]	1823	1			T3	37		T7	18		T8	6
auto[0]	auto[0]	interest[4]	10677	1			T3	155		T7	73		T8	20
auto[0]	auto[0]	interest[64]	5439	1			T3	99		T7	30		T8	12
auto[0]	auto[1]	others[0]	8407	1			T1	1		T3	17		T6	202
auto[0]	auto[1]	others[1]	1358	1			T3	2		T6	47		T7	6
auto[0]	auto[1]	others[2]	1332	1			T3	2		T6	32		T7	6
auto[0]	auto[1]	others[3]	1567	1			T3	6		T6	47		T7	5
auto[0]	auto[1]	interest[1]	945	1			T3	1		T6	28		T7	6
auto[0]	auto[1]	interest[4]	5562	1			T1	1		T3	14		T6	139
auto[0]	auto[1]	interest[64]	2639	1			T3	7		T6	64		T7	12
auto[1]	auto[0]	others[0]	9741	1			T3	137		T7	71		T8	49
auto[1]	auto[0]	others[1]	1566	1			T3	12		T7	17		T8	7
auto[1]	auto[0]	others[2]	1607	1			T3	28		T7	11		T8	7
auto[1]	auto[0]	others[3]	1816	1			T3	24		T7	12		T8	7
auto[1]	auto[0]	interest[1]	1059	1			T3	10		T7	11		T8	4
auto[1]	auto[0]	interest[4]	6319	1			T3	85		T7	49		T8	33
auto[1]	auto[0]	interest[64]	3138	1			T3	47		T7	28		T8	9

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal