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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.04 98.38 93.99 98.62 89.36 97.19 95.45 99.26


Total test records in report: 1130
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html
T1031 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.861910081 Jul 26 05:31:37 PM PDT 24 Jul 26 05:31:41 PM PDT 24 117032867 ps
T1032 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.563108694 Jul 26 05:31:57 PM PDT 24 Jul 26 05:32:01 PM PDT 24 61169720 ps
T96 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.3011702226 Jul 26 05:31:40 PM PDT 24 Jul 26 05:31:44 PM PDT 24 920147489 ps
T1033 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.1802681374 Jul 26 05:31:57 PM PDT 24 Jul 26 05:31:58 PM PDT 24 32714473 ps
T1034 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.1954615003 Jul 26 05:31:56 PM PDT 24 Jul 26 05:31:57 PM PDT 24 41259692 ps
T1035 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3157997708 Jul 26 05:31:39 PM PDT 24 Jul 26 05:31:41 PM PDT 24 186791085 ps
T1036 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.1618544156 Jul 26 05:31:54 PM PDT 24 Jul 26 05:31:55 PM PDT 24 35082721 ps
T136 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.3996416360 Jul 26 05:31:39 PM PDT 24 Jul 26 05:31:43 PM PDT 24 150772121 ps
T1037 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.1336753791 Jul 26 05:31:56 PM PDT 24 Jul 26 05:31:57 PM PDT 24 24048941 ps
T98 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3514372170 Jul 26 05:31:53 PM PDT 24 Jul 26 05:31:56 PM PDT 24 43005441 ps
T92 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.749308035 Jul 26 05:31:42 PM PDT 24 Jul 26 05:31:45 PM PDT 24 70652467 ps
T100 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.4150109960 Jul 26 05:31:54 PM PDT 24 Jul 26 05:31:57 PM PDT 24 207442821 ps
T1038 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.3728837561 Jul 26 05:31:59 PM PDT 24 Jul 26 05:32:00 PM PDT 24 22395014 ps
T115 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.1653428101 Jul 26 05:31:29 PM PDT 24 Jul 26 05:31:31 PM PDT 24 29401272 ps
T94 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.874786339 Jul 26 05:31:53 PM PDT 24 Jul 26 05:31:56 PM PDT 24 393933921 ps
T1039 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.1171876566 Jul 26 05:31:38 PM PDT 24 Jul 26 05:31:41 PM PDT 24 67603689 ps
T155 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.2624962665 Jul 26 05:31:55 PM PDT 24 Jul 26 05:32:09 PM PDT 24 197894595 ps
T1040 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.31331645 Jul 26 05:31:54 PM PDT 24 Jul 26 05:31:55 PM PDT 24 39034089 ps
T151 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2621711932 Jul 26 05:31:39 PM PDT 24 Jul 26 05:31:51 PM PDT 24 763977990 ps
T1041 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.2705639316 Jul 26 05:31:40 PM PDT 24 Jul 26 05:31:41 PM PDT 24 36110366 ps
T101 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.3078314239 Jul 26 05:31:52 PM PDT 24 Jul 26 05:31:54 PM PDT 24 206913286 ps
T1042 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.2176846919 Jul 26 05:31:54 PM PDT 24 Jul 26 05:31:55 PM PDT 24 153967387 ps
T1043 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1706069583 Jul 26 05:31:55 PM PDT 24 Jul 26 05:31:57 PM PDT 24 462125499 ps
T116 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.2828723693 Jul 26 05:31:53 PM PDT 24 Jul 26 05:31:55 PM PDT 24 126387886 ps
T137 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1226091260 Jul 26 05:31:51 PM PDT 24 Jul 26 05:31:55 PM PDT 24 166429622 ps
T93 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.2609764532 Jul 26 05:31:41 PM PDT 24 Jul 26 05:31:45 PM PDT 24 249949743 ps
T1044 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.1937213762 Jul 26 05:31:52 PM PDT 24 Jul 26 05:31:55 PM PDT 24 805735635 ps
T117 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.2027812191 Jul 26 05:31:49 PM PDT 24 Jul 26 05:31:52 PM PDT 24 242470127 ps
T118 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.2261180037 Jul 26 05:31:42 PM PDT 24 Jul 26 05:32:07 PM PDT 24 1817117018 ps
T1045 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.3485100663 Jul 26 05:31:30 PM PDT 24 Jul 26 05:31:31 PM PDT 24 11579430 ps
T1046 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1784629025 Jul 26 05:31:41 PM PDT 24 Jul 26 05:31:43 PM PDT 24 23598621 ps
T1047 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.2940578747 Jul 26 05:31:41 PM PDT 24 Jul 26 05:31:42 PM PDT 24 22801764 ps
T119 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.3663002435 Jul 26 05:31:42 PM PDT 24 Jul 26 05:31:57 PM PDT 24 413614179 ps
T1048 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2264389725 Jul 26 05:31:55 PM PDT 24 Jul 26 05:32:00 PM PDT 24 316762200 ps
T1049 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.127177403 Jul 26 05:31:59 PM PDT 24 Jul 26 05:32:00 PM PDT 24 31255386 ps
T152 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.3923587562 Jul 26 05:31:35 PM PDT 24 Jul 26 05:31:41 PM PDT 24 209342695 ps
T1050 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.2576770608 Jul 26 05:31:38 PM PDT 24 Jul 26 05:31:39 PM PDT 24 41886502 ps
T1051 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3762871562 Jul 26 05:31:50 PM PDT 24 Jul 26 05:31:54 PM PDT 24 239594416 ps
T156 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.4173148753 Jul 26 05:31:56 PM PDT 24 Jul 26 05:32:03 PM PDT 24 442855401 ps
T1052 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3967119435 Jul 26 05:31:30 PM PDT 24 Jul 26 05:31:33 PM PDT 24 82873203 ps
T76 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1948201396 Jul 26 05:31:41 PM PDT 24 Jul 26 05:31:43 PM PDT 24 100715128 ps
T1053 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2681131992 Jul 26 05:31:39 PM PDT 24 Jul 26 05:31:43 PM PDT 24 58336845 ps
T138 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.196881878 Jul 26 05:31:41 PM PDT 24 Jul 26 05:32:03 PM PDT 24 12923888761 ps
T1054 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.4032421540 Jul 26 05:31:27 PM PDT 24 Jul 26 05:31:28 PM PDT 24 29926872 ps
T1055 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.3903309770 Jul 26 05:31:44 PM PDT 24 Jul 26 05:31:45 PM PDT 24 109506189 ps
T1056 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1549581504 Jul 26 05:31:56 PM PDT 24 Jul 26 05:31:57 PM PDT 24 14388724 ps
T1057 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.1991899849 Jul 26 05:31:27 PM PDT 24 Jul 26 05:31:27 PM PDT 24 10888919 ps
T95 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.3564139539 Jul 26 05:31:51 PM PDT 24 Jul 26 05:31:53 PM PDT 24 108193860 ps
T157 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.139039008 Jul 26 05:31:56 PM PDT 24 Jul 26 05:32:16 PM PDT 24 8865696512 ps
T102 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.525244170 Jul 26 05:31:35 PM PDT 24 Jul 26 05:31:40 PM PDT 24 250146967 ps
T1058 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3146580075 Jul 26 05:31:52 PM PDT 24 Jul 26 05:31:54 PM PDT 24 73426950 ps
T1059 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3678011876 Jul 26 05:31:38 PM PDT 24 Jul 26 05:31:41 PM PDT 24 41737410 ps
T1060 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.3329791423 Jul 26 05:31:53 PM PDT 24 Jul 26 05:31:53 PM PDT 24 12719925 ps
T149 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.877183014 Jul 26 05:31:56 PM PDT 24 Jul 26 05:32:18 PM PDT 24 1007082817 ps
T1061 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.811095368 Jul 26 05:31:56 PM PDT 24 Jul 26 05:31:58 PM PDT 24 55819266 ps
T1062 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.1494153816 Jul 26 05:31:53 PM PDT 24 Jul 26 05:31:55 PM PDT 24 77606277 ps
T1063 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.3237786707 Jul 26 05:31:40 PM PDT 24 Jul 26 05:31:42 PM PDT 24 239981497 ps
T1064 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.3517276370 Jul 26 05:31:42 PM PDT 24 Jul 26 05:31:45 PM PDT 24 53767462 ps
T1065 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2252595398 Jul 26 05:31:28 PM PDT 24 Jul 26 05:31:31 PM PDT 24 446368100 ps
T1066 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.2368454742 Jul 26 05:31:58 PM PDT 24 Jul 26 05:31:59 PM PDT 24 39171396 ps
T1067 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3592001564 Jul 26 05:31:53 PM PDT 24 Jul 26 05:31:54 PM PDT 24 11867171 ps
T1068 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.4109066807 Jul 26 05:31:41 PM PDT 24 Jul 26 05:31:44 PM PDT 24 327127248 ps
T147 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.2449348098 Jul 26 05:31:37 PM PDT 24 Jul 26 05:31:41 PM PDT 24 185442905 ps
T1069 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.4247058307 Jul 26 05:31:25 PM PDT 24 Jul 26 05:31:27 PM PDT 24 221399681 ps
T1070 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1944278178 Jul 26 05:31:41 PM PDT 24 Jul 26 05:31:42 PM PDT 24 11974585 ps
T153 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.762220000 Jul 26 05:31:38 PM PDT 24 Jul 26 05:31:54 PM PDT 24 4618368908 ps
T1071 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.2616152623 Jul 26 05:31:54 PM PDT 24 Jul 26 05:31:55 PM PDT 24 54600545 ps
T1072 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.4043062780 Jul 26 05:31:55 PM PDT 24 Jul 26 05:31:57 PM PDT 24 124274504 ps
T1073 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1117661715 Jul 26 05:31:55 PM PDT 24 Jul 26 05:31:57 PM PDT 24 70317291 ps
T1074 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.757754461 Jul 26 05:31:41 PM PDT 24 Jul 26 05:31:45 PM PDT 24 62226034 ps
T1075 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1363127512 Jul 26 05:31:39 PM PDT 24 Jul 26 05:31:40 PM PDT 24 52010763 ps
T1076 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.996755863 Jul 26 05:31:52 PM PDT 24 Jul 26 05:31:56 PM PDT 24 598919859 ps
T1077 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.828022581 Jul 26 05:31:45 PM PDT 24 Jul 26 05:31:47 PM PDT 24 99393704 ps
T1078 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.2912081692 Jul 26 05:31:40 PM PDT 24 Jul 26 05:31:42 PM PDT 24 44165565 ps
T1079 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.3087515615 Jul 26 05:31:54 PM PDT 24 Jul 26 05:31:55 PM PDT 24 11382057 ps
T1080 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.637820814 Jul 26 05:31:43 PM PDT 24 Jul 26 05:31:45 PM PDT 24 206979553 ps
T1081 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1442580069 Jul 26 05:31:39 PM PDT 24 Jul 26 05:31:41 PM PDT 24 23245604 ps
T1082 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3117404402 Jul 26 05:31:41 PM PDT 24 Jul 26 05:31:46 PM PDT 24 197357540 ps
T1083 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1453521668 Jul 26 05:31:51 PM PDT 24 Jul 26 05:31:52 PM PDT 24 69540843 ps
T1084 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2488301897 Jul 26 05:31:39 PM PDT 24 Jul 26 05:31:41 PM PDT 24 84535109 ps
T1085 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.837865511 Jul 26 05:31:56 PM PDT 24 Jul 26 05:31:57 PM PDT 24 21912517 ps
T1086 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3014940176 Jul 26 05:31:35 PM PDT 24 Jul 26 05:31:37 PM PDT 24 279500226 ps
T1087 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2526332736 Jul 26 05:31:51 PM PDT 24 Jul 26 05:31:53 PM PDT 24 81484296 ps
T1088 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.3399675789 Jul 26 05:31:59 PM PDT 24 Jul 26 05:32:00 PM PDT 24 41857769 ps
T150 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.2393003199 Jul 26 05:31:40 PM PDT 24 Jul 26 05:31:55 PM PDT 24 1218987709 ps
T154 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.2894777509 Jul 26 05:31:47 PM PDT 24 Jul 26 05:32:09 PM PDT 24 3264601961 ps
T1089 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.639549433 Jul 26 05:31:41 PM PDT 24 Jul 26 05:31:43 PM PDT 24 58465288 ps
T1090 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.2657161627 Jul 26 05:31:53 PM PDT 24 Jul 26 05:31:54 PM PDT 24 27208606 ps
T1091 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.1131069703 Jul 26 05:31:53 PM PDT 24 Jul 26 05:31:54 PM PDT 24 15766008 ps
T1092 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.2213357131 Jul 26 05:31:59 PM PDT 24 Jul 26 05:32:00 PM PDT 24 17710468 ps
T1093 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.2192568375 Jul 26 05:31:49 PM PDT 24 Jul 26 05:31:50 PM PDT 24 13893624 ps
T1094 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.2438664998 Jul 26 05:31:51 PM PDT 24 Jul 26 05:31:58 PM PDT 24 109727098 ps
T148 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.1227134766 Jul 26 05:31:28 PM PDT 24 Jul 26 05:31:34 PM PDT 24 416428428 ps
T1095 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.1398951836 Jul 26 05:31:29 PM PDT 24 Jul 26 05:31:33 PM PDT 24 688117290 ps
T1096 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.1727587519 Jul 26 05:31:40 PM PDT 24 Jul 26 05:31:40 PM PDT 24 61842105 ps
T77 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2369161026 Jul 26 05:31:28 PM PDT 24 Jul 26 05:31:30 PM PDT 24 159461934 ps
T1097 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.605146816 Jul 26 05:31:39 PM PDT 24 Jul 26 05:31:48 PM PDT 24 385528179 ps
T1098 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.1921283462 Jul 26 05:31:41 PM PDT 24 Jul 26 05:31:44 PM PDT 24 425133722 ps
T1099 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.4288148888 Jul 26 05:31:52 PM PDT 24 Jul 26 05:31:55 PM PDT 24 401146948 ps
T1100 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.641027554 Jul 26 05:31:43 PM PDT 24 Jul 26 05:31:44 PM PDT 24 15401230 ps
T1101 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.246472349 Jul 26 05:31:55 PM PDT 24 Jul 26 05:31:56 PM PDT 24 35384121 ps
T1102 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.1183453705 Jul 26 05:31:51 PM PDT 24 Jul 26 05:31:53 PM PDT 24 29312275 ps
T1103 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.3086846713 Jul 26 05:31:50 PM PDT 24 Jul 26 05:31:51 PM PDT 24 39052871 ps
T1104 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.2697192405 Jul 26 05:31:41 PM PDT 24 Jul 26 05:31:44 PM PDT 24 379447015 ps
T1105 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2469972004 Jul 26 05:31:51 PM PDT 24 Jul 26 05:31:52 PM PDT 24 15470351 ps
T1106 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3639668250 Jul 26 05:31:58 PM PDT 24 Jul 26 05:32:02 PM PDT 24 620631743 ps
T1107 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.8866729 Jul 26 05:31:53 PM PDT 24 Jul 26 05:31:54 PM PDT 24 14973962 ps
T1108 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.3807673202 Jul 26 05:31:43 PM PDT 24 Jul 26 05:31:47 PM PDT 24 197610042 ps
T1109 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.2047439501 Jul 26 05:31:58 PM PDT 24 Jul 26 05:31:59 PM PDT 24 84546887 ps
T1110 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.3105650415 Jul 26 05:31:55 PM PDT 24 Jul 26 05:31:58 PM PDT 24 113750737 ps
T1111 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.4177076900 Jul 26 05:31:40 PM PDT 24 Jul 26 05:31:56 PM PDT 24 1489265375 ps
T1112 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.13759929 Jul 26 05:31:42 PM PDT 24 Jul 26 05:31:55 PM PDT 24 770953195 ps
T1113 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.29148689 Jul 26 05:31:50 PM PDT 24 Jul 26 05:31:51 PM PDT 24 22731379 ps
T1114 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.732625616 Jul 26 05:31:38 PM PDT 24 Jul 26 05:31:40 PM PDT 24 165367160 ps
T1115 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.562184339 Jul 26 05:31:55 PM PDT 24 Jul 26 05:31:57 PM PDT 24 48127534 ps
T1116 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.1336952489 Jul 26 05:31:43 PM PDT 24 Jul 26 05:31:44 PM PDT 24 13609713 ps
T1117 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.1938123572 Jul 26 05:31:57 PM PDT 24 Jul 26 05:31:58 PM PDT 24 187665525 ps
T1118 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.784769588 Jul 26 05:31:36 PM PDT 24 Jul 26 05:31:37 PM PDT 24 22918333 ps
T1119 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2478828432 Jul 26 05:31:39 PM PDT 24 Jul 26 05:31:52 PM PDT 24 3270132702 ps
T1120 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3149949566 Jul 26 05:31:41 PM PDT 24 Jul 26 05:31:43 PM PDT 24 30707013 ps
T1121 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2191441787 Jul 26 05:31:39 PM PDT 24 Jul 26 05:31:43 PM PDT 24 183518323 ps
T1122 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.4076217522 Jul 26 05:31:39 PM PDT 24 Jul 26 05:31:41 PM PDT 24 146018181 ps
T1123 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2390361192 Jul 26 05:31:39 PM PDT 24 Jul 26 05:32:01 PM PDT 24 1007619580 ps
T1124 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.2221453682 Jul 26 05:31:39 PM PDT 24 Jul 26 05:31:41 PM PDT 24 46749150 ps
T1125 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.3024548495 Jul 26 05:31:53 PM PDT 24 Jul 26 05:31:55 PM PDT 24 148184564 ps
T1126 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.1836251559 Jul 26 05:31:54 PM PDT 24 Jul 26 05:31:59 PM PDT 24 61875314 ps
T1127 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3210673133 Jul 26 05:31:41 PM PDT 24 Jul 26 05:31:44 PM PDT 24 85072505 ps
T1128 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.553950786 Jul 26 05:31:50 PM PDT 24 Jul 26 05:31:52 PM PDT 24 53667312 ps
T1129 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2965573473 Jul 26 05:31:37 PM PDT 24 Jul 26 05:31:38 PM PDT 24 22467694 ps
T1130 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.2336299054 Jul 26 05:31:31 PM PDT 24 Jul 26 05:31:53 PM PDT 24 2689429844 ps

Test location /workspace/coverage/default/26.spi_device_stress_all.938860492
Short name T3
Test name
Test status
Simulation time 50499171181 ps
CPU time 427.96 seconds
Started Jul 26 05:34:13 PM PDT 24
Finished Jul 26 05:41:21 PM PDT 24
Peak memory 270872 kb
Host smart-6d5d5b6e-d3ec-4ca5-a980-e46cd9643401
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938860492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stres
s_all.938860492
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.2876620401
Short name T16
Test name
Test status
Simulation time 101459325563 ps
CPU time 529.85 seconds
Started Jul 26 05:35:43 PM PDT 24
Finished Jul 26 05:44:33 PM PDT 24
Peak memory 281504 kb
Host smart-2bb8522b-9a2e-4dff-b3a2-63a5fb99e150
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876620401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.2876620401
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.801830609
Short name T55
Test name
Test status
Simulation time 1157046413 ps
CPU time 3.57 seconds
Started Jul 26 05:31:51 PM PDT 24
Finished Jul 26 05:31:54 PM PDT 24
Peak memory 216732 kb
Host smart-8f8a3435-c899-49bf-b9be-70748ede783c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801830609 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.801830609
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.2954123863
Short name T14
Test name
Test status
Simulation time 244545835722 ps
CPU time 619.49 seconds
Started Jul 26 05:34:23 PM PDT 24
Finished Jul 26 05:44:42 PM PDT 24
Peak memory 267936 kb
Host smart-a2cee061-8bb4-4801-be3b-0b43ce872d82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954123863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.2954123863
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.4218101330
Short name T7
Test name
Test status
Simulation time 989297766206 ps
CPU time 482.93 seconds
Started Jul 26 05:32:48 PM PDT 24
Finished Jul 26 05:40:51 PM PDT 24
Peak memory 257312 kb
Host smart-743e1870-2f6d-4069-af8f-2edbb6071c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218101330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.4218101330
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.2496651965
Short name T56
Test name
Test status
Simulation time 17428412 ps
CPU time 0.74 seconds
Started Jul 26 05:32:38 PM PDT 24
Finished Jul 26 05:32:39 PM PDT 24
Peak memory 216068 kb
Host smart-2513515d-c8f9-4e44-ac68-5400a1d0fef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496651965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.2496651965
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.3662815643
Short name T15
Test name
Test status
Simulation time 5883322816 ps
CPU time 85.84 seconds
Started Jul 26 05:34:05 PM PDT 24
Finished Jul 26 05:35:31 PM PDT 24
Peak memory 265728 kb
Host smart-3cc1de77-46aa-44ef-89eb-653a4d3ec66a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662815643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.3662815643
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.2786347250
Short name T18
Test name
Test status
Simulation time 70896735313 ps
CPU time 400.05 seconds
Started Jul 26 05:34:56 PM PDT 24
Finished Jul 26 05:41:36 PM PDT 24
Peak memory 265504 kb
Host smart-fe4c4675-5e95-43ff-9ca1-7cb1d9fde462
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786347250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.2786347250
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.766528261
Short name T179
Test name
Test status
Simulation time 279871617064 ps
CPU time 657.26 seconds
Started Jul 26 05:33:25 PM PDT 24
Finished Jul 26 05:44:22 PM PDT 24
Peak memory 265776 kb
Host smart-77d39f00-1c84-429b-9a66-4d4324a2b236
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766528261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stres
s_all.766528261
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3421100318
Short name T53
Test name
Test status
Simulation time 2243402532 ps
CPU time 14.91 seconds
Started Jul 26 05:31:28 PM PDT 24
Finished Jul 26 05:31:43 PM PDT 24
Peak memory 215564 kb
Host smart-09f346fc-78c5-452b-bff8-35f82b03bd96
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421100318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.3421100318
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.4081409631
Short name T31
Test name
Test status
Simulation time 43057292293 ps
CPU time 160.01 seconds
Started Jul 26 05:34:07 PM PDT 24
Finished Jul 26 05:36:48 PM PDT 24
Peak memory 257140 kb
Host smart-82201462-5b0f-44a2-b2f7-5a14082ef29e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081409631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.4081409631
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.2412893681
Short name T50
Test name
Test status
Simulation time 17782468 ps
CPU time 0.72 seconds
Started Jul 26 05:32:41 PM PDT 24
Finished Jul 26 05:32:42 PM PDT 24
Peak memory 205440 kb
Host smart-ab0ab5ae-ee3a-462b-9f3c-1f9dbf76d599
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412893681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.2
412893681
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.2927064038
Short name T127
Test name
Test status
Simulation time 2896159565 ps
CPU time 31.28 seconds
Started Jul 26 05:35:20 PM PDT 24
Finished Jul 26 05:35:52 PM PDT 24
Peak memory 241100 kb
Host smart-dbcddfd5-a0c6-4a9d-a08e-889b79feee8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927064038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.2927064038
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.938449013
Short name T83
Test name
Test status
Simulation time 44455058904 ps
CPU time 195.62 seconds
Started Jul 26 05:34:30 PM PDT 24
Finished Jul 26 05:37:46 PM PDT 24
Peak memory 259388 kb
Host smart-007e0038-94f2-4f33-85c9-b56cee45f47d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938449013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmds
.938449013
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.737791628
Short name T20
Test name
Test status
Simulation time 58472389345 ps
CPU time 475.53 seconds
Started Jul 26 05:33:00 PM PDT 24
Finished Jul 26 05:40:56 PM PDT 24
Peak memory 271808 kb
Host smart-93ff930f-9403-48e9-ae1e-3c88d11c26a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737791628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stress
_all.737791628
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.3481219202
Short name T113
Test name
Test status
Simulation time 2304655192 ps
CPU time 23.79 seconds
Started Jul 26 05:31:30 PM PDT 24
Finished Jul 26 05:31:54 PM PDT 24
Peak memory 215400 kb
Host smart-fa583d94-c571-4abe-8245-c891711afd5b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481219202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.3481219202
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.2656277674
Short name T163
Test name
Test status
Simulation time 39723847961 ps
CPU time 166.87 seconds
Started Jul 26 05:33:37 PM PDT 24
Finished Jul 26 05:36:24 PM PDT 24
Peak memory 254680 kb
Host smart-d2b345ee-cf8d-40f6-bcb0-1cbdf546b2eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656277674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.2656277674
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.1227134766
Short name T148
Test name
Test status
Simulation time 416428428 ps
CPU time 5.87 seconds
Started Jul 26 05:31:28 PM PDT 24
Finished Jul 26 05:31:34 PM PDT 24
Peak memory 215576 kb
Host smart-d6d50369-c730-483d-8d3e-8f580406aaf5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227134766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.1
227134766
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.2896000090
Short name T140
Test name
Test status
Simulation time 219507366099 ps
CPU time 967.91 seconds
Started Jul 26 05:33:25 PM PDT 24
Finished Jul 26 05:49:34 PM PDT 24
Peak memory 277244 kb
Host smart-7b52cb01-4241-46d2-a97c-aaff4f50d20c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896000090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.2896000090
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.1767396041
Short name T249
Test name
Test status
Simulation time 39440296094 ps
CPU time 135.75 seconds
Started Jul 26 05:33:23 PM PDT 24
Finished Jul 26 05:35:38 PM PDT 24
Peak memory 264532 kb
Host smart-cb56942e-9c8d-49db-af83-a91e484a7350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767396041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.1767396041
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.2052164385
Short name T58
Test name
Test status
Simulation time 264053824 ps
CPU time 1.09 seconds
Started Jul 26 05:32:42 PM PDT 24
Finished Jul 26 05:32:43 PM PDT 24
Peak memory 236440 kb
Host smart-2332fccb-c84a-4886-b82d-4825b4e74ae8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052164385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.2052164385
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.2158178236
Short name T43
Test name
Test status
Simulation time 5905010184 ps
CPU time 111.48 seconds
Started Jul 26 05:34:07 PM PDT 24
Finished Jul 26 05:35:58 PM PDT 24
Peak memory 252380 kb
Host smart-0f1d57df-1a67-4e10-9699-51e99a683918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158178236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.2158178236
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.1176143792
Short name T141
Test name
Test status
Simulation time 40080581716 ps
CPU time 376.08 seconds
Started Jul 26 05:33:42 PM PDT 24
Finished Jul 26 05:39:58 PM PDT 24
Peak memory 284688 kb
Host smart-bff7908e-dd69-41cf-9713-0e7e09308a05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176143792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.1176143792
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.303666413
Short name T139
Test name
Test status
Simulation time 469767944400 ps
CPU time 1012.82 seconds
Started Jul 26 05:35:14 PM PDT 24
Finished Jul 26 05:52:07 PM PDT 24
Peak memory 272824 kb
Host smart-34de7fd2-a281-4451-99b2-29a427599102
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303666413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stres
s_all.303666413
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.2251795722
Short name T172
Test name
Test status
Simulation time 18707240261 ps
CPU time 128.2 seconds
Started Jul 26 05:33:38 PM PDT 24
Finished Jul 26 05:35:47 PM PDT 24
Peak memory 250332 kb
Host smart-59a5b4fd-1dd7-4add-a0c4-7aa3f463e68e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251795722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.2251795722
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.519370063
Short name T90
Test name
Test status
Simulation time 446123012 ps
CPU time 3.15 seconds
Started Jul 26 05:31:52 PM PDT 24
Finished Jul 26 05:31:55 PM PDT 24
Peak memory 216576 kb
Host smart-31c645a2-607b-497a-bdee-226217f7b897
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519370063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.519370063
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.638920741
Short name T35
Test name
Test status
Simulation time 5945562433 ps
CPU time 12.71 seconds
Started Jul 26 05:34:15 PM PDT 24
Finished Jul 26 05:34:27 PM PDT 24
Peak memory 232868 kb
Host smart-e5a5d1cd-3969-4f69-9a22-94076d4c883d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638920741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.638920741
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.3393969858
Short name T19
Test name
Test status
Simulation time 104393634751 ps
CPU time 96.55 seconds
Started Jul 26 05:34:16 PM PDT 24
Finished Jul 26 05:35:53 PM PDT 24
Peak memory 252572 kb
Host smart-db8a0ecb-535b-47f3-a05d-2ccfa7c5e0c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393969858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.3393969858
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.2052846298
Short name T170
Test name
Test status
Simulation time 12708455213 ps
CPU time 158.2 seconds
Started Jul 26 05:32:42 PM PDT 24
Finished Jul 26 05:35:21 PM PDT 24
Peak memory 266924 kb
Host smart-af31923f-f0ee-45e1-9c4c-ce57fdde9361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052846298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.2052846298
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.3204247636
Short name T25
Test name
Test status
Simulation time 33634582115 ps
CPU time 130.31 seconds
Started Jul 26 05:32:52 PM PDT 24
Finished Jul 26 05:35:03 PM PDT 24
Peak memory 270664 kb
Host smart-fba286a9-3d0f-4dcf-a387-ef77f5fd6ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204247636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.3204247636
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.283768521
Short name T262
Test name
Test status
Simulation time 18039382382 ps
CPU time 179.66 seconds
Started Jul 26 05:33:02 PM PDT 24
Finished Jul 26 05:36:02 PM PDT 24
Peak memory 263552 kb
Host smart-98ce590a-f715-4447-9388-eb8b50514fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283768521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.283768521
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.762220000
Short name T153
Test name
Test status
Simulation time 4618368908 ps
CPU time 15.09 seconds
Started Jul 26 05:31:38 PM PDT 24
Finished Jul 26 05:31:54 PM PDT 24
Peak memory 215956 kb
Host smart-8a68405d-dec8-43f4-8e4e-6206f96c0f9c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762220000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device
_tl_intg_err.762220000
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.139039008
Short name T157
Test name
Test status
Simulation time 8865696512 ps
CPU time 20.73 seconds
Started Jul 26 05:31:56 PM PDT 24
Finished Jul 26 05:32:16 PM PDT 24
Peak memory 215464 kb
Host smart-69f162c3-1326-447d-add5-aa0492ada05f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139039008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device
_tl_intg_err.139039008
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.515946690
Short name T278
Test name
Test status
Simulation time 1105607854 ps
CPU time 25.32 seconds
Started Jul 26 05:33:23 PM PDT 24
Finished Jul 26 05:33:49 PM PDT 24
Peak memory 233016 kb
Host smart-77c28add-d06c-4cae-bda0-b6d78ffb60cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515946690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.515946690
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.3789467810
Short name T245
Test name
Test status
Simulation time 4882890781 ps
CPU time 87.29 seconds
Started Jul 26 05:33:38 PM PDT 24
Finished Jul 26 05:35:05 PM PDT 24
Peak memory 257248 kb
Host smart-4fec60f0-959d-4dce-b586-81cce6a86caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789467810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.3789467810
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.3243009458
Short name T271
Test name
Test status
Simulation time 599023429 ps
CPU time 11.36 seconds
Started Jul 26 05:34:06 PM PDT 24
Finished Jul 26 05:34:17 PM PDT 24
Peak memory 224680 kb
Host smart-0b2125d8-0276-46c4-a328-06c425160ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243009458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.3243009458
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.879473420
Short name T143
Test name
Test status
Simulation time 7644426201 ps
CPU time 127.67 seconds
Started Jul 26 05:34:11 PM PDT 24
Finished Jul 26 05:36:19 PM PDT 24
Peak memory 262148 kb
Host smart-af515469-67fb-4fee-8fa2-fab757ac2660
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879473420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stres
s_all.879473420
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.1295766147
Short name T725
Test name
Test status
Simulation time 178911443 ps
CPU time 5.51 seconds
Started Jul 26 05:32:37 PM PDT 24
Finished Jul 26 05:32:43 PM PDT 24
Peak memory 233896 kb
Host smart-94226068-4195-4b90-9c64-bdb31b7dda6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295766147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.1295766147
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.2062338526
Short name T449
Test name
Test status
Simulation time 30391907658 ps
CPU time 302.8 seconds
Started Jul 26 05:32:43 PM PDT 24
Finished Jul 26 05:37:46 PM PDT 24
Peak memory 249376 kb
Host smart-080df5b2-9184-410c-9f11-153287b23c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062338526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.2062338526
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.2990574305
Short name T29
Test name
Test status
Simulation time 15632927376 ps
CPU time 187.61 seconds
Started Jul 26 05:33:15 PM PDT 24
Finished Jul 26 05:36:23 PM PDT 24
Peak memory 273936 kb
Host smart-6d8b0490-cac6-4e61-8e7a-629fa1d60cf2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990574305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.2990574305
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.4084435656
Short name T187
Test name
Test status
Simulation time 209503573191 ps
CPU time 294.2 seconds
Started Jul 26 05:33:24 PM PDT 24
Finished Jul 26 05:38:19 PM PDT 24
Peak memory 253720 kb
Host smart-8164cba9-7905-43b9-a10d-20403aea0ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084435656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.4084435656
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.865143011
Short name T293
Test name
Test status
Simulation time 6360826026 ps
CPU time 91.42 seconds
Started Jul 26 05:34:14 PM PDT 24
Finished Jul 26 05:35:46 PM PDT 24
Peak memory 257556 kb
Host smart-475a324f-ba30-4cd3-9e55-2268e14de29a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865143011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idle
.865143011
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.3250864516
Short name T219
Test name
Test status
Simulation time 21819074417 ps
CPU time 84.49 seconds
Started Jul 26 05:35:16 PM PDT 24
Finished Jul 26 05:36:40 PM PDT 24
Peak memory 254416 kb
Host smart-74c517f2-4dd7-4f35-9a8e-0c16bc0c230f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250864516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.3250864516
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.1212218752
Short name T236
Test name
Test status
Simulation time 46947540085 ps
CPU time 396.24 seconds
Started Jul 26 05:33:01 PM PDT 24
Finished Jul 26 05:39:37 PM PDT 24
Peak memory 286312 kb
Host smart-1c9ee449-e4b5-44ac-83fa-8488108b1731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212218752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.1212218752
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.104214922
Short name T75
Test name
Test status
Simulation time 87381354 ps
CPU time 1.42 seconds
Started Jul 26 05:31:34 PM PDT 24
Finished Jul 26 05:31:35 PM PDT 24
Peak memory 207108 kb
Host smart-482399ad-30b0-4e3e-a9b0-cd29bfc492df
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104214922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_hw_reset.104214922
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.1398951836
Short name T1095
Test name
Test status
Simulation time 688117290 ps
CPU time 3.81 seconds
Started Jul 26 05:31:29 PM PDT 24
Finished Jul 26 05:31:33 PM PDT 24
Peak memory 215656 kb
Host smart-d67c467f-4838-4f8f-b615-cfd282b44e1b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398951836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.1
398951836
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.3744631201
Short name T84
Test name
Test status
Simulation time 1405056742 ps
CPU time 4.84 seconds
Started Jul 26 05:32:40 PM PDT 24
Finished Jul 26 05:32:45 PM PDT 24
Peak memory 224672 kb
Host smart-1d4f5a8b-7b54-4518-a524-de94de81f760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744631201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.3744631201
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.2336299054
Short name T1130
Test name
Test status
Simulation time 2689429844 ps
CPU time 22.1 seconds
Started Jul 26 05:31:31 PM PDT 24
Finished Jul 26 05:31:53 PM PDT 24
Peak memory 207404 kb
Host smart-43a3e0e3-7826-4ad1-92ce-676c105344a8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336299054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.2336299054
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2369161026
Short name T77
Test name
Test status
Simulation time 159461934 ps
CPU time 1.4 seconds
Started Jul 26 05:31:28 PM PDT 24
Finished Jul 26 05:31:30 PM PDT 24
Peak memory 207100 kb
Host smart-fd1a7e69-5e6b-4de3-bf0a-09689066c7a6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369161026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.2369161026
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1781964728
Short name T107
Test name
Test status
Simulation time 59369358 ps
CPU time 1.64 seconds
Started Jul 26 05:31:30 PM PDT 24
Finished Jul 26 05:31:31 PM PDT 24
Peak memory 216456 kb
Host smart-39330b8c-ea30-41ef-9d93-57929d933866
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781964728 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.1781964728
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2252595398
Short name T1065
Test name
Test status
Simulation time 446368100 ps
CPU time 2.94 seconds
Started Jul 26 05:31:28 PM PDT 24
Finished Jul 26 05:31:31 PM PDT 24
Peak memory 215468 kb
Host smart-2a6906e5-d3b8-4abc-b166-4673c98b7698
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252595398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.2
252595398
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.4032421540
Short name T1054
Test name
Test status
Simulation time 29926872 ps
CPU time 0.73 seconds
Started Jul 26 05:31:27 PM PDT 24
Finished Jul 26 05:31:28 PM PDT 24
Peak memory 203804 kb
Host smart-d3c6e91b-facc-4f20-86b3-b9de6933f352
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032421540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.4
032421540
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.1653428101
Short name T115
Test name
Test status
Simulation time 29401272 ps
CPU time 2.16 seconds
Started Jul 26 05:31:29 PM PDT 24
Finished Jul 26 05:31:31 PM PDT 24
Peak memory 215344 kb
Host smart-59114f30-cded-464f-abb4-598b71fd196d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653428101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.1653428101
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.1991899849
Short name T1057
Test name
Test status
Simulation time 10888919 ps
CPU time 0.71 seconds
Started Jul 26 05:31:27 PM PDT 24
Finished Jul 26 05:31:27 PM PDT 24
Peak memory 203792 kb
Host smart-75e39a2d-ba27-4085-9d75-5f7d8572c20c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991899849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.1991899849
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3967119435
Short name T1052
Test name
Test status
Simulation time 82873203 ps
CPU time 2.93 seconds
Started Jul 26 05:31:30 PM PDT 24
Finished Jul 26 05:31:33 PM PDT 24
Peak memory 215336 kb
Host smart-56f89173-aad1-40be-ad34-9195f3870a80
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967119435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.3967119435
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.3663002435
Short name T119
Test name
Test status
Simulation time 413614179 ps
CPU time 15.57 seconds
Started Jul 26 05:31:42 PM PDT 24
Finished Jul 26 05:31:57 PM PDT 24
Peak memory 215404 kb
Host smart-eec6bb56-2cde-4c28-a0e5-44287105e477
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663002435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.3663002435
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2478828432
Short name T1119
Test name
Test status
Simulation time 3270132702 ps
CPU time 12.66 seconds
Started Jul 26 05:31:39 PM PDT 24
Finished Jul 26 05:31:52 PM PDT 24
Peak memory 207328 kb
Host smart-152da834-38f2-4a75-a0c0-a718dc4cc94c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478828432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.2478828432
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1157924626
Short name T104
Test name
Test status
Simulation time 190752323 ps
CPU time 1.67 seconds
Started Jul 26 05:31:42 PM PDT 24
Finished Jul 26 05:31:44 PM PDT 24
Peak memory 215500 kb
Host smart-0f91c06f-637d-427c-8fad-ce72dd16483f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157924626 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.1157924626
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3014940176
Short name T1086
Test name
Test status
Simulation time 279500226 ps
CPU time 1.8 seconds
Started Jul 26 05:31:35 PM PDT 24
Finished Jul 26 05:31:37 PM PDT 24
Peak memory 220388 kb
Host smart-2731459e-87e4-4b2d-b1de-2a3043b814ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014940176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.3
014940176
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.2662522983
Short name T1027
Test name
Test status
Simulation time 12885742 ps
CPU time 0.74 seconds
Started Jul 26 05:31:26 PM PDT 24
Finished Jul 26 05:31:27 PM PDT 24
Peak memory 203940 kb
Host smart-65d84444-290b-4645-a0d8-938dab15d5c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662522983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.2
662522983
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.4247058307
Short name T1069
Test name
Test status
Simulation time 221399681 ps
CPU time 2.12 seconds
Started Jul 26 05:31:25 PM PDT 24
Finished Jul 26 05:31:27 PM PDT 24
Peak memory 215272 kb
Host smart-03bbcff9-7512-4d62-9fb9-8a7c1878399f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247058307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.4247058307
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.3485100663
Short name T1045
Test name
Test status
Simulation time 11579430 ps
CPU time 0.65 seconds
Started Jul 26 05:31:30 PM PDT 24
Finished Jul 26 05:31:31 PM PDT 24
Peak memory 203892 kb
Host smart-6c0fff57-41c6-4f1e-8af0-ca6b2e8cd25d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485100663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.3485100663
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.757754461
Short name T1074
Test name
Test status
Simulation time 62226034 ps
CPU time 3.79 seconds
Started Jul 26 05:31:41 PM PDT 24
Finished Jul 26 05:31:45 PM PDT 24
Peak memory 215476 kb
Host smart-1699f70d-8cd0-4cc8-abcd-005abcb06949
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757754461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sp
i_device_same_csr_outstanding.757754461
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.3923587562
Short name T152
Test name
Test status
Simulation time 209342695 ps
CPU time 6.62 seconds
Started Jul 26 05:31:35 PM PDT 24
Finished Jul 26 05:31:41 PM PDT 24
Peak memory 215568 kb
Host smart-1baa59dc-4412-45d9-98e2-b419f5550a35
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923587562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.3923587562
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2191441787
Short name T1121
Test name
Test status
Simulation time 183518323 ps
CPU time 3.51 seconds
Started Jul 26 05:31:39 PM PDT 24
Finished Jul 26 05:31:43 PM PDT 24
Peak memory 217316 kb
Host smart-92e45987-5a14-4a63-be8c-8467c3654d26
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191441787 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.2191441787
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.171765976
Short name T112
Test name
Test status
Simulation time 19634411 ps
CPU time 1.36 seconds
Started Jul 26 05:31:38 PM PDT 24
Finished Jul 26 05:31:39 PM PDT 24
Peak memory 215556 kb
Host smart-5712f1f2-0dfb-4a45-8e0e-5f5288b71ef7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171765976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.171765976
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2965573473
Short name T1129
Test name
Test status
Simulation time 22467694 ps
CPU time 0.7 seconds
Started Jul 26 05:31:37 PM PDT 24
Finished Jul 26 05:31:38 PM PDT 24
Peak memory 203848 kb
Host smart-f2ce02cb-b53c-42e6-b524-c52600321169
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965573473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
2965573473
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.338366507
Short name T1026
Test name
Test status
Simulation time 747165181 ps
CPU time 3.38 seconds
Started Jul 26 05:31:40 PM PDT 24
Finished Jul 26 05:31:44 PM PDT 24
Peak memory 215420 kb
Host smart-44be5a51-8150-4fce-9b47-40dab6411834
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338366507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.s
pi_device_same_csr_outstanding.338366507
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.2449348098
Short name T147
Test name
Test status
Simulation time 185442905 ps
CPU time 4.46 seconds
Started Jul 26 05:31:37 PM PDT 24
Finished Jul 26 05:31:41 PM PDT 24
Peak memory 216612 kb
Host smart-b2b1673b-cd02-4dbb-ab4e-4f78836005a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449348098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
2449348098
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.156460980
Short name T105
Test name
Test status
Simulation time 325204959 ps
CPU time 4.03 seconds
Started Jul 26 05:31:53 PM PDT 24
Finished Jul 26 05:31:57 PM PDT 24
Peak memory 217496 kb
Host smart-da066120-ddea-42b1-a6d0-ff1005fe2c3d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156460980 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.156460980
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.1494153816
Short name T1062
Test name
Test status
Simulation time 77606277 ps
CPU time 1.97 seconds
Started Jul 26 05:31:53 PM PDT 24
Finished Jul 26 05:31:55 PM PDT 24
Peak memory 215480 kb
Host smart-3bd88cba-cf90-4c48-b83c-0f1a1c43bc3b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494153816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
1494153816
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.2576770608
Short name T1050
Test name
Test status
Simulation time 41886502 ps
CPU time 0.78 seconds
Started Jul 26 05:31:38 PM PDT 24
Finished Jul 26 05:31:39 PM PDT 24
Peak memory 203960 kb
Host smart-aaf378f3-7a6c-4cb1-89e9-2b605383c4ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576770608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
2576770608
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.553950786
Short name T1128
Test name
Test status
Simulation time 53667312 ps
CPU time 1.78 seconds
Started Jul 26 05:31:50 PM PDT 24
Finished Jul 26 05:31:52 PM PDT 24
Peak memory 215436 kb
Host smart-3db4d93e-7b35-4b0c-b90d-ed72ddc97a06
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553950786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.s
pi_device_same_csr_outstanding.553950786
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3678011876
Short name T1059
Test name
Test status
Simulation time 41737410 ps
CPU time 2.69 seconds
Started Jul 26 05:31:38 PM PDT 24
Finished Jul 26 05:31:41 PM PDT 24
Peak memory 215512 kb
Host smart-46918422-0b47-4993-bb6b-3db2d38011c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678011876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
3678011876
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2621711932
Short name T151
Test name
Test status
Simulation time 763977990 ps
CPU time 12.36 seconds
Started Jul 26 05:31:39 PM PDT 24
Finished Jul 26 05:31:51 PM PDT 24
Peak memory 215896 kb
Host smart-77bab26b-a409-40ea-b97a-b7501eb48650
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621711932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.2621711932
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.996755863
Short name T1076
Test name
Test status
Simulation time 598919859 ps
CPU time 3.58 seconds
Started Jul 26 05:31:52 PM PDT 24
Finished Jul 26 05:31:56 PM PDT 24
Peak memory 217180 kb
Host smart-7832f2bc-c701-4418-967c-6d47137cadf5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996755863 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.996755863
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2526332736
Short name T1087
Test name
Test status
Simulation time 81484296 ps
CPU time 2.18 seconds
Started Jul 26 05:31:51 PM PDT 24
Finished Jul 26 05:31:53 PM PDT 24
Peak memory 207140 kb
Host smart-b5aa6c8d-af20-4628-81a4-60e749db13ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526332736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
2526332736
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.3086846713
Short name T1103
Test name
Test status
Simulation time 39052871 ps
CPU time 0.79 seconds
Started Jul 26 05:31:50 PM PDT 24
Finished Jul 26 05:31:51 PM PDT 24
Peak memory 204248 kb
Host smart-a28dc481-0dfe-4ca5-b78b-84e630ff60e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086846713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
3086846713
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.563108694
Short name T1032
Test name
Test status
Simulation time 61169720 ps
CPU time 3.94 seconds
Started Jul 26 05:31:57 PM PDT 24
Finished Jul 26 05:32:01 PM PDT 24
Peak memory 215512 kb
Host smart-6f47d44f-a2d7-4e40-9b0d-34621ad6c73b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563108694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.s
pi_device_same_csr_outstanding.563108694
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1453521668
Short name T1083
Test name
Test status
Simulation time 69540843 ps
CPU time 1.43 seconds
Started Jul 26 05:31:51 PM PDT 24
Finished Jul 26 05:31:52 PM PDT 24
Peak memory 207488 kb
Host smart-320cc67a-0d0a-44a3-8b5c-2fdd72643877
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453521668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
1453521668
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.4173148753
Short name T156
Test name
Test status
Simulation time 442855401 ps
CPU time 7.38 seconds
Started Jul 26 05:31:56 PM PDT 24
Finished Jul 26 05:32:03 PM PDT 24
Peak memory 215484 kb
Host smart-a9854d55-3a1e-473d-8210-f9d0c3d80fec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173148753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.4173148753
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2225732411
Short name T54
Test name
Test status
Simulation time 25613886 ps
CPU time 1.92 seconds
Started Jul 26 05:31:55 PM PDT 24
Finished Jul 26 05:31:57 PM PDT 24
Peak memory 215700 kb
Host smart-3f034ef0-0460-48ec-8b70-d6aec09b4c13
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225732411 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.2225732411
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1532313760
Short name T109
Test name
Test status
Simulation time 249312544 ps
CPU time 1.93 seconds
Started Jul 26 05:31:52 PM PDT 24
Finished Jul 26 05:31:54 PM PDT 24
Peak memory 207304 kb
Host smart-b0747f9b-714f-4299-a75a-ba1f981fc37e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532313760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
1532313760
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.29148689
Short name T1113
Test name
Test status
Simulation time 22731379 ps
CPU time 0.76 seconds
Started Jul 26 05:31:50 PM PDT 24
Finished Jul 26 05:31:51 PM PDT 24
Peak memory 203804 kb
Host smart-9087583c-6e87-4447-b85b-9728fd268eb0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29148689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.29148689
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.758743230
Short name T1012
Test name
Test status
Simulation time 172389876 ps
CPU time 4.19 seconds
Started Jul 26 05:31:53 PM PDT 24
Finished Jul 26 05:31:57 PM PDT 24
Peak memory 215288 kb
Host smart-606d0ca2-e004-46fb-9279-ad1b21a26154
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758743230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.s
pi_device_same_csr_outstanding.758743230
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.4150109960
Short name T100
Test name
Test status
Simulation time 207442821 ps
CPU time 3.21 seconds
Started Jul 26 05:31:54 PM PDT 24
Finished Jul 26 05:31:57 PM PDT 24
Peak memory 215664 kb
Host smart-91772b42-428d-42de-8bc3-9a23382d42b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150109960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
4150109960
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.2438664998
Short name T1094
Test name
Test status
Simulation time 109727098 ps
CPU time 7.23 seconds
Started Jul 26 05:31:51 PM PDT 24
Finished Jul 26 05:31:58 PM PDT 24
Peak memory 215512 kb
Host smart-3d0fcc10-ed70-4e79-8a70-06ceff9404ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438664998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.2438664998
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3146580075
Short name T1058
Test name
Test status
Simulation time 73426950 ps
CPU time 1.84 seconds
Started Jul 26 05:31:52 PM PDT 24
Finished Jul 26 05:31:54 PM PDT 24
Peak memory 215616 kb
Host smart-d707ee9f-87a8-458b-97f8-c2865776134d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146580075 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.3146580075
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.2027812191
Short name T117
Test name
Test status
Simulation time 242470127 ps
CPU time 2.58 seconds
Started Jul 26 05:31:49 PM PDT 24
Finished Jul 26 05:31:52 PM PDT 24
Peak memory 207308 kb
Host smart-a8ece61c-f675-4db3-b5a3-154bba3d0d3e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027812191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
2027812191
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2785900667
Short name T1019
Test name
Test status
Simulation time 38549856 ps
CPU time 0.71 seconds
Started Jul 26 05:31:52 PM PDT 24
Finished Jul 26 05:31:53 PM PDT 24
Peak memory 204244 kb
Host smart-5471eb6e-99dc-40e5-8b17-7d9f3b75fa23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785900667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
2785900667
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.1937213762
Short name T1044
Test name
Test status
Simulation time 805735635 ps
CPU time 2.93 seconds
Started Jul 26 05:31:52 PM PDT 24
Finished Jul 26 05:31:55 PM PDT 24
Peak memory 215408 kb
Host smart-0b94c0d9-d0fd-4b0e-b282-739578ec9755
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937213762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.1937213762
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.3078314239
Short name T101
Test name
Test status
Simulation time 206913286 ps
CPU time 1.93 seconds
Started Jul 26 05:31:52 PM PDT 24
Finished Jul 26 05:31:54 PM PDT 24
Peak memory 215568 kb
Host smart-c85593c4-eaca-48d8-a538-691b765e062f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078314239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
3078314239
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.327095422
Short name T106
Test name
Test status
Simulation time 669114218 ps
CPU time 11.97 seconds
Started Jul 26 05:31:56 PM PDT 24
Finished Jul 26 05:32:08 PM PDT 24
Peak memory 216344 kb
Host smart-11abce49-2a13-4921-b9c7-e0b5362f41ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327095422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device
_tl_intg_err.327095422
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3514372170
Short name T98
Test name
Test status
Simulation time 43005441 ps
CPU time 2.79 seconds
Started Jul 26 05:31:53 PM PDT 24
Finished Jul 26 05:31:56 PM PDT 24
Peak memory 216608 kb
Host smart-e489cb03-0b35-4c12-8413-287560c6936e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514372170 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.3514372170
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.2828723693
Short name T116
Test name
Test status
Simulation time 126387886 ps
CPU time 2.03 seconds
Started Jul 26 05:31:53 PM PDT 24
Finished Jul 26 05:31:55 PM PDT 24
Peak memory 215392 kb
Host smart-e85cd67c-a6f1-4af6-a4d5-f7a3a26bc595
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828723693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
2828723693
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.3588437994
Short name T1017
Test name
Test status
Simulation time 11454881 ps
CPU time 0.72 seconds
Started Jul 26 05:31:51 PM PDT 24
Finished Jul 26 05:31:52 PM PDT 24
Peak memory 203880 kb
Host smart-9390fe1a-0aed-4792-a36e-b45f045aa7e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588437994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
3588437994
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.811095368
Short name T1061
Test name
Test status
Simulation time 55819266 ps
CPU time 2.01 seconds
Started Jul 26 05:31:56 PM PDT 24
Finished Jul 26 05:31:58 PM PDT 24
Peak memory 215252 kb
Host smart-6970e38c-b812-4ea3-9053-0f8818582a25
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811095368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.s
pi_device_same_csr_outstanding.811095368
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.1836251559
Short name T1126
Test name
Test status
Simulation time 61875314 ps
CPU time 4.02 seconds
Started Jul 26 05:31:54 PM PDT 24
Finished Jul 26 05:31:59 PM PDT 24
Peak memory 215600 kb
Host smart-c51a65dd-c60a-4d5c-be3c-f3b10ddacb68
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836251559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
1836251559
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.2894777509
Short name T154
Test name
Test status
Simulation time 3264601961 ps
CPU time 21.06 seconds
Started Jul 26 05:31:47 PM PDT 24
Finished Jul 26 05:32:09 PM PDT 24
Peak memory 215888 kb
Host smart-6cadd16b-b9fd-418a-a27c-1afc086340f4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894777509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.2894777509
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3639668250
Short name T1106
Test name
Test status
Simulation time 620631743 ps
CPU time 3.93 seconds
Started Jul 26 05:31:58 PM PDT 24
Finished Jul 26 05:32:02 PM PDT 24
Peak memory 217744 kb
Host smart-02035acf-5e9d-4bb7-9664-f970d0651639
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639668250 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.3639668250
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.1183453705
Short name T1102
Test name
Test status
Simulation time 29312275 ps
CPU time 1.83 seconds
Started Jul 26 05:31:51 PM PDT 24
Finished Jul 26 05:31:53 PM PDT 24
Peak memory 215304 kb
Host smart-ab4b769c-cc6c-42d8-b941-f4ce92caa4a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183453705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
1183453705
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.2192568375
Short name T1093
Test name
Test status
Simulation time 13893624 ps
CPU time 0.75 seconds
Started Jul 26 05:31:49 PM PDT 24
Finished Jul 26 05:31:50 PM PDT 24
Peak memory 203848 kb
Host smart-78f2999f-3b2f-4c53-84cd-86e895bce8f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192568375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
2192568375
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3762871562
Short name T1051
Test name
Test status
Simulation time 239594416 ps
CPU time 4.12 seconds
Started Jul 26 05:31:50 PM PDT 24
Finished Jul 26 05:31:54 PM PDT 24
Peak memory 215456 kb
Host smart-c923507e-2aee-4d43-9426-b8a4d3861d6f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762871562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.3762871562
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.3564139539
Short name T95
Test name
Test status
Simulation time 108193860 ps
CPU time 1.85 seconds
Started Jul 26 05:31:51 PM PDT 24
Finished Jul 26 05:31:53 PM PDT 24
Peak memory 215528 kb
Host smart-996c1794-dbd1-4cdc-9e48-b23f9b01f61c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564139539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
3564139539
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.877183014
Short name T149
Test name
Test status
Simulation time 1007082817 ps
CPU time 22.05 seconds
Started Jul 26 05:31:56 PM PDT 24
Finished Jul 26 05:32:18 PM PDT 24
Peak memory 215352 kb
Host smart-5bfb388c-ecf8-4c52-87e3-ffdcdb369cde
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877183014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device
_tl_intg_err.877183014
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1706069583
Short name T1043
Test name
Test status
Simulation time 462125499 ps
CPU time 1.86 seconds
Started Jul 26 05:31:55 PM PDT 24
Finished Jul 26 05:31:57 PM PDT 24
Peak memory 216492 kb
Host smart-5f7f5c39-3917-4638-8bd8-6972eb0d671d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706069583 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.1706069583
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.3024548495
Short name T1125
Test name
Test status
Simulation time 148184564 ps
CPU time 2.13 seconds
Started Jul 26 05:31:53 PM PDT 24
Finished Jul 26 05:31:55 PM PDT 24
Peak memory 215492 kb
Host smart-df20cb34-4ba9-4529-8cda-be5b37ac1f8e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024548495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
3024548495
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.1938123572
Short name T1117
Test name
Test status
Simulation time 187665525 ps
CPU time 0.7 seconds
Started Jul 26 05:31:57 PM PDT 24
Finished Jul 26 05:31:58 PM PDT 24
Peak memory 203924 kb
Host smart-ac77e70c-eada-4414-8f59-a6336e215f07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938123572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
1938123572
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.562184339
Short name T1115
Test name
Test status
Simulation time 48127534 ps
CPU time 1.65 seconds
Started Jul 26 05:31:55 PM PDT 24
Finished Jul 26 05:31:57 PM PDT 24
Peak memory 215380 kb
Host smart-c7859e4c-8f86-4681-b4f0-36447e5d7edb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562184339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.s
pi_device_same_csr_outstanding.562184339
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.874786339
Short name T94
Test name
Test status
Simulation time 393933921 ps
CPU time 2.8 seconds
Started Jul 26 05:31:53 PM PDT 24
Finished Jul 26 05:31:56 PM PDT 24
Peak memory 219092 kb
Host smart-942aaf71-009a-47c5-ba00-d9359b1199ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874786339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.874786339
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.266182470
Short name T103
Test name
Test status
Simulation time 7601726170 ps
CPU time 15.48 seconds
Started Jul 26 05:31:52 PM PDT 24
Finished Jul 26 05:32:07 PM PDT 24
Peak memory 215848 kb
Host smart-4cce2c89-25e6-4a59-a18b-28d17f82ebc5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266182470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device
_tl_intg_err.266182470
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.3105650415
Short name T1110
Test name
Test status
Simulation time 113750737 ps
CPU time 3.43 seconds
Started Jul 26 05:31:55 PM PDT 24
Finished Jul 26 05:31:58 PM PDT 24
Peak memory 216604 kb
Host smart-ff428ee3-789a-40e8-a57e-73bd259c2e2f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105650415 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.3105650415
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.4043062780
Short name T1072
Test name
Test status
Simulation time 124274504 ps
CPU time 2.01 seconds
Started Jul 26 05:31:55 PM PDT 24
Finished Jul 26 05:31:57 PM PDT 24
Peak memory 207112 kb
Host smart-af16ac00-42e1-435e-8aae-3d6caad33742
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043062780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
4043062780
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.2213357131
Short name T1092
Test name
Test status
Simulation time 17710468 ps
CPU time 0.77 seconds
Started Jul 26 05:31:59 PM PDT 24
Finished Jul 26 05:32:00 PM PDT 24
Peak memory 204240 kb
Host smart-85ff9e89-5206-4888-944b-57a8070f8e20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213357131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
2213357131
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2264389725
Short name T1048
Test name
Test status
Simulation time 316762200 ps
CPU time 4.7 seconds
Started Jul 26 05:31:55 PM PDT 24
Finished Jul 26 05:32:00 PM PDT 24
Peak memory 215436 kb
Host smart-8c0809c6-8dd3-4279-a588-c7ae5f461ce8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264389725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.2264389725
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.2624962665
Short name T155
Test name
Test status
Simulation time 197894595 ps
CPU time 13.29 seconds
Started Jul 26 05:31:55 PM PDT 24
Finished Jul 26 05:32:09 PM PDT 24
Peak memory 215448 kb
Host smart-a7b03c98-8e66-429f-9720-7c292eaa2fce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624962665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.2624962665
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.4288148888
Short name T1099
Test name
Test status
Simulation time 401146948 ps
CPU time 2.88 seconds
Started Jul 26 05:31:52 PM PDT 24
Finished Jul 26 05:31:55 PM PDT 24
Peak memory 216776 kb
Host smart-52e5c1bd-3dc3-4c36-85ae-d2d405413489
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288148888 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.4288148888
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1117661715
Short name T1073
Test name
Test status
Simulation time 70317291 ps
CPU time 2.07 seconds
Started Jul 26 05:31:55 PM PDT 24
Finished Jul 26 05:31:57 PM PDT 24
Peak memory 220292 kb
Host smart-74642d92-6e24-40cb-a14a-ee4ab29b5ba9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117661715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
1117661715
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1532452961
Short name T1021
Test name
Test status
Simulation time 28849420 ps
CPU time 0.73 seconds
Started Jul 26 05:31:57 PM PDT 24
Finished Jul 26 05:31:58 PM PDT 24
Peak memory 204136 kb
Host smart-f6c93e91-b7f2-4348-9d7f-117571a631a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532452961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
1532452961
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1226091260
Short name T137
Test name
Test status
Simulation time 166429622 ps
CPU time 4.07 seconds
Started Jul 26 05:31:51 PM PDT 24
Finished Jul 26 05:31:55 PM PDT 24
Peak memory 215412 kb
Host smart-26bb3f69-6267-4593-a0ca-401b455d3f1f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226091260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.1226091260
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1839354793
Short name T91
Test name
Test status
Simulation time 748679711 ps
CPU time 5.08 seconds
Started Jul 26 05:31:57 PM PDT 24
Finished Jul 26 05:32:02 PM PDT 24
Peak memory 215396 kb
Host smart-2f4c336d-91e6-4e2d-99f7-810ab7bec368
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839354793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
1839354793
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.196881878
Short name T138
Test name
Test status
Simulation time 12923888761 ps
CPU time 21.38 seconds
Started Jul 26 05:31:41 PM PDT 24
Finished Jul 26 05:32:03 PM PDT 24
Peak memory 216536 kb
Host smart-103a82aa-c137-44d5-a154-e2ce25979f13
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196881878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_aliasing.196881878
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2264703862
Short name T134
Test name
Test status
Simulation time 11787293486 ps
CPU time 40.44 seconds
Started Jul 26 05:31:42 PM PDT 24
Finished Jul 26 05:32:22 PM PDT 24
Peak memory 207320 kb
Host smart-af57918e-10ec-4380-90dd-8629510c2a04
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264703862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.2264703862
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.694685428
Short name T133
Test name
Test status
Simulation time 41858242 ps
CPU time 1.03 seconds
Started Jul 26 05:31:41 PM PDT 24
Finished Jul 26 05:31:42 PM PDT 24
Peak memory 206952 kb
Host smart-5fa2a6f4-3aff-469f-b918-8367f46c5f87
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694685428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_hw_reset.694685428
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3171942388
Short name T99
Test name
Test status
Simulation time 198842871 ps
CPU time 3.75 seconds
Started Jul 26 05:31:41 PM PDT 24
Finished Jul 26 05:31:45 PM PDT 24
Peak memory 217232 kb
Host smart-c9eb3669-7804-4c32-a0c0-25fc303c2671
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171942388 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.3171942388
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.639549433
Short name T1089
Test name
Test status
Simulation time 58465288 ps
CPU time 1.23 seconds
Started Jul 26 05:31:41 PM PDT 24
Finished Jul 26 05:31:43 PM PDT 24
Peak memory 207228 kb
Host smart-c8f17738-f185-4c4e-85a9-58c68e566c0c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639549433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.639549433
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.659320448
Short name T1028
Test name
Test status
Simulation time 37706881 ps
CPU time 0.7 seconds
Started Jul 26 05:31:51 PM PDT 24
Finished Jul 26 05:31:52 PM PDT 24
Peak memory 204228 kb
Host smart-65621e8d-ec80-41b4-ae95-00b2220a9daf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659320448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.659320448
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.3903309770
Short name T1055
Test name
Test status
Simulation time 109506189 ps
CPU time 1.35 seconds
Started Jul 26 05:31:44 PM PDT 24
Finished Jul 26 05:31:45 PM PDT 24
Peak memory 215412 kb
Host smart-60b20a86-8787-4565-b231-e0c02ca14e29
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903309770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.3903309770
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.2256769130
Short name T1023
Test name
Test status
Simulation time 16577292 ps
CPU time 0.68 seconds
Started Jul 26 05:31:41 PM PDT 24
Finished Jul 26 05:31:42 PM PDT 24
Peak memory 203896 kb
Host smart-78f317c8-c604-43cc-be72-13c920d999f5
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256769130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.2256769130
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.943348584
Short name T1030
Test name
Test status
Simulation time 454253309 ps
CPU time 3.25 seconds
Started Jul 26 05:31:40 PM PDT 24
Finished Jul 26 05:31:44 PM PDT 24
Peak memory 215280 kb
Host smart-9c11ea2d-b8f9-47af-a57a-75ac1a4365fd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943348584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sp
i_device_same_csr_outstanding.943348584
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.2609764532
Short name T93
Test name
Test status
Simulation time 249949743 ps
CPU time 3.96 seconds
Started Jul 26 05:31:41 PM PDT 24
Finished Jul 26 05:31:45 PM PDT 24
Peak memory 215624 kb
Host smart-5d9450f3-d256-437e-bee2-fbbfead30df0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609764532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.2
609764532
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.2144462071
Short name T87
Test name
Test status
Simulation time 362002040 ps
CPU time 18.76 seconds
Started Jul 26 05:31:38 PM PDT 24
Finished Jul 26 05:31:57 PM PDT 24
Peak memory 215520 kb
Host smart-5bd01db5-573a-4054-92ef-82447112776b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144462071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.2144462071
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.1802681374
Short name T1033
Test name
Test status
Simulation time 32714473 ps
CPU time 0.79 seconds
Started Jul 26 05:31:57 PM PDT 24
Finished Jul 26 05:31:58 PM PDT 24
Peak memory 203856 kb
Host smart-c3692a7c-be51-4903-983d-10a755a4815f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802681374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
1802681374
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.3480603460
Short name T1022
Test name
Test status
Simulation time 40937572 ps
CPU time 0.74 seconds
Started Jul 26 05:31:57 PM PDT 24
Finished Jul 26 05:31:58 PM PDT 24
Peak memory 203820 kb
Host smart-fad787ca-f381-4345-ac44-c832e7b31f90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480603460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
3480603460
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3592001564
Short name T1067
Test name
Test status
Simulation time 11867171 ps
CPU time 0.75 seconds
Started Jul 26 05:31:53 PM PDT 24
Finished Jul 26 05:31:54 PM PDT 24
Peak memory 204228 kb
Host smart-9d897572-f5b6-4732-ac3c-030dd8cd6fc6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592001564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
3592001564
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2469972004
Short name T1105
Test name
Test status
Simulation time 15470351 ps
CPU time 0.73 seconds
Started Jul 26 05:31:51 PM PDT 24
Finished Jul 26 05:31:52 PM PDT 24
Peak memory 203776 kb
Host smart-f3a130a3-bf9c-4828-896d-7712575d0714
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469972004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
2469972004
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1549581504
Short name T1056
Test name
Test status
Simulation time 14388724 ps
CPU time 0.73 seconds
Started Jul 26 05:31:56 PM PDT 24
Finished Jul 26 05:31:57 PM PDT 24
Peak memory 203788 kb
Host smart-c7abeaee-6d04-40a3-b17d-f24c046f701a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549581504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
1549581504
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.1954615003
Short name T1034
Test name
Test status
Simulation time 41259692 ps
CPU time 0.72 seconds
Started Jul 26 05:31:56 PM PDT 24
Finished Jul 26 05:31:57 PM PDT 24
Peak memory 203940 kb
Host smart-86d9174b-fa89-4696-a594-d7c5ba47914f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954615003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
1954615003
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.4067000806
Short name T1015
Test name
Test status
Simulation time 13057417 ps
CPU time 0.74 seconds
Started Jul 26 05:32:05 PM PDT 24
Finished Jul 26 05:32:05 PM PDT 24
Peak memory 203932 kb
Host smart-3309dd82-4112-4383-9a53-149ca637c3a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067000806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
4067000806
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.837865511
Short name T1085
Test name
Test status
Simulation time 21912517 ps
CPU time 0.7 seconds
Started Jul 26 05:31:56 PM PDT 24
Finished Jul 26 05:31:57 PM PDT 24
Peak memory 203896 kb
Host smart-3a1db7b7-c5ad-4a27-a26c-e999a500e4c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837865511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.837865511
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.8866729
Short name T1107
Test name
Test status
Simulation time 14973962 ps
CPU time 0.81 seconds
Started Jul 26 05:31:53 PM PDT 24
Finished Jul 26 05:31:54 PM PDT 24
Peak memory 203920 kb
Host smart-98a86636-dea1-44d9-aa32-4855b008ec16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8866729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.8866729
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.3329791423
Short name T1060
Test name
Test status
Simulation time 12719925 ps
CPU time 0.72 seconds
Started Jul 26 05:31:53 PM PDT 24
Finished Jul 26 05:31:53 PM PDT 24
Peak memory 203928 kb
Host smart-60ee3d28-9919-48c9-a46a-7a41e69a0ef2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329791423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
3329791423
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.4177076900
Short name T1111
Test name
Test status
Simulation time 1489265375 ps
CPU time 16.3 seconds
Started Jul 26 05:31:40 PM PDT 24
Finished Jul 26 05:31:56 PM PDT 24
Peak memory 207128 kb
Host smart-920c94ca-5416-4ea6-9835-b29e63a17c45
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177076900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.4177076900
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3052267991
Short name T110
Test name
Test status
Simulation time 557522866 ps
CPU time 33.32 seconds
Started Jul 26 05:31:39 PM PDT 24
Finished Jul 26 05:32:13 PM PDT 24
Peak memory 207196 kb
Host smart-21d4b4cb-a7dc-4b0f-ad3d-434d0b370539
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052267991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.3052267991
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1948201396
Short name T76
Test name
Test status
Simulation time 100715128 ps
CPU time 1.15 seconds
Started Jul 26 05:31:41 PM PDT 24
Finished Jul 26 05:31:43 PM PDT 24
Peak memory 207236 kb
Host smart-050ffbc7-849c-4bfd-a784-35af9331a674
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948201396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.1948201396
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.3517276370
Short name T1064
Test name
Test status
Simulation time 53767462 ps
CPU time 3.43 seconds
Started Jul 26 05:31:42 PM PDT 24
Finished Jul 26 05:31:45 PM PDT 24
Peak memory 217416 kb
Host smart-5e15fef6-2443-46b5-88e0-26b5af83a298
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517276370 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.3517276370
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.2697192405
Short name T1104
Test name
Test status
Simulation time 379447015 ps
CPU time 2.41 seconds
Started Jul 26 05:31:41 PM PDT 24
Finished Jul 26 05:31:44 PM PDT 24
Peak memory 215468 kb
Host smart-50fea20d-6feb-4476-bfc1-f0631babc606
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697192405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.2
697192405
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.1336952489
Short name T1116
Test name
Test status
Simulation time 13609713 ps
CPU time 0.75 seconds
Started Jul 26 05:31:43 PM PDT 24
Finished Jul 26 05:31:44 PM PDT 24
Peak memory 203936 kb
Host smart-038e8684-5b9b-402e-8657-e2b8d506eed6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336952489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.1
336952489
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.4255495103
Short name T114
Test name
Test status
Simulation time 103273153 ps
CPU time 1.89 seconds
Started Jul 26 05:31:45 PM PDT 24
Finished Jul 26 05:31:47 PM PDT 24
Peak memory 215352 kb
Host smart-b724c33d-f15b-45cd-a800-767ed6c837ec
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255495103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.4255495103
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1944278178
Short name T1070
Test name
Test status
Simulation time 11974585 ps
CPU time 0.68 seconds
Started Jul 26 05:31:41 PM PDT 24
Finished Jul 26 05:31:42 PM PDT 24
Peak memory 204176 kb
Host smart-30c4af65-47d2-4293-86e1-d5e15feec37c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944278178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.1944278178
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.3237786707
Short name T1063
Test name
Test status
Simulation time 239981497 ps
CPU time 2.05 seconds
Started Jul 26 05:31:40 PM PDT 24
Finished Jul 26 05:31:42 PM PDT 24
Peak memory 215468 kb
Host smart-1d988b88-9991-484b-85ae-83835a4dc862
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237786707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.3237786707
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.3807673202
Short name T1108
Test name
Test status
Simulation time 197610042 ps
CPU time 3.97 seconds
Started Jul 26 05:31:43 PM PDT 24
Finished Jul 26 05:31:47 PM PDT 24
Peak memory 215556 kb
Host smart-ebe0ef79-5cba-4492-aab8-69c7457984a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807673202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.3
807673202
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1660057947
Short name T97
Test name
Test status
Simulation time 880384176 ps
CPU time 23.58 seconds
Started Jul 26 05:31:40 PM PDT 24
Finished Jul 26 05:32:04 PM PDT 24
Peak memory 215724 kb
Host smart-005038e7-c23f-4a6a-a05b-02e250d8962a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660057947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.1660057947
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.657422277
Short name T1011
Test name
Test status
Simulation time 14659342 ps
CPU time 0.76 seconds
Started Jul 26 05:31:56 PM PDT 24
Finished Jul 26 05:31:57 PM PDT 24
Peak memory 204220 kb
Host smart-e12b114d-4e3c-41d5-8819-4ca1c435b48c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657422277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.657422277
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.2176846919
Short name T1042
Test name
Test status
Simulation time 153967387 ps
CPU time 0.77 seconds
Started Jul 26 05:31:54 PM PDT 24
Finished Jul 26 05:31:55 PM PDT 24
Peak memory 203920 kb
Host smart-5f832deb-ada2-4d1b-9c1d-df8d98e9d0fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176846919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
2176846919
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.2203770443
Short name T1014
Test name
Test status
Simulation time 20455537 ps
CPU time 0.77 seconds
Started Jul 26 05:31:56 PM PDT 24
Finished Jul 26 05:31:57 PM PDT 24
Peak memory 203936 kb
Host smart-f5990c43-69f9-4564-a3c3-332d287446e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203770443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
2203770443
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.1618544156
Short name T1036
Test name
Test status
Simulation time 35082721 ps
CPU time 0.76 seconds
Started Jul 26 05:31:54 PM PDT 24
Finished Jul 26 05:31:55 PM PDT 24
Peak memory 203916 kb
Host smart-a69bbcb5-8c54-40ae-95ba-c471f2debf9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618544156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
1618544156
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.3399675789
Short name T1088
Test name
Test status
Simulation time 41857769 ps
CPU time 0.73 seconds
Started Jul 26 05:31:59 PM PDT 24
Finished Jul 26 05:32:00 PM PDT 24
Peak memory 203912 kb
Host smart-b85ee5e9-6eb5-43c0-98da-ea32c3c4ef95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399675789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
3399675789
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.127177403
Short name T1049
Test name
Test status
Simulation time 31255386 ps
CPU time 0.75 seconds
Started Jul 26 05:31:59 PM PDT 24
Finished Jul 26 05:32:00 PM PDT 24
Peak memory 204232 kb
Host smart-0692ea86-5e4f-49c1-adeb-851e6d3ae621
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127177403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.127177403
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.1131069703
Short name T1091
Test name
Test status
Simulation time 15766008 ps
CPU time 0.74 seconds
Started Jul 26 05:31:53 PM PDT 24
Finished Jul 26 05:31:54 PM PDT 24
Peak memory 203916 kb
Host smart-25c6e726-4359-417e-8d9e-19f5e6773314
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131069703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
1131069703
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.2368454742
Short name T1066
Test name
Test status
Simulation time 39171396 ps
CPU time 0.8 seconds
Started Jul 26 05:31:58 PM PDT 24
Finished Jul 26 05:31:59 PM PDT 24
Peak memory 204228 kb
Host smart-f4063ae4-2ae7-40f2-a908-02ced399f4b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368454742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
2368454742
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.3066880764
Short name T1024
Test name
Test status
Simulation time 55387443 ps
CPU time 0.76 seconds
Started Jul 26 05:31:51 PM PDT 24
Finished Jul 26 05:31:52 PM PDT 24
Peak memory 203924 kb
Host smart-4c5e9eed-edf5-40ea-890e-4f4311f66868
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066880764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
3066880764
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.2616152623
Short name T1071
Test name
Test status
Simulation time 54600545 ps
CPU time 0.73 seconds
Started Jul 26 05:31:54 PM PDT 24
Finished Jul 26 05:31:55 PM PDT 24
Peak memory 203848 kb
Host smart-3e35ae60-637d-498b-aea1-35327636dbd9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616152623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
2616152623
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.2261180037
Short name T118
Test name
Test status
Simulation time 1817117018 ps
CPU time 24.17 seconds
Started Jul 26 05:31:42 PM PDT 24
Finished Jul 26 05:32:07 PM PDT 24
Peak memory 215440 kb
Host smart-bc8cffed-c763-449b-8d2e-ba712686ad63
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261180037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.2261180037
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.2707074205
Short name T111
Test name
Test status
Simulation time 536611367 ps
CPU time 34.36 seconds
Started Jul 26 05:31:43 PM PDT 24
Finished Jul 26 05:32:18 PM PDT 24
Peak memory 215412 kb
Host smart-5731f4af-2213-49d7-b7b3-65c0f7a7d270
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707074205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.2707074205
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.641027554
Short name T1100
Test name
Test status
Simulation time 15401230 ps
CPU time 0.96 seconds
Started Jul 26 05:31:43 PM PDT 24
Finished Jul 26 05:31:44 PM PDT 24
Peak memory 207080 kb
Host smart-d9938b46-5cf2-4a75-b6fb-9ef3a00419c0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641027554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_hw_reset.641027554
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1784629025
Short name T1046
Test name
Test status
Simulation time 23598621 ps
CPU time 1.25 seconds
Started Jul 26 05:31:41 PM PDT 24
Finished Jul 26 05:31:43 PM PDT 24
Peak memory 207244 kb
Host smart-1f467993-e995-40f2-bd8c-44a2fe5e20bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784629025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.1
784629025
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.2705639316
Short name T1041
Test name
Test status
Simulation time 36110366 ps
CPU time 0.75 seconds
Started Jul 26 05:31:40 PM PDT 24
Finished Jul 26 05:31:41 PM PDT 24
Peak memory 204200 kb
Host smart-08b75c6a-1d6d-453b-9984-7313ab2e9d15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705639316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.2
705639316
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.637820814
Short name T1080
Test name
Test status
Simulation time 206979553 ps
CPU time 1.83 seconds
Started Jul 26 05:31:43 PM PDT 24
Finished Jul 26 05:31:45 PM PDT 24
Peak memory 215316 kb
Host smart-f6281590-43cf-4415-9856-2825d5f8dd74
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637820814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_
device_mem_partial_access.637820814
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1934305515
Short name T1018
Test name
Test status
Simulation time 10796779 ps
CPU time 0.66 seconds
Started Jul 26 05:31:40 PM PDT 24
Finished Jul 26 05:31:41 PM PDT 24
Peak memory 203732 kb
Host smart-c7bd3d1c-25e5-470d-8aa3-ab3599defe1a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934305515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.1934305515
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.828022581
Short name T1077
Test name
Test status
Simulation time 99393704 ps
CPU time 1.87 seconds
Started Jul 26 05:31:45 PM PDT 24
Finished Jul 26 05:31:47 PM PDT 24
Peak memory 215460 kb
Host smart-a29aadb5-24d5-4513-9929-57166d2604ab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828022581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sp
i_device_same_csr_outstanding.828022581
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2488301897
Short name T1084
Test name
Test status
Simulation time 84535109 ps
CPU time 1.47 seconds
Started Jul 26 05:31:39 PM PDT 24
Finished Jul 26 05:31:41 PM PDT 24
Peak memory 215560 kb
Host smart-41c23d1d-8048-4ccb-82d7-592381cfc205
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488301897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.2
488301897
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.3263327825
Short name T1029
Test name
Test status
Simulation time 191727117 ps
CPU time 12.89 seconds
Started Jul 26 05:31:40 PM PDT 24
Finished Jul 26 05:31:53 PM PDT 24
Peak memory 215284 kb
Host smart-fb07e706-5b1b-4762-9903-709e8c7a63f1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263327825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.3263327825
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.1336753791
Short name T1037
Test name
Test status
Simulation time 24048941 ps
CPU time 0.71 seconds
Started Jul 26 05:31:56 PM PDT 24
Finished Jul 26 05:31:57 PM PDT 24
Peak memory 204100 kb
Host smart-a1a81c10-1a00-495c-ba4f-b5009d5ccae6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336753791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
1336753791
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.246472349
Short name T1101
Test name
Test status
Simulation time 35384121 ps
CPU time 0.72 seconds
Started Jul 26 05:31:55 PM PDT 24
Finished Jul 26 05:31:56 PM PDT 24
Peak memory 203840 kb
Host smart-deb5774e-df38-458e-ac6e-9ee77bafb2a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246472349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.246472349
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.2657161627
Short name T1090
Test name
Test status
Simulation time 27208606 ps
CPU time 0.75 seconds
Started Jul 26 05:31:53 PM PDT 24
Finished Jul 26 05:31:54 PM PDT 24
Peak memory 203940 kb
Host smart-6dee74c4-947c-4167-a47e-ce6f5e9ac73c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657161627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
2657161627
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2635263765
Short name T1020
Test name
Test status
Simulation time 49353557 ps
CPU time 0.74 seconds
Started Jul 26 05:31:58 PM PDT 24
Finished Jul 26 05:31:59 PM PDT 24
Peak memory 203912 kb
Host smart-4c280251-5952-4ead-a952-33862640e3ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635263765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
2635263765
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.3728837561
Short name T1038
Test name
Test status
Simulation time 22395014 ps
CPU time 0.77 seconds
Started Jul 26 05:31:59 PM PDT 24
Finished Jul 26 05:32:00 PM PDT 24
Peak memory 203916 kb
Host smart-a373566a-cd35-47eb-9483-4677d3d339b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728837561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
3728837561
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.2462842175
Short name T1025
Test name
Test status
Simulation time 32095211 ps
CPU time 0.68 seconds
Started Jul 26 05:31:55 PM PDT 24
Finished Jul 26 05:31:56 PM PDT 24
Peak memory 203928 kb
Host smart-1528d272-fb54-4021-840f-798385ccc6f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462842175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
2462842175
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.2047439501
Short name T1109
Test name
Test status
Simulation time 84546887 ps
CPU time 0.7 seconds
Started Jul 26 05:31:58 PM PDT 24
Finished Jul 26 05:31:59 PM PDT 24
Peak memory 204228 kb
Host smart-9f176b1f-d9e0-4aad-b7ab-79fa6cb49809
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047439501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
2047439501
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.644707060
Short name T1013
Test name
Test status
Simulation time 28521974 ps
CPU time 0.81 seconds
Started Jul 26 05:31:53 PM PDT 24
Finished Jul 26 05:31:53 PM PDT 24
Peak memory 203920 kb
Host smart-3ce39a3b-6582-402f-b9e1-ec6a09e6c893
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644707060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.644707060
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.31331645
Short name T1040
Test name
Test status
Simulation time 39034089 ps
CPU time 0.77 seconds
Started Jul 26 05:31:54 PM PDT 24
Finished Jul 26 05:31:55 PM PDT 24
Peak memory 204248 kb
Host smart-68b6f0c3-2b37-4417-bf02-97ec1534d3be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31331645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.31331645
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.3087515615
Short name T1079
Test name
Test status
Simulation time 11382057 ps
CPU time 0.83 seconds
Started Jul 26 05:31:54 PM PDT 24
Finished Jul 26 05:31:55 PM PDT 24
Peak memory 204260 kb
Host smart-575952d3-7209-4fe0-9155-8484c35cb018
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087515615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
3087515615
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.732625616
Short name T1114
Test name
Test status
Simulation time 165367160 ps
CPU time 2.63 seconds
Started Jul 26 05:31:38 PM PDT 24
Finished Jul 26 05:31:40 PM PDT 24
Peak memory 217968 kb
Host smart-12d11f1f-7f2b-40ee-8db4-4a861dbc8a16
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732625616 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.732625616
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.4076217522
Short name T1122
Test name
Test status
Simulation time 146018181 ps
CPU time 2.67 seconds
Started Jul 26 05:31:39 PM PDT 24
Finished Jul 26 05:31:41 PM PDT 24
Peak memory 215400 kb
Host smart-22c906de-7b28-486f-803b-12344ae32f66
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076217522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.4
076217522
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3640305765
Short name T1016
Test name
Test status
Simulation time 33753471 ps
CPU time 0.76 seconds
Started Jul 26 05:31:43 PM PDT 24
Finished Jul 26 05:31:44 PM PDT 24
Peak memory 203932 kb
Host smart-19592ac5-2d5b-4fc9-a06d-9a480bdc9e44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640305765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.3
640305765
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.3996416360
Short name T136
Test name
Test status
Simulation time 150772121 ps
CPU time 3.42 seconds
Started Jul 26 05:31:39 PM PDT 24
Finished Jul 26 05:31:43 PM PDT 24
Peak memory 215436 kb
Host smart-98fa112f-e6e4-4061-9469-b325b18ff8f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996416360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.3996416360
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.3011702226
Short name T96
Test name
Test status
Simulation time 920147489 ps
CPU time 3.73 seconds
Started Jul 26 05:31:40 PM PDT 24
Finished Jul 26 05:31:44 PM PDT 24
Peak memory 215460 kb
Host smart-d9248398-df45-4ac4-a57c-e285e803bb98
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011702226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.3
011702226
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.2440201273
Short name T89
Test name
Test status
Simulation time 113775249 ps
CPU time 7.14 seconds
Started Jul 26 05:31:42 PM PDT 24
Finished Jul 26 05:31:50 PM PDT 24
Peak memory 215444 kb
Host smart-3a8b0947-97f5-42e3-b997-ba806a859440
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440201273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.2440201273
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3210673133
Short name T1127
Test name
Test status
Simulation time 85072505 ps
CPU time 2.5 seconds
Started Jul 26 05:31:41 PM PDT 24
Finished Jul 26 05:31:44 PM PDT 24
Peak memory 216400 kb
Host smart-8f87820d-eecf-4961-8073-ec700ea3ac16
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210673133 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.3210673133
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.2221453682
Short name T1124
Test name
Test status
Simulation time 46749150 ps
CPU time 1.31 seconds
Started Jul 26 05:31:39 PM PDT 24
Finished Jul 26 05:31:41 PM PDT 24
Peak memory 215376 kb
Host smart-a027ccdb-0b9f-48e1-bca7-99e07de80135
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221453682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.2
221453682
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.1727587519
Short name T1096
Test name
Test status
Simulation time 61842105 ps
CPU time 0.71 seconds
Started Jul 26 05:31:40 PM PDT 24
Finished Jul 26 05:31:40 PM PDT 24
Peak memory 203912 kb
Host smart-85467575-d4eb-4ea2-a9ec-308981db1e84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727587519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.1
727587519
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.861910081
Short name T1031
Test name
Test status
Simulation time 117032867 ps
CPU time 4.21 seconds
Started Jul 26 05:31:37 PM PDT 24
Finished Jul 26 05:31:41 PM PDT 24
Peak memory 215440 kb
Host smart-ee8910ca-7cc0-4d5a-b9ef-afab4a5ec9fe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861910081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sp
i_device_same_csr_outstanding.861910081
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.1171876566
Short name T1039
Test name
Test status
Simulation time 67603689 ps
CPU time 2.21 seconds
Started Jul 26 05:31:38 PM PDT 24
Finished Jul 26 05:31:41 PM PDT 24
Peak memory 215428 kb
Host smart-9705b145-cdd0-4918-b40a-9ec714a92298
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171876566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.1
171876566
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.605146816
Short name T1097
Test name
Test status
Simulation time 385528179 ps
CPU time 9.28 seconds
Started Jul 26 05:31:39 PM PDT 24
Finished Jul 26 05:31:48 PM PDT 24
Peak memory 215840 kb
Host smart-887f4a7d-dd47-4508-bbc0-efae917455ef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605146816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_
tl_intg_err.605146816
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3157997708
Short name T1035
Test name
Test status
Simulation time 186791085 ps
CPU time 1.83 seconds
Started Jul 26 05:31:39 PM PDT 24
Finished Jul 26 05:31:41 PM PDT 24
Peak memory 215488 kb
Host smart-43951798-c9d8-4249-97eb-1bce3d4a89a0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157997708 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.3157997708
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.2912081692
Short name T1078
Test name
Test status
Simulation time 44165565 ps
CPU time 1.41 seconds
Started Jul 26 05:31:40 PM PDT 24
Finished Jul 26 05:31:42 PM PDT 24
Peak memory 215332 kb
Host smart-8ad968bb-7bb2-41b1-ae2f-cafd3905c693
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912081692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.2
912081692
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.2940578747
Short name T1047
Test name
Test status
Simulation time 22801764 ps
CPU time 0.76 seconds
Started Jul 26 05:31:41 PM PDT 24
Finished Jul 26 05:31:42 PM PDT 24
Peak memory 203924 kb
Host smart-0762a224-7137-4745-b42e-fcf14a2384f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940578747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.2
940578747
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3117404402
Short name T1082
Test name
Test status
Simulation time 197357540 ps
CPU time 4.23 seconds
Started Jul 26 05:31:41 PM PDT 24
Finished Jul 26 05:31:46 PM PDT 24
Peak memory 215388 kb
Host smart-d5b2e59a-8038-4376-bca0-119b066cb8b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117404402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.3117404402
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.525244170
Short name T102
Test name
Test status
Simulation time 250146967 ps
CPU time 4.11 seconds
Started Jul 26 05:31:35 PM PDT 24
Finished Jul 26 05:31:40 PM PDT 24
Peak memory 215844 kb
Host smart-6091e135-69d4-46c6-8e26-c3c7124953be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525244170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.525244170
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.2393003199
Short name T150
Test name
Test status
Simulation time 1218987709 ps
CPU time 14.46 seconds
Started Jul 26 05:31:40 PM PDT 24
Finished Jul 26 05:31:55 PM PDT 24
Peak memory 215444 kb
Host smart-d1d28bca-7360-4d61-b506-2ce92e4b1b73
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393003199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.2393003199
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2681131992
Short name T1053
Test name
Test status
Simulation time 58336845 ps
CPU time 3.5 seconds
Started Jul 26 05:31:39 PM PDT 24
Finished Jul 26 05:31:43 PM PDT 24
Peak memory 218060 kb
Host smart-867de875-b427-4663-a55e-a0e7bc5119da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681131992 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.2681131992
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.4109066807
Short name T1068
Test name
Test status
Simulation time 327127248 ps
CPU time 2.56 seconds
Started Jul 26 05:31:41 PM PDT 24
Finished Jul 26 05:31:44 PM PDT 24
Peak memory 215412 kb
Host smart-4c439239-8dca-4ebd-ba9f-75096afa098a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109066807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.4
109066807
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1363127512
Short name T1075
Test name
Test status
Simulation time 52010763 ps
CPU time 0.77 seconds
Started Jul 26 05:31:39 PM PDT 24
Finished Jul 26 05:31:40 PM PDT 24
Peak memory 204244 kb
Host smart-30ae4a64-a430-4771-9604-3b9428efc8d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363127512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.1
363127512
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.3699214494
Short name T135
Test name
Test status
Simulation time 290509646 ps
CPU time 1.92 seconds
Started Jul 26 05:31:39 PM PDT 24
Finished Jul 26 05:31:41 PM PDT 24
Peak memory 215484 kb
Host smart-1f66353f-591a-4efa-ac70-94e0f1f0c881
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699214494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.3699214494
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2693490234
Short name T88
Test name
Test status
Simulation time 404509964 ps
CPU time 2.49 seconds
Started Jul 26 05:31:38 PM PDT 24
Finished Jul 26 05:31:41 PM PDT 24
Peak memory 215500 kb
Host smart-f83dbca6-33f4-49a9-85ea-e4943e812364
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693490234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.2
693490234
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.13759929
Short name T1112
Test name
Test status
Simulation time 770953195 ps
CPU time 13.32 seconds
Started Jul 26 05:31:42 PM PDT 24
Finished Jul 26 05:31:55 PM PDT 24
Peak memory 216056 kb
Host smart-3252aba0-843c-40dd-9f06-bb120f84ca6f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13759929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_t
l_intg_err.13759929
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1442580069
Short name T1081
Test name
Test status
Simulation time 23245604 ps
CPU time 1.52 seconds
Started Jul 26 05:31:39 PM PDT 24
Finished Jul 26 05:31:41 PM PDT 24
Peak memory 215416 kb
Host smart-b337d2aa-b02f-431f-bd0d-42aa1ada31a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442580069 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.1442580069
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3149949566
Short name T1120
Test name
Test status
Simulation time 30707013 ps
CPU time 2.14 seconds
Started Jul 26 05:31:41 PM PDT 24
Finished Jul 26 05:31:43 PM PDT 24
Peak memory 215496 kb
Host smart-16d34c9d-a343-4b65-a11d-06621dfdb035
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149949566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.3
149949566
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.784769588
Short name T1118
Test name
Test status
Simulation time 22918333 ps
CPU time 0.73 seconds
Started Jul 26 05:31:36 PM PDT 24
Finished Jul 26 05:31:37 PM PDT 24
Peak memory 204232 kb
Host smart-856d4809-38af-4858-886c-c3b8bd1aad2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784769588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.784769588
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.1921283462
Short name T1098
Test name
Test status
Simulation time 425133722 ps
CPU time 3.09 seconds
Started Jul 26 05:31:41 PM PDT 24
Finished Jul 26 05:31:44 PM PDT 24
Peak memory 215408 kb
Host smart-0cbe5c41-6e19-4f2c-8d51-cc974e714a7c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921283462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.1921283462
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.749308035
Short name T92
Test name
Test status
Simulation time 70652467 ps
CPU time 2.09 seconds
Started Jul 26 05:31:42 PM PDT 24
Finished Jul 26 05:31:45 PM PDT 24
Peak memory 215536 kb
Host smart-5d1272b8-24b7-417f-b734-9606ed9f7e7b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749308035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.749308035
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2390361192
Short name T1123
Test name
Test status
Simulation time 1007619580 ps
CPU time 22.42 seconds
Started Jul 26 05:31:39 PM PDT 24
Finished Jul 26 05:32:01 PM PDT 24
Peak memory 215476 kb
Host smart-7234092a-81d2-40d3-b18a-0ad6221ac136
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390361192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.2390361192
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.2054560120
Short name T52
Test name
Test status
Simulation time 11378396 ps
CPU time 0.71 seconds
Started Jul 26 05:32:41 PM PDT 24
Finished Jul 26 05:32:42 PM PDT 24
Peak memory 204992 kb
Host smart-946ceaf8-b707-47d8-977f-503d0982672a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054560120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.2
054560120
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.999456827
Short name T605
Test name
Test status
Simulation time 137260805 ps
CPU time 3.12 seconds
Started Jul 26 05:32:41 PM PDT 24
Finished Jul 26 05:32:44 PM PDT 24
Peak memory 232848 kb
Host smart-5b43fd90-0698-4364-ae00-db070b038857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999456827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.999456827
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.363665251
Short name T520
Test name
Test status
Simulation time 67044080 ps
CPU time 0.79 seconds
Started Jul 26 05:32:25 PM PDT 24
Finished Jul 26 05:32:26 PM PDT 24
Peak memory 206940 kb
Host smart-f3d74362-0e7b-4c68-85ef-eda7d86816ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363665251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.363665251
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.3109939836
Short name T892
Test name
Test status
Simulation time 16547669891 ps
CPU time 73.61 seconds
Started Jul 26 05:32:40 PM PDT 24
Finished Jul 26 05:33:54 PM PDT 24
Peak memory 249296 kb
Host smart-fceac4ef-2f34-4a3c-8420-175271b9ad56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109939836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.3109939836
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.1244033865
Short name T244
Test name
Test status
Simulation time 72049409575 ps
CPU time 256.67 seconds
Started Jul 26 05:32:41 PM PDT 24
Finished Jul 26 05:36:58 PM PDT 24
Peak memory 251340 kb
Host smart-9a0e75af-f9b4-490f-9fc8-669cbf17c41d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244033865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.1244033865
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.2904535662
Short name T491
Test name
Test status
Simulation time 6487085707 ps
CPU time 96.59 seconds
Started Jul 26 05:32:39 PM PDT 24
Finished Jul 26 05:34:16 PM PDT 24
Peak memory 264780 kb
Host smart-9cc9bbbf-a58f-4ac3-a5fa-4d286fd71d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904535662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.2904535662
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.2495128923
Short name T341
Test name
Test status
Simulation time 90180522117 ps
CPU time 155.08 seconds
Started Jul 26 05:32:36 PM PDT 24
Finished Jul 26 05:35:11 PM PDT 24
Peak memory 249424 kb
Host smart-b3e8cdaa-012f-4c15-aac4-9e31576ebd89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495128923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds
.2495128923
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_intercept.1821385167
Short name T633
Test name
Test status
Simulation time 6179308109 ps
CPU time 19.51 seconds
Started Jul 26 05:32:38 PM PDT 24
Finished Jul 26 05:32:57 PM PDT 24
Peak memory 224600 kb
Host smart-371b43b4-de2d-4956-8767-1662eb07ba48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821385167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.1821385167
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.100726625
Short name T923
Test name
Test status
Simulation time 2065046273 ps
CPU time 22.28 seconds
Started Jul 26 05:32:37 PM PDT 24
Finished Jul 26 05:33:00 PM PDT 24
Peak memory 224648 kb
Host smart-e1b61337-cdcb-4e46-b5c3-e5b04fc5aef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100726625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.100726625
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.3331139658
Short name T442
Test name
Test status
Simulation time 1393225584 ps
CPU time 3.66 seconds
Started Jul 26 05:32:37 PM PDT 24
Finished Jul 26 05:32:41 PM PDT 24
Peak memory 224560 kb
Host smart-8e472fa6-1122-4ba0-9826-c590ea6351d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331139658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.3331139658
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.2722345433
Short name T432
Test name
Test status
Simulation time 190148733 ps
CPU time 4.62 seconds
Started Jul 26 05:32:39 PM PDT 24
Finished Jul 26 05:32:44 PM PDT 24
Peak memory 223380 kb
Host smart-2ba7f276-c612-4900-827b-395dd6c784b6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2722345433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.2722345433
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.3948515423
Short name T251
Test name
Test status
Simulation time 19849008585 ps
CPU time 48.9 seconds
Started Jul 26 05:32:38 PM PDT 24
Finished Jul 26 05:33:27 PM PDT 24
Peak memory 241116 kb
Host smart-c998836d-021a-452d-bfaa-920f3d1a1030
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948515423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.3948515423
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.130669276
Short name T445
Test name
Test status
Simulation time 27342053393 ps
CPU time 42.02 seconds
Started Jul 26 05:32:36 PM PDT 24
Finished Jul 26 05:33:19 PM PDT 24
Peak memory 220432 kb
Host smart-bca21e92-7a1b-4645-b3b1-01d56ffe0810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130669276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.130669276
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.4176085672
Short name T938
Test name
Test status
Simulation time 340696539 ps
CPU time 2.09 seconds
Started Jul 26 05:32:42 PM PDT 24
Finished Jul 26 05:32:44 PM PDT 24
Peak memory 207912 kb
Host smart-74f479be-5c4a-4a54-813b-2b99d8099506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176085672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.4176085672
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.4212213614
Short name T569
Test name
Test status
Simulation time 114009238 ps
CPU time 2 seconds
Started Jul 26 05:32:42 PM PDT 24
Finished Jul 26 05:32:44 PM PDT 24
Peak memory 216340 kb
Host smart-635f3950-88ae-4742-bfc0-b2b7f7d6962a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212213614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.4212213614
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.252701318
Short name T416
Test name
Test status
Simulation time 22259680 ps
CPU time 0.71 seconds
Started Jul 26 05:32:39 PM PDT 24
Finished Jul 26 05:32:40 PM PDT 24
Peak memory 205708 kb
Host smart-389dd8d5-9511-419a-a8ba-971a4d74ae51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252701318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.252701318
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.4228978664
Short name T917
Test name
Test status
Simulation time 108691268 ps
CPU time 2.21 seconds
Started Jul 26 05:32:43 PM PDT 24
Finished Jul 26 05:32:45 PM PDT 24
Peak memory 224280 kb
Host smart-96ad52a5-a2e4-4aa0-8f5a-fb49b3e7800e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228978664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.4228978664
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.2545120111
Short name T780
Test name
Test status
Simulation time 22511351 ps
CPU time 0.69 seconds
Started Jul 26 05:32:41 PM PDT 24
Finished Jul 26 05:32:42 PM PDT 24
Peak memory 205816 kb
Host smart-6b6ee302-4e1a-472b-88d0-662f8907029f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545120111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.2
545120111
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.3606814704
Short name T80
Test name
Test status
Simulation time 1678640109 ps
CPU time 15.61 seconds
Started Jul 26 05:32:41 PM PDT 24
Finished Jul 26 05:32:57 PM PDT 24
Peak memory 232824 kb
Host smart-b123c6e7-3e25-4819-9d8c-31f4fa8bb567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606814704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.3606814704
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.1771328699
Short name T301
Test name
Test status
Simulation time 20635770 ps
CPU time 0.78 seconds
Started Jul 26 05:32:43 PM PDT 24
Finished Jul 26 05:32:44 PM PDT 24
Peak memory 206692 kb
Host smart-7569b995-9df0-473a-b443-c9e3d893dc88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771328699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.1771328699
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.4239435594
Short name T462
Test name
Test status
Simulation time 37847546222 ps
CPU time 269.71 seconds
Started Jul 26 05:32:40 PM PDT 24
Finished Jul 26 05:37:10 PM PDT 24
Peak memory 255564 kb
Host smart-3b24ed14-0608-4822-9ece-2512c6074e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239435594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.4239435594
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.4226414239
Short name T273
Test name
Test status
Simulation time 2062728079 ps
CPU time 8.94 seconds
Started Jul 26 05:32:41 PM PDT 24
Finished Jul 26 05:32:51 PM PDT 24
Peak memory 224524 kb
Host smart-bb35b664-01d1-40e2-a582-7769a1c500aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226414239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.4226414239
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.266347950
Short name T247
Test name
Test status
Simulation time 210857533102 ps
CPU time 388.83 seconds
Started Jul 26 05:32:41 PM PDT 24
Finished Jul 26 05:39:10 PM PDT 24
Peak memory 250360 kb
Host smart-b266e283-5242-4365-8e68-bc8413e2210d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266347950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds.
266347950
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_intercept.4183119818
Short name T597
Test name
Test status
Simulation time 377802321 ps
CPU time 3.02 seconds
Started Jul 26 05:32:42 PM PDT 24
Finished Jul 26 05:32:45 PM PDT 24
Peak memory 224536 kb
Host smart-b9dbf111-433f-4308-ba0e-cdc8e0213dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183119818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.4183119818
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.1431257192
Short name T951
Test name
Test status
Simulation time 17398551720 ps
CPU time 44.72 seconds
Started Jul 26 05:32:43 PM PDT 24
Finished Jul 26 05:33:28 PM PDT 24
Peak memory 232940 kb
Host smart-1b12e75e-6476-4cd2-9674-d4376efef621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431257192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.1431257192
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.2466456722
Short name T667
Test name
Test status
Simulation time 1771534205 ps
CPU time 7.12 seconds
Started Jul 26 05:32:39 PM PDT 24
Finished Jul 26 05:32:46 PM PDT 24
Peak memory 232804 kb
Host smart-edb2b2c9-f068-4812-85f3-a974c1b06c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466456722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.2466456722
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.3632283678
Short name T174
Test name
Test status
Simulation time 9928089747 ps
CPU time 16.24 seconds
Started Jul 26 05:32:43 PM PDT 24
Finished Jul 26 05:32:59 PM PDT 24
Peak memory 241060 kb
Host smart-3d2bf273-a8f9-4014-be37-9f54144013dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632283678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.3632283678
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.960526217
Short name T440
Test name
Test status
Simulation time 5264921272 ps
CPU time 15.33 seconds
Started Jul 26 05:32:42 PM PDT 24
Finished Jul 26 05:32:57 PM PDT 24
Peak memory 219988 kb
Host smart-8535b6ce-d4d5-4eb4-b543-9e6e411e03ce
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=960526217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_direc
t.960526217
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.4140932118
Short name T57
Test name
Test status
Simulation time 83459756 ps
CPU time 1.27 seconds
Started Jul 26 05:32:36 PM PDT 24
Finished Jul 26 05:32:38 PM PDT 24
Peak memory 235804 kb
Host smart-26bb85b9-64d5-4141-b542-cdf8e6318c16
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140932118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.4140932118
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.4006704968
Short name T258
Test name
Test status
Simulation time 13568313959 ps
CPU time 206.3 seconds
Started Jul 26 05:32:41 PM PDT 24
Finished Jul 26 05:36:08 PM PDT 24
Peak memory 253396 kb
Host smart-cbe94ab1-7b77-4d19-b742-11fb086985e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006704968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.4006704968
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.3421195904
Short name T284
Test name
Test status
Simulation time 5250708340 ps
CPU time 21.15 seconds
Started Jul 26 05:32:41 PM PDT 24
Finished Jul 26 05:33:03 PM PDT 24
Peak memory 220804 kb
Host smart-39bdb0b9-de6b-483c-9bbb-439286b49514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421195904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.3421195904
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.2395377177
Short name T910
Test name
Test status
Simulation time 11610201 ps
CPU time 0.71 seconds
Started Jul 26 05:32:41 PM PDT 24
Finished Jul 26 05:32:42 PM PDT 24
Peak memory 205800 kb
Host smart-0f9416b1-f4e4-4790-ad21-6c36c6469daf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395377177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.2395377177
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.2241985654
Short name T981
Test name
Test status
Simulation time 294827825 ps
CPU time 4.57 seconds
Started Jul 26 05:32:41 PM PDT 24
Finished Jul 26 05:32:46 PM PDT 24
Peak memory 216392 kb
Host smart-6842c0b3-55ec-4acb-9313-bce5ca6b0f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241985654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.2241985654
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.476077845
Short name T305
Test name
Test status
Simulation time 162774228 ps
CPU time 0.77 seconds
Started Jul 26 05:32:40 PM PDT 24
Finished Jul 26 05:32:41 PM PDT 24
Peak memory 206072 kb
Host smart-cd3bb0b1-34c6-4498-ad1c-e625e848d3e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476077845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.476077845
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.1041936860
Short name T197
Test name
Test status
Simulation time 3051910195 ps
CPU time 6.83 seconds
Started Jul 26 05:32:39 PM PDT 24
Finished Jul 26 05:32:46 PM PDT 24
Peak memory 232880 kb
Host smart-6348f839-c30e-48a0-8650-d2169055f043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041936860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.1041936860
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.2908130922
Short name T874
Test name
Test status
Simulation time 11456324 ps
CPU time 0.67 seconds
Started Jul 26 05:33:16 PM PDT 24
Finished Jul 26 05:33:17 PM PDT 24
Peak memory 204996 kb
Host smart-c76caa05-38e4-48fd-9944-ec82b43c150a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908130922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
2908130922
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.789221086
Short name T64
Test name
Test status
Simulation time 2789729733 ps
CPU time 20.95 seconds
Started Jul 26 05:33:16 PM PDT 24
Finished Jul 26 05:33:37 PM PDT 24
Peak memory 232860 kb
Host smart-157e54b6-72a4-45d0-9847-2596b063075c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789221086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.789221086
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.203184319
Short name T668
Test name
Test status
Simulation time 69020513 ps
CPU time 0.77 seconds
Started Jul 26 05:33:13 PM PDT 24
Finished Jul 26 05:33:14 PM PDT 24
Peak memory 207020 kb
Host smart-c80aeb9f-dd41-4c5b-8bb8-8069b514bbfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203184319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.203184319
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.1954744617
Short name T160
Test name
Test status
Simulation time 90451134895 ps
CPU time 237.39 seconds
Started Jul 26 05:33:12 PM PDT 24
Finished Jul 26 05:37:10 PM PDT 24
Peak memory 266228 kb
Host smart-8b1fa9ca-f3d3-4c14-92a7-a790731919a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954744617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.1954744617
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.151165491
Short name T413
Test name
Test status
Simulation time 32992242053 ps
CPU time 330.8 seconds
Started Jul 26 05:33:18 PM PDT 24
Finished Jul 26 05:38:49 PM PDT 24
Peak memory 256976 kb
Host smart-008a854e-b0ab-4eae-9d6e-f730916dd418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151165491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.151165491
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.3488842066
Short name T700
Test name
Test status
Simulation time 25858255716 ps
CPU time 256.89 seconds
Started Jul 26 05:33:17 PM PDT 24
Finished Jul 26 05:37:34 PM PDT 24
Peak memory 249280 kb
Host smart-27d2fbbe-67fe-4f77-8db0-7e4b9b2fde65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488842066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.3488842066
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.118535221
Short name T559
Test name
Test status
Simulation time 2668826344 ps
CPU time 9.09 seconds
Started Jul 26 05:33:16 PM PDT 24
Finished Jul 26 05:33:26 PM PDT 24
Peak memory 236600 kb
Host smart-c9274b09-6d31-481d-934b-fd45ff02154c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118535221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.118535221
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.3629833229
Short name T12
Test name
Test status
Simulation time 27221474863 ps
CPU time 202.1 seconds
Started Jul 26 05:33:16 PM PDT 24
Finished Jul 26 05:36:38 PM PDT 24
Peak memory 249312 kb
Host smart-a3254cb5-5436-4ec9-9ac6-5cbfa7b71173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629833229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmd
s.3629833229
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_intercept.2173440956
Short name T542
Test name
Test status
Simulation time 225892468 ps
CPU time 4.55 seconds
Started Jul 26 05:33:11 PM PDT 24
Finished Jul 26 05:33:16 PM PDT 24
Peak memory 232864 kb
Host smart-91fbacd9-b95c-4ce0-8ed6-35e861fae856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173440956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.2173440956
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.128520164
Short name T760
Test name
Test status
Simulation time 14524682631 ps
CPU time 42.97 seconds
Started Jul 26 05:33:14 PM PDT 24
Finished Jul 26 05:33:57 PM PDT 24
Peak memory 224728 kb
Host smart-2e6b7ea3-9349-442b-885d-e467513abc0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128520164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.128520164
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.294912995
Short name T626
Test name
Test status
Simulation time 5973466863 ps
CPU time 18.92 seconds
Started Jul 26 05:33:16 PM PDT 24
Finished Jul 26 05:33:35 PM PDT 24
Peak memory 232840 kb
Host smart-598a7854-94fb-42ad-8629-8ee0cfe28ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294912995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swap
.294912995
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.1358925718
Short name T860
Test name
Test status
Simulation time 5554877324 ps
CPU time 5.57 seconds
Started Jul 26 05:33:18 PM PDT 24
Finished Jul 26 05:33:24 PM PDT 24
Peak memory 232840 kb
Host smart-768e51f5-5088-4082-8acc-4089b50470ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358925718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.1358925718
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.1800036632
Short name T132
Test name
Test status
Simulation time 1058134553 ps
CPU time 6.75 seconds
Started Jul 26 05:33:12 PM PDT 24
Finished Jul 26 05:33:19 PM PDT 24
Peak memory 219016 kb
Host smart-68a62575-be75-47f5-98b7-7bf71724323d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1800036632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.1800036632
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.3319312172
Short name T832
Test name
Test status
Simulation time 38605032 ps
CPU time 1.02 seconds
Started Jul 26 05:33:14 PM PDT 24
Finished Jul 26 05:33:15 PM PDT 24
Peak memory 206896 kb
Host smart-c7315ab9-9b6f-4a54-b1d8-9dc1f5f7c78f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319312172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.3319312172
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.187651782
Short name T623
Test name
Test status
Simulation time 32486489785 ps
CPU time 45.5 seconds
Started Jul 26 05:33:14 PM PDT 24
Finished Jul 26 05:33:59 PM PDT 24
Peak memory 216400 kb
Host smart-1e7022cd-3bf9-4a5d-9dc6-24b544c4bd20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187651782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.187651782
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.1612207174
Short name T450
Test name
Test status
Simulation time 1772654661 ps
CPU time 5.1 seconds
Started Jul 26 05:33:15 PM PDT 24
Finished Jul 26 05:33:20 PM PDT 24
Peak memory 216420 kb
Host smart-026f17c3-8396-40a8-9680-70e0ea836d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612207174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.1612207174
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.2494117742
Short name T850
Test name
Test status
Simulation time 55813303 ps
CPU time 0.86 seconds
Started Jul 26 05:33:15 PM PDT 24
Finished Jul 26 05:33:16 PM PDT 24
Peak memory 206684 kb
Host smart-1a39dd50-c167-4f2a-a01a-66cf40f400c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494117742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.2494117742
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.1825664894
Short name T800
Test name
Test status
Simulation time 120677283 ps
CPU time 0.74 seconds
Started Jul 26 05:33:14 PM PDT 24
Finished Jul 26 05:33:15 PM PDT 24
Peak memory 206040 kb
Host smart-39eeaeed-47c3-4d82-9402-b58972c7ce07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825664894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.1825664894
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.3174719041
Short name T226
Test name
Test status
Simulation time 18658664949 ps
CPU time 17.75 seconds
Started Jul 26 05:33:08 PM PDT 24
Finished Jul 26 05:33:26 PM PDT 24
Peak memory 224728 kb
Host smart-5c714521-03d5-4517-a08b-c06734b8fb61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174719041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.3174719041
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.1797913383
Short name T718
Test name
Test status
Simulation time 12730931 ps
CPU time 0.73 seconds
Started Jul 26 05:33:18 PM PDT 24
Finished Jul 26 05:33:19 PM PDT 24
Peak memory 205864 kb
Host smart-05951a12-ff9e-4751-8dd7-8e91279b36d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797913383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
1797913383
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.3953082220
Short name T885
Test name
Test status
Simulation time 1804181577 ps
CPU time 11.98 seconds
Started Jul 26 05:33:18 PM PDT 24
Finished Jul 26 05:33:30 PM PDT 24
Peak memory 232824 kb
Host smart-0e0204a1-18e3-4f39-8a19-d48c2ad975f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953082220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.3953082220
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.3203493929
Short name T439
Test name
Test status
Simulation time 37257380 ps
CPU time 0.8 seconds
Started Jul 26 05:33:14 PM PDT 24
Finished Jul 26 05:33:15 PM PDT 24
Peak memory 206716 kb
Host smart-0fcfdd59-763a-4c37-a5d5-5cbf433ebc32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203493929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.3203493929
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.1901364467
Short name T38
Test name
Test status
Simulation time 13141275923 ps
CPU time 66.98 seconds
Started Jul 26 05:33:12 PM PDT 24
Finished Jul 26 05:34:19 PM PDT 24
Peak memory 251096 kb
Host smart-6fd80ed8-341c-4657-b393-05ef70dbcb95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901364467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.1901364467
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.2848589623
Short name T74
Test name
Test status
Simulation time 62030503857 ps
CPU time 181.64 seconds
Started Jul 26 05:33:16 PM PDT 24
Finished Jul 26 05:36:18 PM PDT 24
Peak memory 249680 kb
Host smart-1739f447-0777-4902-bf64-3e27fbbb1f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848589623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.2848589623
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.2131470368
Short name T454
Test name
Test status
Simulation time 13883440657 ps
CPU time 147.03 seconds
Started Jul 26 05:33:17 PM PDT 24
Finished Jul 26 05:35:44 PM PDT 24
Peak memory 253100 kb
Host smart-78169607-6ff8-4600-93b0-c273335a2ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131470368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.2131470368
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.520105870
Short name T267
Test name
Test status
Simulation time 2464447881 ps
CPU time 8.85 seconds
Started Jul 26 05:33:16 PM PDT 24
Finished Jul 26 05:33:25 PM PDT 24
Peak memory 224680 kb
Host smart-9e020c1f-8be7-4858-b4a7-43acf5475295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520105870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.520105870
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.345842956
Short name T177
Test name
Test status
Simulation time 58041158053 ps
CPU time 212.26 seconds
Started Jul 26 05:33:17 PM PDT 24
Finished Jul 26 05:36:50 PM PDT 24
Peak memory 255004 kb
Host smart-2e626a7b-a585-4b5c-af00-e38e378ad9a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345842956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmds
.345842956
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_intercept.4084062306
Short name T969
Test name
Test status
Simulation time 484959098 ps
CPU time 4.37 seconds
Started Jul 26 05:33:17 PM PDT 24
Finished Jul 26 05:33:21 PM PDT 24
Peak memory 232868 kb
Host smart-c2739aed-5c51-4832-a255-c27a91331fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084062306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.4084062306
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.939163357
Short name T866
Test name
Test status
Simulation time 1250389116 ps
CPU time 14.09 seconds
Started Jul 26 05:33:18 PM PDT 24
Finished Jul 26 05:33:32 PM PDT 24
Peak memory 249256 kb
Host smart-d1a2e19a-988b-4c8e-b9ad-c5b1707e4ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939163357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.939163357
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.1805182137
Short name T655
Test name
Test status
Simulation time 4736090719 ps
CPU time 6.66 seconds
Started Jul 26 05:33:18 PM PDT 24
Finished Jul 26 05:33:24 PM PDT 24
Peak memory 232920 kb
Host smart-aed4e66f-c819-48e7-aacd-ecea9c7bfaf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805182137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.1805182137
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.1260724341
Short name T813
Test name
Test status
Simulation time 1396275131 ps
CPU time 5.99 seconds
Started Jul 26 05:33:15 PM PDT 24
Finished Jul 26 05:33:21 PM PDT 24
Peak memory 232848 kb
Host smart-c3661b18-dda3-4576-9a93-16ed0a313fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260724341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.1260724341
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.999889763
Short name T130
Test name
Test status
Simulation time 73088991 ps
CPU time 3.89 seconds
Started Jul 26 05:33:13 PM PDT 24
Finished Jul 26 05:33:17 PM PDT 24
Peak memory 223176 kb
Host smart-cb059622-6461-4697-975a-6863662040b9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=999889763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dire
ct.999889763
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.2499400871
Short name T959
Test name
Test status
Simulation time 2116109544 ps
CPU time 10.28 seconds
Started Jul 26 05:33:13 PM PDT 24
Finished Jul 26 05:33:24 PM PDT 24
Peak memory 216388 kb
Host smart-d3dd408d-3c58-483d-b3ab-0869f1f6ff72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499400871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.2499400871
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.387669633
Short name T713
Test name
Test status
Simulation time 19663751037 ps
CPU time 5.47 seconds
Started Jul 26 05:33:17 PM PDT 24
Finished Jul 26 05:33:23 PM PDT 24
Peak memory 216404 kb
Host smart-fe36641c-d73a-4286-8c7f-ebf4b0e0be9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387669633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.387669633
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.425791911
Short name T797
Test name
Test status
Simulation time 325162078 ps
CPU time 7.31 seconds
Started Jul 26 05:33:15 PM PDT 24
Finished Jul 26 05:33:23 PM PDT 24
Peak memory 216664 kb
Host smart-b23872fb-58dc-4e70-aef7-926a5c547e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425791911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.425791911
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.710617190
Short name T299
Test name
Test status
Simulation time 201323551 ps
CPU time 0.73 seconds
Started Jul 26 05:33:14 PM PDT 24
Finished Jul 26 05:33:15 PM PDT 24
Peak memory 206076 kb
Host smart-18f7334e-f86c-4ead-a5bc-51eab2993078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710617190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.710617190
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.2676329671
Short name T644
Test name
Test status
Simulation time 581410342 ps
CPU time 10.15 seconds
Started Jul 26 05:33:16 PM PDT 24
Finished Jul 26 05:33:27 PM PDT 24
Peak memory 236136 kb
Host smart-4fa1ed16-f43a-4bce-81b6-1f9aebf6931a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676329671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.2676329671
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.1116262562
Short name T830
Test name
Test status
Simulation time 15458057 ps
CPU time 0.76 seconds
Started Jul 26 05:33:24 PM PDT 24
Finished Jul 26 05:33:25 PM PDT 24
Peak memory 205488 kb
Host smart-c647600c-04e8-45ae-9f57-183d1801f3e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116262562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
1116262562
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.1432345345
Short name T859
Test name
Test status
Simulation time 1774249379 ps
CPU time 4.36 seconds
Started Jul 26 05:33:19 PM PDT 24
Finished Jul 26 05:33:24 PM PDT 24
Peak memory 224576 kb
Host smart-5ea498af-d805-478e-a1df-fb0cf24f8d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432345345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.1432345345
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.2190329292
Short name T460
Test name
Test status
Simulation time 33413820 ps
CPU time 0.77 seconds
Started Jul 26 05:33:17 PM PDT 24
Finished Jul 26 05:33:18 PM PDT 24
Peak memory 206716 kb
Host smart-05c24e79-c45d-49a4-a6de-f748f6f46234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190329292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.2190329292
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.4044554170
Short name T323
Test name
Test status
Simulation time 1175663953 ps
CPU time 24.95 seconds
Started Jul 26 05:33:24 PM PDT 24
Finished Jul 26 05:33:49 PM PDT 24
Peak memory 253932 kb
Host smart-9dde8c0e-eae9-476e-8301-16b599d1f4df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044554170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.4044554170
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.294270345
Short name T809
Test name
Test status
Simulation time 19331470147 ps
CPU time 51.19 seconds
Started Jul 26 05:33:23 PM PDT 24
Finished Jul 26 05:34:14 PM PDT 24
Peak memory 249096 kb
Host smart-9943435d-1787-499b-a89a-cc0bfa958fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294270345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idle
.294270345
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.1061160515
Short name T279
Test name
Test status
Simulation time 17445768037 ps
CPU time 45.62 seconds
Started Jul 26 05:33:19 PM PDT 24
Finished Jul 26 05:34:04 PM PDT 24
Peak memory 232840 kb
Host smart-4c592b7d-bec2-46b4-a9ab-39fdfb5923ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061160515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.1061160515
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.4203462920
Short name T710
Test name
Test status
Simulation time 17805992108 ps
CPU time 123.51 seconds
Started Jul 26 05:33:21 PM PDT 24
Finished Jul 26 05:35:24 PM PDT 24
Peak memory 256888 kb
Host smart-055662e1-80dc-4782-ab6a-339dc97ad687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203462920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmd
s.4203462920
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_intercept.4294883998
Short name T200
Test name
Test status
Simulation time 1603092584 ps
CPU time 16.09 seconds
Started Jul 26 05:33:15 PM PDT 24
Finished Jul 26 05:33:32 PM PDT 24
Peak memory 232820 kb
Host smart-14507060-e48b-4bb2-93cc-0fe63974a01a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294883998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.4294883998
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.728007805
Short name T693
Test name
Test status
Simulation time 1614592244 ps
CPU time 13.99 seconds
Started Jul 26 05:33:19 PM PDT 24
Finished Jul 26 05:33:33 PM PDT 24
Peak memory 232712 kb
Host smart-2ac14d20-1948-4d1a-954e-1a6f5906f7dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728007805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.728007805
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.910317924
Short name T600
Test name
Test status
Simulation time 536521279 ps
CPU time 5.99 seconds
Started Jul 26 05:33:16 PM PDT 24
Finished Jul 26 05:33:22 PM PDT 24
Peak memory 237956 kb
Host smart-921dfbea-5f9a-4873-86f0-6947d7f7fa3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910317924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swap
.910317924
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.2916221291
Short name T897
Test name
Test status
Simulation time 2316589686 ps
CPU time 10.02 seconds
Started Jul 26 05:33:18 PM PDT 24
Finished Jul 26 05:33:28 PM PDT 24
Peak memory 232928 kb
Host smart-e4548f15-18f0-42d1-98d7-28cb2db85733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916221291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.2916221291
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.1611182781
Short name T45
Test name
Test status
Simulation time 1688958935 ps
CPU time 13.17 seconds
Started Jul 26 05:33:25 PM PDT 24
Finished Jul 26 05:33:39 PM PDT 24
Peak memory 221716 kb
Host smart-764f0ef8-eaa7-4629-8c6a-b23c69af3736
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1611182781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.1611182781
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.2593993424
Short name T386
Test name
Test status
Simulation time 95263712021 ps
CPU time 243.91 seconds
Started Jul 26 05:33:27 PM PDT 24
Finished Jul 26 05:37:31 PM PDT 24
Peak memory 249368 kb
Host smart-708ddef4-af69-43fe-a654-bf9f6a3e0012
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593993424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.2593993424
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.2599230388
Short name T390
Test name
Test status
Simulation time 11624317765 ps
CPU time 56.7 seconds
Started Jul 26 05:33:18 PM PDT 24
Finished Jul 26 05:34:15 PM PDT 24
Peak memory 216420 kb
Host smart-b11a93d4-8179-43cf-8dce-af0779fcae4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599230388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.2599230388
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.1583991886
Short name T619
Test name
Test status
Simulation time 5678043926 ps
CPU time 15.12 seconds
Started Jul 26 05:33:16 PM PDT 24
Finished Jul 26 05:33:31 PM PDT 24
Peak memory 216452 kb
Host smart-6f419899-3748-4771-9ad8-bc2f5c137b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583991886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.1583991886
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.3677106349
Short name T537
Test name
Test status
Simulation time 150089741 ps
CPU time 2.45 seconds
Started Jul 26 05:33:16 PM PDT 24
Finished Jul 26 05:33:18 PM PDT 24
Peak memory 216376 kb
Host smart-d8ca1e56-b944-4377-8442-22fa12f4bc04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677106349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.3677106349
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.3912082756
Short name T290
Test name
Test status
Simulation time 105228076 ps
CPU time 0.79 seconds
Started Jul 26 05:33:14 PM PDT 24
Finished Jul 26 05:33:15 PM PDT 24
Peak memory 206076 kb
Host smart-42fc3f45-bb63-456c-a064-ef5832911156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912082756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.3912082756
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.1078703108
Short name T408
Test name
Test status
Simulation time 32742996 ps
CPU time 2.19 seconds
Started Jul 26 05:33:18 PM PDT 24
Finished Jul 26 05:33:20 PM PDT 24
Peak memory 224064 kb
Host smart-94f3c8a1-d104-4757-bd34-0c0745ed9bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078703108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.1078703108
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.19238616
Short name T66
Test name
Test status
Simulation time 19460957 ps
CPU time 0.72 seconds
Started Jul 26 05:33:23 PM PDT 24
Finished Jul 26 05:33:24 PM PDT 24
Peak memory 205036 kb
Host smart-0cf8920c-ced4-405b-8530-08fe37484e25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19238616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.19238616
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.2349127672
Short name T334
Test name
Test status
Simulation time 425098902 ps
CPU time 2.37 seconds
Started Jul 26 05:33:25 PM PDT 24
Finished Jul 26 05:33:28 PM PDT 24
Peak memory 224676 kb
Host smart-0c9d5162-7bea-4974-833e-12def576a8d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349127672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.2349127672
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.3949036156
Short name T941
Test name
Test status
Simulation time 44305516 ps
CPU time 0.78 seconds
Started Jul 26 05:33:26 PM PDT 24
Finished Jul 26 05:33:27 PM PDT 24
Peak memory 206608 kb
Host smart-173d824f-a022-43bc-86ec-86b971113689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949036156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.3949036156
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.1153948684
Short name T192
Test name
Test status
Simulation time 9568519701 ps
CPU time 46.98 seconds
Started Jul 26 05:33:23 PM PDT 24
Finished Jul 26 05:34:10 PM PDT 24
Peak memory 249324 kb
Host smart-d3c11671-3975-41b0-9e82-bacc1138d048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153948684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.1153948684
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.3827155675
Short name T73
Test name
Test status
Simulation time 120495732752 ps
CPU time 245.89 seconds
Started Jul 26 05:33:24 PM PDT 24
Finished Jul 26 05:37:30 PM PDT 24
Peak memory 254564 kb
Host smart-95dbb723-d0cb-4fea-9347-d3e79a3d9a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827155675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.3827155675
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.2608456476
Short name T173
Test name
Test status
Simulation time 562130561004 ps
CPU time 426.8 seconds
Started Jul 26 05:33:26 PM PDT 24
Finished Jul 26 05:40:33 PM PDT 24
Peak memory 264260 kb
Host smart-26fc2cb4-d0aa-429f-9819-9dfeeb6d5ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608456476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.2608456476
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.1972972444
Short name T347
Test name
Test status
Simulation time 1735641170 ps
CPU time 12.88 seconds
Started Jul 26 05:33:27 PM PDT 24
Finished Jul 26 05:33:40 PM PDT 24
Peak memory 238636 kb
Host smart-1c10585a-bb71-4479-905c-a94493215e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972972444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmd
s.1972972444
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_intercept.2833595946
Short name T225
Test name
Test status
Simulation time 161757475 ps
CPU time 2.54 seconds
Started Jul 26 05:33:25 PM PDT 24
Finished Jul 26 05:33:27 PM PDT 24
Peak memory 232904 kb
Host smart-5377ef81-6c12-4c41-afa5-aebd33bb9c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833595946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.2833595946
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.1253253752
Short name T804
Test name
Test status
Simulation time 11780011854 ps
CPU time 64.47 seconds
Started Jul 26 05:33:23 PM PDT 24
Finished Jul 26 05:34:27 PM PDT 24
Peak memory 232948 kb
Host smart-7962fc76-bd58-4a07-a05b-eb7bd993cdc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253253752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.1253253752
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.1025938652
Short name T169
Test name
Test status
Simulation time 14227244741 ps
CPU time 15.35 seconds
Started Jul 26 05:33:25 PM PDT 24
Finished Jul 26 05:33:40 PM PDT 24
Peak memory 240696 kb
Host smart-fc334ca0-82a9-46d7-a41b-432470713e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025938652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.1025938652
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.2340374349
Short name T696
Test name
Test status
Simulation time 410192589 ps
CPU time 4.55 seconds
Started Jul 26 05:33:28 PM PDT 24
Finished Jul 26 05:33:33 PM PDT 24
Peak memory 232880 kb
Host smart-444a726b-2681-4694-bec0-c675755af122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340374349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.2340374349
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.3631517507
Short name T896
Test name
Test status
Simulation time 20443373240 ps
CPU time 12.3 seconds
Started Jul 26 05:33:29 PM PDT 24
Finished Jul 26 05:33:42 PM PDT 24
Peak memory 219192 kb
Host smart-ca50632a-2a1d-4fb4-a9d8-1617e12e3609
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3631517507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.3631517507
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.1967392702
Short name T481
Test name
Test status
Simulation time 19855958843 ps
CPU time 24.63 seconds
Started Jul 26 05:33:24 PM PDT 24
Finished Jul 26 05:33:49 PM PDT 24
Peak memory 220776 kb
Host smart-c789e4f1-0043-489f-b6df-581e4a283454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967392702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.1967392702
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.2220360425
Short name T580
Test name
Test status
Simulation time 10689471322 ps
CPU time 7.4 seconds
Started Jul 26 05:33:25 PM PDT 24
Finished Jul 26 05:33:32 PM PDT 24
Peak memory 217588 kb
Host smart-f7d965ee-878d-4227-b1a0-71b8b305eab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220360425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.2220360425
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.3405650740
Short name T898
Test name
Test status
Simulation time 182765624 ps
CPU time 2.46 seconds
Started Jul 26 05:33:27 PM PDT 24
Finished Jul 26 05:33:29 PM PDT 24
Peak memory 216440 kb
Host smart-6f40f615-6f38-4e7a-86e1-5f417259343a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405650740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.3405650740
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.4249819443
Short name T447
Test name
Test status
Simulation time 28706650 ps
CPU time 0.81 seconds
Started Jul 26 05:33:26 PM PDT 24
Finished Jul 26 05:33:27 PM PDT 24
Peak memory 206096 kb
Host smart-ac916fb6-7b31-4993-912c-b548f46f9636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249819443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.4249819443
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.3965531348
Short name T681
Test name
Test status
Simulation time 390286925 ps
CPU time 5 seconds
Started Jul 26 05:33:25 PM PDT 24
Finished Jul 26 05:33:30 PM PDT 24
Peak memory 233044 kb
Host smart-4ab78de4-13b0-4909-bc0b-1062d5a21f63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965531348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.3965531348
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.4027920000
Short name T490
Test name
Test status
Simulation time 52416544 ps
CPU time 0.74 seconds
Started Jul 26 05:33:27 PM PDT 24
Finished Jul 26 05:33:28 PM PDT 24
Peak memory 205420 kb
Host smart-fa9efd4f-b70c-41df-971c-803a1a5d5fb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027920000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
4027920000
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.3212601249
Short name T343
Test name
Test status
Simulation time 424003148 ps
CPU time 4.83 seconds
Started Jul 26 05:33:26 PM PDT 24
Finished Jul 26 05:33:31 PM PDT 24
Peak memory 224504 kb
Host smart-380c4e82-edcc-4c2a-875e-ccaea47cf3ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212601249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.3212601249
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.3878267868
Short name T857
Test name
Test status
Simulation time 44648901 ps
CPU time 0.73 seconds
Started Jul 26 05:33:23 PM PDT 24
Finished Jul 26 05:33:24 PM PDT 24
Peak memory 205688 kb
Host smart-a4b3787e-3c50-4414-9614-2de979f12fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878267868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.3878267868
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.3207195251
Short name T974
Test name
Test status
Simulation time 3220820414 ps
CPU time 75.17 seconds
Started Jul 26 05:33:25 PM PDT 24
Finished Jul 26 05:34:40 PM PDT 24
Peak memory 257304 kb
Host smart-2ca02250-7e35-4d81-8cd6-0ece46d2a8d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207195251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.3207195251
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.301555296
Short name T509
Test name
Test status
Simulation time 324062936334 ps
CPU time 187.8 seconds
Started Jul 26 05:33:24 PM PDT 24
Finished Jul 26 05:36:32 PM PDT 24
Peak memory 249296 kb
Host smart-48322556-1c6c-426d-a02b-91fd10628a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301555296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idle
.301555296
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.2387172761
Short name T277
Test name
Test status
Simulation time 1599510209 ps
CPU time 11.68 seconds
Started Jul 26 05:33:29 PM PDT 24
Finished Jul 26 05:33:41 PM PDT 24
Peak memory 240888 kb
Host smart-f44f82ac-e77f-4960-9a31-9f1dba00efd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387172761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.2387172761
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.2422503811
Short name T704
Test name
Test status
Simulation time 1002935572 ps
CPU time 10.62 seconds
Started Jul 26 05:33:26 PM PDT 24
Finished Jul 26 05:33:37 PM PDT 24
Peak memory 234880 kb
Host smart-9774bebd-713f-4342-8de6-555e70de13f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422503811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmd
s.2422503811
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_intercept.2780853569
Short name T648
Test name
Test status
Simulation time 1825990589 ps
CPU time 15.46 seconds
Started Jul 26 05:33:25 PM PDT 24
Finished Jul 26 05:33:41 PM PDT 24
Peak memory 232888 kb
Host smart-44e745b0-784d-4edf-8749-5e75378579b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780853569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.2780853569
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.2404679236
Short name T622
Test name
Test status
Simulation time 559503824 ps
CPU time 5.67 seconds
Started Jul 26 05:33:25 PM PDT 24
Finished Jul 26 05:33:31 PM PDT 24
Peak memory 232776 kb
Host smart-ff942f72-6fac-47fa-8ae2-c18afdfe5e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404679236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.2404679236
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.4243879251
Short name T13
Test name
Test status
Simulation time 1941293915 ps
CPU time 3.07 seconds
Started Jul 26 05:33:25 PM PDT 24
Finished Jul 26 05:33:29 PM PDT 24
Peak memory 224620 kb
Host smart-4f9720af-6c6a-4282-a672-68c05dc87489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243879251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.4243879251
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.3199320963
Short name T631
Test name
Test status
Simulation time 5127739783 ps
CPU time 9.44 seconds
Started Jul 26 05:33:28 PM PDT 24
Finished Jul 26 05:33:37 PM PDT 24
Peak memory 232908 kb
Host smart-24406191-a284-4995-9436-516fcc99b2f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199320963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.3199320963
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.2338361022
Short name T810
Test name
Test status
Simulation time 145107604 ps
CPU time 3.3 seconds
Started Jul 26 05:33:24 PM PDT 24
Finished Jul 26 05:33:27 PM PDT 24
Peak memory 221132 kb
Host smart-eaad824d-014f-4e35-8959-36273c7c5042
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2338361022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.2338361022
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.4250506791
Short name T124
Test name
Test status
Simulation time 6521194643 ps
CPU time 64.94 seconds
Started Jul 26 05:33:25 PM PDT 24
Finished Jul 26 05:34:30 PM PDT 24
Peak memory 249392 kb
Host smart-009c6713-c455-428b-a25a-d47f9a615ffb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250506791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.4250506791
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.1445345877
Short name T831
Test name
Test status
Simulation time 11624322448 ps
CPU time 12.81 seconds
Started Jul 26 05:33:23 PM PDT 24
Finished Jul 26 05:33:35 PM PDT 24
Peak memory 216624 kb
Host smart-bd7fed79-389c-41af-b9b5-81d23be63c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445345877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.1445345877
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.923100871
Short name T558
Test name
Test status
Simulation time 490775439 ps
CPU time 3.57 seconds
Started Jul 26 05:33:23 PM PDT 24
Finished Jul 26 05:33:27 PM PDT 24
Peak memory 216428 kb
Host smart-9a258971-5aea-4c87-8faf-046cdcf9b521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923100871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.923100871
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.1633081155
Short name T470
Test name
Test status
Simulation time 1143955668 ps
CPU time 8.05 seconds
Started Jul 26 05:33:22 PM PDT 24
Finished Jul 26 05:33:30 PM PDT 24
Peak memory 216356 kb
Host smart-32bc5f04-1891-4f8e-92c4-2abb07a77bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633081155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.1633081155
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.3973142969
Short name T500
Test name
Test status
Simulation time 37519872 ps
CPU time 0.75 seconds
Started Jul 26 05:33:26 PM PDT 24
Finished Jul 26 05:33:26 PM PDT 24
Peak memory 205952 kb
Host smart-30048987-6699-45a4-be6e-6f56383f24d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973142969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.3973142969
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.2064804089
Short name T586
Test name
Test status
Simulation time 1470015132 ps
CPU time 9.14 seconds
Started Jul 26 05:33:25 PM PDT 24
Finished Jul 26 05:33:35 PM PDT 24
Peak memory 232896 kb
Host smart-362138fe-a4ff-4e79-8a3f-b38d8555589d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064804089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.2064804089
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.335973524
Short name T980
Test name
Test status
Simulation time 20340661 ps
CPU time 0.73 seconds
Started Jul 26 05:33:26 PM PDT 24
Finished Jul 26 05:33:27 PM PDT 24
Peak memory 205544 kb
Host smart-e8550cc5-8afa-4b48-a140-c03fde98dc99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335973524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.335973524
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.3420370544
Short name T456
Test name
Test status
Simulation time 249829462 ps
CPU time 3.13 seconds
Started Jul 26 05:33:30 PM PDT 24
Finished Jul 26 05:33:33 PM PDT 24
Peak memory 232832 kb
Host smart-cf13dd27-4dce-49c4-99b1-e301cc2b23a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420370544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.3420370544
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.2790382914
Short name T441
Test name
Test status
Simulation time 25016741 ps
CPU time 0.8 seconds
Started Jul 26 05:33:29 PM PDT 24
Finished Jul 26 05:33:30 PM PDT 24
Peak memory 206588 kb
Host smart-715a7ef2-70f3-4b3d-96f3-a3d84a3e64b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790382914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.2790382914
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.1338058086
Short name T824
Test name
Test status
Simulation time 66168607706 ps
CPU time 89.33 seconds
Started Jul 26 05:33:23 PM PDT 24
Finished Jul 26 05:34:52 PM PDT 24
Peak memory 253508 kb
Host smart-4aec890a-1206-43fc-bd76-c2a4f02fe3e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338058086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.1338058086
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.3085606466
Short name T39
Test name
Test status
Simulation time 14839475418 ps
CPU time 54.69 seconds
Started Jul 26 05:33:36 PM PDT 24
Finished Jul 26 05:34:31 PM PDT 24
Peak memory 240724 kb
Host smart-8e3f5b95-cabd-43fc-bcd8-d4050a0d6aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085606466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.3085606466
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.2479858862
Short name T202
Test name
Test status
Simulation time 195333972424 ps
CPU time 184.16 seconds
Started Jul 26 05:33:23 PM PDT 24
Finished Jul 26 05:36:28 PM PDT 24
Peak memory 255940 kb
Host smart-3ae72fbe-bb33-4ccf-8e44-8b6cfd8f1b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479858862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.2479858862
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.1335793809
Short name T752
Test name
Test status
Simulation time 358163907 ps
CPU time 4.39 seconds
Started Jul 26 05:33:30 PM PDT 24
Finished Jul 26 05:33:35 PM PDT 24
Peak memory 224600 kb
Host smart-8ad17d85-5d8b-447d-bf00-ece8e3dbd20a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335793809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.1335793809
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.1409562999
Short name T658
Test name
Test status
Simulation time 462822303 ps
CPU time 11.17 seconds
Started Jul 26 05:33:30 PM PDT 24
Finished Jul 26 05:33:42 PM PDT 24
Peak memory 232864 kb
Host smart-5661ba3e-f251-496e-8348-af988b7f7992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409562999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmd
s.1409562999
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_intercept.1457521544
Short name T182
Test name
Test status
Simulation time 2577875500 ps
CPU time 15.96 seconds
Started Jul 26 05:33:29 PM PDT 24
Finished Jul 26 05:33:45 PM PDT 24
Peak memory 232912 kb
Host smart-fb0c6613-bd1a-4caf-8da2-a27e1621ad74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457521544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.1457521544
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.4254047310
Short name T385
Test name
Test status
Simulation time 2683139937 ps
CPU time 34.74 seconds
Started Jul 26 05:33:26 PM PDT 24
Finished Jul 26 05:34:01 PM PDT 24
Peak memory 224676 kb
Host smart-a45c326d-8e0c-4d21-9427-f6c0a79246a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254047310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.4254047310
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.1590736842
Short name T205
Test name
Test status
Simulation time 16308935708 ps
CPU time 12.67 seconds
Started Jul 26 05:33:29 PM PDT 24
Finished Jul 26 05:33:42 PM PDT 24
Peak memory 224596 kb
Host smart-0d75c591-e441-4948-bece-0ed54c49efd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590736842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.1590736842
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.558379145
Short name T945
Test name
Test status
Simulation time 14254589658 ps
CPU time 7.11 seconds
Started Jul 26 05:33:22 PM PDT 24
Finished Jul 26 05:33:30 PM PDT 24
Peak memory 224652 kb
Host smart-29901e6b-c857-43da-b046-3d72d5544924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558379145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.558379145
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.3078144480
Short name T709
Test name
Test status
Simulation time 814289258 ps
CPU time 10.14 seconds
Started Jul 26 05:33:30 PM PDT 24
Finished Jul 26 05:33:40 PM PDT 24
Peak memory 222368 kb
Host smart-a8f64cf6-3bec-4050-848f-10cb119e1163
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3078144480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.3078144480
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.2351434105
Short name T530
Test name
Test status
Simulation time 2686350661 ps
CPU time 10.17 seconds
Started Jul 26 05:33:28 PM PDT 24
Finished Jul 26 05:33:39 PM PDT 24
Peak memory 216796 kb
Host smart-3769855b-8e23-4fe3-bdea-e02943422a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351434105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.2351434105
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.1343585514
Short name T721
Test name
Test status
Simulation time 3947332290 ps
CPU time 6.05 seconds
Started Jul 26 05:33:31 PM PDT 24
Finished Jul 26 05:33:38 PM PDT 24
Peak memory 216688 kb
Host smart-19983ce0-07c5-4914-96c7-670a8d2b4dbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343585514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.1343585514
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.582154291
Short name T548
Test name
Test status
Simulation time 259687537 ps
CPU time 2.33 seconds
Started Jul 26 05:33:25 PM PDT 24
Finished Jul 26 05:33:27 PM PDT 24
Peak memory 216408 kb
Host smart-ca969e57-2f6a-43da-ae38-2301aa987001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582154291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.582154291
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.3030581691
Short name T1000
Test name
Test status
Simulation time 14440997 ps
CPU time 0.68 seconds
Started Jul 26 05:33:30 PM PDT 24
Finished Jul 26 05:33:31 PM PDT 24
Peak memory 206076 kb
Host smart-899fb3d4-b9b3-489f-91b0-1a933e8d7d11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030581691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.3030581691
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.296340863
Short name T915
Test name
Test status
Simulation time 8323215107 ps
CPU time 10.85 seconds
Started Jul 26 05:33:28 PM PDT 24
Finished Jul 26 05:33:39 PM PDT 24
Peak memory 224748 kb
Host smart-5829d046-9f90-49b5-94d4-8f911363516f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296340863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.296340863
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.762629537
Short name T707
Test name
Test status
Simulation time 23594149 ps
CPU time 0.72 seconds
Started Jul 26 05:33:27 PM PDT 24
Finished Jul 26 05:33:28 PM PDT 24
Peak memory 205008 kb
Host smart-bf79a1c5-d6db-4f0a-9d06-3427615df1dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762629537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.762629537
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.110769145
Short name T211
Test name
Test status
Simulation time 4280876766 ps
CPU time 10.63 seconds
Started Jul 26 05:33:30 PM PDT 24
Finished Jul 26 05:33:41 PM PDT 24
Peak memory 232836 kb
Host smart-99b62bf0-8716-433a-acaa-21b220506459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110769145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.110769145
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.2017727055
Short name T786
Test name
Test status
Simulation time 44974591 ps
CPU time 0.78 seconds
Started Jul 26 05:33:26 PM PDT 24
Finished Jul 26 05:33:27 PM PDT 24
Peak memory 206704 kb
Host smart-651f8d17-a935-4884-a24e-dd23167f080f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017727055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.2017727055
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.526906721
Short name T522
Test name
Test status
Simulation time 15018026795 ps
CPU time 113.98 seconds
Started Jul 26 05:33:37 PM PDT 24
Finished Jul 26 05:35:31 PM PDT 24
Peak memory 254384 kb
Host smart-bce50b88-6d65-4c2d-9b28-b1abdebdfe00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526906721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.526906721
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.3862431586
Short name T649
Test name
Test status
Simulation time 17986281466 ps
CPU time 161.9 seconds
Started Jul 26 05:33:37 PM PDT 24
Finished Jul 26 05:36:19 PM PDT 24
Peak memory 257104 kb
Host smart-7645d11a-7353-485d-87a7-6cec09d086c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862431586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.3862431586
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.960046778
Short name T736
Test name
Test status
Simulation time 999840935 ps
CPU time 11 seconds
Started Jul 26 05:33:32 PM PDT 24
Finished Jul 26 05:33:43 PM PDT 24
Peak memory 240100 kb
Host smart-3c102873-f4b8-4243-a696-188de8f876da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960046778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.960046778
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.1054939995
Short name T453
Test name
Test status
Simulation time 5035112379 ps
CPU time 29.51 seconds
Started Jul 26 05:33:30 PM PDT 24
Finished Jul 26 05:34:00 PM PDT 24
Peak memory 224664 kb
Host smart-545ccd32-19c9-426f-afe2-4193d7be06a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054939995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmd
s.1054939995
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_intercept.2049669605
Short name T340
Test name
Test status
Simulation time 37111453 ps
CPU time 2.56 seconds
Started Jul 26 05:33:31 PM PDT 24
Finished Jul 26 05:33:34 PM PDT 24
Peak memory 232452 kb
Host smart-4eacf66b-6966-4fa8-b172-001f0c886314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049669605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.2049669605
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.966957621
Short name T697
Test name
Test status
Simulation time 405583298 ps
CPU time 3.32 seconds
Started Jul 26 05:33:30 PM PDT 24
Finished Jul 26 05:33:33 PM PDT 24
Peak memory 224612 kb
Host smart-f29acadb-8259-4685-99e8-8850b1fea45a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966957621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.966957621
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.2856473129
Short name T839
Test name
Test status
Simulation time 6314497356 ps
CPU time 12.6 seconds
Started Jul 26 05:33:35 PM PDT 24
Finished Jul 26 05:33:48 PM PDT 24
Peak memory 232832 kb
Host smart-4195c9fd-5532-420a-bc95-68db44dbba66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856473129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.2856473129
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.2147067160
Short name T764
Test name
Test status
Simulation time 204520227 ps
CPU time 2.48 seconds
Started Jul 26 05:33:31 PM PDT 24
Finished Jul 26 05:33:34 PM PDT 24
Peak memory 218548 kb
Host smart-7949f13e-973e-4bba-bf79-f27f333e9864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147067160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.2147067160
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.2955620024
Short name T662
Test name
Test status
Simulation time 271754640 ps
CPU time 6.26 seconds
Started Jul 26 05:33:37 PM PDT 24
Finished Jul 26 05:33:43 PM PDT 24
Peak memory 222576 kb
Host smart-440c91df-ff36-42ca-99c7-c08b79425ced
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2955620024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.2955620024
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.2456457236
Short name T145
Test name
Test status
Simulation time 426748593820 ps
CPU time 603.52 seconds
Started Jul 26 05:33:25 PM PDT 24
Finished Jul 26 05:43:29 PM PDT 24
Peak memory 265088 kb
Host smart-c7b05dd0-5dd8-42aa-a7c8-098ed0fde4a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456457236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.2456457236
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.3697296226
Short name T591
Test name
Test status
Simulation time 18992506093 ps
CPU time 48.49 seconds
Started Jul 26 05:33:25 PM PDT 24
Finished Jul 26 05:34:14 PM PDT 24
Peak memory 216672 kb
Host smart-7015fd32-a921-457e-a1c5-65e26ac68bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697296226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.3697296226
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.1752688869
Short name T307
Test name
Test status
Simulation time 5002980860 ps
CPU time 3.88 seconds
Started Jul 26 05:33:30 PM PDT 24
Finished Jul 26 05:33:34 PM PDT 24
Peak memory 216440 kb
Host smart-1b76b6e5-8432-4eb9-8394-b9226ed18a36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752688869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.1752688869
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.4220674434
Short name T603
Test name
Test status
Simulation time 70451473 ps
CPU time 1.32 seconds
Started Jul 26 05:33:31 PM PDT 24
Finished Jul 26 05:33:32 PM PDT 24
Peak memory 216404 kb
Host smart-3a67c904-768e-425e-93f9-2bf620e3cbdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220674434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.4220674434
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.1426842543
Short name T292
Test name
Test status
Simulation time 97060788 ps
CPU time 0.8 seconds
Started Jul 26 05:33:33 PM PDT 24
Finished Jul 26 05:33:34 PM PDT 24
Peak memory 206076 kb
Host smart-25189dab-06fe-4901-a3fe-b50b92da0e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426842543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.1426842543
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.1844134874
Short name T473
Test name
Test status
Simulation time 5361358942 ps
CPU time 9.58 seconds
Started Jul 26 05:33:31 PM PDT 24
Finished Jul 26 05:33:41 PM PDT 24
Peak memory 236688 kb
Host smart-6d0689f3-af19-48c4-bf52-a26b033e2c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844134874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.1844134874
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.3883446220
Short name T1009
Test name
Test status
Simulation time 11651517 ps
CPU time 0.74 seconds
Started Jul 26 05:33:34 PM PDT 24
Finished Jul 26 05:33:35 PM PDT 24
Peak memory 205468 kb
Host smart-f1021b3d-cf7c-48fb-84ea-99e391f80240
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883446220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
3883446220
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.2353375783
Short name T82
Test name
Test status
Simulation time 1937109506 ps
CPU time 7.39 seconds
Started Jul 26 05:33:38 PM PDT 24
Finished Jul 26 05:33:46 PM PDT 24
Peak memory 232880 kb
Host smart-cff634f9-24fb-4746-9d4c-7791a8d80e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353375783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.2353375783
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.4030302829
Short name T819
Test name
Test status
Simulation time 61402251 ps
CPU time 0.8 seconds
Started Jul 26 05:33:30 PM PDT 24
Finished Jul 26 05:33:31 PM PDT 24
Peak memory 206672 kb
Host smart-c5ec9dd7-4049-4f4f-b832-89a48718b34e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030302829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.4030302829
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.1820741327
Short name T123
Test name
Test status
Simulation time 4777297920 ps
CPU time 65.96 seconds
Started Jul 26 05:33:33 PM PDT 24
Finished Jul 26 05:34:40 PM PDT 24
Peak memory 249352 kb
Host smart-69cf274c-76ff-4df6-98c9-7b2fa08853eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820741327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.1820741327
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.3455941654
Short name T120
Test name
Test status
Simulation time 53045907523 ps
CPU time 229.91 seconds
Started Jul 26 05:33:35 PM PDT 24
Finished Jul 26 05:37:26 PM PDT 24
Peak memory 253072 kb
Host smart-100e02b4-4293-4022-aa45-2003e7fce44b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455941654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.3455941654
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.3001341451
Short name T880
Test name
Test status
Simulation time 260010708 ps
CPU time 5.69 seconds
Started Jul 26 05:33:34 PM PDT 24
Finished Jul 26 05:33:39 PM PDT 24
Peak memory 224568 kb
Host smart-f0192c82-c8d6-494e-ab9d-f93651766ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001341451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.3001341451
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.4153609872
Short name T566
Test name
Test status
Simulation time 3708160697 ps
CPU time 34.27 seconds
Started Jul 26 05:33:41 PM PDT 24
Finished Jul 26 05:34:16 PM PDT 24
Peak memory 249300 kb
Host smart-8645cedb-bfc6-4516-826b-fe6abcd3ff32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153609872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmd
s.4153609872
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_intercept.3616457864
Short name T48
Test name
Test status
Simulation time 407612748 ps
CPU time 6.53 seconds
Started Jul 26 05:33:36 PM PDT 24
Finished Jul 26 05:33:43 PM PDT 24
Peak memory 224544 kb
Host smart-774aa96d-db09-4f67-9109-73c0b48a039b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616457864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.3616457864
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.3899248274
Short name T529
Test name
Test status
Simulation time 9083117536 ps
CPU time 79.28 seconds
Started Jul 26 05:33:33 PM PDT 24
Finished Jul 26 05:34:53 PM PDT 24
Peak memory 232700 kb
Host smart-3fda0845-3c1c-4c30-aeb1-0aaf9a340552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899248274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.3899248274
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.3063474580
Short name T498
Test name
Test status
Simulation time 124855241 ps
CPU time 2.41 seconds
Started Jul 26 05:33:40 PM PDT 24
Finished Jul 26 05:33:43 PM PDT 24
Peak memory 224592 kb
Host smart-e7840f4f-872a-45b1-bac8-540187bafad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063474580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.3063474580
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.621703281
Short name T952
Test name
Test status
Simulation time 5836858694 ps
CPU time 10.88 seconds
Started Jul 26 05:33:34 PM PDT 24
Finished Jul 26 05:33:45 PM PDT 24
Peak memory 240772 kb
Host smart-b7491ba6-779b-452d-9974-5009b36601c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621703281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.621703281
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.3451678758
Short name T835
Test name
Test status
Simulation time 3617553237 ps
CPU time 11.58 seconds
Started Jul 26 05:33:34 PM PDT 24
Finished Jul 26 05:33:46 PM PDT 24
Peak memory 219244 kb
Host smart-8ea5098a-69ad-4680-9281-f10629ba95b2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3451678758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.3451678758
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.3547535461
Short name T42
Test name
Test status
Simulation time 57937898491 ps
CPU time 599.38 seconds
Started Jul 26 05:33:34 PM PDT 24
Finished Jul 26 05:43:33 PM PDT 24
Peak memory 281264 kb
Host smart-d6aabd0e-add9-4d54-abb8-61cc8e12572f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547535461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.3547535461
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.3252042556
Short name T872
Test name
Test status
Simulation time 1501994741 ps
CPU time 5.15 seconds
Started Jul 26 05:33:35 PM PDT 24
Finished Jul 26 05:33:40 PM PDT 24
Peak memory 216640 kb
Host smart-b3951a9f-cb08-4926-9ca0-86ba4c3a2e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252042556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.3252042556
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.1733933721
Short name T912
Test name
Test status
Simulation time 1373137227 ps
CPU time 4.51 seconds
Started Jul 26 05:33:30 PM PDT 24
Finished Jul 26 05:33:35 PM PDT 24
Peak memory 216360 kb
Host smart-1dc085d4-50b9-434d-8119-a4584461b205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733933721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.1733933721
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.673024190
Short name T368
Test name
Test status
Simulation time 63372861 ps
CPU time 1.07 seconds
Started Jul 26 05:33:42 PM PDT 24
Finished Jul 26 05:33:43 PM PDT 24
Peak memory 207944 kb
Host smart-368c9e03-23b8-4d03-a24f-8d646c875afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673024190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.673024190
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.1643377340
Short name T400
Test name
Test status
Simulation time 13206275 ps
CPU time 0.73 seconds
Started Jul 26 05:33:40 PM PDT 24
Finished Jul 26 05:33:41 PM PDT 24
Peak memory 205692 kb
Host smart-077dd68e-d62a-495f-ab33-fc5295cb0221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643377340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.1643377340
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.2557019926
Short name T388
Test name
Test status
Simulation time 299637361 ps
CPU time 3.69 seconds
Started Jul 26 05:33:35 PM PDT 24
Finished Jul 26 05:33:39 PM PDT 24
Peak memory 224688 kb
Host smart-a336ac40-4d61-45be-b092-6defcf1424e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557019926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.2557019926
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.1986401193
Short name T908
Test name
Test status
Simulation time 37827486 ps
CPU time 0.73 seconds
Started Jul 26 05:33:34 PM PDT 24
Finished Jul 26 05:33:35 PM PDT 24
Peak memory 204940 kb
Host smart-958ce732-89d9-4e0d-a1af-ad50ed37a911
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986401193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
1986401193
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.665269501
Short name T842
Test name
Test status
Simulation time 3214589132 ps
CPU time 11.74 seconds
Started Jul 26 05:33:40 PM PDT 24
Finished Jul 26 05:33:52 PM PDT 24
Peak memory 232868 kb
Host smart-072b2db0-ef6e-4fe7-a7bf-17bfc883d927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665269501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.665269501
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.1254315123
Short name T791
Test name
Test status
Simulation time 15295273 ps
CPU time 0.74 seconds
Started Jul 26 05:33:38 PM PDT 24
Finished Jul 26 05:33:39 PM PDT 24
Peak memory 207028 kb
Host smart-bc611452-7708-4875-a0e3-915f98b2ce6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254315123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.1254315123
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.2103033133
Short name T995
Test name
Test status
Simulation time 10031917688 ps
CPU time 54.33 seconds
Started Jul 26 05:33:41 PM PDT 24
Finished Jul 26 05:34:36 PM PDT 24
Peak memory 240136 kb
Host smart-7294906e-36c9-48cf-8db6-b95a89e7b229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103033133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.2103033133
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.1706931214
Short name T326
Test name
Test status
Simulation time 451496404 ps
CPU time 2.76 seconds
Started Jul 26 05:33:40 PM PDT 24
Finished Jul 26 05:33:43 PM PDT 24
Peak memory 217884 kb
Host smart-46f9167f-4de1-4f7c-a560-731e406cca54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706931214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.1706931214
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.2239647152
Short name T656
Test name
Test status
Simulation time 1788565337 ps
CPU time 17.97 seconds
Started Jul 26 05:33:42 PM PDT 24
Finished Jul 26 05:34:00 PM PDT 24
Peak memory 232836 kb
Host smart-28b92e6d-cda1-4531-a930-d3ca01894281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239647152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.2239647152
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.1480366936
Short name T85
Test name
Test status
Simulation time 1953648011 ps
CPU time 14.42 seconds
Started Jul 26 05:33:32 PM PDT 24
Finished Jul 26 05:33:47 PM PDT 24
Peak memory 249208 kb
Host smart-89205346-2a0a-4b99-85c0-7da51cc64b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480366936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmd
s.1480366936
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/18.spi_device_intercept.1147783579
Short name T962
Test name
Test status
Simulation time 4970179230 ps
CPU time 3.9 seconds
Started Jul 26 05:33:34 PM PDT 24
Finished Jul 26 05:33:38 PM PDT 24
Peak memory 219080 kb
Host smart-4db0c3b6-1e7d-4cbd-8a39-be453fc5befd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147783579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.1147783579
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.1074929453
Short name T480
Test name
Test status
Simulation time 3486079473 ps
CPU time 18.58 seconds
Started Jul 26 05:33:37 PM PDT 24
Finished Jul 26 05:33:56 PM PDT 24
Peak memory 232936 kb
Host smart-947a14ab-961c-4f1b-ac63-8ab5434623d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074929453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.1074929453
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.813002484
Short name T624
Test name
Test status
Simulation time 35500912 ps
CPU time 2.42 seconds
Started Jul 26 05:33:35 PM PDT 24
Finished Jul 26 05:33:38 PM PDT 24
Peak memory 232668 kb
Host smart-bf7454f1-fbcc-4938-8392-326fb3eed10f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813002484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swap
.813002484
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.1306199786
Short name T369
Test name
Test status
Simulation time 133951394 ps
CPU time 2.39 seconds
Started Jul 26 05:33:35 PM PDT 24
Finished Jul 26 05:33:38 PM PDT 24
Peak memory 232532 kb
Host smart-7f220dc0-5ac7-4de2-8ddc-8855e9700d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306199786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.1306199786
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.513468526
Short name T496
Test name
Test status
Simulation time 1497977494 ps
CPU time 13.46 seconds
Started Jul 26 05:33:40 PM PDT 24
Finished Jul 26 05:33:54 PM PDT 24
Peak memory 222028 kb
Host smart-90f2faa7-f9ca-46ca-8a60-20faf1626c41
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=513468526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dire
ct.513468526
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.2971193292
Short name T653
Test name
Test status
Simulation time 43031469423 ps
CPU time 237.02 seconds
Started Jul 26 05:33:40 PM PDT 24
Finished Jul 26 05:37:38 PM PDT 24
Peak memory 262060 kb
Host smart-54741d82-071a-4b23-9773-9085c2d9dbd8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971193292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.2971193292
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.4017760203
Short name T877
Test name
Test status
Simulation time 3052485010 ps
CPU time 15.47 seconds
Started Jul 26 05:33:33 PM PDT 24
Finished Jul 26 05:33:49 PM PDT 24
Peak memory 216492 kb
Host smart-8263789c-21f1-4150-9cdd-907ec81d7428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017760203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.4017760203
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.3091539687
Short name T805
Test name
Test status
Simulation time 10473507507 ps
CPU time 15.55 seconds
Started Jul 26 05:33:34 PM PDT 24
Finished Jul 26 05:33:50 PM PDT 24
Peak memory 216380 kb
Host smart-31d9e8bc-cbed-4a75-9804-4a446f28f9dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091539687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.3091539687
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.3795705680
Short name T983
Test name
Test status
Simulation time 32302972 ps
CPU time 1.18 seconds
Started Jul 26 05:33:33 PM PDT 24
Finished Jul 26 05:33:35 PM PDT 24
Peak memory 207936 kb
Host smart-a79f20ae-c76f-4a58-a527-9c8ef047f42a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795705680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.3795705680
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.3215292860
Short name T617
Test name
Test status
Simulation time 120272222 ps
CPU time 1.03 seconds
Started Jul 26 05:33:37 PM PDT 24
Finished Jul 26 05:33:38 PM PDT 24
Peak memory 206076 kb
Host smart-fae07271-13c9-4936-b43e-a8939660cace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215292860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.3215292860
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.884166590
Short name T165
Test name
Test status
Simulation time 382049654 ps
CPU time 6.54 seconds
Started Jul 26 05:33:43 PM PDT 24
Finished Jul 26 05:33:49 PM PDT 24
Peak memory 224556 kb
Host smart-917ba978-91b6-454b-9408-133ce36f8332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884166590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.884166590
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.3092059499
Short name T706
Test name
Test status
Simulation time 24911291 ps
CPU time 0.72 seconds
Started Jul 26 05:33:35 PM PDT 24
Finished Jul 26 05:33:36 PM PDT 24
Peak memory 206068 kb
Host smart-5ebadecb-9b09-485b-ac13-be38f56aea6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092059499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
3092059499
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.2098619305
Short name T417
Test name
Test status
Simulation time 1162190921 ps
CPU time 6.32 seconds
Started Jul 26 05:33:37 PM PDT 24
Finished Jul 26 05:33:43 PM PDT 24
Peak memory 224564 kb
Host smart-90bfafdf-8ee5-49f7-b997-04a67546b975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098619305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.2098619305
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.3546161876
Short name T722
Test name
Test status
Simulation time 67486331 ps
CPU time 0.77 seconds
Started Jul 26 05:33:38 PM PDT 24
Finished Jul 26 05:33:39 PM PDT 24
Peak memory 207024 kb
Host smart-057bb256-4779-475a-bda8-699551187ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546161876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.3546161876
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.85152606
Short name T614
Test name
Test status
Simulation time 7445278550 ps
CPU time 50.99 seconds
Started Jul 26 05:33:40 PM PDT 24
Finished Jul 26 05:34:31 PM PDT 24
Peak memory 250692 kb
Host smart-531554d8-b58f-4644-98ba-f037e9671ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85152606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.85152606
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.2129086092
Short name T27
Test name
Test status
Simulation time 41278300800 ps
CPU time 190.86 seconds
Started Jul 26 05:33:45 PM PDT 24
Finished Jul 26 05:36:56 PM PDT 24
Peak memory 249360 kb
Host smart-279f0b04-946a-4071-b79e-76240b001836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129086092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.2129086092
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.307956636
Short name T858
Test name
Test status
Simulation time 102948947939 ps
CPU time 216.09 seconds
Started Jul 26 05:33:46 PM PDT 24
Finished Jul 26 05:37:22 PM PDT 24
Peak memory 257532 kb
Host smart-9d7c3ddd-10c3-4afc-beb6-ba9fe4bf376e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307956636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idle
.307956636
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.1652332640
Short name T685
Test name
Test status
Simulation time 90837394 ps
CPU time 4.09 seconds
Started Jul 26 05:33:36 PM PDT 24
Finished Jul 26 05:33:40 PM PDT 24
Peak memory 232872 kb
Host smart-cb90a5e4-7391-47b4-a07e-b5bd42248b3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652332640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.1652332640
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.3422072299
Short name T158
Test name
Test status
Simulation time 29694982617 ps
CPU time 213.88 seconds
Started Jul 26 05:33:35 PM PDT 24
Finished Jul 26 05:37:10 PM PDT 24
Peak memory 249236 kb
Host smart-15582200-fdde-44ff-866b-b1fc850a0469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422072299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmd
s.3422072299
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_intercept.1526760802
Short name T294
Test name
Test status
Simulation time 681465772 ps
CPU time 8.91 seconds
Started Jul 26 05:33:39 PM PDT 24
Finished Jul 26 05:33:48 PM PDT 24
Peak memory 224664 kb
Host smart-64aa4181-f6d8-4bc9-bac0-68427e9299e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526760802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.1526760802
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.1366983921
Short name T803
Test name
Test status
Simulation time 13140000270 ps
CPU time 103.9 seconds
Started Jul 26 05:33:35 PM PDT 24
Finished Jul 26 05:35:19 PM PDT 24
Peak memory 240788 kb
Host smart-242ca643-3b37-48b7-b5e4-6b5cad81a4cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366983921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.1366983921
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.1733416945
Short name T985
Test name
Test status
Simulation time 9257027257 ps
CPU time 21.62 seconds
Started Jul 26 05:33:33 PM PDT 24
Finished Jul 26 05:33:54 PM PDT 24
Peak memory 224740 kb
Host smart-9af6af6f-0340-4fa3-91ec-6b6f37bb7809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733416945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.1733416945
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.1847931533
Short name T221
Test name
Test status
Simulation time 14590139463 ps
CPU time 13.43 seconds
Started Jul 26 05:33:38 PM PDT 24
Finished Jul 26 05:33:52 PM PDT 24
Peak memory 240420 kb
Host smart-fd9c243a-d45d-4e9d-8630-6f8c28752342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847931533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.1847931533
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.2729342205
Short name T960
Test name
Test status
Simulation time 964101301 ps
CPU time 4.25 seconds
Started Jul 26 05:33:35 PM PDT 24
Finished Jul 26 05:33:39 PM PDT 24
Peak memory 222924 kb
Host smart-9c5a3aed-3689-4a46-a000-7f8a4fcf7d1f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2729342205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.2729342205
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.1390454365
Short name T405
Test name
Test status
Simulation time 2672045701 ps
CPU time 20.45 seconds
Started Jul 26 05:33:42 PM PDT 24
Finished Jul 26 05:34:03 PM PDT 24
Peak memory 216620 kb
Host smart-f201100c-ac6d-458c-8ea7-857cf7eb63f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390454365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.1390454365
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.1684656288
Short name T834
Test name
Test status
Simulation time 5915801236 ps
CPU time 9.95 seconds
Started Jul 26 05:33:40 PM PDT 24
Finished Jul 26 05:33:51 PM PDT 24
Peak memory 216472 kb
Host smart-c261aa97-9bdd-417e-8d0d-460f0502dcdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684656288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.1684656288
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.2881789543
Short name T427
Test name
Test status
Simulation time 52357519 ps
CPU time 0.94 seconds
Started Jul 26 05:33:42 PM PDT 24
Finished Jul 26 05:33:43 PM PDT 24
Peak memory 207124 kb
Host smart-14b0d8ae-66e1-4a9e-9669-f39b0b9ac033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881789543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.2881789543
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.3272800037
Short name T10
Test name
Test status
Simulation time 11035016 ps
CPU time 0.74 seconds
Started Jul 26 05:33:37 PM PDT 24
Finished Jul 26 05:33:38 PM PDT 24
Peak memory 205656 kb
Host smart-05fdd803-d470-41d7-b426-79658fcfdc52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272800037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.3272800037
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.469352345
Short name T999
Test name
Test status
Simulation time 6342040696 ps
CPU time 9.4 seconds
Started Jul 26 05:33:42 PM PDT 24
Finished Jul 26 05:33:51 PM PDT 24
Peak memory 232876 kb
Host smart-d0057873-1999-4c45-9ddb-716bcb2bbe2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469352345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.469352345
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.2129634473
Short name T504
Test name
Test status
Simulation time 6612518095 ps
CPU time 30.5 seconds
Started Jul 26 05:32:42 PM PDT 24
Finished Jul 26 05:33:13 PM PDT 24
Peak memory 224324 kb
Host smart-dc4bb3b5-9d58-490e-9497-d635d6174846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129634473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.2129634473
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.3291678970
Short name T833
Test name
Test status
Simulation time 91948266 ps
CPU time 0.78 seconds
Started Jul 26 05:32:39 PM PDT 24
Finished Jul 26 05:32:40 PM PDT 24
Peak memory 206716 kb
Host smart-f67db2d8-db50-4453-956a-0aba7a9ec723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291678970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.3291678970
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.3099041329
Short name T422
Test name
Test status
Simulation time 31665859960 ps
CPU time 230.98 seconds
Started Jul 26 05:32:37 PM PDT 24
Finished Jul 26 05:36:29 PM PDT 24
Peak memory 251512 kb
Host smart-ff0ff765-e086-40e4-bef5-2e1505ceb7aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099041329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.3099041329
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.3491394743
Short name T543
Test name
Test status
Simulation time 9595443099 ps
CPU time 84.5 seconds
Started Jul 26 05:32:41 PM PDT 24
Finished Jul 26 05:34:06 PM PDT 24
Peak memory 237564 kb
Host smart-ee1cd8bb-c964-452f-a0f6-84266ab92a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491394743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.3491394743
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.2316649258
Short name T899
Test name
Test status
Simulation time 21329497849 ps
CPU time 57.87 seconds
Started Jul 26 05:32:42 PM PDT 24
Finished Jul 26 05:33:40 PM PDT 24
Peak memory 250052 kb
Host smart-3aac3fd0-3569-4f0a-a32c-80d62d493c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316649258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.2316649258
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.2255243675
Short name T268
Test name
Test status
Simulation time 4808009094 ps
CPU time 74.99 seconds
Started Jul 26 05:32:41 PM PDT 24
Finished Jul 26 05:33:57 PM PDT 24
Peak memory 232780 kb
Host smart-59b95add-1937-44fd-8bb0-87b0e47da1b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255243675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.2255243675
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.3807210745
Short name T740
Test name
Test status
Simulation time 114449396971 ps
CPU time 192.33 seconds
Started Jul 26 05:32:37 PM PDT 24
Finished Jul 26 05:35:49 PM PDT 24
Peak memory 250108 kb
Host smart-ba7e99c5-10cb-445a-8a15-1260a6c31104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807210745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds
.3807210745
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_intercept.813808224
Short name T304
Test name
Test status
Simulation time 347183256 ps
CPU time 2.44 seconds
Started Jul 26 05:32:38 PM PDT 24
Finished Jul 26 05:32:41 PM PDT 24
Peak memory 224592 kb
Host smart-cba30926-e6f7-4bf0-86dc-0a1bc732595f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813808224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.813808224
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.3028868844
Short name T108
Test name
Test status
Simulation time 8780510425 ps
CPU time 21.75 seconds
Started Jul 26 05:32:42 PM PDT 24
Finished Jul 26 05:33:04 PM PDT 24
Peak memory 239876 kb
Host smart-8b67e5bf-4dea-4b69-b5bb-e215edf507f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028868844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.3028868844
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.712921754
Short name T314
Test name
Test status
Simulation time 60288995 ps
CPU time 2.47 seconds
Started Jul 26 05:32:38 PM PDT 24
Finished Jul 26 05:32:41 PM PDT 24
Peak memory 232464 kb
Host smart-85b613a9-c1ea-42da-a66f-9c77d897c218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712921754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap.
712921754
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.1260229354
Short name T852
Test name
Test status
Simulation time 398775149 ps
CPU time 4.33 seconds
Started Jul 26 05:32:40 PM PDT 24
Finished Jul 26 05:32:44 PM PDT 24
Peak memory 224660 kb
Host smart-08e5d437-a4b2-4342-a6dd-c7647ebef0a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260229354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.1260229354
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.212218109
Short name T838
Test name
Test status
Simulation time 1643806768 ps
CPU time 12.68 seconds
Started Jul 26 05:32:37 PM PDT 24
Finished Jul 26 05:32:50 PM PDT 24
Peak memory 220448 kb
Host smart-b8291069-d3be-4af5-8093-3ac8466e7ecb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=212218109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_direc
t.212218109
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.1876638226
Short name T59
Test name
Test status
Simulation time 1256976107 ps
CPU time 1.16 seconds
Started Jul 26 05:32:38 PM PDT 24
Finished Jul 26 05:32:39 PM PDT 24
Peak memory 235904 kb
Host smart-f1e8b624-863a-4666-8b08-1987f77b3a42
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876638226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.1876638226
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.3362449778
Short name T30
Test name
Test status
Simulation time 105994473143 ps
CPU time 496.54 seconds
Started Jul 26 05:32:41 PM PDT 24
Finished Jul 26 05:40:58 PM PDT 24
Peak memory 281512 kb
Host smart-fcf5d85e-f7ae-4303-b232-fa0d38583d4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362449778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.3362449778
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.1844928042
Short name T884
Test name
Test status
Simulation time 240867823 ps
CPU time 1.82 seconds
Started Jul 26 05:32:39 PM PDT 24
Finished Jul 26 05:32:41 PM PDT 24
Peak memory 216348 kb
Host smart-9a6f5c6e-0ee9-40eb-ab4e-c18866795c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844928042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.1844928042
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.329935929
Short name T687
Test name
Test status
Simulation time 629577187 ps
CPU time 3.49 seconds
Started Jul 26 05:32:42 PM PDT 24
Finished Jul 26 05:32:46 PM PDT 24
Peak memory 216016 kb
Host smart-c8f548af-6e96-444b-8674-fad62a16f54f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329935929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.329935929
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.3434152644
Short name T409
Test name
Test status
Simulation time 40614547 ps
CPU time 2.31 seconds
Started Jul 26 05:32:37 PM PDT 24
Finished Jul 26 05:32:40 PM PDT 24
Peak memory 216392 kb
Host smart-26288fb2-b9c3-4857-83d5-9686d4c3818e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434152644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.3434152644
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.4100837232
Short name T692
Test name
Test status
Simulation time 301134826 ps
CPU time 0.82 seconds
Started Jul 26 05:32:38 PM PDT 24
Finished Jul 26 05:32:39 PM PDT 24
Peak memory 206080 kb
Host smart-354ca78f-5eea-4883-afd1-458d1fd06628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100837232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.4100837232
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.3501441350
Short name T428
Test name
Test status
Simulation time 5530042121 ps
CPU time 12.61 seconds
Started Jul 26 05:32:44 PM PDT 24
Finished Jul 26 05:32:57 PM PDT 24
Peak memory 232908 kb
Host smart-b87dc168-82dd-4350-aa8a-fd6e0ebb51ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501441350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.3501441350
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.1621248746
Short name T886
Test name
Test status
Simulation time 15948528 ps
CPU time 0.76 seconds
Started Jul 26 05:33:48 PM PDT 24
Finished Jul 26 05:33:49 PM PDT 24
Peak memory 205512 kb
Host smart-3940b237-ecd1-4735-8b65-0c383a38b7e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621248746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
1621248746
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.1962579952
Short name T79
Test name
Test status
Simulation time 1657174666 ps
CPU time 17.71 seconds
Started Jul 26 05:33:50 PM PDT 24
Finished Jul 26 05:34:08 PM PDT 24
Peak memory 224628 kb
Host smart-4ab72de1-fc4e-4d3f-9bd3-a4ae12dc1350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962579952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.1962579952
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.3780238690
Short name T324
Test name
Test status
Simulation time 178014995 ps
CPU time 0.77 seconds
Started Jul 26 05:33:40 PM PDT 24
Finished Jul 26 05:33:41 PM PDT 24
Peak memory 207016 kb
Host smart-16272f0b-476c-4e82-b8ce-3e1e97cb3740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780238690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.3780238690
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.3819127235
Short name T72
Test name
Test status
Simulation time 2323642878 ps
CPU time 54.68 seconds
Started Jul 26 05:33:49 PM PDT 24
Finished Jul 26 05:34:44 PM PDT 24
Peak memory 273340 kb
Host smart-c2203044-85ee-4615-8e0b-bfd15a2f2d04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819127235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.3819127235
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.3846693098
Short name T350
Test name
Test status
Simulation time 5528548080 ps
CPU time 89.56 seconds
Started Jul 26 05:33:51 PM PDT 24
Finished Jul 26 05:35:20 PM PDT 24
Peak memory 254916 kb
Host smart-264c3071-fed5-419c-8ee2-e645700a89b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846693098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.3846693098
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.3729054034
Short name T233
Test name
Test status
Simulation time 61238495557 ps
CPU time 588.24 seconds
Started Jul 26 05:33:48 PM PDT 24
Finished Jul 26 05:43:36 PM PDT 24
Peak memory 262236 kb
Host smart-4afa0af1-c4f4-4c92-8523-12cf29d51f0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729054034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.3729054034
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.49160928
Short name T128
Test name
Test status
Simulation time 320979814 ps
CPU time 6.97 seconds
Started Jul 26 05:33:51 PM PDT 24
Finished Jul 26 05:33:58 PM PDT 24
Peak memory 232756 kb
Host smart-94de3b30-aa1d-48c8-b6dc-9b3bb2e58f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49160928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.49160928
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.1702555255
Short name T701
Test name
Test status
Simulation time 16275772998 ps
CPU time 137.08 seconds
Started Jul 26 05:33:48 PM PDT 24
Finished Jul 26 05:36:06 PM PDT 24
Peak memory 249312 kb
Host smart-84ff12c3-e409-4cc4-919b-8d3a38862141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702555255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmd
s.1702555255
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_intercept.4087628633
Short name T196
Test name
Test status
Simulation time 21858555611 ps
CPU time 30.91 seconds
Started Jul 26 05:33:48 PM PDT 24
Finished Jul 26 05:34:19 PM PDT 24
Peak memory 230204 kb
Host smart-f6a94128-5e63-45cf-a1d9-e75e80f92bc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087628633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.4087628633
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.568624310
Short name T795
Test name
Test status
Simulation time 105675059 ps
CPU time 3.46 seconds
Started Jul 26 05:33:50 PM PDT 24
Finished Jul 26 05:33:53 PM PDT 24
Peak memory 224596 kb
Host smart-9a45e462-ad9b-4236-9c7a-55df8243ebfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568624310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.568624310
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.1032223237
Short name T733
Test name
Test status
Simulation time 573224501 ps
CPU time 4.68 seconds
Started Jul 26 05:33:48 PM PDT 24
Finished Jul 26 05:33:53 PM PDT 24
Peak memory 239272 kb
Host smart-069d338e-a4b8-4482-839c-0b7073a3999f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032223237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.1032223237
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.2030330242
Short name T714
Test name
Test status
Simulation time 12628747651 ps
CPU time 19.78 seconds
Started Jul 26 05:33:52 PM PDT 24
Finished Jul 26 05:34:12 PM PDT 24
Peak memory 224648 kb
Host smart-fc5be9bc-e74d-4f10-a570-6a3c4ae73c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030330242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.2030330242
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.3126185799
Short name T469
Test name
Test status
Simulation time 669075286 ps
CPU time 4.39 seconds
Started Jul 26 05:33:47 PM PDT 24
Finished Jul 26 05:33:51 PM PDT 24
Peak memory 218904 kb
Host smart-04da2802-c237-45c7-8480-c936e5e2aae4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3126185799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.3126185799
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.2207935286
Short name T927
Test name
Test status
Simulation time 511588441824 ps
CPU time 693.63 seconds
Started Jul 26 05:33:47 PM PDT 24
Finished Jul 26 05:45:21 PM PDT 24
Peak memory 268568 kb
Host smart-ce2f999a-3bfb-4e68-a3ba-a6cce0fd55d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207935286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.2207935286
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.2079219752
Short name T316
Test name
Test status
Simulation time 387183180 ps
CPU time 7.72 seconds
Started Jul 26 05:33:46 PM PDT 24
Finished Jul 26 05:33:54 PM PDT 24
Peak memory 216400 kb
Host smart-d96b5383-f08b-4846-8893-84d74d898db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079219752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.2079219752
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.2028135143
Short name T6
Test name
Test status
Simulation time 8320462745 ps
CPU time 13.82 seconds
Started Jul 26 05:33:42 PM PDT 24
Finished Jul 26 05:33:56 PM PDT 24
Peak memory 216464 kb
Host smart-2f3b01f6-b6bb-408e-a49b-5ac821cad7cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028135143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.2028135143
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.4109966454
Short name T647
Test name
Test status
Simulation time 195229076 ps
CPU time 2.9 seconds
Started Jul 26 05:33:48 PM PDT 24
Finished Jul 26 05:33:51 PM PDT 24
Peak memory 216368 kb
Host smart-429f234d-1beb-49cb-8fc7-9150ef714923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109966454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.4109966454
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.978330937
Short name T535
Test name
Test status
Simulation time 478131218 ps
CPU time 1.08 seconds
Started Jul 26 05:33:49 PM PDT 24
Finished Jul 26 05:33:51 PM PDT 24
Peak memory 206984 kb
Host smart-3d3bbac1-cc80-46e7-9e39-e17e6db2a1b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978330937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.978330937
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.3964265343
Short name T203
Test name
Test status
Simulation time 881172500 ps
CPU time 5.31 seconds
Started Jul 26 05:33:50 PM PDT 24
Finished Jul 26 05:33:55 PM PDT 24
Peak memory 224676 kb
Host smart-1e96fff4-280d-4e9d-b5d6-57d46a41c2c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964265343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.3964265343
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.3695414009
Short name T680
Test name
Test status
Simulation time 10829852 ps
CPU time 0.73 seconds
Started Jul 26 05:33:51 PM PDT 24
Finished Jul 26 05:33:52 PM PDT 24
Peak memory 204896 kb
Host smart-af5ae001-0b8f-4315-a70d-cdf9f0573cfe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695414009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
3695414009
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.2695773883
Short name T213
Test name
Test status
Simulation time 411545758 ps
CPU time 6.85 seconds
Started Jul 26 05:33:49 PM PDT 24
Finished Jul 26 05:33:56 PM PDT 24
Peak memory 232792 kb
Host smart-bcc5b5b1-7d93-47c8-a107-2bdb5f3927d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695773883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.2695773883
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.3527484658
Short name T891
Test name
Test status
Simulation time 19744280 ps
CPU time 0.78 seconds
Started Jul 26 05:33:47 PM PDT 24
Finished Jul 26 05:33:48 PM PDT 24
Peak memory 206708 kb
Host smart-736c5a98-5f7d-4aa9-8732-3c070bc1d256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527484658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.3527484658
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.3477907594
Short name T942
Test name
Test status
Simulation time 57569421560 ps
CPU time 54.99 seconds
Started Jul 26 05:33:46 PM PDT 24
Finished Jul 26 05:34:42 PM PDT 24
Peak memory 249160 kb
Host smart-e1f4b171-428f-4c47-a94b-418300afbd45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477907594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.3477907594
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.1650960410
Short name T37
Test name
Test status
Simulation time 299498684860 ps
CPU time 160.98 seconds
Started Jul 26 05:33:51 PM PDT 24
Finished Jul 26 05:36:32 PM PDT 24
Peak memory 249312 kb
Host smart-1d42dc25-169d-4477-8a09-de3afd802266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650960410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.1650960410
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.541117510
Short name T395
Test name
Test status
Simulation time 34200147926 ps
CPU time 187.42 seconds
Started Jul 26 05:33:51 PM PDT 24
Finished Jul 26 05:36:58 PM PDT 24
Peak memory 253076 kb
Host smart-76abba8a-f907-4387-9be5-b569bb849920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541117510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idle
.541117510
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.1548626243
Short name T672
Test name
Test status
Simulation time 6191051794 ps
CPU time 42.02 seconds
Started Jul 26 05:33:49 PM PDT 24
Finished Jul 26 05:34:31 PM PDT 24
Peak memory 250800 kb
Host smart-96d9701e-245d-420b-8b93-ac027f759186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548626243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.1548626243
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.3691384701
Short name T159
Test name
Test status
Simulation time 4640842459 ps
CPU time 56.37 seconds
Started Jul 26 05:33:50 PM PDT 24
Finished Jul 26 05:34:47 PM PDT 24
Peak memory 255676 kb
Host smart-1ec5a4c2-4863-4afa-a218-3daace4b2952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691384701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmd
s.3691384701
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_intercept.3310066267
Short name T615
Test name
Test status
Simulation time 746790546 ps
CPU time 7.66 seconds
Started Jul 26 05:33:50 PM PDT 24
Finished Jul 26 05:33:58 PM PDT 24
Peak memory 232820 kb
Host smart-ef0b8912-580c-4c31-a082-0e031ea15a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310066267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.3310066267
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.1208413053
Short name T964
Test name
Test status
Simulation time 24759443166 ps
CPU time 42.23 seconds
Started Jul 26 05:33:49 PM PDT 24
Finished Jul 26 05:34:31 PM PDT 24
Peak memory 224688 kb
Host smart-775b9052-3e87-42da-a0cf-3706c1702192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208413053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.1208413053
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.2470960328
Short name T1002
Test name
Test status
Simulation time 331194184 ps
CPU time 3.21 seconds
Started Jul 26 05:33:49 PM PDT 24
Finished Jul 26 05:33:53 PM PDT 24
Peak memory 232760 kb
Host smart-08210d27-2d1f-4a5d-a030-c1cc7301e547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470960328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.2470960328
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.1567127279
Short name T374
Test name
Test status
Simulation time 204299597 ps
CPU time 2.34 seconds
Started Jul 26 05:33:49 PM PDT 24
Finished Jul 26 05:33:51 PM PDT 24
Peak memory 223960 kb
Host smart-7f756b61-670a-469b-bc87-f3bc1b2e7844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567127279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.1567127279
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.3700141683
Short name T126
Test name
Test status
Simulation time 468603472 ps
CPU time 4.03 seconds
Started Jul 26 05:33:49 PM PDT 24
Finished Jul 26 05:33:53 PM PDT 24
Peak memory 223124 kb
Host smart-87f0da65-c8f7-44ef-8531-4d49b1a8e5e2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3700141683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.3700141683
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.777062235
Short name T246
Test name
Test status
Simulation time 129133296610 ps
CPU time 547.51 seconds
Started Jul 26 05:33:48 PM PDT 24
Finished Jul 26 05:42:56 PM PDT 24
Peak memory 266388 kb
Host smart-e8f756f3-76e0-4c10-adb8-5fd7b4592581
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777062235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stres
s_all.777062235
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.750236933
Short name T627
Test name
Test status
Simulation time 9570565574 ps
CPU time 14.13 seconds
Started Jul 26 05:33:53 PM PDT 24
Finished Jul 26 05:34:07 PM PDT 24
Peak memory 216660 kb
Host smart-7dcbdf1b-1d6a-41b0-8c7c-032a6357fb4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750236933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.750236933
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.2616049289
Short name T459
Test name
Test status
Simulation time 4332885544 ps
CPU time 5.67 seconds
Started Jul 26 05:33:48 PM PDT 24
Finished Jul 26 05:33:54 PM PDT 24
Peak memory 216464 kb
Host smart-713d4c49-ad2f-46bf-b04d-90aaef2a24c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616049289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.2616049289
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.2107777595
Short name T682
Test name
Test status
Simulation time 80278969 ps
CPU time 1.57 seconds
Started Jul 26 05:33:47 PM PDT 24
Finished Jul 26 05:33:49 PM PDT 24
Peak memory 216404 kb
Host smart-592cfccb-ddee-4b96-b55f-b5c7f609276e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107777595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.2107777595
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.4283252731
Short name T592
Test name
Test status
Simulation time 169155505 ps
CPU time 0.89 seconds
Started Jul 26 05:33:50 PM PDT 24
Finished Jul 26 05:33:51 PM PDT 24
Peak memory 206012 kb
Host smart-99b45ca3-3cf1-492b-9167-e9c0b77bf977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283252731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.4283252731
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.999001229
Short name T855
Test name
Test status
Simulation time 919603806 ps
CPU time 7.03 seconds
Started Jul 26 05:33:48 PM PDT 24
Finished Jul 26 05:33:56 PM PDT 24
Peak memory 241216 kb
Host smart-4273c7bb-43f8-4e8e-941a-87987af16fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999001229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.999001229
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.4027946010
Short name T458
Test name
Test status
Simulation time 22719113 ps
CPU time 0.72 seconds
Started Jul 26 05:34:07 PM PDT 24
Finished Jul 26 05:34:08 PM PDT 24
Peak memory 204988 kb
Host smart-c7e9ea1d-1db2-45e1-a857-be618572dc81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027946010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
4027946010
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.394925301
Short name T81
Test name
Test status
Simulation time 197015076 ps
CPU time 2.77 seconds
Started Jul 26 05:34:06 PM PDT 24
Finished Jul 26 05:34:09 PM PDT 24
Peak memory 232848 kb
Host smart-c3bdcb62-b4aa-4985-a432-12386805b8e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394925301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.394925301
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.15040492
Short name T757
Test name
Test status
Simulation time 230326619 ps
CPU time 0.71 seconds
Started Jul 26 05:33:49 PM PDT 24
Finished Jul 26 05:33:50 PM PDT 24
Peak memory 205708 kb
Host smart-b9ef818d-395c-4d7c-94ab-c7dbf835cbcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15040492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.15040492
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.891484673
Short name T34
Test name
Test status
Simulation time 45303198903 ps
CPU time 357.77 seconds
Started Jul 26 05:34:03 PM PDT 24
Finished Jul 26 05:40:01 PM PDT 24
Peak memory 253360 kb
Host smart-9c3fc4bb-a2a9-4ffe-ba73-96ab4770a4ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891484673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.891484673
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.1303462335
Short name T826
Test name
Test status
Simulation time 21708268958 ps
CPU time 48.05 seconds
Started Jul 26 05:34:08 PM PDT 24
Finished Jul 26 05:34:56 PM PDT 24
Peak memory 251672 kb
Host smart-a8c3e7ce-44ea-42e7-9b5f-9b48addd8b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303462335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.1303462335
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.2909375528
Short name T506
Test name
Test status
Simulation time 896843696 ps
CPU time 12.16 seconds
Started Jul 26 05:34:08 PM PDT 24
Finished Jul 26 05:34:20 PM PDT 24
Peak memory 232820 kb
Host smart-6951bb8e-f523-481e-9947-32bd169cc5aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909375528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.2909375528
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.135411839
Short name T815
Test name
Test status
Simulation time 5853426219 ps
CPU time 16.05 seconds
Started Jul 26 05:34:02 PM PDT 24
Finished Jul 26 05:34:18 PM PDT 24
Peak memory 235076 kb
Host smart-ec781ac9-e5a4-407d-b052-cfeaddc03eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135411839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmds
.135411839
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_intercept.2574467504
Short name T551
Test name
Test status
Simulation time 135135298 ps
CPU time 2.6 seconds
Started Jul 26 05:34:02 PM PDT 24
Finished Jul 26 05:34:05 PM PDT 24
Peak memory 232736 kb
Host smart-710b6cbe-5a5b-41fb-bfa3-ecc45c886dea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574467504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.2574467504
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.743225034
Short name T702
Test name
Test status
Simulation time 3802358000 ps
CPU time 14.51 seconds
Started Jul 26 05:34:03 PM PDT 24
Finished Jul 26 05:34:18 PM PDT 24
Peak memory 224740 kb
Host smart-0fd3517e-c816-42ea-8909-f8a5c122df5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743225034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.743225034
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.179386826
Short name T474
Test name
Test status
Simulation time 3111737440 ps
CPU time 11.07 seconds
Started Jul 26 05:34:01 PM PDT 24
Finished Jul 26 05:34:13 PM PDT 24
Peak memory 232832 kb
Host smart-bc64081a-3cdf-4ec2-91ee-78ef40d5aa26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179386826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swap
.179386826
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.3887203011
Short name T63
Test name
Test status
Simulation time 402720341 ps
CPU time 3.53 seconds
Started Jul 26 05:34:03 PM PDT 24
Finished Jul 26 05:34:06 PM PDT 24
Peak memory 232800 kb
Host smart-750bcadc-3306-4bbb-bbc2-41a9d7f1f265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887203011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.3887203011
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.360804163
Short name T739
Test name
Test status
Simulation time 711269714 ps
CPU time 11.62 seconds
Started Jul 26 05:34:03 PM PDT 24
Finished Jul 26 05:34:15 PM PDT 24
Peak memory 222504 kb
Host smart-d8334934-b818-4bad-8970-dcaa58278eed
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=360804163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dire
ct.360804163
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.3088044993
Short name T21
Test name
Test status
Simulation time 28735027570 ps
CPU time 104.91 seconds
Started Jul 26 05:34:01 PM PDT 24
Finished Jul 26 05:35:46 PM PDT 24
Peak memory 252136 kb
Host smart-20bb4029-dcfd-4377-9434-91bb85b4be1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088044993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.3088044993
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.3579727916
Short name T438
Test name
Test status
Simulation time 48479677054 ps
CPU time 50.89 seconds
Started Jul 26 05:33:51 PM PDT 24
Finished Jul 26 05:34:42 PM PDT 24
Peak memory 216384 kb
Host smart-20190de6-f7f5-4278-8db1-5c2273da06d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579727916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.3579727916
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.3471562707
Short name T611
Test name
Test status
Simulation time 15667144 ps
CPU time 0.74 seconds
Started Jul 26 05:33:49 PM PDT 24
Finished Jul 26 05:33:49 PM PDT 24
Peak memory 205804 kb
Host smart-b68f6d31-391e-44c4-bff8-5cc8643f6e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471562707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.3471562707
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.2939328312
Short name T23
Test name
Test status
Simulation time 335787052 ps
CPU time 7.24 seconds
Started Jul 26 05:34:01 PM PDT 24
Finished Jul 26 05:34:09 PM PDT 24
Peak memory 216348 kb
Host smart-aad0f107-d70f-4445-b7df-7fbc932e1564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939328312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.2939328312
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.186274680
Short name T571
Test name
Test status
Simulation time 28785365 ps
CPU time 0.7 seconds
Started Jul 26 05:33:48 PM PDT 24
Finished Jul 26 05:33:49 PM PDT 24
Peak memory 205708 kb
Host smart-dc00c02a-4821-43f3-8fda-0b9d16e5efa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186274680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.186274680
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.4183994534
Short name T869
Test name
Test status
Simulation time 35734579226 ps
CPU time 25.52 seconds
Started Jul 26 05:34:01 PM PDT 24
Finished Jul 26 05:34:26 PM PDT 24
Peak memory 224700 kb
Host smart-d98c7812-a979-442b-bb1d-f4a110669e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183994534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.4183994534
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.3922039117
Short name T358
Test name
Test status
Simulation time 11394928 ps
CPU time 0.72 seconds
Started Jul 26 05:34:07 PM PDT 24
Finished Jul 26 05:34:08 PM PDT 24
Peak memory 204924 kb
Host smart-fc1e5fc5-2ed8-4308-96c3-e16c83a8ee7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922039117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
3922039117
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.917933411
Short name T328
Test name
Test status
Simulation time 33428601 ps
CPU time 2.7 seconds
Started Jul 26 05:34:06 PM PDT 24
Finished Jul 26 05:34:09 PM PDT 24
Peak memory 232472 kb
Host smart-dee18438-bc19-4fb2-8031-843c80eadbaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917933411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.917933411
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.349443781
Short name T661
Test name
Test status
Simulation time 78697371 ps
CPU time 0.81 seconds
Started Jul 26 05:34:07 PM PDT 24
Finished Jul 26 05:34:08 PM PDT 24
Peak memory 207016 kb
Host smart-955228b6-cedb-4a6d-9f1e-8fa9e37a0f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349443781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.349443781
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.2159039642
Short name T875
Test name
Test status
Simulation time 124582730570 ps
CPU time 229.1 seconds
Started Jul 26 05:36:43 PM PDT 24
Finished Jul 26 05:40:32 PM PDT 24
Peak memory 238832 kb
Host smart-ee32d69d-1375-4fad-b163-c4d411e275a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159039642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.2159039642
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.2713058490
Short name T954
Test name
Test status
Simulation time 374021057132 ps
CPU time 344.56 seconds
Started Jul 26 05:34:05 PM PDT 24
Finished Jul 26 05:39:50 PM PDT 24
Peak memory 254316 kb
Host smart-2d1d83df-d2d6-4a40-b1ed-221861900c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713058490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.2713058490
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.2995063651
Short name T772
Test name
Test status
Simulation time 295725956115 ps
CPU time 277.07 seconds
Started Jul 26 05:34:02 PM PDT 24
Finished Jul 26 05:38:40 PM PDT 24
Peak memory 257552 kb
Host smart-1503105c-f232-4ee1-9e87-f1a3ddf10cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995063651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.2995063651
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.865809819
Short name T643
Test name
Test status
Simulation time 10413782125 ps
CPU time 23.56 seconds
Started Jul 26 05:34:03 PM PDT 24
Finished Jul 26 05:34:26 PM PDT 24
Peak memory 238736 kb
Host smart-aaca9b33-ffd4-4e82-9a4c-fd75a04f25d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865809819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmds
.865809819
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_intercept.2110249155
Short name T741
Test name
Test status
Simulation time 306953551 ps
CPU time 2.84 seconds
Started Jul 26 05:34:04 PM PDT 24
Finished Jul 26 05:34:07 PM PDT 24
Peak memory 232748 kb
Host smart-8320ad44-88b6-4b15-9b77-6798915cef75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110249155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.2110249155
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.2461673444
Short name T207
Test name
Test status
Simulation time 5991628341 ps
CPU time 33.92 seconds
Started Jul 26 05:56:34 PM PDT 24
Finished Jul 26 05:57:08 PM PDT 24
Peak memory 240852 kb
Host smart-f6fe9877-acb3-42f8-9451-68ecb92d8077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461673444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.2461673444
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.584288353
Short name T519
Test name
Test status
Simulation time 132835735 ps
CPU time 2.95 seconds
Started Jul 26 05:34:07 PM PDT 24
Finished Jul 26 05:34:10 PM PDT 24
Peak memory 232784 kb
Host smart-1fb52e9e-c567-4a29-b1cb-9911b4f97df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584288353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swap
.584288353
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.975639227
Short name T921
Test name
Test status
Simulation time 173788943 ps
CPU time 3.4 seconds
Started Jul 26 05:34:05 PM PDT 24
Finished Jul 26 05:34:09 PM PDT 24
Peak memory 232868 kb
Host smart-bb6d4bf2-1452-419b-b0b3-0597d93899c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975639227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.975639227
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.698211051
Short name T339
Test name
Test status
Simulation time 2542704662 ps
CPU time 4.85 seconds
Started Jul 26 05:34:06 PM PDT 24
Finished Jul 26 05:34:11 PM PDT 24
Peak memory 222652 kb
Host smart-4e5b8aec-932e-489d-b609-49310491fe8c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=698211051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dire
ct.698211051
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.1247625284
Short name T775
Test name
Test status
Simulation time 3882914308 ps
CPU time 24.75 seconds
Started Jul 26 05:34:05 PM PDT 24
Finished Jul 26 05:34:30 PM PDT 24
Peak memory 216432 kb
Host smart-934830db-13ab-494d-9c51-2a236b3f0166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247625284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.1247625284
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.4001726787
Short name T532
Test name
Test status
Simulation time 318682367 ps
CPU time 2.49 seconds
Started Jul 26 05:34:04 PM PDT 24
Finished Jul 26 05:34:07 PM PDT 24
Peak memory 216360 kb
Host smart-a407326e-b9ad-4073-a306-eb059e0a6290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001726787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.4001726787
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.3613849064
Short name T315
Test name
Test status
Simulation time 458161527 ps
CPU time 4.9 seconds
Started Jul 26 05:34:07 PM PDT 24
Finished Jul 26 05:34:12 PM PDT 24
Peak memory 216380 kb
Host smart-e23fa6fd-55f3-415a-b443-72749c7e19c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613849064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.3613849064
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.2654953589
Short name T494
Test name
Test status
Simulation time 49946113 ps
CPU time 0.85 seconds
Started Jul 26 05:34:04 PM PDT 24
Finished Jul 26 05:34:05 PM PDT 24
Peak memory 206092 kb
Host smart-9f4f0545-3c66-40ff-995b-64e5bc91e901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654953589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.2654953589
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.3682206785
Short name T621
Test name
Test status
Simulation time 247220083 ps
CPU time 2.83 seconds
Started Jul 26 05:34:03 PM PDT 24
Finished Jul 26 05:34:06 PM PDT 24
Peak memory 224648 kb
Host smart-829eda4d-cfa6-4fd7-86c3-b739908bdae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682206785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.3682206785
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.1954465841
Short name T712
Test name
Test status
Simulation time 174476058 ps
CPU time 0.76 seconds
Started Jul 26 05:34:04 PM PDT 24
Finished Jul 26 05:34:05 PM PDT 24
Peak memory 204924 kb
Host smart-1b2e9b0d-7012-4002-86fd-1b571c04fc14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954465841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
1954465841
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.4266648276
Short name T448
Test name
Test status
Simulation time 453527854 ps
CPU time 4.53 seconds
Started Jul 26 05:34:05 PM PDT 24
Finished Jul 26 05:34:10 PM PDT 24
Peak memory 232896 kb
Host smart-c35bbe60-2165-4145-a16e-a406a63569ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266648276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.4266648276
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.408750749
Short name T978
Test name
Test status
Simulation time 20646374 ps
CPU time 0.77 seconds
Started Jul 26 05:34:05 PM PDT 24
Finished Jul 26 05:34:06 PM PDT 24
Peak memory 206748 kb
Host smart-e03e64c9-00bb-4e7e-801c-e4090629ba9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408750749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.408750749
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.644407801
Short name T737
Test name
Test status
Simulation time 47020459468 ps
CPU time 153.37 seconds
Started Jul 26 05:34:10 PM PDT 24
Finished Jul 26 05:36:43 PM PDT 24
Peak memory 267100 kb
Host smart-8782644c-5550-43c7-b271-1dff933527ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644407801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.644407801
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.3247898159
Short name T754
Test name
Test status
Simulation time 14456239604 ps
CPU time 56.16 seconds
Started Jul 26 05:34:08 PM PDT 24
Finished Jul 26 05:35:04 PM PDT 24
Peak memory 224792 kb
Host smart-c7e4ebf2-29bf-4f90-977d-197cc2a56dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247898159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.3247898159
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.519844105
Short name T407
Test name
Test status
Simulation time 114332373 ps
CPU time 3.22 seconds
Started Jul 26 05:34:04 PM PDT 24
Finished Jul 26 05:34:08 PM PDT 24
Peak memory 232728 kb
Host smart-61a43699-a934-4fe5-b4a3-212f883c0dad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519844105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.519844105
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.2434078970
Short name T380
Test name
Test status
Simulation time 13132822980 ps
CPU time 130.66 seconds
Started Jul 26 05:34:08 PM PDT 24
Finished Jul 26 05:36:19 PM PDT 24
Peak memory 252804 kb
Host smart-f5d09461-429c-42c0-9491-52086446a41f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434078970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmd
s.2434078970
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/24.spi_device_intercept.463458178
Short name T223
Test name
Test status
Simulation time 1234058988 ps
CPU time 6.24 seconds
Started Jul 26 05:34:05 PM PDT 24
Finished Jul 26 05:34:11 PM PDT 24
Peak memory 224620 kb
Host smart-f6541b9a-8ef3-442f-a0eb-3d4092f5a787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463458178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.463458178
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.3481447811
Short name T2
Test name
Test status
Simulation time 1210872665 ps
CPU time 9.14 seconds
Started Jul 26 05:34:05 PM PDT 24
Finished Jul 26 05:34:14 PM PDT 24
Peak memory 224684 kb
Host smart-2359f7b0-228b-4a81-a5dd-a1a3800c6b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481447811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.3481447811
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.2729030908
Short name T406
Test name
Test status
Simulation time 6197228289 ps
CPU time 17.61 seconds
Started Jul 26 05:34:05 PM PDT 24
Finished Jul 26 05:34:23 PM PDT 24
Peak memory 224740 kb
Host smart-046ca77a-7f24-496b-bbab-6259bdd8326e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729030908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.2729030908
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.2518142302
Short name T699
Test name
Test status
Simulation time 698298925 ps
CPU time 3.03 seconds
Started Jul 26 05:34:04 PM PDT 24
Finished Jul 26 05:34:08 PM PDT 24
Peak memory 224596 kb
Host smart-e3578292-22b5-4d85-b5e6-513bfe0f71e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518142302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.2518142302
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.3076784618
Short name T641
Test name
Test status
Simulation time 2862444673 ps
CPU time 8.71 seconds
Started Jul 26 05:34:07 PM PDT 24
Finished Jul 26 05:34:16 PM PDT 24
Peak memory 221964 kb
Host smart-1160b971-930d-4f03-b74d-17b5ee013b03
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3076784618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.3076784618
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.234712356
Short name T144
Test name
Test status
Simulation time 52884372 ps
CPU time 1.05 seconds
Started Jul 26 05:34:06 PM PDT 24
Finished Jul 26 05:34:07 PM PDT 24
Peak memory 207064 kb
Host smart-0311bf3c-f96c-4a7b-adfb-7ee01c0cdb10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234712356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stres
s_all.234712356
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.1793683973
Short name T564
Test name
Test status
Simulation time 2063048620 ps
CPU time 10.32 seconds
Started Jul 26 05:34:05 PM PDT 24
Finished Jul 26 05:34:15 PM PDT 24
Peak memory 216724 kb
Host smart-c64116f3-9ac4-4bf2-92a7-a3b2cf3420ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793683973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.1793683973
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.1406081493
Short name T767
Test name
Test status
Simulation time 1083751140 ps
CPU time 6.43 seconds
Started Jul 26 05:34:06 PM PDT 24
Finished Jul 26 05:34:13 PM PDT 24
Peak memory 216300 kb
Host smart-aad65ae4-124d-45f6-aacd-aa2ded31c0e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406081493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.1406081493
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.3992832742
Short name T396
Test name
Test status
Simulation time 89489198 ps
CPU time 1.55 seconds
Started Jul 26 05:34:05 PM PDT 24
Finished Jul 26 05:34:06 PM PDT 24
Peak memory 216356 kb
Host smart-c2774951-8fc6-412f-ad20-361e3e6aaac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992832742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.3992832742
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.1948487385
Short name T308
Test name
Test status
Simulation time 103890316 ps
CPU time 1.01 seconds
Started Jul 26 05:34:05 PM PDT 24
Finished Jul 26 05:34:06 PM PDT 24
Peak memory 207008 kb
Host smart-5ec2fd2b-603f-490a-8221-14a90b71da97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948487385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.1948487385
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.2338345664
Short name T666
Test name
Test status
Simulation time 3929956199 ps
CPU time 9.42 seconds
Started Jul 26 05:34:07 PM PDT 24
Finished Jul 26 05:34:16 PM PDT 24
Peak memory 235420 kb
Host smart-be2c07bf-a5bb-439b-b6c7-eb873ac68039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338345664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.2338345664
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.2147791167
Short name T639
Test name
Test status
Simulation time 27334478 ps
CPU time 0.73 seconds
Started Jul 26 05:34:21 PM PDT 24
Finished Jul 26 05:34:22 PM PDT 24
Peak memory 205412 kb
Host smart-fb29aa20-57f7-4cc1-a6cc-8ace075024cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147791167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
2147791167
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.430281272
Short name T846
Test name
Test status
Simulation time 8007744263 ps
CPU time 14.03 seconds
Started Jul 26 05:34:17 PM PDT 24
Finished Jul 26 05:34:31 PM PDT 24
Peak memory 224732 kb
Host smart-03edb3d7-257a-4b20-a82e-cd847de2e7cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430281272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.430281272
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.760240317
Short name T816
Test name
Test status
Simulation time 16682466 ps
CPU time 0.8 seconds
Started Jul 26 05:34:02 PM PDT 24
Finished Jul 26 05:34:03 PM PDT 24
Peak memory 207012 kb
Host smart-f641f388-eb40-4104-9498-6f96d82f8e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760240317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.760240317
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.3640040117
Short name T1008
Test name
Test status
Simulation time 19966552 ps
CPU time 0.74 seconds
Started Jul 26 05:34:12 PM PDT 24
Finished Jul 26 05:34:13 PM PDT 24
Peak memory 215796 kb
Host smart-40a831b1-17c1-49d7-9a07-0be485a97114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640040117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.3640040117
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.2960291243
Short name T198
Test name
Test status
Simulation time 71122141939 ps
CPU time 238.52 seconds
Started Jul 26 05:34:18 PM PDT 24
Finished Jul 26 05:38:16 PM PDT 24
Peak memory 249384 kb
Host smart-68fad991-8fe4-495e-a759-b01cd24bb935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960291243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.2960291243
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.3172567653
Short name T370
Test name
Test status
Simulation time 22659160419 ps
CPU time 98.19 seconds
Started Jul 26 05:34:28 PM PDT 24
Finished Jul 26 05:36:07 PM PDT 24
Peak memory 260896 kb
Host smart-38811237-2ed9-4067-875b-2b800be6f945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172567653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.3172567653
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.3661092273
Short name T759
Test name
Test status
Simulation time 85305778 ps
CPU time 2.64 seconds
Started Jul 26 05:34:14 PM PDT 24
Finished Jul 26 05:34:17 PM PDT 24
Peak memory 232864 kb
Host smart-3082c613-396e-47d6-b536-495cc2060e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661092273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.3661092273
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.1804274537
Short name T378
Test name
Test status
Simulation time 274364614060 ps
CPU time 145.19 seconds
Started Jul 26 05:34:14 PM PDT 24
Finished Jul 26 05:36:39 PM PDT 24
Peak memory 241088 kb
Host smart-e8a5ab5c-a751-47b2-852b-79a20fd1536d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804274537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmd
s.1804274537
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_intercept.1513380535
Short name T966
Test name
Test status
Simulation time 650529635 ps
CPU time 4.28 seconds
Started Jul 26 05:34:01 PM PDT 24
Finished Jul 26 05:34:06 PM PDT 24
Peak memory 232812 kb
Host smart-b624a472-c34d-4d92-be32-e833b886999c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513380535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.1513380535
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.1633133070
Short name T990
Test name
Test status
Simulation time 827044180 ps
CPU time 4.32 seconds
Started Jul 26 05:34:14 PM PDT 24
Finished Jul 26 05:34:18 PM PDT 24
Peak memory 224684 kb
Host smart-91c30c0d-f4eb-4958-b3a0-159976b7fc22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633133070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.1633133070
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.2255472938
Short name T229
Test name
Test status
Simulation time 691557963 ps
CPU time 4.46 seconds
Started Jul 26 05:34:06 PM PDT 24
Finished Jul 26 05:34:10 PM PDT 24
Peak memory 232792 kb
Host smart-05d566ec-bac2-4005-9ddd-cc5abe447036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255472938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.2255472938
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.1677529373
Short name T216
Test name
Test status
Simulation time 7999789147 ps
CPU time 4.83 seconds
Started Jul 26 05:34:08 PM PDT 24
Finished Jul 26 05:34:13 PM PDT 24
Peak memory 232788 kb
Host smart-1ac35614-1965-4d36-aed3-f643adcfa487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677529373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.1677529373
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.2237961023
Short name T963
Test name
Test status
Simulation time 979548571 ps
CPU time 4.5 seconds
Started Jul 26 05:34:25 PM PDT 24
Finished Jul 26 05:34:30 PM PDT 24
Peak memory 223064 kb
Host smart-515a264b-9314-4df5-a535-6e184a791059
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2237961023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.2237961023
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.337188015
Short name T26
Test name
Test status
Simulation time 4726747924 ps
CPU time 11.68 seconds
Started Jul 26 05:34:02 PM PDT 24
Finished Jul 26 05:34:13 PM PDT 24
Peak memory 216496 kb
Host smart-45f7814b-9211-420f-a4c2-8ee9981fe850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337188015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.337188015
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.2457098819
Short name T861
Test name
Test status
Simulation time 560543618 ps
CPU time 3.37 seconds
Started Jul 26 05:34:03 PM PDT 24
Finished Jul 26 05:34:06 PM PDT 24
Peak memory 216428 kb
Host smart-5bb121c3-c540-474b-b4e0-a2bcbab61777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457098819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.2457098819
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.3301449006
Short name T544
Test name
Test status
Simulation time 164847407 ps
CPU time 1.19 seconds
Started Jul 26 05:34:02 PM PDT 24
Finished Jul 26 05:34:03 PM PDT 24
Peak memory 216308 kb
Host smart-e2e9a485-bbbf-4ac3-af90-1f98b5098bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301449006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.3301449006
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.4062709384
Short name T652
Test name
Test status
Simulation time 138571528 ps
CPU time 0.8 seconds
Started Jul 26 05:34:01 PM PDT 24
Finished Jul 26 05:34:02 PM PDT 24
Peak memory 206080 kb
Host smart-c1c34bc2-3302-47f7-9bbf-96ef4d9913c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062709384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.4062709384
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.1366246391
Short name T761
Test name
Test status
Simulation time 1632959075 ps
CPU time 7.73 seconds
Started Jul 26 05:34:11 PM PDT 24
Finished Jul 26 05:34:19 PM PDT 24
Peak memory 236812 kb
Host smart-7f70f7a3-141e-4e21-a889-245c0a616312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366246391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.1366246391
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.3646504632
Short name T973
Test name
Test status
Simulation time 24764952 ps
CPU time 0.72 seconds
Started Jul 26 05:34:18 PM PDT 24
Finished Jul 26 05:34:19 PM PDT 24
Peak memory 205596 kb
Host smart-6b08b4e5-0cc6-4e89-9542-78987f364681
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646504632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
3646504632
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.2684477878
Short name T756
Test name
Test status
Simulation time 1512264243 ps
CPU time 3.31 seconds
Started Jul 26 05:34:24 PM PDT 24
Finished Jul 26 05:34:27 PM PDT 24
Peak memory 224528 kb
Host smart-640b9f5d-5d49-4d17-bb12-244b44ce4da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684477878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.2684477878
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.2748151970
Short name T785
Test name
Test status
Simulation time 63650794 ps
CPU time 0.8 seconds
Started Jul 26 05:34:18 PM PDT 24
Finished Jul 26 05:34:19 PM PDT 24
Peak memory 206684 kb
Host smart-73c5beab-80b5-4289-bc77-445ab46c37ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748151970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.2748151970
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.3449755957
Short name T218
Test name
Test status
Simulation time 54502892015 ps
CPU time 218.49 seconds
Started Jul 26 05:34:14 PM PDT 24
Finished Jul 26 05:37:53 PM PDT 24
Peak memory 256384 kb
Host smart-062cdaf5-6803-41c4-83a1-ded259845ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449755957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.3449755957
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.3662853329
Short name T930
Test name
Test status
Simulation time 25837884442 ps
CPU time 95.02 seconds
Started Jul 26 05:34:13 PM PDT 24
Finished Jul 26 05:35:48 PM PDT 24
Peak memory 252360 kb
Host smart-8d83f779-e68c-4e80-904c-01a69e1e0a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662853329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.3662853329
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.3938014765
Short name T270
Test name
Test status
Simulation time 191795190 ps
CPU time 8.89 seconds
Started Jul 26 05:34:16 PM PDT 24
Finished Jul 26 05:34:25 PM PDT 24
Peak memory 240948 kb
Host smart-74d6d616-2847-4154-a376-0d935b327650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938014765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.3938014765
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.1079688554
Short name T865
Test name
Test status
Simulation time 4129645331 ps
CPU time 23.04 seconds
Started Jul 26 05:34:10 PM PDT 24
Finished Jul 26 05:34:33 PM PDT 24
Peak memory 252276 kb
Host smart-36941c02-3aa7-4c47-adaf-64df6f1770d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079688554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmd
s.1079688554
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_intercept.4236544848
Short name T336
Test name
Test status
Simulation time 914575926 ps
CPU time 6.83 seconds
Started Jul 26 05:34:11 PM PDT 24
Finished Jul 26 05:34:18 PM PDT 24
Peak memory 232800 kb
Host smart-629ee1f8-2e25-4a79-b133-0f6d0f65d419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236544848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.4236544848
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.3069535720
Short name T953
Test name
Test status
Simulation time 8696126752 ps
CPU time 75.67 seconds
Started Jul 26 05:34:13 PM PDT 24
Finished Jul 26 05:35:29 PM PDT 24
Peak memory 241012 kb
Host smart-2464e279-68bb-4617-a480-e8e85a240561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069535720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.3069535720
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.3193309120
Short name T931
Test name
Test status
Simulation time 585089918 ps
CPU time 5.86 seconds
Started Jul 26 05:34:13 PM PDT 24
Finished Jul 26 05:34:19 PM PDT 24
Peak memory 232824 kb
Host smart-5fae97f7-08c8-448e-9dcb-56afd9740dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193309120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.3193309120
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.1599947733
Short name T444
Test name
Test status
Simulation time 32126121016 ps
CPU time 19.98 seconds
Started Jul 26 05:34:13 PM PDT 24
Finished Jul 26 05:34:33 PM PDT 24
Peak memory 234076 kb
Host smart-7116feaf-ef3c-4aa4-b6c1-a63baa9633e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599947733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.1599947733
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.2396527525
Short name T665
Test name
Test status
Simulation time 290225960 ps
CPU time 3.59 seconds
Started Jul 26 05:34:18 PM PDT 24
Finished Jul 26 05:34:22 PM PDT 24
Peak memory 223176 kb
Host smart-25a351a2-a9df-42db-a1df-1ff709f0bfa3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2396527525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.2396527525
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.2087187359
Short name T28
Test name
Test status
Simulation time 51651344053 ps
CPU time 28.21 seconds
Started Jul 26 05:34:17 PM PDT 24
Finished Jul 26 05:34:46 PM PDT 24
Peak memory 216524 kb
Host smart-83830264-e9ae-49d2-80b4-5dab4316ad9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087187359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.2087187359
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.1795211213
Short name T825
Test name
Test status
Simulation time 155760491 ps
CPU time 1.02 seconds
Started Jul 26 05:34:24 PM PDT 24
Finished Jul 26 05:34:25 PM PDT 24
Peak memory 206084 kb
Host smart-4c1ca697-c746-4afc-a206-28f3fd473a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795211213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.1795211213
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.1330516800
Short name T492
Test name
Test status
Simulation time 1145083223 ps
CPU time 5.7 seconds
Started Jul 26 05:34:26 PM PDT 24
Finished Jul 26 05:34:31 PM PDT 24
Peak memory 216284 kb
Host smart-5e25ca4d-d991-4bd0-9a18-88453bbc4a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330516800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.1330516800
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.3358823599
Short name T906
Test name
Test status
Simulation time 377513548 ps
CPU time 1.02 seconds
Started Jul 26 05:34:14 PM PDT 24
Finished Jul 26 05:34:15 PM PDT 24
Peak memory 207044 kb
Host smart-26e2dced-f59e-4830-8938-8fd2e45c6814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358823599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.3358823599
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.2316877673
Short name T967
Test name
Test status
Simulation time 3979427682 ps
CPU time 6.18 seconds
Started Jul 26 05:34:15 PM PDT 24
Finished Jul 26 05:34:21 PM PDT 24
Peak memory 228780 kb
Host smart-84e84b3a-a0f7-4e6c-bcdd-4147dd87485a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316877673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.2316877673
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.3844967878
Short name T638
Test name
Test status
Simulation time 44512853 ps
CPU time 0.74 seconds
Started Jul 26 05:34:12 PM PDT 24
Finished Jul 26 05:34:13 PM PDT 24
Peak memory 205820 kb
Host smart-441010bd-d2a5-45d4-a9f0-cfcc1f2cdb29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844967878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
3844967878
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.753796532
Short name T887
Test name
Test status
Simulation time 4088422415 ps
CPU time 8.77 seconds
Started Jul 26 05:34:13 PM PDT 24
Finished Jul 26 05:34:22 PM PDT 24
Peak memory 224676 kb
Host smart-65465c2b-e0e5-4359-a8ad-928f63b2a6b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753796532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.753796532
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.3994360624
Short name T572
Test name
Test status
Simulation time 46569597 ps
CPU time 0.75 seconds
Started Jul 26 05:34:16 PM PDT 24
Finished Jul 26 05:34:17 PM PDT 24
Peak memory 205964 kb
Host smart-3fdd6d7e-2f61-4a7d-9eb7-cb5d4867fe27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994360624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.3994360624
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.3326233564
Short name T166
Test name
Test status
Simulation time 27431135855 ps
CPU time 112.12 seconds
Started Jul 26 05:34:12 PM PDT 24
Finished Jul 26 05:36:04 PM PDT 24
Peak memory 250424 kb
Host smart-38d94585-e5f1-4090-b84e-09b1d844685e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326233564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.3326233564
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.217228131
Short name T376
Test name
Test status
Simulation time 1887110412 ps
CPU time 22.79 seconds
Started Jul 26 05:34:16 PM PDT 24
Finished Jul 26 05:34:39 PM PDT 24
Peak memory 217812 kb
Host smart-0740a262-837d-4ce9-89bc-8a10f323d129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217228131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.217228131
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.3125633411
Short name T677
Test name
Test status
Simulation time 81560055897 ps
CPU time 188.11 seconds
Started Jul 26 05:34:15 PM PDT 24
Finished Jul 26 05:37:23 PM PDT 24
Peak memory 249308 kb
Host smart-18364688-3788-48f9-a200-0f0bd66866a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125633411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.3125633411
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.2544876304
Short name T986
Test name
Test status
Simulation time 566813435 ps
CPU time 7.16 seconds
Started Jul 26 05:34:18 PM PDT 24
Finished Jul 26 05:34:25 PM PDT 24
Peak memory 248564 kb
Host smart-f8969871-9766-45d7-a46a-6af097367174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544876304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.2544876304
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.1850695351
Short name T770
Test name
Test status
Simulation time 13887603 ps
CPU time 0.77 seconds
Started Jul 26 05:34:17 PM PDT 24
Finished Jul 26 05:34:18 PM PDT 24
Peak memory 215828 kb
Host smart-65df0c28-0bdb-407c-bdb7-da80094b5912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850695351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmd
s.1850695351
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_intercept.1105253080
Short name T589
Test name
Test status
Simulation time 2914125618 ps
CPU time 9.93 seconds
Started Jul 26 05:34:12 PM PDT 24
Finished Jul 26 05:34:22 PM PDT 24
Peak memory 224636 kb
Host smart-1597d7ab-02e2-4a0f-aa57-fcc111e2a615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105253080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.1105253080
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.2459572788
Short name T210
Test name
Test status
Simulation time 20590873926 ps
CPU time 63.17 seconds
Started Jul 26 05:34:26 PM PDT 24
Finished Jul 26 05:35:29 PM PDT 24
Peak memory 248920 kb
Host smart-1b41c16c-55a2-4ef6-b8b2-56129df0abde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459572788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.2459572788
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.4123068395
Short name T227
Test name
Test status
Simulation time 3074483965 ps
CPU time 9.53 seconds
Started Jul 26 05:34:13 PM PDT 24
Finished Jul 26 05:34:22 PM PDT 24
Peak memory 224580 kb
Host smart-70380198-1717-4dc5-be3d-7122c752e75d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123068395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.4123068395
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.73819883
Short name T683
Test name
Test status
Simulation time 122193759 ps
CPU time 2.55 seconds
Started Jul 26 05:34:13 PM PDT 24
Finished Jul 26 05:34:16 PM PDT 24
Peak memory 232748 kb
Host smart-ade5e1fc-e39a-4c5f-bfef-f5789b314a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73819883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.73819883
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.4085384480
Short name T131
Test name
Test status
Simulation time 293873300 ps
CPU time 4.58 seconds
Started Jul 26 05:34:16 PM PDT 24
Finished Jul 26 05:34:20 PM PDT 24
Peak memory 222052 kb
Host smart-853b198b-7d54-4a62-a3e4-28fc21e763cc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4085384480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.4085384480
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.2451022378
Short name T348
Test name
Test status
Simulation time 2120796007 ps
CPU time 23.14 seconds
Started Jul 26 05:34:18 PM PDT 24
Finished Jul 26 05:34:41 PM PDT 24
Peak memory 220136 kb
Host smart-46f7a97c-8dcb-490f-a9dd-924bfa6ba76d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451022378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.2451022378
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.4160176357
Short name T940
Test name
Test status
Simulation time 2025511679 ps
CPU time 6.04 seconds
Started Jul 26 05:34:13 PM PDT 24
Finished Jul 26 05:34:20 PM PDT 24
Peak memory 216368 kb
Host smart-a0e6c604-b6a0-4121-a1a0-d545d002c2da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160176357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.4160176357
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.1905341973
Short name T563
Test name
Test status
Simulation time 176775110 ps
CPU time 1.28 seconds
Started Jul 26 05:34:11 PM PDT 24
Finished Jul 26 05:34:12 PM PDT 24
Peak memory 216272 kb
Host smart-87965f20-217c-4788-9cef-87844584c2da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905341973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.1905341973
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.4225604088
Short name T1
Test name
Test status
Simulation time 53079331 ps
CPU time 0.72 seconds
Started Jul 26 05:34:13 PM PDT 24
Finished Jul 26 05:34:14 PM PDT 24
Peak memory 206088 kb
Host smart-c456a3a7-41f6-4904-9732-6ea017c6a937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225604088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.4225604088
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.1671283584
Short name T239
Test name
Test status
Simulation time 40650910832 ps
CPU time 14.97 seconds
Started Jul 26 05:34:11 PM PDT 24
Finished Jul 26 05:34:26 PM PDT 24
Peak memory 232800 kb
Host smart-bb8d9bb0-aa44-4610-b213-96501f9244ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671283584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.1671283584
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.4004945390
Short name T991
Test name
Test status
Simulation time 20876091 ps
CPU time 0.73 seconds
Started Jul 26 05:34:22 PM PDT 24
Finished Jul 26 05:34:23 PM PDT 24
Peak memory 205404 kb
Host smart-21a7ce17-7509-457c-8116-dc7d0b2a6c6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004945390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
4004945390
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.3930590060
Short name T208
Test name
Test status
Simulation time 5282091430 ps
CPU time 17.63 seconds
Started Jul 26 05:34:16 PM PDT 24
Finished Jul 26 05:34:34 PM PDT 24
Peak memory 224652 kb
Host smart-31006e50-756c-42c1-abe0-358daf1d3b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930590060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.3930590060
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.2848506955
Short name T414
Test name
Test status
Simulation time 31213400 ps
CPU time 0.79 seconds
Started Jul 26 05:34:18 PM PDT 24
Finished Jul 26 05:34:19 PM PDT 24
Peak memory 206712 kb
Host smart-ca03c3e1-19f5-4a51-9213-bab3ac173fe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848506955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.2848506955
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.440604704
Short name T220
Test name
Test status
Simulation time 3663822827 ps
CPU time 81.59 seconds
Started Jul 26 05:34:14 PM PDT 24
Finished Jul 26 05:35:36 PM PDT 24
Peak memory 257480 kb
Host smart-ac4fecf4-a29f-4e70-9246-132402c8159d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440604704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.440604704
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.3152333822
Short name T254
Test name
Test status
Simulation time 6433808712 ps
CPU time 38.62 seconds
Started Jul 26 05:34:17 PM PDT 24
Finished Jul 26 05:34:56 PM PDT 24
Peak memory 249332 kb
Host smart-6ea5cd02-7e71-4bf1-b3f1-4c4506ac10e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152333822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.3152333822
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.4235907529
Short name T607
Test name
Test status
Simulation time 56309454255 ps
CPU time 109.1 seconds
Started Jul 26 05:34:17 PM PDT 24
Finished Jul 26 05:36:06 PM PDT 24
Peak memory 256092 kb
Host smart-30e511e9-bcfe-4f71-b087-f31f0dc48957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235907529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.4235907529
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.913746506
Short name T968
Test name
Test status
Simulation time 123639095 ps
CPU time 2.99 seconds
Started Jul 26 05:34:21 PM PDT 24
Finished Jul 26 05:34:24 PM PDT 24
Peak memory 232684 kb
Host smart-ab1f393b-cddb-4a10-9b74-7e655e07af50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913746506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.913746506
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.645712101
Short name T926
Test name
Test status
Simulation time 88086378138 ps
CPU time 138.17 seconds
Started Jul 26 05:34:17 PM PDT 24
Finished Jul 26 05:36:36 PM PDT 24
Peak memory 262740 kb
Host smart-232bbcb4-f143-4236-a1af-7dca6af1260c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645712101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmds
.645712101
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.2597408526
Short name T890
Test name
Test status
Simulation time 655053066 ps
CPU time 5.51 seconds
Started Jul 26 05:34:14 PM PDT 24
Finished Jul 26 05:34:20 PM PDT 24
Peak memory 224672 kb
Host smart-528234ee-a11c-4719-8448-39564a51cb72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597408526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.2597408526
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.2670336914
Short name T516
Test name
Test status
Simulation time 6895408206 ps
CPU time 35.45 seconds
Started Jul 26 05:34:18 PM PDT 24
Finished Jul 26 05:34:53 PM PDT 24
Peak memory 232932 kb
Host smart-6bec64bf-943d-485b-a69b-fb5180e2bc7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670336914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.2670336914
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.3017883125
Short name T937
Test name
Test status
Simulation time 1278302974 ps
CPU time 3.02 seconds
Started Jul 26 05:34:14 PM PDT 24
Finished Jul 26 05:34:17 PM PDT 24
Peak memory 224616 kb
Host smart-67dbb867-bad1-47cf-9518-e1bac467795b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017883125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.3017883125
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.146905185
Short name T401
Test name
Test status
Simulation time 1800721267 ps
CPU time 6.76 seconds
Started Jul 26 05:34:26 PM PDT 24
Finished Jul 26 05:34:33 PM PDT 24
Peak memory 222184 kb
Host smart-2a15135a-d97a-447e-bb82-e1a4242d59d5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=146905185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dire
ct.146905185
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.1985199885
Short name T22
Test name
Test status
Simulation time 58195270088 ps
CPU time 266.04 seconds
Started Jul 26 05:34:17 PM PDT 24
Finished Jul 26 05:38:43 PM PDT 24
Peak memory 256892 kb
Host smart-63544918-9979-4838-bd94-06060f4c43fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985199885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.1985199885
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.1883242702
Short name T777
Test name
Test status
Simulation time 1993463843 ps
CPU time 20.14 seconds
Started Jul 26 05:34:15 PM PDT 24
Finished Jul 26 05:34:35 PM PDT 24
Peak memory 216624 kb
Host smart-f4eee6ec-e4a5-441d-b965-f507a67fa032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883242702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.1883242702
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.3051010374
Short name T311
Test name
Test status
Simulation time 10739761094 ps
CPU time 8.33 seconds
Started Jul 26 05:34:12 PM PDT 24
Finished Jul 26 05:34:21 PM PDT 24
Peak memory 216456 kb
Host smart-533ea9a9-95a1-4f23-8084-8d50eff81088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051010374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.3051010374
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.3798724678
Short name T997
Test name
Test status
Simulation time 34509179 ps
CPU time 0.71 seconds
Started Jul 26 05:34:15 PM PDT 24
Finished Jul 26 05:34:15 PM PDT 24
Peak memory 206016 kb
Host smart-bc4b4aee-d3f0-4c7e-aaf7-e760df942b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798724678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.3798724678
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.1153006667
Short name T349
Test name
Test status
Simulation time 162665726 ps
CPU time 0.92 seconds
Started Jul 26 05:34:23 PM PDT 24
Finished Jul 26 05:34:24 PM PDT 24
Peak memory 206332 kb
Host smart-ba21a01f-9bd1-404f-bca8-e57c112810c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153006667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.1153006667
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.2562671182
Short name T798
Test name
Test status
Simulation time 35510161 ps
CPU time 2.28 seconds
Started Jul 26 05:34:26 PM PDT 24
Finished Jul 26 05:34:28 PM PDT 24
Peak memory 224520 kb
Host smart-06780535-39a0-4eea-8815-d566e8cf79ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562671182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.2562671182
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.1371799469
Short name T44
Test name
Test status
Simulation time 41349836 ps
CPU time 0.73 seconds
Started Jul 26 05:34:26 PM PDT 24
Finished Jul 26 05:34:27 PM PDT 24
Peak memory 205024 kb
Host smart-82160628-9679-4608-bb9f-01774b91c775
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371799469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
1371799469
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.1550475475
Short name T415
Test name
Test status
Simulation time 675125797 ps
CPU time 3.34 seconds
Started Jul 26 05:34:24 PM PDT 24
Finished Jul 26 05:34:28 PM PDT 24
Peak memory 224616 kb
Host smart-7f59b65d-0633-48f8-8e7c-e1a4cb871f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550475475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.1550475475
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.564069414
Short name T939
Test name
Test status
Simulation time 23197441 ps
CPU time 0.76 seconds
Started Jul 26 05:34:16 PM PDT 24
Finished Jul 26 05:34:17 PM PDT 24
Peak memory 207020 kb
Host smart-f0d5704c-cc75-4795-815a-2f27d74c6f4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564069414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.564069414
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.353162019
Short name T178
Test name
Test status
Simulation time 83296685075 ps
CPU time 333.93 seconds
Started Jul 26 05:34:30 PM PDT 24
Finished Jul 26 05:40:04 PM PDT 24
Peak memory 262064 kb
Host smart-41d11d05-97b8-4b7d-b84d-5f276888f289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353162019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.353162019
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.4000108538
Short name T180
Test name
Test status
Simulation time 872912892 ps
CPU time 18.19 seconds
Started Jul 26 05:34:25 PM PDT 24
Finished Jul 26 05:34:43 PM PDT 24
Peak memory 224724 kb
Host smart-0354161f-897d-4666-a7f5-80370b7d3896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000108538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.4000108538
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.2698034518
Short name T186
Test name
Test status
Simulation time 24295600739 ps
CPU time 84.27 seconds
Started Jul 26 05:34:29 PM PDT 24
Finished Jul 26 05:35:53 PM PDT 24
Peak memory 249580 kb
Host smart-89bb3a70-baa2-4caf-bb60-c2f6723816fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698034518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.2698034518
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.2022153110
Short name T547
Test name
Test status
Simulation time 95594430 ps
CPU time 3.06 seconds
Started Jul 26 05:34:25 PM PDT 24
Finished Jul 26 05:34:28 PM PDT 24
Peak memory 232840 kb
Host smart-aa3175d4-4a87-4bd6-a504-656c1426fd90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022153110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.2022153110
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.2211352158
Short name T669
Test name
Test status
Simulation time 13371349166 ps
CPU time 117.28 seconds
Started Jul 26 05:34:27 PM PDT 24
Finished Jul 26 05:36:24 PM PDT 24
Peak memory 253092 kb
Host smart-a680c6df-2741-4ec6-a277-6bde1edd41bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211352158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmd
s.2211352158
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_intercept.3912781616
Short name T950
Test name
Test status
Simulation time 30180424 ps
CPU time 2.19 seconds
Started Jul 26 05:34:14 PM PDT 24
Finished Jul 26 05:34:16 PM PDT 24
Peak memory 226948 kb
Host smart-53c0aece-f30f-49b4-a8a3-dcab01df485a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912781616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.3912781616
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.3030102859
Short name T958
Test name
Test status
Simulation time 1172899869 ps
CPU time 9.58 seconds
Started Jul 26 05:34:19 PM PDT 24
Finished Jul 26 05:34:29 PM PDT 24
Peak memory 240876 kb
Host smart-58fc5ff7-de00-4097-8226-4fcd44ae5784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030102859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.3030102859
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.1659246211
Short name T457
Test name
Test status
Simulation time 2721586845 ps
CPU time 13.75 seconds
Started Jul 26 05:34:18 PM PDT 24
Finished Jul 26 05:34:32 PM PDT 24
Peak memory 232936 kb
Host smart-53e4ae22-6aba-4480-881f-63936d2b5ab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659246211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.1659246211
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.3745809767
Short name T562
Test name
Test status
Simulation time 5827975430 ps
CPU time 5.46 seconds
Started Jul 26 05:34:18 PM PDT 24
Finished Jul 26 05:34:23 PM PDT 24
Peak memory 224696 kb
Host smart-b0956fef-62f7-46b6-b837-a57c12bf4779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745809767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.3745809767
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.1236245416
Short name T546
Test name
Test status
Simulation time 387838997 ps
CPU time 4.33 seconds
Started Jul 26 05:34:24 PM PDT 24
Finished Jul 26 05:34:29 PM PDT 24
Peak memory 223344 kb
Host smart-1427707e-382b-4796-805f-a918a75c38f0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1236245416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.1236245416
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.1238620735
Short name T451
Test name
Test status
Simulation time 361930945 ps
CPU time 1.13 seconds
Started Jul 26 05:34:28 PM PDT 24
Finished Jul 26 05:34:29 PM PDT 24
Peak memory 207916 kb
Host smart-2fa85dda-8857-42f6-b5bf-3cb4bdb3fbea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238620735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.1238620735
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.3747543000
Short name T610
Test name
Test status
Simulation time 4289500319 ps
CPU time 12.68 seconds
Started Jul 26 05:34:22 PM PDT 24
Finished Jul 26 05:34:35 PM PDT 24
Peak memory 216660 kb
Host smart-69472765-73ba-423e-b01f-40ca2972a5db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747543000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.3747543000
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.4272587748
Short name T1005
Test name
Test status
Simulation time 11365339 ps
CPU time 0.7 seconds
Started Jul 26 05:34:22 PM PDT 24
Finished Jul 26 05:34:22 PM PDT 24
Peak memory 205656 kb
Host smart-18a55d7a-58cc-48a0-bdda-8d5a2dffc69a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272587748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.4272587748
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.1079438856
Short name T437
Test name
Test status
Simulation time 994625057 ps
CPU time 5.97 seconds
Started Jul 26 05:34:17 PM PDT 24
Finished Jul 26 05:34:24 PM PDT 24
Peak memory 216432 kb
Host smart-6541de28-2311-466b-a5b5-c87d41ae8c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079438856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.1079438856
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.839824225
Short name T486
Test name
Test status
Simulation time 59391306 ps
CPU time 0.77 seconds
Started Jul 26 05:34:22 PM PDT 24
Finished Jul 26 05:34:23 PM PDT 24
Peak memory 205948 kb
Host smart-6ef57503-456d-448e-afc7-da8dda0664c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839824225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.839824225
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.2314119192
Short name T402
Test name
Test status
Simulation time 44513865 ps
CPU time 2.21 seconds
Started Jul 26 05:34:24 PM PDT 24
Finished Jul 26 05:34:26 PM PDT 24
Peak memory 232508 kb
Host smart-99feb3f6-c5fb-4855-8a19-9076a7ae129a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314119192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.2314119192
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.2440797941
Short name T382
Test name
Test status
Simulation time 29273170 ps
CPU time 0.71 seconds
Started Jul 26 05:32:59 PM PDT 24
Finished Jul 26 05:33:00 PM PDT 24
Peak memory 205476 kb
Host smart-83e4a7d1-fb0b-4b1a-9b46-c1c294e30540
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440797941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.2
440797941
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.713359119
Short name T616
Test name
Test status
Simulation time 62768246 ps
CPU time 2.34 seconds
Started Jul 26 05:32:51 PM PDT 24
Finished Jul 26 05:32:54 PM PDT 24
Peak memory 224788 kb
Host smart-3b072633-65c0-43b6-998c-16be0fda4cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713359119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.713359119
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.1210516394
Short name T345
Test name
Test status
Simulation time 14317202 ps
CPU time 0.79 seconds
Started Jul 26 05:32:41 PM PDT 24
Finished Jul 26 05:32:42 PM PDT 24
Peak memory 207024 kb
Host smart-4aec0684-49fc-4b59-8b2e-2c1518ec604f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210516394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.1210516394
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.3027313610
Short name T766
Test name
Test status
Simulation time 26108686 ps
CPU time 0.8 seconds
Started Jul 26 05:32:48 PM PDT 24
Finished Jul 26 05:32:49 PM PDT 24
Peak memory 215820 kb
Host smart-b1d6e847-dddc-4658-a3a6-7cfc9a5a5119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027313610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.3027313610
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.4266530882
Short name T255
Test name
Test status
Simulation time 60117389417 ps
CPU time 260.82 seconds
Started Jul 26 05:32:48 PM PDT 24
Finished Jul 26 05:37:09 PM PDT 24
Peak memory 249436 kb
Host smart-bfbb41da-b40d-40ca-94da-c471c3abc36f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266530882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.4266530882
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.171069694
Short name T762
Test name
Test status
Simulation time 376360084 ps
CPU time 7.14 seconds
Started Jul 26 05:32:59 PM PDT 24
Finished Jul 26 05:33:07 PM PDT 24
Peak memory 224524 kb
Host smart-fe2f0d9a-5adf-49ac-b306-d0d074bfb63b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171069694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.171069694
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.3687030921
Short name T552
Test name
Test status
Simulation time 29028032 ps
CPU time 0.86 seconds
Started Jul 26 05:32:53 PM PDT 24
Finished Jul 26 05:32:54 PM PDT 24
Peak memory 215880 kb
Host smart-8ba9716a-0030-41f6-9500-e59f3bef1036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687030921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds
.3687030921
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_intercept.2514435355
Short name T540
Test name
Test status
Simulation time 174938941 ps
CPU time 6.06 seconds
Started Jul 26 05:32:59 PM PDT 24
Finished Jul 26 05:33:05 PM PDT 24
Peak memory 232696 kb
Host smart-5ec95fd8-b0cd-4d96-9cc4-0f33b085bb8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514435355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.2514435355
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.294885703
Short name T206
Test name
Test status
Simulation time 7378138475 ps
CPU time 18.83 seconds
Started Jul 26 05:32:50 PM PDT 24
Finished Jul 26 05:33:09 PM PDT 24
Peak memory 240924 kb
Host smart-a1bd4265-0b51-48ac-a526-2920f237b98a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294885703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.294885703
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.2652436826
Short name T256
Test name
Test status
Simulation time 9675172853 ps
CPU time 4.89 seconds
Started Jul 26 05:32:51 PM PDT 24
Finished Jul 26 05:32:56 PM PDT 24
Peak memory 224940 kb
Host smart-2167f6c4-5b8f-4e3b-82dc-1888a0d79d59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652436826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.2652436826
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.2760831379
Short name T802
Test name
Test status
Simulation time 1479731857 ps
CPU time 2.78 seconds
Started Jul 26 05:32:37 PM PDT 24
Finished Jul 26 05:32:40 PM PDT 24
Peak memory 232780 kb
Host smart-2240aacc-ec8a-49be-ae58-506fbf8a1a5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760831379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.2760831379
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.396980531
Short name T5
Test name
Test status
Simulation time 4191777968 ps
CPU time 17.36 seconds
Started Jul 26 05:32:50 PM PDT 24
Finished Jul 26 05:33:07 PM PDT 24
Peak memory 222792 kb
Host smart-158fa070-dcae-4fcd-a511-0c771ca264c9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=396980531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_direc
t.396980531
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.2941591054
Short name T61
Test name
Test status
Simulation time 56263762 ps
CPU time 1.04 seconds
Started Jul 26 05:32:49 PM PDT 24
Finished Jul 26 05:32:50 PM PDT 24
Peak memory 235728 kb
Host smart-f62faa30-8879-41c0-a1d5-f1dd5fa6f0f2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941591054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.2941591054
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.1533744163
Short name T579
Test name
Test status
Simulation time 3023258910 ps
CPU time 13.33 seconds
Started Jul 26 05:32:49 PM PDT 24
Finished Jul 26 05:33:02 PM PDT 24
Peak memory 224728 kb
Host smart-a48c5d6c-13a2-4846-8d7d-9e0abbed2202
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533744163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.1533744163
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.4220440120
Short name T310
Test name
Test status
Simulation time 523277507 ps
CPU time 3.49 seconds
Started Jul 26 05:32:42 PM PDT 24
Finished Jul 26 05:32:46 PM PDT 24
Peak memory 216372 kb
Host smart-2c6d383e-7afd-4a7f-95e5-469d6263ce37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220440120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.4220440120
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.555055314
Short name T745
Test name
Test status
Simulation time 4297304771 ps
CPU time 12.35 seconds
Started Jul 26 05:32:40 PM PDT 24
Finished Jul 26 05:32:53 PM PDT 24
Peak memory 216412 kb
Host smart-03fe5df8-3f00-4afd-869e-31b371e2c651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555055314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.555055314
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.1811330501
Short name T65
Test name
Test status
Simulation time 1242953858 ps
CPU time 6.83 seconds
Started Jul 26 05:32:45 PM PDT 24
Finished Jul 26 05:32:52 PM PDT 24
Peak memory 216368 kb
Host smart-7fac29b1-548a-4aba-9d1c-c7d7ff3c3022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811330501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.1811330501
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.3801462959
Short name T686
Test name
Test status
Simulation time 38974622 ps
CPU time 0.75 seconds
Started Jul 26 05:32:41 PM PDT 24
Finished Jul 26 05:32:42 PM PDT 24
Peak memory 205348 kb
Host smart-3299b844-d244-41c9-8a49-847f0f1b458e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801462959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.3801462959
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.1107897698
Short name T911
Test name
Test status
Simulation time 2002444036 ps
CPU time 4.49 seconds
Started Jul 26 05:32:48 PM PDT 24
Finished Jul 26 05:32:52 PM PDT 24
Peak memory 224608 kb
Host smart-fbab1f8a-8454-4991-b51c-c3320e5667f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107897698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.1107897698
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.3758706491
Short name T769
Test name
Test status
Simulation time 13611420 ps
CPU time 0.77 seconds
Started Jul 26 05:34:29 PM PDT 24
Finished Jul 26 05:34:30 PM PDT 24
Peak memory 205784 kb
Host smart-b7ac2de2-4ad5-44aa-a30b-04431e7883be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758706491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
3758706491
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.4067104742
Short name T1004
Test name
Test status
Simulation time 107984559 ps
CPU time 2.21 seconds
Started Jul 26 05:34:30 PM PDT 24
Finished Jul 26 05:34:32 PM PDT 24
Peak memory 224592 kb
Host smart-599d281b-c26a-47e7-9ae4-36ddd7074f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067104742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.4067104742
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.2592730672
Short name T322
Test name
Test status
Simulation time 58306092 ps
CPU time 0.82 seconds
Started Jul 26 05:34:22 PM PDT 24
Finished Jul 26 05:34:23 PM PDT 24
Peak memory 206672 kb
Host smart-85603617-f61b-405c-b65b-dabd9f00d8be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592730672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.2592730672
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.3473876880
Short name T235
Test name
Test status
Simulation time 18329229568 ps
CPU time 127.79 seconds
Started Jul 26 05:34:22 PM PDT 24
Finished Jul 26 05:36:30 PM PDT 24
Peak memory 256480 kb
Host smart-e33fe3e9-4011-49c4-88e0-c578442e6398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473876880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.3473876880
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.841100915
Short name T162
Test name
Test status
Simulation time 6632110900 ps
CPU time 39.15 seconds
Started Jul 26 05:34:31 PM PDT 24
Finished Jul 26 05:35:10 PM PDT 24
Peak memory 238824 kb
Host smart-cb220774-70c5-415f-b7f5-99ac8d16e671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841100915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.841100915
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.1597419317
Short name T765
Test name
Test status
Simulation time 14045253727 ps
CPU time 85.92 seconds
Started Jul 26 05:34:28 PM PDT 24
Finished Jul 26 05:35:54 PM PDT 24
Peak memory 261140 kb
Host smart-130d8f81-03a3-4ab6-94d3-b15da9b6fae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597419317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.1597419317
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.1204322656
Short name T541
Test name
Test status
Simulation time 117546040 ps
CPU time 3.13 seconds
Started Jul 26 05:34:23 PM PDT 24
Finished Jul 26 05:34:26 PM PDT 24
Peak memory 224676 kb
Host smart-bebeb68c-892a-4d3a-a535-aa837142e778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204322656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.1204322656
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.2561379363
Short name T217
Test name
Test status
Simulation time 4707392841 ps
CPU time 61.04 seconds
Started Jul 26 05:34:23 PM PDT 24
Finished Jul 26 05:35:24 PM PDT 24
Peak memory 257400 kb
Host smart-60025f6f-5d92-4e79-b1a0-324a623c92f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561379363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmd
s.2561379363
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/30.spi_device_intercept.2371216664
Short name T567
Test name
Test status
Simulation time 2718446769 ps
CPU time 9.72 seconds
Started Jul 26 05:34:24 PM PDT 24
Finished Jul 26 05:34:34 PM PDT 24
Peak memory 232872 kb
Host smart-d0150fae-d365-4631-8872-55cd64e79979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371216664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.2371216664
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.191154320
Short name T820
Test name
Test status
Simulation time 3859868733 ps
CPU time 19.91 seconds
Started Jul 26 05:34:27 PM PDT 24
Finished Jul 26 05:34:47 PM PDT 24
Peak memory 249548 kb
Host smart-81a89864-5be7-4a7c-848b-28d66ee869bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191154320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.191154320
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.21904139
Short name T848
Test name
Test status
Simulation time 2394187058 ps
CPU time 4.8 seconds
Started Jul 26 05:34:22 PM PDT 24
Finished Jul 26 05:34:27 PM PDT 24
Peak memory 232908 kb
Host smart-eff99466-7915-4381-bdcc-8fb1c6534528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21904139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swap.21904139
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.25118817
Short name T854
Test name
Test status
Simulation time 674513657 ps
CPU time 9.51 seconds
Started Jul 26 05:34:27 PM PDT 24
Finished Jul 26 05:34:36 PM PDT 24
Peak memory 224560 kb
Host smart-f87072f2-023c-4664-ac96-1b530f4da186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25118817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.25118817
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.1514590624
Short name T129
Test name
Test status
Simulation time 353565182 ps
CPU time 3.98 seconds
Started Jul 26 05:34:23 PM PDT 24
Finished Jul 26 05:34:27 PM PDT 24
Peak memory 218960 kb
Host smart-6ba238ac-894b-45ed-bcab-78e87318a6f3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1514590624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.1514590624
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.3763560781
Short name T286
Test name
Test status
Simulation time 7829376385 ps
CPU time 48.02 seconds
Started Jul 26 05:34:25 PM PDT 24
Finished Jul 26 05:35:13 PM PDT 24
Peak memory 216460 kb
Host smart-bbc7c752-dbb2-45e0-9057-d004d5a037e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763560781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.3763560781
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.761398068
Short name T297
Test name
Test status
Simulation time 9445555459 ps
CPU time 8.16 seconds
Started Jul 26 05:34:24 PM PDT 24
Finished Jul 26 05:34:33 PM PDT 24
Peak memory 216488 kb
Host smart-f8ae295f-ae46-4266-9e1f-ca5d6a95bb47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761398068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.761398068
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.1584275776
Short name T768
Test name
Test status
Simulation time 46194145 ps
CPU time 0.94 seconds
Started Jul 26 05:34:25 PM PDT 24
Finished Jul 26 05:34:26 PM PDT 24
Peak memory 207068 kb
Host smart-cdfb17e6-3b1e-45e8-9978-f0a83dc074f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584275776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.1584275776
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.414608434
Short name T46
Test name
Test status
Simulation time 20200868 ps
CPU time 0.7 seconds
Started Jul 26 05:34:25 PM PDT 24
Finished Jul 26 05:34:26 PM PDT 24
Peak memory 206012 kb
Host smart-ab4e8a26-0fa7-450f-9a02-82f0586a2c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414608434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.414608434
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.315053350
Short name T164
Test name
Test status
Simulation time 379160617 ps
CPU time 5.37 seconds
Started Jul 26 05:34:27 PM PDT 24
Finished Jul 26 05:34:32 PM PDT 24
Peak memory 237588 kb
Host smart-a5c18904-f8a3-4c15-b7d3-1830ece0c016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315053350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.315053350
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.1442802284
Short name T430
Test name
Test status
Simulation time 20702149 ps
CPU time 0.73 seconds
Started Jul 26 05:34:24 PM PDT 24
Finished Jul 26 05:34:25 PM PDT 24
Peak memory 205896 kb
Host smart-3f0b4906-85bd-4702-887a-642d83793794
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442802284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
1442802284
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.691567833
Short name T751
Test name
Test status
Simulation time 665290085 ps
CPU time 3.89 seconds
Started Jul 26 05:34:29 PM PDT 24
Finished Jul 26 05:34:33 PM PDT 24
Peak memory 224840 kb
Host smart-4675ad6d-5c95-466d-8202-f5d517328351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691567833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.691567833
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.1629083285
Short name T972
Test name
Test status
Simulation time 126239080 ps
CPU time 0.83 seconds
Started Jul 26 05:34:26 PM PDT 24
Finished Jul 26 05:34:27 PM PDT 24
Peak memory 206984 kb
Host smart-240680ee-a003-4b0f-ae06-a0f74d42135f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629083285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.1629083285
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.4067881940
Short name T924
Test name
Test status
Simulation time 147214956147 ps
CPU time 255.56 seconds
Started Jul 26 05:34:27 PM PDT 24
Finished Jul 26 05:38:43 PM PDT 24
Peak memory 257092 kb
Host smart-373a422d-fa28-47b2-b521-e1adc12e77d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067881940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.4067881940
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.180336652
Short name T230
Test name
Test status
Simulation time 72980774245 ps
CPU time 350.08 seconds
Started Jul 26 05:34:26 PM PDT 24
Finished Jul 26 05:40:16 PM PDT 24
Peak memory 256064 kb
Host smart-278b1fd4-3c89-4702-b9f3-e0188636550b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180336652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.180336652
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.3256533782
Short name T175
Test name
Test status
Simulation time 34781391485 ps
CPU time 152.97 seconds
Started Jul 26 05:34:30 PM PDT 24
Finished Jul 26 05:37:03 PM PDT 24
Peak memory 249360 kb
Host smart-5e22c76d-65c8-46b4-90f0-a42ad93bbd62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256533782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.3256533782
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.1213805823
Short name T755
Test name
Test status
Simulation time 55537034 ps
CPU time 2.76 seconds
Started Jul 26 05:34:24 PM PDT 24
Finished Jul 26 05:34:27 PM PDT 24
Peak memory 232852 kb
Host smart-281f6169-115d-484b-8df5-aeddb1b81d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213805823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.1213805823
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.791245368
Short name T176
Test name
Test status
Simulation time 369797306 ps
CPU time 4.68 seconds
Started Jul 26 05:34:29 PM PDT 24
Finished Jul 26 05:34:34 PM PDT 24
Peak memory 224656 kb
Host smart-0c872b76-e95e-45a6-a428-6aabd0a1757f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791245368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.791245368
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.1117143572
Short name T598
Test name
Test status
Simulation time 265993722 ps
CPU time 2.18 seconds
Started Jul 26 05:34:23 PM PDT 24
Finished Jul 26 05:34:25 PM PDT 24
Peak memory 223904 kb
Host smart-afd6b222-c618-426e-ae12-58613d97da1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117143572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.1117143572
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.1500436954
Short name T488
Test name
Test status
Simulation time 1561192855 ps
CPU time 6.23 seconds
Started Jul 26 05:34:24 PM PDT 24
Finished Jul 26 05:34:31 PM PDT 24
Peak memory 224604 kb
Host smart-8a45c8cb-faf2-484a-b0fc-d0437b76ed2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500436954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.1500436954
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.4081963880
Short name T989
Test name
Test status
Simulation time 4657691286 ps
CPU time 12.57 seconds
Started Jul 26 05:34:31 PM PDT 24
Finished Jul 26 05:34:44 PM PDT 24
Peak memory 232756 kb
Host smart-c4177dec-0399-4fe6-9789-90d8c1b403c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081963880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.4081963880
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.896093651
Short name T881
Test name
Test status
Simulation time 1914711839 ps
CPU time 4.28 seconds
Started Jul 26 05:34:27 PM PDT 24
Finished Jul 26 05:34:31 PM PDT 24
Peak memory 219140 kb
Host smart-8e9070c2-bda4-4c4a-aac8-04f891dfb66c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=896093651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dire
ct.896093651
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.2875504453
Short name T998
Test name
Test status
Simulation time 209656247 ps
CPU time 0.96 seconds
Started Jul 26 05:34:25 PM PDT 24
Finished Jul 26 05:34:26 PM PDT 24
Peak memory 207036 kb
Host smart-bc3db940-8cf5-4c33-955c-46887482aa51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875504453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.2875504453
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.2037432275
Short name T379
Test name
Test status
Simulation time 8258963756 ps
CPU time 26.7 seconds
Started Jul 26 05:34:31 PM PDT 24
Finished Jul 26 05:34:58 PM PDT 24
Peak memory 216480 kb
Host smart-a8b6e6e8-3bd8-4747-8e58-040fd15d9719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037432275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.2037432275
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.2897820042
Short name T475
Test name
Test status
Simulation time 1091805402 ps
CPU time 6.78 seconds
Started Jul 26 05:34:26 PM PDT 24
Finished Jul 26 05:34:33 PM PDT 24
Peak memory 216356 kb
Host smart-5b4d36c8-3fc1-4858-bc3f-90da0e2a6a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897820042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.2897820042
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.614727833
Short name T1007
Test name
Test status
Simulation time 176386386 ps
CPU time 1.1 seconds
Started Jul 26 05:34:27 PM PDT 24
Finished Jul 26 05:34:28 PM PDT 24
Peak memory 207428 kb
Host smart-06babf4f-a299-47fc-8472-e661cf6c2fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614727833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.614727833
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.242714804
Short name T510
Test name
Test status
Simulation time 97259295 ps
CPU time 0.81 seconds
Started Jul 26 05:34:25 PM PDT 24
Finished Jul 26 05:34:26 PM PDT 24
Peak memory 206068 kb
Host smart-db20a84b-ad0f-4805-9ea9-5a38cb48023f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242714804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.242714804
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.4085696040
Short name T871
Test name
Test status
Simulation time 118676775 ps
CPU time 2.65 seconds
Started Jul 26 05:34:23 PM PDT 24
Finished Jul 26 05:34:26 PM PDT 24
Peak memory 224632 kb
Host smart-b49ba135-2c21-4c1f-a83f-ff951cabcb35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085696040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.4085696040
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.55420968
Short name T302
Test name
Test status
Simulation time 53172931 ps
CPU time 0.73 seconds
Started Jul 26 05:34:37 PM PDT 24
Finished Jul 26 05:34:38 PM PDT 24
Peak memory 205564 kb
Host smart-ef0becb4-e366-4ca7-b058-e66bf7eea190
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55420968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.55420968
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.134276873
Short name T377
Test name
Test status
Simulation time 343243528 ps
CPU time 5.88 seconds
Started Jul 26 05:34:26 PM PDT 24
Finished Jul 26 05:34:32 PM PDT 24
Peak memory 224492 kb
Host smart-b90e15cf-e729-422a-9cdd-f5d52b57dc2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134276873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.134276873
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.478125003
Short name T561
Test name
Test status
Simulation time 45097928 ps
CPU time 0.77 seconds
Started Jul 26 05:34:25 PM PDT 24
Finished Jul 26 05:34:26 PM PDT 24
Peak memory 206696 kb
Host smart-6fb5c401-00ae-49df-af73-fe1c310b727c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478125003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.478125003
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.2596030591
Short name T664
Test name
Test status
Simulation time 202734359 ps
CPU time 4.68 seconds
Started Jul 26 05:34:30 PM PDT 24
Finished Jul 26 05:34:35 PM PDT 24
Peak memory 235192 kb
Host smart-5e6b71a7-a348-49d6-8b41-1892e88474a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596030591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.2596030591
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.2323606673
Short name T904
Test name
Test status
Simulation time 701469728 ps
CPU time 4 seconds
Started Jul 26 05:34:35 PM PDT 24
Finished Jul 26 05:34:39 PM PDT 24
Peak memory 224656 kb
Host smart-02367eb7-b526-4b95-83d9-e6f047c38abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323606673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.2323606673
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.1385804302
Short name T868
Test name
Test status
Simulation time 4087638154 ps
CPU time 9.81 seconds
Started Jul 26 05:34:38 PM PDT 24
Finished Jul 26 05:34:48 PM PDT 24
Peak memory 232812 kb
Host smart-b2cee2f4-1862-49c6-8b54-4571d5c3d0d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385804302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.1385804302
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.2879655098
Short name T266
Test name
Test status
Simulation time 156617019 ps
CPU time 4.4 seconds
Started Jul 26 05:34:23 PM PDT 24
Finished Jul 26 05:34:27 PM PDT 24
Peak memory 232868 kb
Host smart-0d2f7509-45ee-4ab8-a7db-c2145f078173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879655098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.2879655098
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_intercept.2725016538
Short name T333
Test name
Test status
Simulation time 223350818 ps
CPU time 4.99 seconds
Started Jul 26 05:34:24 PM PDT 24
Finished Jul 26 05:34:29 PM PDT 24
Peak memory 232876 kb
Host smart-85d80104-50e4-4d96-b0e3-1ce48f26c939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725016538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.2725016538
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.1152812836
Short name T894
Test name
Test status
Simulation time 2084838459 ps
CPU time 8.25 seconds
Started Jul 26 05:34:26 PM PDT 24
Finished Jul 26 05:34:34 PM PDT 24
Peak memory 240760 kb
Host smart-8648a250-55ca-4f7e-bab6-b01434509320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152812836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.1152812836
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.1478431371
Short name T191
Test name
Test status
Simulation time 5102866362 ps
CPU time 7.84 seconds
Started Jul 26 05:34:25 PM PDT 24
Finished Jul 26 05:34:33 PM PDT 24
Peak memory 232836 kb
Host smart-aa33909b-67e8-4c7c-895f-030a4ede9ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478431371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.1478431371
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.851352224
Short name T332
Test name
Test status
Simulation time 256416514 ps
CPU time 2.42 seconds
Started Jul 26 05:34:26 PM PDT 24
Finished Jul 26 05:34:29 PM PDT 24
Peak memory 232468 kb
Host smart-c0a616bc-7d94-4eae-afcf-06923d0f05f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851352224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.851352224
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.1205852245
Short name T367
Test name
Test status
Simulation time 368949007 ps
CPU time 5.02 seconds
Started Jul 26 05:34:24 PM PDT 24
Finished Jul 26 05:34:30 PM PDT 24
Peak memory 222836 kb
Host smart-5731cdf2-e005-429d-a0d3-db0fda44906e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1205852245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.1205852245
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.1270751732
Short name T996
Test name
Test status
Simulation time 2654743661 ps
CPU time 54.99 seconds
Started Jul 26 05:34:40 PM PDT 24
Finished Jul 26 05:35:35 PM PDT 24
Peak memory 252908 kb
Host smart-f0c7b593-b4e2-426c-b7be-eb8de9fe1de6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270751732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.1270751732
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.3581185358
Short name T646
Test name
Test status
Simulation time 5043615284 ps
CPU time 18.92 seconds
Started Jul 26 05:34:31 PM PDT 24
Finished Jul 26 05:34:50 PM PDT 24
Peak memory 216792 kb
Host smart-826be12e-ece7-40b2-a4ab-a22461e63f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581185358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.3581185358
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.778169207
Short name T657
Test name
Test status
Simulation time 2542351667 ps
CPU time 5.73 seconds
Started Jul 26 05:34:26 PM PDT 24
Finished Jul 26 05:34:32 PM PDT 24
Peak memory 216464 kb
Host smart-0261d72a-4eab-4054-9cbd-259710693492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778169207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.778169207
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.4048924553
Short name T283
Test name
Test status
Simulation time 79235505 ps
CPU time 1.19 seconds
Started Jul 26 05:34:24 PM PDT 24
Finished Jul 26 05:34:26 PM PDT 24
Peak memory 216392 kb
Host smart-484831f4-97fc-4505-89a3-821d805d218c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048924553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.4048924553
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.2664314467
Short name T325
Test name
Test status
Simulation time 64711040 ps
CPU time 0.91 seconds
Started Jul 26 05:34:27 PM PDT 24
Finished Jul 26 05:34:28 PM PDT 24
Peak memory 206296 kb
Host smart-5cbf507c-d95d-4a99-af34-6f456e9acee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664314467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.2664314467
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.2498976946
Short name T671
Test name
Test status
Simulation time 118459289 ps
CPU time 2.85 seconds
Started Jul 26 05:34:23 PM PDT 24
Finished Jul 26 05:34:26 PM PDT 24
Peak memory 232808 kb
Host smart-de1dd9d7-b553-4b15-9eb3-b4fcc5c6fe60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498976946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.2498976946
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.638130299
Short name T300
Test name
Test status
Simulation time 44141870 ps
CPU time 0.71 seconds
Started Jul 26 05:34:35 PM PDT 24
Finished Jul 26 05:34:36 PM PDT 24
Peak memory 204928 kb
Host smart-9381dd58-c483-46b1-b4bb-a776854f0b3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638130299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.638130299
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.2115790938
Short name T215
Test name
Test status
Simulation time 373693469 ps
CPU time 5.18 seconds
Started Jul 26 05:34:35 PM PDT 24
Finished Jul 26 05:34:40 PM PDT 24
Peak memory 232836 kb
Host smart-97279359-75c8-4508-9e27-db3dcdf60a26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115790938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.2115790938
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.3976429104
Short name T482
Test name
Test status
Simulation time 40010411 ps
CPU time 0.76 seconds
Started Jul 26 05:34:39 PM PDT 24
Finished Jul 26 05:34:40 PM PDT 24
Peak memory 206668 kb
Host smart-fb7a83c0-5cca-45bf-8e55-7b263b7561d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976429104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.3976429104
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.3944851023
Short name T901
Test name
Test status
Simulation time 7988023163 ps
CPU time 81.17 seconds
Started Jul 26 05:34:38 PM PDT 24
Finished Jul 26 05:35:59 PM PDT 24
Peak memory 256512 kb
Host smart-635caefb-eeb8-4368-a938-d85bba67fab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944851023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.3944851023
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.824975372
Short name T534
Test name
Test status
Simulation time 63164986282 ps
CPU time 287.43 seconds
Started Jul 26 05:34:43 PM PDT 24
Finished Jul 26 05:39:30 PM PDT 24
Peak memory 265664 kb
Host smart-856072df-424c-4bd5-98fd-1366bd7cd557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824975372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.824975372
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.861522196
Short name T257
Test name
Test status
Simulation time 6171982930 ps
CPU time 121.03 seconds
Started Jul 26 05:34:38 PM PDT 24
Finished Jul 26 05:36:40 PM PDT 24
Peak memory 264264 kb
Host smart-dd398324-db14-4015-bf8a-35438aa9ada2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861522196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idle
.861522196
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.546940013
Short name T864
Test name
Test status
Simulation time 4156974556 ps
CPU time 7.66 seconds
Started Jul 26 05:34:34 PM PDT 24
Finished Jul 26 05:34:42 PM PDT 24
Peak memory 247840 kb
Host smart-44d874e6-32da-456b-91d5-7ac306fd11ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546940013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.546940013
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.611417896
Short name T577
Test name
Test status
Simulation time 46770354650 ps
CPU time 59.74 seconds
Started Jul 26 05:34:40 PM PDT 24
Finished Jul 26 05:35:40 PM PDT 24
Peak memory 249180 kb
Host smart-cd670585-b696-4f2f-9503-eaed0779fd49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611417896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmds
.611417896
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_intercept.3039993167
Short name T69
Test name
Test status
Simulation time 417753681 ps
CPU time 6.2 seconds
Started Jul 26 05:34:36 PM PDT 24
Finished Jul 26 05:34:43 PM PDT 24
Peak memory 224560 kb
Host smart-cce597d4-acb9-4122-a131-1cce01b09ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039993167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.3039993167
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.393220601
Short name T184
Test name
Test status
Simulation time 7118188729 ps
CPU time 13.81 seconds
Started Jul 26 05:34:38 PM PDT 24
Finished Jul 26 05:34:52 PM PDT 24
Peak memory 232876 kb
Host smart-8366a571-7d45-4e09-96d0-47189f37890d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393220601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.393220601
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.1753725191
Short name T994
Test name
Test status
Simulation time 339059872 ps
CPU time 4.99 seconds
Started Jul 26 05:34:39 PM PDT 24
Finished Jul 26 05:34:44 PM PDT 24
Peak memory 232860 kb
Host smart-120a24d3-f9cb-428f-ac34-28e2604c308b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753725191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.1753725191
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.3928415665
Short name T738
Test name
Test status
Simulation time 103816692884 ps
CPU time 36.87 seconds
Started Jul 26 05:34:37 PM PDT 24
Finished Jul 26 05:35:14 PM PDT 24
Peak memory 224676 kb
Host smart-d76672ca-81d7-4340-9e24-294d80116631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928415665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.3928415665
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.3494692444
Short name T632
Test name
Test status
Simulation time 3530155931 ps
CPU time 20.34 seconds
Started Jul 26 05:34:35 PM PDT 24
Finished Jul 26 05:34:55 PM PDT 24
Peak memory 221428 kb
Host smart-d0bfc509-15f8-43c1-8b5c-a2e040058ab4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3494692444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.3494692444
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.3888339036
Short name T121
Test name
Test status
Simulation time 259378166286 ps
CPU time 250.7 seconds
Started Jul 26 05:34:35 PM PDT 24
Finished Jul 26 05:38:46 PM PDT 24
Peak memory 256896 kb
Host smart-4133ea71-5045-4f92-8633-51bbb468bf05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888339036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.3888339036
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.2042074996
Short name T287
Test name
Test status
Simulation time 3998791274 ps
CPU time 32.01 seconds
Started Jul 26 05:34:35 PM PDT 24
Finished Jul 26 05:35:07 PM PDT 24
Peak memory 216676 kb
Host smart-1c21266a-e66b-4664-ac53-9a3a4bdf42f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042074996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.2042074996
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.151712009
Short name T526
Test name
Test status
Simulation time 13263963576 ps
CPU time 16.85 seconds
Started Jul 26 05:34:36 PM PDT 24
Finished Jul 26 05:34:53 PM PDT 24
Peak memory 216416 kb
Host smart-77ce5ec3-2689-4a87-8abc-c80cb6676e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151712009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.151712009
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.2456640431
Short name T354
Test name
Test status
Simulation time 36505315 ps
CPU time 1.32 seconds
Started Jul 26 05:34:35 PM PDT 24
Finished Jul 26 05:34:36 PM PDT 24
Peak memory 216384 kb
Host smart-e5667bca-917f-4534-a0da-b3b736665b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456640431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.2456640431
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.1947363294
Short name T650
Test name
Test status
Simulation time 33881772 ps
CPU time 0.66 seconds
Started Jul 26 05:34:35 PM PDT 24
Finished Jul 26 05:34:36 PM PDT 24
Peak memory 205576 kb
Host smart-0381cc20-713b-4579-8429-e3c43dcecf13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947363294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.1947363294
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.2049645382
Short name T799
Test name
Test status
Simulation time 114619075 ps
CPU time 2.7 seconds
Started Jul 26 05:34:40 PM PDT 24
Finished Jul 26 05:34:42 PM PDT 24
Peak memory 232668 kb
Host smart-48f882d2-fb4b-4b9f-b230-a0bdba771d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049645382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.2049645382
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.3937082375
Short name T612
Test name
Test status
Simulation time 14561289 ps
CPU time 0.73 seconds
Started Jul 26 05:34:36 PM PDT 24
Finished Jul 26 05:34:37 PM PDT 24
Peak memory 205844 kb
Host smart-0cf17b07-2cf0-4f7f-ab4e-875393c7ea2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937082375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
3937082375
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.640489074
Short name T303
Test name
Test status
Simulation time 61856874 ps
CPU time 2.44 seconds
Started Jul 26 05:34:39 PM PDT 24
Finished Jul 26 05:34:41 PM PDT 24
Peak memory 232456 kb
Host smart-f0f65dd6-d69e-413f-b578-633538ed8d09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640489074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.640489074
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.635717418
Short name T582
Test name
Test status
Simulation time 16894471 ps
CPU time 0.78 seconds
Started Jul 26 05:34:37 PM PDT 24
Finished Jul 26 05:34:38 PM PDT 24
Peak memory 207032 kb
Host smart-bd8efc09-4e32-4d4d-9a4e-111ba878b39d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635717418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.635717418
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.2834939384
Short name T888
Test name
Test status
Simulation time 7148785261 ps
CPU time 70.11 seconds
Started Jul 26 05:34:37 PM PDT 24
Finished Jul 26 05:35:47 PM PDT 24
Peak memory 272964 kb
Host smart-b39a3f72-539e-43c2-9c6c-ff3b88c1c673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834939384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.2834939384
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.1463279601
Short name T790
Test name
Test status
Simulation time 59969685532 ps
CPU time 304.27 seconds
Started Jul 26 05:34:33 PM PDT 24
Finished Jul 26 05:39:37 PM PDT 24
Peak memory 265764 kb
Host smart-a8938753-fda8-4500-80e2-ac6cd5e16fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463279601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.1463279601
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.2245034277
Short name T507
Test name
Test status
Simulation time 10977742953 ps
CPU time 74.61 seconds
Started Jul 26 05:34:35 PM PDT 24
Finished Jul 26 05:35:50 PM PDT 24
Peak memory 249372 kb
Host smart-27f57a2f-56a8-49cd-9631-dbb0202c15b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245034277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.2245034277
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.945820027
Short name T269
Test name
Test status
Simulation time 7123470307 ps
CPU time 38.65 seconds
Started Jul 26 05:34:35 PM PDT 24
Finished Jul 26 05:35:14 PM PDT 24
Peak memory 240896 kb
Host smart-9e3b8ecf-d3cb-407f-b8a0-a7f6f90afae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945820027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.945820027
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.2774694158
Short name T578
Test name
Test status
Simulation time 8801838644 ps
CPU time 61.96 seconds
Started Jul 26 05:34:39 PM PDT 24
Finished Jul 26 05:35:41 PM PDT 24
Peak memory 269228 kb
Host smart-e394d1f7-baba-41ef-8d6e-aa089650bbbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774694158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmd
s.2774694158
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/34.spi_device_intercept.4070909953
Short name T587
Test name
Test status
Simulation time 5429287552 ps
CPU time 23.73 seconds
Started Jul 26 05:34:35 PM PDT 24
Finished Jul 26 05:34:59 PM PDT 24
Peak memory 224736 kb
Host smart-d93cda5d-b124-4e9e-b254-349a28439801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070909953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.4070909953
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.162051767
Short name T485
Test name
Test status
Simulation time 96990705 ps
CPU time 2.51 seconds
Started Jul 26 05:34:35 PM PDT 24
Finished Jul 26 05:34:38 PM PDT 24
Peak memory 224696 kb
Host smart-9baa234f-9a91-4b4b-8daa-2bb62f73c35a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162051767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.162051767
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.96680781
Short name T171
Test name
Test status
Simulation time 40151127866 ps
CPU time 10.53 seconds
Started Jul 26 05:34:37 PM PDT 24
Finished Jul 26 05:34:48 PM PDT 24
Peak memory 232864 kb
Host smart-6d144f80-4657-44e3-87b0-f448f2df0f0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96680781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swap.96680781
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.2097037170
Short name T306
Test name
Test status
Simulation time 254786454 ps
CPU time 2.51 seconds
Started Jul 26 05:34:37 PM PDT 24
Finished Jul 26 05:34:40 PM PDT 24
Peak memory 232520 kb
Host smart-e2d5194c-fce7-4c08-9adf-41ad12bc0b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097037170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.2097037170
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.586313227
Short name T4
Test name
Test status
Simulation time 2936025178 ps
CPU time 9.95 seconds
Started Jul 26 05:34:38 PM PDT 24
Finished Jul 26 05:34:48 PM PDT 24
Peak memory 223388 kb
Host smart-aa8d942c-ab9e-4419-8b65-fae41b5085c1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=586313227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dire
ct.586313227
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.469057723
Short name T993
Test name
Test status
Simulation time 260219209 ps
CPU time 1.16 seconds
Started Jul 26 05:34:38 PM PDT 24
Finished Jul 26 05:34:39 PM PDT 24
Peak memory 207156 kb
Host smart-b9f959f7-f0a8-41c1-a1e6-2ea839abf181
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469057723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stres
s_all.469057723
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.801999384
Short name T338
Test name
Test status
Simulation time 964250295 ps
CPU time 12.9 seconds
Started Jul 26 05:34:36 PM PDT 24
Finished Jul 26 05:34:49 PM PDT 24
Peak memory 216528 kb
Host smart-a8d96bf3-2a52-4443-a8ef-baec4c5e1f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801999384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.801999384
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.3948794864
Short name T346
Test name
Test status
Simulation time 5301886853 ps
CPU time 13.7 seconds
Started Jul 26 05:34:39 PM PDT 24
Finished Jul 26 05:34:52 PM PDT 24
Peak memory 216464 kb
Host smart-cdf00134-fd11-45b6-9634-be2f47596730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948794864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.3948794864
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.1723286802
Short name T588
Test name
Test status
Simulation time 97289813 ps
CPU time 0.82 seconds
Started Jul 26 05:34:36 PM PDT 24
Finished Jul 26 05:34:37 PM PDT 24
Peak memory 206080 kb
Host smart-b4960a3d-cbac-4bdc-88aa-bbf407388979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723286802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.1723286802
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.1325715227
Short name T801
Test name
Test status
Simulation time 99487540 ps
CPU time 0.85 seconds
Started Jul 26 05:34:39 PM PDT 24
Finished Jul 26 05:34:40 PM PDT 24
Peak memory 206396 kb
Host smart-3c704e47-13b1-4df7-af3d-1beaa9e0c9f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325715227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.1325715227
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.1113305469
Short name T429
Test name
Test status
Simulation time 895367087 ps
CPU time 3.62 seconds
Started Jul 26 05:34:39 PM PDT 24
Finished Jul 26 05:34:43 PM PDT 24
Peak memory 224652 kb
Host smart-1d212870-d9ad-4365-bde0-e6923bff4794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113305469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.1113305469
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.3036985477
Short name T565
Test name
Test status
Simulation time 22686242 ps
CPU time 0.72 seconds
Started Jul 26 05:34:50 PM PDT 24
Finished Jul 26 05:34:51 PM PDT 24
Peak memory 205556 kb
Host smart-62d34b30-d8fd-4176-a09e-57d13a73e750
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036985477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
3036985477
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.2371894494
Short name T545
Test name
Test status
Simulation time 315005382 ps
CPU time 3.65 seconds
Started Jul 26 05:34:50 PM PDT 24
Finished Jul 26 05:34:54 PM PDT 24
Peak memory 232884 kb
Host smart-3a0a3437-6201-4e55-8b40-761684e0b6c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371894494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.2371894494
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.1186789420
Short name T464
Test name
Test status
Simulation time 36920833 ps
CPU time 0.8 seconds
Started Jul 26 05:34:38 PM PDT 24
Finished Jul 26 05:34:39 PM PDT 24
Peak memory 206688 kb
Host smart-52652b7e-b88e-4807-b86e-e09cc5a27afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186789420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.1186789420
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.4182960221
Short name T253
Test name
Test status
Simulation time 19205626109 ps
CPU time 124.83 seconds
Started Jul 26 05:34:50 PM PDT 24
Finished Jul 26 05:36:55 PM PDT 24
Peak memory 256112 kb
Host smart-9a71287a-3ae6-4dff-b8ed-633ec7ce0ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182960221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.4182960221
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.881592679
Short name T807
Test name
Test status
Simulation time 2777608017 ps
CPU time 36.18 seconds
Started Jul 26 05:34:50 PM PDT 24
Finished Jul 26 05:35:27 PM PDT 24
Peak memory 240692 kb
Host smart-530dbbde-389f-4b3b-99fa-aef174358c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881592679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.881592679
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.1338632193
Short name T285
Test name
Test status
Simulation time 6893405134 ps
CPU time 11.73 seconds
Started Jul 26 05:34:50 PM PDT 24
Finished Jul 26 05:35:02 PM PDT 24
Peak memory 217652 kb
Host smart-ee9d290f-f941-4194-b541-f7565832df8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338632193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.1338632193
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.157953151
Short name T902
Test name
Test status
Simulation time 1121238521 ps
CPU time 7.95 seconds
Started Jul 26 05:34:51 PM PDT 24
Finished Jul 26 05:34:59 PM PDT 24
Peak memory 239488 kb
Host smart-ba3c8ed7-cfff-4098-a981-23b7cdb6ba56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157953151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.157953151
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.2250943885
Short name T372
Test name
Test status
Simulation time 42757525 ps
CPU time 0.75 seconds
Started Jul 26 05:34:51 PM PDT 24
Finished Jul 26 05:34:52 PM PDT 24
Peak memory 215796 kb
Host smart-a6f1f8b4-71e5-4b1c-afb5-4f9302af9979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250943885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmd
s.2250943885
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_intercept.203836498
Short name T497
Test name
Test status
Simulation time 1371705037 ps
CPU time 6.11 seconds
Started Jul 26 05:34:51 PM PDT 24
Finished Jul 26 05:34:57 PM PDT 24
Peak memory 224704 kb
Host smart-11c24852-2b48-4c46-a2e8-45ca3bfb94be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203836498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.203836498
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.343720495
Short name T928
Test name
Test status
Simulation time 4513872212 ps
CPU time 46.06 seconds
Started Jul 26 05:34:50 PM PDT 24
Finished Jul 26 05:35:36 PM PDT 24
Peak memory 240888 kb
Host smart-9de9ec2b-aebb-49dd-a210-0f549ba894d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343720495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.343720495
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.999607990
Short name T250
Test name
Test status
Simulation time 200225905 ps
CPU time 2.43 seconds
Started Jul 26 05:34:50 PM PDT 24
Finished Jul 26 05:34:52 PM PDT 24
Peak memory 224568 kb
Host smart-bbd71a98-e4e5-4cd4-befa-056fd5e3c434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999607990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swap
.999607990
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.2896315518
Short name T970
Test name
Test status
Simulation time 1190180041 ps
CPU time 6.34 seconds
Started Jul 26 05:34:53 PM PDT 24
Finished Jul 26 05:34:59 PM PDT 24
Peak memory 232780 kb
Host smart-dc1e9cd9-ab48-4bfa-a1ce-168aa937d7d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896315518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.2896315518
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.1179093144
Short name T312
Test name
Test status
Simulation time 207098129 ps
CPU time 4.25 seconds
Started Jul 26 05:34:51 PM PDT 24
Finished Jul 26 05:34:55 PM PDT 24
Peak memory 220384 kb
Host smart-09255e6b-0abe-4abb-9bb3-480fc8c04495
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1179093144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.1179093144
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.3899680728
Short name T394
Test name
Test status
Simulation time 5312086427 ps
CPU time 8.26 seconds
Started Jul 26 05:34:37 PM PDT 24
Finished Jul 26 05:34:46 PM PDT 24
Peak memory 216396 kb
Host smart-df55ccf9-ba15-4283-9ec2-2c0593ca6d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899680728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.3899680728
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.3832511670
Short name T673
Test name
Test status
Simulation time 224955956 ps
CPU time 1.42 seconds
Started Jul 26 05:34:37 PM PDT 24
Finished Jul 26 05:34:38 PM PDT 24
Peak memory 207908 kb
Host smart-849b6bbc-d132-4bb5-8ce9-87d858a01149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832511670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.3832511670
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.3553875530
Short name T465
Test name
Test status
Simulation time 228068332 ps
CPU time 1.7 seconds
Started Jul 26 05:34:51 PM PDT 24
Finished Jul 26 05:34:53 PM PDT 24
Peak memory 216440 kb
Host smart-1a24ce8e-d4cb-4f9b-bde6-5abc1b7720e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553875530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.3553875530
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.2831005975
Short name T863
Test name
Test status
Simulation time 81533551 ps
CPU time 0.97 seconds
Started Jul 26 05:34:53 PM PDT 24
Finished Jul 26 05:34:54 PM PDT 24
Peak memory 206032 kb
Host smart-9cbc5d8f-5c61-46a0-8116-d9ff62d8bc4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831005975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.2831005975
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.1333543801
Short name T426
Test name
Test status
Simulation time 26330510995 ps
CPU time 21.56 seconds
Started Jul 26 05:34:51 PM PDT 24
Finished Jul 26 05:35:13 PM PDT 24
Peak memory 241084 kb
Host smart-2c7928a7-b54f-4ac8-b503-f6ef79ab2592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333543801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.1333543801
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.3856394989
Short name T818
Test name
Test status
Simulation time 10751111 ps
CPU time 0.71 seconds
Started Jul 26 05:35:05 PM PDT 24
Finished Jul 26 05:35:06 PM PDT 24
Peak memory 204940 kb
Host smart-dfc8c238-7b79-403f-9a33-a5e49d7bcf10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856394989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
3856394989
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.1429589977
Short name T849
Test name
Test status
Simulation time 380763586 ps
CPU time 2.41 seconds
Started Jul 26 05:34:53 PM PDT 24
Finished Jul 26 05:34:56 PM PDT 24
Peak memory 224604 kb
Host smart-3bb961e1-2e6b-4a48-98e4-3b0b812a6d4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429589977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.1429589977
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.1016914231
Short name T49
Test name
Test status
Simulation time 16347025 ps
CPU time 0.84 seconds
Started Jul 26 05:34:53 PM PDT 24
Finished Jul 26 05:34:54 PM PDT 24
Peak memory 205692 kb
Host smart-81f257a3-2d19-4205-8006-67ae9a5ade54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016914231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.1016914231
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.1977936814
Short name T342
Test name
Test status
Simulation time 41863112968 ps
CPU time 154.68 seconds
Started Jul 26 05:34:51 PM PDT 24
Finished Jul 26 05:37:26 PM PDT 24
Peak memory 255456 kb
Host smart-b92ab93e-30a4-4f1d-ba99-aab50af39564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977936814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.1977936814
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.1503319375
Short name T467
Test name
Test status
Simulation time 6352010058 ps
CPU time 46.56 seconds
Started Jul 26 05:34:51 PM PDT 24
Finished Jul 26 05:35:38 PM PDT 24
Peak memory 235024 kb
Host smart-cffad1e8-f807-4ba1-95f0-576e7662bc5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503319375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.1503319375
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.1247264632
Short name T675
Test name
Test status
Simulation time 2634451941 ps
CPU time 49.59 seconds
Started Jul 26 05:34:51 PM PDT 24
Finished Jul 26 05:35:41 PM PDT 24
Peak memory 250648 kb
Host smart-9f92a29d-0a4c-4d16-8df8-a8b11604625f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247264632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.1247264632
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.3903311891
Short name T873
Test name
Test status
Simulation time 522515230 ps
CPU time 8.41 seconds
Started Jul 26 05:34:52 PM PDT 24
Finished Jul 26 05:35:01 PM PDT 24
Peak memory 224628 kb
Host smart-b5abcafb-3f0e-4e70-9561-a61af500b3d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903311891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.3903311891
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.918934492
Short name T916
Test name
Test status
Simulation time 3772117543 ps
CPU time 58.59 seconds
Started Jul 26 05:34:53 PM PDT 24
Finished Jul 26 05:35:52 PM PDT 24
Peak memory 257008 kb
Host smart-258c14c8-a225-4982-9806-3d4306d7fd39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918934492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmds
.918934492
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_intercept.254494355
Short name T295
Test name
Test status
Simulation time 56930867 ps
CPU time 2.06 seconds
Started Jul 26 05:34:52 PM PDT 24
Finished Jul 26 05:34:54 PM PDT 24
Peak memory 223212 kb
Host smart-279ac948-8404-47db-ba7a-e96298a31f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254494355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.254494355
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.1066099750
Short name T629
Test name
Test status
Simulation time 1704771476 ps
CPU time 19.08 seconds
Started Jul 26 05:34:52 PM PDT 24
Finished Jul 26 05:35:11 PM PDT 24
Peak memory 234824 kb
Host smart-a4aff9d1-bf3e-4842-9059-580dbb6afb1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066099750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.1066099750
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.2436159090
Short name T9
Test name
Test status
Simulation time 15026483113 ps
CPU time 8.3 seconds
Started Jul 26 05:34:52 PM PDT 24
Finished Jul 26 05:35:01 PM PDT 24
Peak memory 232840 kb
Host smart-e07fe471-e9e4-4cd9-8e4a-3e1f698c9435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436159090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.2436159090
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.2060965916
Short name T604
Test name
Test status
Simulation time 174976981 ps
CPU time 2.48 seconds
Started Jul 26 05:34:53 PM PDT 24
Finished Jul 26 05:34:55 PM PDT 24
Peak memory 224612 kb
Host smart-ec6aa422-b3fb-40a3-9d85-06af2b3dfdf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060965916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.2060965916
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.1560626050
Short name T630
Test name
Test status
Simulation time 869058684 ps
CPU time 7.03 seconds
Started Jul 26 05:34:51 PM PDT 24
Finished Jul 26 05:34:58 PM PDT 24
Peak memory 220552 kb
Host smart-191bb868-95b1-4abc-bd02-4c00bde018a5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1560626050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.1560626050
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.347609970
Short name T637
Test name
Test status
Simulation time 1705072727 ps
CPU time 12.11 seconds
Started Jul 26 05:34:51 PM PDT 24
Finished Jul 26 05:35:04 PM PDT 24
Peak memory 217740 kb
Host smart-e28d3075-c25c-4cce-b34f-1e333158760b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347609970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stres
s_all.347609970
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.2519589966
Short name T753
Test name
Test status
Simulation time 6272265352 ps
CPU time 38.3 seconds
Started Jul 26 05:34:53 PM PDT 24
Finished Jul 26 05:35:32 PM PDT 24
Peak memory 216432 kb
Host smart-413812ea-2390-4005-9a28-201a53ab2096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519589966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.2519589966
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.2734404216
Short name T889
Test name
Test status
Simulation time 637441019 ps
CPU time 5.15 seconds
Started Jul 26 05:34:51 PM PDT 24
Finished Jul 26 05:34:56 PM PDT 24
Peak memory 216356 kb
Host smart-9b60f7a8-002f-4117-9a1c-88600939c76b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734404216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.2734404216
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.1471241652
Short name T574
Test name
Test status
Simulation time 257494652 ps
CPU time 2.97 seconds
Started Jul 26 05:34:51 PM PDT 24
Finished Jul 26 05:34:54 PM PDT 24
Peak memory 216332 kb
Host smart-4a4bd5db-b666-44a9-9f57-81353ec5de1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471241652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.1471241652
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.3511867162
Short name T329
Test name
Test status
Simulation time 181339323 ps
CPU time 0.89 seconds
Started Jul 26 05:34:52 PM PDT 24
Finished Jul 26 05:34:53 PM PDT 24
Peak memory 206044 kb
Host smart-bc85f162-dad2-4def-a790-6f4fac4aa309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511867162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.3511867162
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.202322928
Short name T514
Test name
Test status
Simulation time 137842201 ps
CPU time 2.55 seconds
Started Jul 26 05:34:51 PM PDT 24
Finished Jul 26 05:34:54 PM PDT 24
Peak memory 234140 kb
Host smart-22caf841-f14d-4cf5-988b-20a991eabf15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202322928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.202322928
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.1213373639
Short name T319
Test name
Test status
Simulation time 18821963 ps
CPU time 0.76 seconds
Started Jul 26 05:35:05 PM PDT 24
Finished Jul 26 05:35:06 PM PDT 24
Peak memory 205532 kb
Host smart-3674f968-a63e-472e-b586-a90bfda26348
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213373639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
1213373639
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.946818066
Short name T909
Test name
Test status
Simulation time 1447530885 ps
CPU time 5.22 seconds
Started Jul 26 05:35:05 PM PDT 24
Finished Jul 26 05:35:10 PM PDT 24
Peak memory 224620 kb
Host smart-2f464e87-c678-4a62-b258-c580e560c7d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946818066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.946818066
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.3210801915
Short name T936
Test name
Test status
Simulation time 12567861 ps
CPU time 0.77 seconds
Started Jul 26 05:35:03 PM PDT 24
Finished Jul 26 05:35:04 PM PDT 24
Peak memory 205680 kb
Host smart-7dcfcb30-99f3-4829-a197-dd54ed53b4f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210801915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.3210801915
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.1402430793
Short name T556
Test name
Test status
Simulation time 13756815098 ps
CPU time 98.6 seconds
Started Jul 26 05:35:02 PM PDT 24
Finished Jul 26 05:36:41 PM PDT 24
Peak memory 252056 kb
Host smart-1451c280-2553-4aad-ada4-e73af5417a00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402430793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.1402430793
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.3706829885
Short name T550
Test name
Test status
Simulation time 39026728388 ps
CPU time 40.08 seconds
Started Jul 26 05:35:04 PM PDT 24
Finished Jul 26 05:35:44 PM PDT 24
Peak memory 217816 kb
Host smart-d38e6dd0-5ed4-4031-aab4-b0a23e7018cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706829885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.3706829885
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.749441310
Short name T232
Test name
Test status
Simulation time 16186845398 ps
CPU time 106.91 seconds
Started Jul 26 05:35:09 PM PDT 24
Finished Jul 26 05:36:56 PM PDT 24
Peak memory 261732 kb
Host smart-2dd5c518-fc6c-411e-9a6c-29c4fe63775d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749441310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idle
.749441310
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.2375021507
Short name T421
Test name
Test status
Simulation time 3015190803 ps
CPU time 13.35 seconds
Started Jul 26 05:35:04 PM PDT 24
Finished Jul 26 05:35:18 PM PDT 24
Peak memory 241108 kb
Host smart-755a5216-5844-44bb-8d04-a3a1374af661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375021507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.2375021507
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.69824416
Short name T575
Test name
Test status
Simulation time 122758413808 ps
CPU time 453.76 seconds
Started Jul 26 05:35:05 PM PDT 24
Finished Jul 26 05:42:39 PM PDT 24
Peak memory 265224 kb
Host smart-f67a6d3d-1cef-499b-94f7-b031d6a4e1dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69824416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmds.69824416
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_intercept.4283743744
Short name T634
Test name
Test status
Simulation time 328514546 ps
CPU time 3.39 seconds
Started Jul 26 05:35:03 PM PDT 24
Finished Jul 26 05:35:07 PM PDT 24
Peak memory 232812 kb
Host smart-1b7031a3-23e6-4c98-8c00-0c25ea942017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283743744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.4283743744
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.3602308519
Short name T676
Test name
Test status
Simulation time 3501770898 ps
CPU time 33.85 seconds
Started Jul 26 05:35:04 PM PDT 24
Finished Jul 26 05:35:38 PM PDT 24
Peak memory 233824 kb
Host smart-e0feea73-6fc6-4921-85c9-2f07ccf6e5f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602308519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.3602308519
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.4132842448
Short name T878
Test name
Test status
Simulation time 7057810675 ps
CPU time 9.76 seconds
Started Jul 26 05:35:03 PM PDT 24
Finished Jul 26 05:35:13 PM PDT 24
Peak memory 232928 kb
Host smart-ddec0880-9d05-4014-a399-9d460e740c8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132842448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.4132842448
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.1253064275
Short name T593
Test name
Test status
Simulation time 117446993 ps
CPU time 2.45 seconds
Started Jul 26 05:35:04 PM PDT 24
Finished Jul 26 05:35:07 PM PDT 24
Peak memory 224584 kb
Host smart-419090a5-5544-49f1-a201-f3227c2999ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253064275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.1253064275
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.2852899149
Short name T555
Test name
Test status
Simulation time 1006329535 ps
CPU time 12.66 seconds
Started Jul 26 05:35:04 PM PDT 24
Finished Jul 26 05:35:17 PM PDT 24
Peak memory 223148 kb
Host smart-abbe8a15-3f75-4509-adc2-d54a8ac85e41
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2852899149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.2852899149
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.2818525276
Short name T913
Test name
Test status
Simulation time 167019072525 ps
CPU time 400.26 seconds
Started Jul 26 05:35:04 PM PDT 24
Finished Jul 26 05:41:44 PM PDT 24
Peak memory 250176 kb
Host smart-b2fb0bd8-6d54-40d3-a461-7116eb289f12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818525276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.2818525276
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.3853125362
Short name T635
Test name
Test status
Simulation time 7560237629 ps
CPU time 44.52 seconds
Started Jul 26 05:35:04 PM PDT 24
Finished Jul 26 05:35:49 PM PDT 24
Peak memory 216476 kb
Host smart-42df04ea-a206-4cb2-8384-16c54f14d254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853125362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.3853125362
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.204889366
Short name T298
Test name
Test status
Simulation time 6620711783 ps
CPU time 6.35 seconds
Started Jul 26 05:35:03 PM PDT 24
Finished Jul 26 05:35:10 PM PDT 24
Peak memory 216408 kb
Host smart-822a5c24-3404-4dbf-8f84-173c9d5686e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204889366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.204889366
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.1664043609
Short name T393
Test name
Test status
Simulation time 78577623 ps
CPU time 1.45 seconds
Started Jul 26 05:35:05 PM PDT 24
Finished Jul 26 05:35:07 PM PDT 24
Peak memory 216348 kb
Host smart-11f64d72-35e5-448d-90c0-a2df81a38178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664043609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.1664043609
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.3915866946
Short name T599
Test name
Test status
Simulation time 354557964 ps
CPU time 1.03 seconds
Started Jul 26 05:35:05 PM PDT 24
Finished Jul 26 05:35:06 PM PDT 24
Peak memory 207112 kb
Host smart-ad3c7d14-acd5-4c9e-8a58-6aa23b9d4438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915866946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.3915866946
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.4066319300
Short name T240
Test name
Test status
Simulation time 12422049556 ps
CPU time 20.14 seconds
Started Jul 26 05:35:05 PM PDT 24
Finished Jul 26 05:35:25 PM PDT 24
Peak memory 237064 kb
Host smart-f0345941-5292-4b76-a7a4-f40a78953839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066319300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.4066319300
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.2477625537
Short name T670
Test name
Test status
Simulation time 14244286 ps
CPU time 0.78 seconds
Started Jul 26 05:35:07 PM PDT 24
Finished Jul 26 05:35:08 PM PDT 24
Peak memory 204980 kb
Host smart-af779dc9-d659-4a2e-aade-716c3e2a5059
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477625537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
2477625537
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.2220998084
Short name T403
Test name
Test status
Simulation time 743707955 ps
CPU time 8.45 seconds
Started Jul 26 05:35:07 PM PDT 24
Finished Jul 26 05:35:16 PM PDT 24
Peak memory 232872 kb
Host smart-4a9b361e-ffe2-4c9d-950a-40d70ab651b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220998084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.2220998084
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.2620915934
Short name T594
Test name
Test status
Simulation time 31929333 ps
CPU time 0.77 seconds
Started Jul 26 05:35:04 PM PDT 24
Finished Jul 26 05:35:05 PM PDT 24
Peak memory 205692 kb
Host smart-a44b56e4-17c0-45fc-9edb-8dd14836b9ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620915934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.2620915934
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.3518424415
Short name T194
Test name
Test status
Simulation time 3084375750 ps
CPU time 65.01 seconds
Started Jul 26 05:35:09 PM PDT 24
Finished Jul 26 05:36:14 PM PDT 24
Peak memory 255776 kb
Host smart-19676b07-ecfb-42c5-8b9e-d7eb001f7028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518424415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.3518424415
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.2126396696
Short name T411
Test name
Test status
Simulation time 54596353706 ps
CPU time 245.98 seconds
Started Jul 26 05:35:07 PM PDT 24
Finished Jul 26 05:39:13 PM PDT 24
Peak memory 249520 kb
Host smart-8e762606-38d9-48f8-915d-78cf1cd04157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126396696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.2126396696
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.2430994371
Short name T436
Test name
Test status
Simulation time 19727147607 ps
CPU time 157.75 seconds
Started Jul 26 05:35:07 PM PDT 24
Finished Jul 26 05:37:45 PM PDT 24
Peak memory 252648 kb
Host smart-032fabf0-4dc2-42a2-a94f-a6e259b64d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430994371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.2430994371
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.1363682066
Short name T987
Test name
Test status
Simulation time 6687054728 ps
CPU time 30.66 seconds
Started Jul 26 05:35:07 PM PDT 24
Finished Jul 26 05:35:38 PM PDT 24
Peak memory 233960 kb
Host smart-3c1ecb64-db55-4765-910a-5c7ba03030d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363682066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.1363682066
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.1416816794
Short name T410
Test name
Test status
Simulation time 22282129546 ps
CPU time 76.86 seconds
Started Jul 26 05:35:07 PM PDT 24
Finished Jul 26 05:36:24 PM PDT 24
Peak memory 257496 kb
Host smart-7edf3c9f-0117-4a49-9ee3-08d0d7a67cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416816794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmd
s.1416816794
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_intercept.2486751734
Short name T934
Test name
Test status
Simulation time 411837575 ps
CPU time 2.28 seconds
Started Jul 26 05:35:08 PM PDT 24
Finished Jul 26 05:35:10 PM PDT 24
Peak memory 224244 kb
Host smart-b78217a0-9109-4d02-bc17-06217c9a4383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486751734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.2486751734
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.4091961601
Short name T841
Test name
Test status
Simulation time 814273568 ps
CPU time 3.66 seconds
Started Jul 26 05:35:08 PM PDT 24
Finished Jul 26 05:35:12 PM PDT 24
Peak memory 224588 kb
Host smart-8aa5aa81-e782-4674-a0b2-31a57295d54d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091961601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.4091961601
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.2835049793
Short name T452
Test name
Test status
Simulation time 212440893 ps
CPU time 3.03 seconds
Started Jul 26 05:35:08 PM PDT 24
Finished Jul 26 05:35:11 PM PDT 24
Peak memory 232848 kb
Host smart-165f9b47-b497-4c8f-a676-551fe06382db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835049793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.2835049793
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.1264847148
Short name T398
Test name
Test status
Simulation time 4436251276 ps
CPU time 7.57 seconds
Started Jul 26 05:35:09 PM PDT 24
Finished Jul 26 05:35:17 PM PDT 24
Peak memory 224676 kb
Host smart-83a75120-df15-448b-aae6-e04346461b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264847148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.1264847148
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.30255279
Short name T812
Test name
Test status
Simulation time 2687471506 ps
CPU time 10.14 seconds
Started Jul 26 05:35:04 PM PDT 24
Finished Jul 26 05:35:15 PM PDT 24
Peak memory 220800 kb
Host smart-bd869ac9-9a5c-437e-82c6-690444a136c8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=30255279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_direc
t.30255279
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.4077785773
Short name T122
Test name
Test status
Simulation time 17105719292 ps
CPU time 180.16 seconds
Started Jul 26 05:35:05 PM PDT 24
Finished Jul 26 05:38:06 PM PDT 24
Peak memory 287088 kb
Host smart-3a891cb0-1fca-485e-9867-6a73eea8fe27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077785773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.4077785773
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.2087871755
Short name T609
Test name
Test status
Simulation time 41052685 ps
CPU time 0.75 seconds
Started Jul 26 05:35:05 PM PDT 24
Finished Jul 26 05:35:06 PM PDT 24
Peak memory 205856 kb
Host smart-a6b3bbdb-54d9-4a80-9a98-5bda5ba0baab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087871755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.2087871755
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.1033025652
Short name T425
Test name
Test status
Simulation time 675290450 ps
CPU time 4.47 seconds
Started Jul 26 05:35:07 PM PDT 24
Finished Jul 26 05:35:11 PM PDT 24
Peak memory 216256 kb
Host smart-51ede908-e479-4c81-a085-ff8d180a66e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033025652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.1033025652
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.762732823
Short name T296
Test name
Test status
Simulation time 75872277 ps
CPU time 0.97 seconds
Started Jul 26 05:35:07 PM PDT 24
Finished Jul 26 05:35:08 PM PDT 24
Peak memory 207252 kb
Host smart-180be4d0-87df-4618-8a98-03a2359a2328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762732823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.762732823
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.528841666
Short name T847
Test name
Test status
Simulation time 47194320 ps
CPU time 0.86 seconds
Started Jul 26 05:35:06 PM PDT 24
Finished Jul 26 05:35:07 PM PDT 24
Peak memory 206004 kb
Host smart-0a0eeb47-b51c-4eb1-a873-5aab522fcec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528841666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.528841666
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.3001884980
Short name T679
Test name
Test status
Simulation time 395476243 ps
CPU time 2.64 seconds
Started Jul 26 05:35:04 PM PDT 24
Finished Jul 26 05:35:07 PM PDT 24
Peak memory 232856 kb
Host smart-245a06a0-8205-4c79-be94-b5aa9395b4c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001884980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.3001884980
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.4140078551
Short name T317
Test name
Test status
Simulation time 30152632 ps
CPU time 0.71 seconds
Started Jul 26 05:35:05 PM PDT 24
Finished Jul 26 05:35:06 PM PDT 24
Peak memory 205012 kb
Host smart-8a98baed-7253-4884-b14f-7c3eb9c98b2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140078551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
4140078551
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.439340436
Short name T243
Test name
Test status
Simulation time 1504826898 ps
CPU time 3.94 seconds
Started Jul 26 05:35:08 PM PDT 24
Finished Jul 26 05:35:12 PM PDT 24
Peak memory 224568 kb
Host smart-e04c1260-d716-44cb-b820-1a7b21e660e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439340436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.439340436
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.2893459809
Short name T484
Test name
Test status
Simulation time 17035692 ps
CPU time 0.78 seconds
Started Jul 26 05:35:08 PM PDT 24
Finished Jul 26 05:35:09 PM PDT 24
Peak memory 206612 kb
Host smart-5bba9155-2df4-4273-a1a1-d7342577d0f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893459809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.2893459809
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.583324326
Short name T922
Test name
Test status
Simulation time 5872178741 ps
CPU time 39.3 seconds
Started Jul 26 05:35:01 PM PDT 24
Finished Jul 26 05:35:40 PM PDT 24
Peak memory 232852 kb
Host smart-11fe35bb-085c-4068-b507-99d696a33ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583324326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.583324326
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.2276245453
Short name T992
Test name
Test status
Simulation time 2544011390 ps
CPU time 52.6 seconds
Started Jul 26 05:35:03 PM PDT 24
Finished Jul 26 05:35:56 PM PDT 24
Peak memory 240944 kb
Host smart-8a4eccfc-3217-4080-86b2-b542c5c40b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276245453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.2276245453
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.856672060
Short name T528
Test name
Test status
Simulation time 450927253 ps
CPU time 4.95 seconds
Started Jul 26 05:35:05 PM PDT 24
Finished Jul 26 05:35:11 PM PDT 24
Peak memory 217532 kb
Host smart-53b5f5a3-7cb6-4589-824b-d366911d5326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856672060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idle
.856672060
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.3890280456
Short name T744
Test name
Test status
Simulation time 1025384328 ps
CPU time 8.93 seconds
Started Jul 26 05:35:06 PM PDT 24
Finished Jul 26 05:35:16 PM PDT 24
Peak memory 232788 kb
Host smart-3841dd8b-c5b7-4bd9-a447-78b904b86795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890280456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.3890280456
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.2175063183
Short name T851
Test name
Test status
Simulation time 73500373351 ps
CPU time 134.26 seconds
Started Jul 26 05:35:04 PM PDT 24
Finished Jul 26 05:37:18 PM PDT 24
Peak memory 250028 kb
Host smart-fce58340-e46b-4c61-8f8f-3879e1de5f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175063183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmd
s.2175063183
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/39.spi_device_intercept.2012505257
Short name T678
Test name
Test status
Simulation time 923775995 ps
CPU time 11.02 seconds
Started Jul 26 05:35:08 PM PDT 24
Finished Jul 26 05:35:19 PM PDT 24
Peak memory 232760 kb
Host smart-6073c8ba-3c80-4a8a-acec-183656af23d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012505257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.2012505257
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.2099721264
Short name T698
Test name
Test status
Simulation time 1997617734 ps
CPU time 13.8 seconds
Started Jul 26 05:35:07 PM PDT 24
Finished Jul 26 05:35:21 PM PDT 24
Peak memory 240724 kb
Host smart-7b502502-2826-439c-95ee-d1646acc3e3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099721264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.2099721264
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.3215066467
Short name T503
Test name
Test status
Simulation time 147176417 ps
CPU time 2.98 seconds
Started Jul 26 05:35:07 PM PDT 24
Finished Jul 26 05:35:10 PM PDT 24
Peak memory 232876 kb
Host smart-097e6cef-11cc-4549-bebd-01b2adfe2e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215066467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.3215066467
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.1526173143
Short name T905
Test name
Test status
Simulation time 492617203 ps
CPU time 5.82 seconds
Started Jul 26 05:35:08 PM PDT 24
Finished Jul 26 05:35:14 PM PDT 24
Peak memory 224680 kb
Host smart-88d2ff75-f437-4bb6-a129-178ed87b4849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526173143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.1526173143
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.1552997073
Short name T70
Test name
Test status
Simulation time 13042402960 ps
CPU time 12.15 seconds
Started Jul 26 05:35:03 PM PDT 24
Finished Jul 26 05:35:15 PM PDT 24
Peak memory 220756 kb
Host smart-9b80ec70-4f22-422e-a944-1ce8a3742b5b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1552997073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.1552997073
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.699988825
Short name T418
Test name
Test status
Simulation time 123513189 ps
CPU time 0.94 seconds
Started Jul 26 05:35:02 PM PDT 24
Finished Jul 26 05:35:03 PM PDT 24
Peak memory 206916 kb
Host smart-93423cf5-b9be-42ca-8ebe-8d4716a524f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699988825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stres
s_all.699988825
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.3612920149
Short name T929
Test name
Test status
Simulation time 1756277063 ps
CPU time 8.08 seconds
Started Jul 26 05:35:07 PM PDT 24
Finished Jul 26 05:35:16 PM PDT 24
Peak memory 216576 kb
Host smart-dbf5ef68-3b3a-43b9-b7f5-71e59064c3ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612920149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.3612920149
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.3808485425
Short name T505
Test name
Test status
Simulation time 4413304631 ps
CPU time 4.78 seconds
Started Jul 26 05:35:07 PM PDT 24
Finished Jul 26 05:35:12 PM PDT 24
Peak memory 216484 kb
Host smart-a349c073-ff0d-4e1e-b8ca-01c723225e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808485425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.3808485425
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.2295770980
Short name T371
Test name
Test status
Simulation time 216758812 ps
CPU time 5.29 seconds
Started Jul 26 05:35:05 PM PDT 24
Finished Jul 26 05:35:10 PM PDT 24
Peak memory 216220 kb
Host smart-1b850e98-a72f-4718-87cc-b4fad966c351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295770980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.2295770980
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.2474085922
Short name T608
Test name
Test status
Simulation time 102748358 ps
CPU time 1.02 seconds
Started Jul 26 05:35:09 PM PDT 24
Finished Jul 26 05:35:10 PM PDT 24
Peak memory 207096 kb
Host smart-9f7293c4-8c45-4079-98d5-daf9aae897c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474085922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.2474085922
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.1386368949
Short name T984
Test name
Test status
Simulation time 1994920913 ps
CPU time 10.11 seconds
Started Jul 26 05:35:07 PM PDT 24
Finished Jul 26 05:35:17 PM PDT 24
Peak memory 232872 kb
Host smart-f5b943c7-79bd-4a5a-b435-85415d1865ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386368949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.1386368949
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.1291851484
Short name T618
Test name
Test status
Simulation time 29874471 ps
CPU time 0.79 seconds
Started Jul 26 05:33:00 PM PDT 24
Finished Jul 26 05:33:01 PM PDT 24
Peak memory 205472 kb
Host smart-31a14ee1-d1f6-43ff-858e-ded9284fc6b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291851484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.1
291851484
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.1920219009
Short name T525
Test name
Test status
Simulation time 105699712 ps
CPU time 2.42 seconds
Started Jul 26 05:32:47 PM PDT 24
Finished Jul 26 05:32:50 PM PDT 24
Peak memory 232476 kb
Host smart-a50e7368-bb34-4ddb-a258-78f970872ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920219009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.1920219009
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.3719939066
Short name T560
Test name
Test status
Simulation time 14910440 ps
CPU time 0.76 seconds
Started Jul 26 05:32:50 PM PDT 24
Finished Jul 26 05:32:51 PM PDT 24
Peak memory 206940 kb
Host smart-a3bc8fa7-ecd4-436e-ab45-3b85b7e9aace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719939066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.3719939066
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.2896729217
Short name T1006
Test name
Test status
Simulation time 2671402811 ps
CPU time 54.78 seconds
Started Jul 26 05:33:00 PM PDT 24
Finished Jul 26 05:33:54 PM PDT 24
Peak memory 249928 kb
Host smart-ff8dbcb3-f1ca-4107-8e24-31ae973c7549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896729217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.2896729217
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.3590223187
Short name T259
Test name
Test status
Simulation time 39919915213 ps
CPU time 170.88 seconds
Started Jul 26 05:32:48 PM PDT 24
Finished Jul 26 05:35:39 PM PDT 24
Peak memory 273464 kb
Host smart-5a71cf9f-2c28-4707-ab13-1f46f0e07bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590223187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.3590223187
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.96209938
Short name T947
Test name
Test status
Simulation time 142573781 ps
CPU time 3.42 seconds
Started Jul 26 05:32:47 PM PDT 24
Finished Jul 26 05:32:51 PM PDT 24
Peak memory 233324 kb
Host smart-c407a1e2-6233-43ce-aa75-928cba241d11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96209938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.96209938
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.2682810482
Short name T773
Test name
Test status
Simulation time 12150144799 ps
CPU time 101.53 seconds
Started Jul 26 05:32:50 PM PDT 24
Finished Jul 26 05:34:31 PM PDT 24
Peak memory 252316 kb
Host smart-b7846c70-75f4-4af7-a9c8-0cbbc54ba5b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682810482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds
.2682810482
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/4.spi_device_intercept.1906870310
Short name T68
Test name
Test status
Simulation time 1662922824 ps
CPU time 5.12 seconds
Started Jul 26 05:32:51 PM PDT 24
Finished Jul 26 05:32:56 PM PDT 24
Peak memory 224656 kb
Host smart-8375c531-1ef4-4fd2-97b2-65c7dc6c2918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906870310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.1906870310
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.1504362
Short name T965
Test name
Test status
Simulation time 11127216541 ps
CPU time 26.32 seconds
Started Jul 26 05:33:02 PM PDT 24
Finished Jul 26 05:33:29 PM PDT 24
Peak memory 232784 kb
Host smart-4dbd997b-ce2d-4fee-8a61-a2e9412086ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.1504362
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.2404062571
Short name T512
Test name
Test status
Simulation time 194903466 ps
CPU time 3.01 seconds
Started Jul 26 05:32:48 PM PDT 24
Finished Jul 26 05:32:51 PM PDT 24
Peak memory 224664 kb
Host smart-aeab4037-35fa-43c5-a92f-e41e065dac2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404062571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.2404062571
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.1106175008
Short name T212
Test name
Test status
Simulation time 6706670221 ps
CPU time 20.63 seconds
Started Jul 26 05:32:51 PM PDT 24
Finished Jul 26 05:33:11 PM PDT 24
Peak memory 224704 kb
Host smart-ce5101d1-d250-4334-a76d-6fbb65a5ee0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106175008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.1106175008
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.1699674585
Short name T330
Test name
Test status
Simulation time 95465213 ps
CPU time 3.97 seconds
Started Jul 26 05:32:51 PM PDT 24
Finished Jul 26 05:32:55 PM PDT 24
Peak memory 223428 kb
Host smart-41cbd37a-98ce-49ea-bc9e-321ed5b9313a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1699674585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.1699674585
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.3032265860
Short name T60
Test name
Test status
Simulation time 340195392 ps
CPU time 0.99 seconds
Started Jul 26 05:32:52 PM PDT 24
Finished Jul 26 05:32:53 PM PDT 24
Peak memory 235796 kb
Host smart-3b733d0f-411b-4777-9a60-fcf319ea2c37
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032265860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.3032265860
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.398751807
Short name T265
Test name
Test status
Simulation time 295757117250 ps
CPU time 778.6 seconds
Started Jul 26 05:32:51 PM PDT 24
Finished Jul 26 05:45:50 PM PDT 24
Peak memory 282160 kb
Host smart-033b066e-20cf-437e-88f2-351e310cacf0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398751807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stress
_all.398751807
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.83384452
Short name T356
Test name
Test status
Simulation time 3680367046 ps
CPU time 13.03 seconds
Started Jul 26 05:32:48 PM PDT 24
Finished Jul 26 05:33:01 PM PDT 24
Peak memory 216424 kb
Host smart-b5c65953-701b-4835-9e2d-b6847cd7cedd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83384452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.83384452
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.3849479014
Short name T24
Test name
Test status
Simulation time 4433782069 ps
CPU time 15.49 seconds
Started Jul 26 05:32:50 PM PDT 24
Finished Jul 26 05:33:05 PM PDT 24
Peak memory 216464 kb
Host smart-fbf15a77-fdb1-45eb-b7f8-8cafdd8f0733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849479014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.3849479014
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.3987703204
Short name T288
Test name
Test status
Simulation time 40889932 ps
CPU time 1.53 seconds
Started Jul 26 05:32:52 PM PDT 24
Finished Jul 26 05:32:53 PM PDT 24
Peak memory 216300 kb
Host smart-fd7dba81-d224-4d94-8a4e-45686ca748b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987703204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.3987703204
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.648910980
Short name T774
Test name
Test status
Simulation time 13491034 ps
CPU time 0.71 seconds
Started Jul 26 05:32:51 PM PDT 24
Finished Jul 26 05:32:52 PM PDT 24
Peak memory 205636 kb
Host smart-0e90353d-6cd1-4590-a503-4c0dce5f1f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648910980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.648910980
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.2592898562
Short name T521
Test name
Test status
Simulation time 6538503024 ps
CPU time 26.49 seconds
Started Jul 26 05:32:48 PM PDT 24
Finished Jul 26 05:33:14 PM PDT 24
Peak memory 232856 kb
Host smart-5200def8-78b9-4f63-8166-9f39ac90cabe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592898562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.2592898562
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.4163314678
Short name T651
Test name
Test status
Simulation time 11268649 ps
CPU time 0.73 seconds
Started Jul 26 05:35:19 PM PDT 24
Finished Jul 26 05:35:20 PM PDT 24
Peak memory 205524 kb
Host smart-abe5079a-84d0-415a-bff4-cd58b4cb10af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163314678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
4163314678
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.2417143471
Short name T161
Test name
Test status
Simulation time 255036825 ps
CPU time 2.31 seconds
Started Jul 26 05:35:09 PM PDT 24
Finished Jul 26 05:35:11 PM PDT 24
Peak memory 224608 kb
Host smart-322d3375-d5cb-4e03-a182-765a0632664d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417143471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.2417143471
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.1650980315
Short name T359
Test name
Test status
Simulation time 41052785 ps
CPU time 0.82 seconds
Started Jul 26 05:35:04 PM PDT 24
Finished Jul 26 05:35:05 PM PDT 24
Peak memory 207040 kb
Host smart-b37b0566-5dd6-43ae-b2c0-534d0e2fca0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650980315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.1650980315
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.3572082414
Short name T932
Test name
Test status
Simulation time 6791796532 ps
CPU time 69.19 seconds
Started Jul 26 05:35:09 PM PDT 24
Finished Jul 26 05:36:19 PM PDT 24
Peak memory 240244 kb
Host smart-fc98f7e1-b7c4-40c1-8cd4-7d96aeb81d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572082414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.3572082414
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.3673581999
Short name T743
Test name
Test status
Simulation time 31937614802 ps
CPU time 318.91 seconds
Started Jul 26 05:35:18 PM PDT 24
Finished Jul 26 05:40:37 PM PDT 24
Peak memory 258796 kb
Host smart-4b3b9d14-4d1f-48b6-a97c-f060ed0f8787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673581999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.3673581999
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.2169296007
Short name T280
Test name
Test status
Simulation time 2988296368 ps
CPU time 10.63 seconds
Started Jul 26 05:35:04 PM PDT 24
Finished Jul 26 05:35:15 PM PDT 24
Peak memory 232912 kb
Host smart-2a0bd112-ee76-488e-ab7d-368680fb870c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169296007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.2169296007
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.1458580109
Short name T531
Test name
Test status
Simulation time 30339010483 ps
CPU time 99.51 seconds
Started Jul 26 05:35:04 PM PDT 24
Finished Jul 26 05:36:44 PM PDT 24
Peak memory 239460 kb
Host smart-402ac367-6e6b-4c57-85b8-573b3c284e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458580109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmd
s.1458580109
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_intercept.1202898275
Short name T867
Test name
Test status
Simulation time 558520305 ps
CPU time 3.34 seconds
Started Jul 26 05:35:03 PM PDT 24
Finished Jul 26 05:35:07 PM PDT 24
Peak memory 224640 kb
Host smart-bf619b73-263c-42b2-bc36-97ac32817bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202898275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.1202898275
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.3112358711
Short name T190
Test name
Test status
Simulation time 3197753415 ps
CPU time 29.46 seconds
Started Jul 26 05:35:04 PM PDT 24
Finished Jul 26 05:35:34 PM PDT 24
Peak memory 235540 kb
Host smart-f45d6e79-4325-406f-86ba-50e00cd6f0f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112358711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.3112358711
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.1145959664
Short name T640
Test name
Test status
Simulation time 322459552 ps
CPU time 4.21 seconds
Started Jul 26 05:35:05 PM PDT 24
Finished Jul 26 05:35:09 PM PDT 24
Peak memory 224636 kb
Host smart-bf02e292-1650-4b7c-a03f-21ccbf0b9a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145959664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.1145959664
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.515973661
Short name T723
Test name
Test status
Simulation time 314670561 ps
CPU time 4.64 seconds
Started Jul 26 05:35:06 PM PDT 24
Finished Jul 26 05:35:10 PM PDT 24
Peak memory 224604 kb
Host smart-6dc1cd81-6040-41dc-8600-96bbf6eb1db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515973661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.515973661
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.174679076
Short name T919
Test name
Test status
Simulation time 1478606126 ps
CPU time 12.63 seconds
Started Jul 26 05:35:04 PM PDT 24
Finished Jul 26 05:35:17 PM PDT 24
Peak memory 219304 kb
Host smart-c476b15d-a5ee-48e3-9420-7a56fbe373dc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=174679076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dire
ct.174679076
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.2616872190
Short name T976
Test name
Test status
Simulation time 35457835269 ps
CPU time 178.43 seconds
Started Jul 26 05:35:20 PM PDT 24
Finished Jul 26 05:38:19 PM PDT 24
Peak memory 273936 kb
Host smart-7cb3f8bd-8f2f-462a-b460-5d6ab8f99875
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616872190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.2616872190
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.3600332345
Short name T495
Test name
Test status
Simulation time 45733662222 ps
CPU time 39.48 seconds
Started Jul 26 05:35:02 PM PDT 24
Finished Jul 26 05:35:42 PM PDT 24
Peak memory 216396 kb
Host smart-735e0526-3b55-4fc7-9953-e22c0847d220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600332345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.3600332345
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.533103704
Short name T412
Test name
Test status
Simulation time 24276104816 ps
CPU time 15.42 seconds
Started Jul 26 05:35:04 PM PDT 24
Finished Jul 26 05:35:19 PM PDT 24
Peak memory 216496 kb
Host smart-463b3c00-b3e7-466c-9096-00e68c3dc71b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533103704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.533103704
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.2946702743
Short name T882
Test name
Test status
Simulation time 191437216 ps
CPU time 1.4 seconds
Started Jul 26 05:35:05 PM PDT 24
Finished Jul 26 05:35:07 PM PDT 24
Peak memory 216364 kb
Host smart-aaed257f-ba00-4331-a5ab-3ee17792a1e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946702743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.2946702743
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.4265161274
Short name T674
Test name
Test status
Simulation time 98922577 ps
CPU time 0.73 seconds
Started Jul 26 05:35:05 PM PDT 24
Finished Jul 26 05:35:05 PM PDT 24
Peak memory 206024 kb
Host smart-0e3a9cfd-1fca-4363-a748-1029b7a268cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265161274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.4265161274
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.2690191045
Short name T1003
Test name
Test status
Simulation time 178971901 ps
CPU time 2 seconds
Started Jul 26 05:35:05 PM PDT 24
Finished Jul 26 05:35:07 PM PDT 24
Peak memory 224160 kb
Host smart-66665624-9ec0-433a-aebc-834418fa03f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690191045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.2690191045
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.1960586599
Short name T979
Test name
Test status
Simulation time 20687236 ps
CPU time 0.71 seconds
Started Jul 26 05:35:22 PM PDT 24
Finished Jul 26 05:35:23 PM PDT 24
Peak memory 205804 kb
Host smart-1ef97555-9bb1-4f36-b1c1-cdd37ec1e9f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960586599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
1960586599
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.1521026333
Short name T977
Test name
Test status
Simulation time 227308824 ps
CPU time 3.1 seconds
Started Jul 26 05:35:19 PM PDT 24
Finished Jul 26 05:35:23 PM PDT 24
Peak memory 232792 kb
Host smart-53aa2f2e-eff4-4261-8d6f-65aed5fc5b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521026333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.1521026333
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.3452508585
Short name T431
Test name
Test status
Simulation time 15888729 ps
CPU time 0.76 seconds
Started Jul 26 05:35:16 PM PDT 24
Finished Jul 26 05:35:17 PM PDT 24
Peak memory 205872 kb
Host smart-f1eb3725-cddd-41f8-981b-ca265434898a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452508585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.3452508585
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.3153954542
Short name T193
Test name
Test status
Simulation time 7252199848 ps
CPU time 94.04 seconds
Started Jul 26 05:35:16 PM PDT 24
Finished Jul 26 05:36:51 PM PDT 24
Peak memory 249348 kb
Host smart-5172e06c-f90e-448a-9054-be2779f8c6eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153954542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.3153954542
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.3145154591
Short name T684
Test name
Test status
Simulation time 28333791178 ps
CPU time 82.29 seconds
Started Jul 26 05:35:19 PM PDT 24
Finished Jul 26 05:36:41 PM PDT 24
Peak memory 257540 kb
Host smart-9e56e7b5-d520-4b6a-b672-f74259ed28d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145154591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.3145154591
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.3186453323
Short name T523
Test name
Test status
Simulation time 22097607994 ps
CPU time 194.43 seconds
Started Jul 26 05:35:16 PM PDT 24
Finished Jul 26 05:38:30 PM PDT 24
Peak memory 241192 kb
Host smart-6411885d-e837-434d-94b0-ecffe7709d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186453323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.3186453323
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.2703081215
Short name T86
Test name
Test status
Simulation time 6133076121 ps
CPU time 26.73 seconds
Started Jul 26 05:35:19 PM PDT 24
Finished Jul 26 05:35:47 PM PDT 24
Peak memory 253980 kb
Host smart-58e81224-e01b-4571-b552-954c1ef36d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703081215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmd
s.2703081215
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.2265394343
Short name T596
Test name
Test status
Simulation time 2007920163 ps
CPU time 19.91 seconds
Started Jul 26 05:35:17 PM PDT 24
Finished Jul 26 05:35:37 PM PDT 24
Peak memory 232740 kb
Host smart-3d2f6e87-37b4-4d8d-8569-853c1e8185f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265394343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.2265394343
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.1607464128
Short name T695
Test name
Test status
Simulation time 207558864 ps
CPU time 2.39 seconds
Started Jul 26 05:35:20 PM PDT 24
Finished Jul 26 05:35:23 PM PDT 24
Peak memory 232536 kb
Host smart-fb1619b3-441a-4ce9-b4be-385a73154dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607464128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.1607464128
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.1700389417
Short name T893
Test name
Test status
Simulation time 14651026347 ps
CPU time 15.93 seconds
Started Jul 26 05:35:23 PM PDT 24
Finished Jul 26 05:35:39 PM PDT 24
Peak memory 232876 kb
Host smart-34028247-4ae1-456f-b3e7-01652f5f15ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700389417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.1700389417
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.1784152740
Short name T146
Test name
Test status
Simulation time 3555199889 ps
CPU time 7.67 seconds
Started Jul 26 05:35:19 PM PDT 24
Finished Jul 26 05:35:28 PM PDT 24
Peak memory 224712 kb
Host smart-d2954411-fb7c-45f2-9c51-82cc775522c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784152740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.1784152740
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.460839874
Short name T654
Test name
Test status
Simulation time 355300928 ps
CPU time 6.2 seconds
Started Jul 26 05:35:17 PM PDT 24
Finished Jul 26 05:35:24 PM PDT 24
Peak memory 218876 kb
Host smart-a0246123-db61-4fa8-8303-7962bf84c4da
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=460839874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dire
ct.460839874
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.1407268933
Short name T501
Test name
Test status
Simulation time 8988461883 ps
CPU time 29.28 seconds
Started Jul 26 05:35:17 PM PDT 24
Finished Jul 26 05:35:46 PM PDT 24
Peak memory 218968 kb
Host smart-f341ac6f-dca8-446a-b117-1aa1afb0287a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407268933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.1407268933
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.1032685447
Short name T443
Test name
Test status
Simulation time 2583757361 ps
CPU time 11.76 seconds
Started Jul 26 05:35:24 PM PDT 24
Finished Jul 26 05:35:36 PM PDT 24
Peak memory 216468 kb
Host smart-defbf532-a987-49c8-89ee-9f04e6bdef96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032685447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.1032685447
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.289044933
Short name T583
Test name
Test status
Simulation time 429924837 ps
CPU time 4.4 seconds
Started Jul 26 05:35:19 PM PDT 24
Finished Jul 26 05:35:23 PM PDT 24
Peak memory 216376 kb
Host smart-f858a4d5-bf46-466c-a298-ed0dc89f9265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289044933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.289044933
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.2590079474
Short name T724
Test name
Test status
Simulation time 441133042 ps
CPU time 1.76 seconds
Started Jul 26 05:35:20 PM PDT 24
Finished Jul 26 05:35:22 PM PDT 24
Peak memory 216432 kb
Host smart-09ad0f31-e64a-4e05-bdab-7b58a1d364d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590079474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.2590079474
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.200533428
Short name T749
Test name
Test status
Simulation time 102521145 ps
CPU time 0.88 seconds
Started Jul 26 05:35:19 PM PDT 24
Finished Jul 26 05:35:20 PM PDT 24
Peak memory 206084 kb
Host smart-30f7e766-a45e-4617-980f-207165415ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200533428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.200533428
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.843732661
Short name T814
Test name
Test status
Simulation time 440733660 ps
CPU time 2.83 seconds
Started Jul 26 05:35:16 PM PDT 24
Finished Jul 26 05:35:19 PM PDT 24
Peak memory 232672 kb
Host smart-fcc61a9c-41c2-4608-8ec1-1c34e7f5c0f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843732661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.843732661
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.1628224629
Short name T493
Test name
Test status
Simulation time 17295875 ps
CPU time 0.72 seconds
Started Jul 26 05:35:17 PM PDT 24
Finished Jul 26 05:35:17 PM PDT 24
Peak memory 205412 kb
Host smart-f275fab5-4ac9-4fb0-a18c-f5e1c239c9da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628224629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
1628224629
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.3276668006
Short name T688
Test name
Test status
Simulation time 9135339040 ps
CPU time 5.59 seconds
Started Jul 26 05:35:27 PM PDT 24
Finished Jul 26 05:35:32 PM PDT 24
Peak memory 218884 kb
Host smart-c297b8a1-73a2-43f6-be42-3b6d6df243a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276668006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.3276668006
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.1000096579
Short name T920
Test name
Test status
Simulation time 39342222 ps
CPU time 0.76 seconds
Started Jul 26 05:35:15 PM PDT 24
Finished Jul 26 05:35:16 PM PDT 24
Peak memory 206720 kb
Host smart-60d64e26-f34d-4c18-9c9c-c1c3f617ffd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000096579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.1000096579
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.3731531859
Short name T729
Test name
Test status
Simulation time 20075847 ps
CPU time 0.75 seconds
Started Jul 26 05:35:15 PM PDT 24
Finished Jul 26 05:35:16 PM PDT 24
Peak memory 215768 kb
Host smart-42f3449f-5f59-4d8b-a5e7-7360755a63d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731531859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.3731531859
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.2734746930
Short name T125
Test name
Test status
Simulation time 15397240716 ps
CPU time 91.69 seconds
Started Jul 26 05:35:16 PM PDT 24
Finished Jul 26 05:36:48 PM PDT 24
Peak memory 264448 kb
Host smart-22323fad-5d11-4100-94cd-e827772c8001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734746930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.2734746930
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.1080090047
Short name T32
Test name
Test status
Simulation time 35902310216 ps
CPU time 98.99 seconds
Started Jul 26 05:35:23 PM PDT 24
Finished Jul 26 05:37:02 PM PDT 24
Peak memory 257028 kb
Host smart-c2319169-662e-4fdf-847e-2039861429ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080090047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.1080090047
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.17236948
Short name T935
Test name
Test status
Simulation time 81578726709 ps
CPU time 65.87 seconds
Started Jul 26 05:35:19 PM PDT 24
Finished Jul 26 05:36:26 PM PDT 24
Peak memory 233944 kb
Host smart-93d76072-9a40-4deb-aa1d-9c3f68d57e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17236948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.17236948
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.2298348364
Short name T663
Test name
Test status
Simulation time 8099340957 ps
CPU time 18.67 seconds
Started Jul 26 05:35:19 PM PDT 24
Finished Jul 26 05:35:38 PM PDT 24
Peak memory 236048 kb
Host smart-764ced26-46af-474b-920e-9ae84daf1b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298348364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmd
s.2298348364
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_intercept.1109886714
Short name T746
Test name
Test status
Simulation time 397935541 ps
CPU time 2.23 seconds
Started Jul 26 05:35:18 PM PDT 24
Finished Jul 26 05:35:21 PM PDT 24
Peak memory 223172 kb
Host smart-05837351-0474-460a-8b7f-7319eb56ff42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109886714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.1109886714
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.2674435073
Short name T224
Test name
Test status
Simulation time 14537909124 ps
CPU time 34.4 seconds
Started Jul 26 05:35:21 PM PDT 24
Finished Jul 26 05:35:56 PM PDT 24
Peak memory 239608 kb
Host smart-15c5ac43-e10a-40f8-9cd0-44c0a89931b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674435073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.2674435073
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.963729507
Short name T228
Test name
Test status
Simulation time 911901937 ps
CPU time 2.81 seconds
Started Jul 26 05:35:16 PM PDT 24
Finished Jul 26 05:35:19 PM PDT 24
Peak memory 224520 kb
Host smart-f8e06d14-989e-4ba1-a8dd-f7552d925a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963729507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swap
.963729507
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.2451897654
Short name T472
Test name
Test status
Simulation time 1647277282 ps
CPU time 5.46 seconds
Started Jul 26 05:35:19 PM PDT 24
Finished Jul 26 05:35:24 PM PDT 24
Peak memory 232808 kb
Host smart-cb916c56-a8de-496b-bb3d-1377b023a5e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451897654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.2451897654
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.1093382019
Short name T946
Test name
Test status
Simulation time 82021671 ps
CPU time 3.53 seconds
Started Jul 26 05:35:16 PM PDT 24
Finished Jul 26 05:35:20 PM PDT 24
Peak memory 223296 kb
Host smart-c109f4b9-e5eb-442a-8a66-69d7a94f9a99
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1093382019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.1093382019
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.3850750520
Short name T879
Test name
Test status
Simulation time 2388791692 ps
CPU time 7.16 seconds
Started Jul 26 05:35:19 PM PDT 24
Finished Jul 26 05:35:26 PM PDT 24
Peak memory 216436 kb
Host smart-75d052c4-c23e-430e-9ef9-7a87942c491c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850750520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.3850750520
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.1554729620
Short name T399
Test name
Test status
Simulation time 1134954311 ps
CPU time 4.74 seconds
Started Jul 26 05:35:18 PM PDT 24
Finished Jul 26 05:35:23 PM PDT 24
Peak memory 216424 kb
Host smart-4d959282-6b6d-4b8d-a422-9fbad8abca66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554729620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.1554729620
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.282882984
Short name T783
Test name
Test status
Simulation time 307608263 ps
CPU time 8.21 seconds
Started Jul 26 05:35:19 PM PDT 24
Finished Jul 26 05:35:27 PM PDT 24
Peak memory 216244 kb
Host smart-8001e845-075b-4502-ae95-f73fcd88c914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282882984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.282882984
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.150848134
Short name T728
Test name
Test status
Simulation time 52176896 ps
CPU time 0.72 seconds
Started Jul 26 05:35:15 PM PDT 24
Finished Jul 26 05:35:16 PM PDT 24
Peak memory 206024 kb
Host smart-789f10da-22c0-4bd4-996e-f424c60c7a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150848134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.150848134
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.3358174544
Short name T553
Test name
Test status
Simulation time 2286506366 ps
CPU time 6.94 seconds
Started Jul 26 05:35:18 PM PDT 24
Finished Jul 26 05:35:25 PM PDT 24
Peak memory 240916 kb
Host smart-8aa71693-3455-4231-958c-d85f434135ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358174544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.3358174544
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.1401158753
Short name T446
Test name
Test status
Simulation time 13479160 ps
CPU time 0.74 seconds
Started Jul 26 05:35:24 PM PDT 24
Finished Jul 26 05:35:25 PM PDT 24
Peak memory 205868 kb
Host smart-2bf68115-3085-471a-a8c4-f1e63dd35015
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401158753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
1401158753
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.1588161067
Short name T788
Test name
Test status
Simulation time 130974797 ps
CPU time 2.46 seconds
Started Jul 26 05:35:20 PM PDT 24
Finished Jul 26 05:35:23 PM PDT 24
Peak memory 232796 kb
Host smart-51895e87-1137-4282-9094-6f9e247dcc87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588161067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.1588161067
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.3250665759
Short name T477
Test name
Test status
Simulation time 34640699 ps
CPU time 0.84 seconds
Started Jul 26 05:35:18 PM PDT 24
Finished Jul 26 05:35:19 PM PDT 24
Peak memory 206932 kb
Host smart-b6127d65-9a22-4d78-86a7-cc19b89f833e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250665759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.3250665759
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.3967117364
Short name T201
Test name
Test status
Simulation time 44777589644 ps
CPU time 322.08 seconds
Started Jul 26 05:35:20 PM PDT 24
Finished Jul 26 05:40:42 PM PDT 24
Peak memory 266608 kb
Host smart-4547f8aa-226e-4300-b3f5-83e11d9c0594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967117364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.3967117364
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.1408662379
Short name T353
Test name
Test status
Simulation time 185586597104 ps
CPU time 224.17 seconds
Started Jul 26 05:35:20 PM PDT 24
Finished Jul 26 05:39:04 PM PDT 24
Peak memory 254364 kb
Host smart-3bce5e3a-caf1-49cc-85f8-0587fcd38640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408662379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.1408662379
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.4242843237
Short name T264
Test name
Test status
Simulation time 2175238202 ps
CPU time 55.57 seconds
Started Jul 26 05:35:20 PM PDT 24
Finished Jul 26 05:36:16 PM PDT 24
Peak memory 252688 kb
Host smart-e6cfd1b9-aeb1-4c8c-9d23-7bb477744069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242843237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.4242843237
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.3728209893
Short name T538
Test name
Test status
Simulation time 576567273 ps
CPU time 16 seconds
Started Jul 26 05:35:19 PM PDT 24
Finished Jul 26 05:35:35 PM PDT 24
Peak memory 234844 kb
Host smart-1d76de14-9715-44e1-9b2b-84d5f8091af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728209893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.3728209893
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.1576144789
Short name T944
Test name
Test status
Simulation time 211757067403 ps
CPU time 309.6 seconds
Started Jul 26 05:35:18 PM PDT 24
Finished Jul 26 05:40:28 PM PDT 24
Peak memory 255536 kb
Host smart-843e2e1f-58a6-47cc-9121-02332d2a7433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576144789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmd
s.1576144789
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_intercept.797093710
Short name T11
Test name
Test status
Simulation time 3562470521 ps
CPU time 11.74 seconds
Started Jul 26 05:35:17 PM PDT 24
Finished Jul 26 05:35:29 PM PDT 24
Peak memory 232896 kb
Host smart-ddce7b9c-974f-4a64-a7f2-2619f4f3cc76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797093710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.797093710
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.4276803302
Short name T181
Test name
Test status
Simulation time 6055833023 ps
CPU time 14.58 seconds
Started Jul 26 05:35:19 PM PDT 24
Finished Jul 26 05:35:34 PM PDT 24
Peak memory 248988 kb
Host smart-e8bf775c-1d18-4752-998b-4f8a152790da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276803302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.4276803302
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.2963755917
Short name T690
Test name
Test status
Simulation time 35515441 ps
CPU time 2.5 seconds
Started Jul 26 05:35:16 PM PDT 24
Finished Jul 26 05:35:19 PM PDT 24
Peak memory 232528 kb
Host smart-66d21c21-9a23-4025-9ed4-fe4a7335309a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963755917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.2963755917
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.599640228
Short name T362
Test name
Test status
Simulation time 2352287354 ps
CPU time 17.75 seconds
Started Jul 26 05:35:23 PM PDT 24
Finished Jul 26 05:35:41 PM PDT 24
Peak memory 240356 kb
Host smart-3535211e-d0b2-4ceb-ae17-bf59cada7d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599640228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.599640228
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.919622475
Short name T327
Test name
Test status
Simulation time 549028979 ps
CPU time 4.75 seconds
Started Jul 26 05:35:19 PM PDT 24
Finished Jul 26 05:35:24 PM PDT 24
Peak memory 220572 kb
Host smart-0f36497f-100f-4ee6-bbd3-6ac4f18eb1da
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=919622475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dire
ct.919622475
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.2012076297
Short name T17
Test name
Test status
Simulation time 164336260278 ps
CPU time 329.77 seconds
Started Jul 26 05:35:20 PM PDT 24
Finished Jul 26 05:40:50 PM PDT 24
Peak memory 256672 kb
Host smart-8961f181-ef87-4518-ac70-42edea2eae8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012076297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.2012076297
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.2456130047
Short name T381
Test name
Test status
Simulation time 99565108036 ps
CPU time 44.21 seconds
Started Jul 26 05:35:21 PM PDT 24
Finished Jul 26 05:36:06 PM PDT 24
Peak memory 220508 kb
Host smart-53e21cd2-d399-4c91-b75e-0ee31057a408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456130047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.2456130047
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.742509548
Short name T642
Test name
Test status
Simulation time 24384550 ps
CPU time 0.72 seconds
Started Jul 26 05:35:15 PM PDT 24
Finished Jul 26 05:35:16 PM PDT 24
Peak memory 205764 kb
Host smart-ada54a3a-9657-4c13-bdfa-111224af5833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742509548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.742509548
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.1872184567
Short name T827
Test name
Test status
Simulation time 136553597 ps
CPU time 1.4 seconds
Started Jul 26 05:35:18 PM PDT 24
Finished Jul 26 05:35:20 PM PDT 24
Peak memory 216388 kb
Host smart-8bd375db-16da-422d-8b3c-9ab4ae107bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872184567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.1872184567
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.1975636990
Short name T384
Test name
Test status
Simulation time 64991429 ps
CPU time 0.9 seconds
Started Jul 26 05:35:18 PM PDT 24
Finished Jul 26 05:35:19 PM PDT 24
Peak memory 206096 kb
Host smart-8d6744b3-ef3a-4479-a932-2aecdfe79c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975636990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.1975636990
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.1059260965
Short name T320
Test name
Test status
Simulation time 558777243 ps
CPU time 5.03 seconds
Started Jul 26 05:35:17 PM PDT 24
Finished Jul 26 05:35:22 PM PDT 24
Peak memory 224620 kb
Host smart-75dc9b0b-f121-4ab6-8102-193500cd9772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059260965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.1059260965
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.602888805
Short name T466
Test name
Test status
Simulation time 20556486 ps
CPU time 0.72 seconds
Started Jul 26 05:35:23 PM PDT 24
Finished Jul 26 05:35:24 PM PDT 24
Peak memory 204964 kb
Host smart-16c15ef3-0272-4edf-acaa-3316c386e92c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602888805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.602888805
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.596514743
Short name T78
Test name
Test status
Simulation time 3514761064 ps
CPU time 28.9 seconds
Started Jul 26 05:35:17 PM PDT 24
Finished Jul 26 05:35:46 PM PDT 24
Peak memory 232808 kb
Host smart-bd962db3-94f3-4741-88eb-d37ed7193641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596514743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.596514743
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.3283356578
Short name T585
Test name
Test status
Simulation time 20667347 ps
CPU time 0.8 seconds
Started Jul 26 05:35:19 PM PDT 24
Finished Jul 26 05:35:21 PM PDT 24
Peak memory 206708 kb
Host smart-787eea06-c890-476a-b875-8e030f11987d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283356578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.3283356578
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.114061408
Short name T727
Test name
Test status
Simulation time 17367457 ps
CPU time 0.77 seconds
Started Jul 26 05:35:20 PM PDT 24
Finished Jul 26 05:35:21 PM PDT 24
Peak memory 215856 kb
Host smart-527354fe-9a81-46a4-be34-cd1ff035aafc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114061408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.114061408
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.466484990
Short name T183
Test name
Test status
Simulation time 43082019579 ps
CPU time 207.01 seconds
Started Jul 26 05:35:21 PM PDT 24
Finished Jul 26 05:38:48 PM PDT 24
Peak memory 252244 kb
Host smart-8f9f26b0-d217-4e98-8f2d-57837919dad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466484990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.466484990
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.735641097
Short name T263
Test name
Test status
Simulation time 93749738082 ps
CPU time 185.17 seconds
Started Jul 26 05:35:19 PM PDT 24
Finished Jul 26 05:38:25 PM PDT 24
Peak memory 265104 kb
Host smart-e4952176-9473-49e3-8d2f-b0f3a68ac857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735641097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idle
.735641097
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.1492254495
Short name T47
Test name
Test status
Simulation time 717378236 ps
CPU time 4.11 seconds
Started Jul 26 05:35:18 PM PDT 24
Finished Jul 26 05:35:22 PM PDT 24
Peak memory 241060 kb
Host smart-f99314c8-e134-48ca-9d81-6d9a68bb0202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492254495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.1492254495
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.378194483
Short name T895
Test name
Test status
Simulation time 15600505 ps
CPU time 0.83 seconds
Started Jul 26 05:35:20 PM PDT 24
Finished Jul 26 05:35:21 PM PDT 24
Peak memory 215780 kb
Host smart-16a326d5-c655-4e0b-bc91-533b7af64b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378194483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmds
.378194483
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_intercept.351468172
Short name T823
Test name
Test status
Simulation time 574566059 ps
CPU time 7.71 seconds
Started Jul 26 05:35:23 PM PDT 24
Finished Jul 26 05:35:31 PM PDT 24
Peak memory 232792 kb
Host smart-bc9e10b6-1e1f-4304-8ba0-3b24164d9310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351468172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.351468172
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.3685797578
Short name T748
Test name
Test status
Simulation time 1067054396 ps
CPU time 7.59 seconds
Started Jul 26 05:35:20 PM PDT 24
Finished Jul 26 05:35:28 PM PDT 24
Peak memory 224676 kb
Host smart-25664845-a676-4aa0-b91d-40bb9d6c8033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685797578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.3685797578
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.1308441745
Short name T424
Test name
Test status
Simulation time 347064304 ps
CPU time 4.71 seconds
Started Jul 26 05:35:17 PM PDT 24
Finished Jul 26 05:35:22 PM PDT 24
Peak memory 224516 kb
Host smart-70f51c33-3cc8-41b3-b1ce-b7a923bbcd12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308441745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.1308441745
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.2024941918
Short name T925
Test name
Test status
Simulation time 38710616363 ps
CPU time 12.24 seconds
Started Jul 26 05:35:18 PM PDT 24
Finished Jul 26 05:35:30 PM PDT 24
Peak memory 232828 kb
Host smart-243578b2-30f4-4acd-97c6-57b34fe6898f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024941918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.2024941918
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.3958629858
Short name T33
Test name
Test status
Simulation time 2296244861 ps
CPU time 4.79 seconds
Started Jul 26 05:35:19 PM PDT 24
Finished Jul 26 05:35:24 PM PDT 24
Peak memory 222788 kb
Host smart-03000aa4-d3eb-4868-b031-80de5dc314a6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3958629858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.3958629858
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.2329189987
Short name T794
Test name
Test status
Simulation time 49202111898 ps
CPU time 201.42 seconds
Started Jul 26 05:35:23 PM PDT 24
Finished Jul 26 05:38:45 PM PDT 24
Peak memory 252972 kb
Host smart-cb89d020-056d-4f17-82ca-4e128af82338
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329189987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.2329189987
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.1837331911
Short name T360
Test name
Test status
Simulation time 16649738 ps
CPU time 0.75 seconds
Started Jul 26 05:35:18 PM PDT 24
Finished Jul 26 05:35:19 PM PDT 24
Peak memory 205740 kb
Host smart-5cabef5f-d767-4720-afd3-002e3936abb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837331911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.1837331911
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.4101857534
Short name T62
Test name
Test status
Simulation time 14286541842 ps
CPU time 4.45 seconds
Started Jul 26 05:35:18 PM PDT 24
Finished Jul 26 05:35:23 PM PDT 24
Peak memory 217592 kb
Host smart-8e8cb998-807b-4ae2-b75e-70b0afb508dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101857534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.4101857534
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.447159348
Short name T554
Test name
Test status
Simulation time 366657088 ps
CPU time 2.62 seconds
Started Jul 26 05:35:23 PM PDT 24
Finished Jul 26 05:35:26 PM PDT 24
Peak memory 216292 kb
Host smart-073856c8-67b7-4bec-a605-5f145d873b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447159348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.447159348
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.374140234
Short name T782
Test name
Test status
Simulation time 47445326 ps
CPU time 0.89 seconds
Started Jul 26 05:35:22 PM PDT 24
Finished Jul 26 05:35:23 PM PDT 24
Peak memory 207012 kb
Host smart-5531c158-5621-41f8-a990-04b08ffdc27b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374140234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.374140234
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.1549670707
Short name T419
Test name
Test status
Simulation time 3518984550 ps
CPU time 18.57 seconds
Started Jul 26 05:35:20 PM PDT 24
Finished Jul 26 05:35:39 PM PDT 24
Peak memory 235436 kb
Host smart-d4ea396f-302c-44a8-87e7-7eef33f1d30e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549670707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.1549670707
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.3252516199
Short name T792
Test name
Test status
Simulation time 53154982 ps
CPU time 0.74 seconds
Started Jul 26 05:35:30 PM PDT 24
Finished Jul 26 05:35:31 PM PDT 24
Peak memory 205004 kb
Host smart-555fb6e3-1e5c-4220-83ba-f3e8f2bd92b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252516199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
3252516199
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.3770044088
Short name T659
Test name
Test status
Simulation time 94351568 ps
CPU time 3 seconds
Started Jul 26 05:35:33 PM PDT 24
Finished Jul 26 05:35:36 PM PDT 24
Peak memory 232832 kb
Host smart-7e713e13-0cbb-4a6c-ba78-6b8efaf69473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770044088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.3770044088
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.3005999686
Short name T337
Test name
Test status
Simulation time 47273575 ps
CPU time 0.75 seconds
Started Jul 26 05:35:31 PM PDT 24
Finished Jul 26 05:35:32 PM PDT 24
Peak memory 207032 kb
Host smart-9c7b66a6-5c9a-40a5-8082-647f252ab176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005999686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.3005999686
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.3494654601
Short name T956
Test name
Test status
Simulation time 42247082592 ps
CPU time 272.77 seconds
Started Jul 26 05:35:34 PM PDT 24
Finished Jul 26 05:40:07 PM PDT 24
Peak memory 249340 kb
Host smart-fb99341f-efdf-445d-bda8-a2529de9a125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494654601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.3494654601
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.842578479
Short name T8
Test name
Test status
Simulation time 48850175736 ps
CPU time 194.79 seconds
Started Jul 26 05:35:34 PM PDT 24
Finished Jul 26 05:38:49 PM PDT 24
Peak memory 273508 kb
Host smart-2316e849-3955-412e-9071-3c53a57e8caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842578479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.842578479
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.3264481743
Short name T524
Test name
Test status
Simulation time 16197769994 ps
CPU time 87.96 seconds
Started Jul 26 05:35:31 PM PDT 24
Finished Jul 26 05:36:59 PM PDT 24
Peak memory 238812 kb
Host smart-b91f66ff-b3c0-4116-90b3-856940a83a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264481743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.3264481743
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.2504212033
Short name T272
Test name
Test status
Simulation time 157047193 ps
CPU time 4.85 seconds
Started Jul 26 05:35:33 PM PDT 24
Finished Jul 26 05:35:38 PM PDT 24
Peak memory 224568 kb
Host smart-902d2dde-66ea-4f71-aae8-71b675ef5393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504212033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.2504212033
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.786728889
Short name T489
Test name
Test status
Simulation time 17411742273 ps
CPU time 143.66 seconds
Started Jul 26 05:35:31 PM PDT 24
Finished Jul 26 05:37:55 PM PDT 24
Peak memory 249288 kb
Host smart-7f9e13f0-b1e1-4c9e-8b09-5d7373123999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786728889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmds
.786728889
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_intercept.3500153337
Short name T209
Test name
Test status
Simulation time 3945947108 ps
CPU time 44.45 seconds
Started Jul 26 05:35:30 PM PDT 24
Finished Jul 26 05:36:14 PM PDT 24
Peak memory 224664 kb
Host smart-5afcaad0-6eb3-475b-b79d-5cfc229bfad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500153337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.3500153337
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.3669087614
Short name T234
Test name
Test status
Simulation time 933364726 ps
CPU time 18.64 seconds
Started Jul 26 05:35:30 PM PDT 24
Finished Jul 26 05:35:49 PM PDT 24
Peak memory 232800 kb
Host smart-20466572-33be-44bf-8e86-5088f23c6fc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669087614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.3669087614
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.1927106466
Short name T517
Test name
Test status
Simulation time 2546224976 ps
CPU time 4.49 seconds
Started Jul 26 05:35:32 PM PDT 24
Finished Jul 26 05:35:36 PM PDT 24
Peak memory 224704 kb
Host smart-5502161e-ff4b-4f57-86b6-9c3c2d6b37af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927106466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.1927106466
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.1061041167
Short name T711
Test name
Test status
Simulation time 13529948871 ps
CPU time 6.21 seconds
Started Jul 26 05:35:31 PM PDT 24
Finished Jul 26 05:35:37 PM PDT 24
Peak memory 224720 kb
Host smart-7d303495-854a-4778-b6f3-f84c158bd356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061041167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.1061041167
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.1811776010
Short name T387
Test name
Test status
Simulation time 1042225499 ps
CPU time 4.57 seconds
Started Jul 26 05:35:32 PM PDT 24
Finished Jul 26 05:35:37 PM PDT 24
Peak memory 223420 kb
Host smart-812291a9-6758-47fc-b4db-f1199d1b3568
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1811776010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.1811776010
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.760301122
Short name T383
Test name
Test status
Simulation time 48409206 ps
CPU time 0.94 seconds
Started Jul 26 05:35:32 PM PDT 24
Finished Jul 26 05:35:33 PM PDT 24
Peak memory 207460 kb
Host smart-318e2d98-1be9-45a0-8a08-2c62feaaa9f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760301122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stres
s_all.760301122
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.3800501031
Short name T36
Test name
Test status
Simulation time 2809039053 ps
CPU time 4.21 seconds
Started Jul 26 05:35:34 PM PDT 24
Finished Jul 26 05:35:39 PM PDT 24
Peak memory 216660 kb
Host smart-56be788b-5960-4189-b1c9-ffdd493449d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800501031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.3800501031
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.3261109881
Short name T781
Test name
Test status
Simulation time 1542697753 ps
CPU time 2.9 seconds
Started Jul 26 05:35:30 PM PDT 24
Finished Jul 26 05:35:33 PM PDT 24
Peak memory 216356 kb
Host smart-1c03d301-11d9-4e23-925b-092036181d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261109881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.3261109881
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.2552304373
Short name T1001
Test name
Test status
Simulation time 53483578 ps
CPU time 1.14 seconds
Started Jul 26 05:35:28 PM PDT 24
Finished Jul 26 05:35:29 PM PDT 24
Peak memory 207988 kb
Host smart-33a26ffe-1adf-499a-b6a4-577bd6521a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552304373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.2552304373
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.3793587556
Short name T778
Test name
Test status
Simulation time 50009487 ps
CPU time 0.84 seconds
Started Jul 26 05:35:34 PM PDT 24
Finished Jul 26 05:35:35 PM PDT 24
Peak memory 205972 kb
Host smart-8f41b043-a4d5-42b5-9d6d-5cd69da2baa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793587556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.3793587556
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.2792309916
Short name T214
Test name
Test status
Simulation time 87045619 ps
CPU time 2.79 seconds
Started Jul 26 05:35:32 PM PDT 24
Finished Jul 26 05:35:35 PM PDT 24
Peak memory 232704 kb
Host smart-588efefd-ff98-425f-83f8-8b1180698aab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792309916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.2792309916
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.1059579872
Short name T331
Test name
Test status
Simulation time 12654463 ps
CPU time 0.71 seconds
Started Jul 26 05:35:30 PM PDT 24
Finished Jul 26 05:35:31 PM PDT 24
Peak memory 204872 kb
Host smart-938c593e-667e-40a7-af59-28a1054fa524
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059579872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
1059579872
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.4202371064
Short name T606
Test name
Test status
Simulation time 2024060572 ps
CPU time 13.05 seconds
Started Jul 26 05:35:35 PM PDT 24
Finished Jul 26 05:35:48 PM PDT 24
Peak memory 232824 kb
Host smart-844385e0-e99c-4335-af97-8913d979d78f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202371064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.4202371064
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.837905437
Short name T590
Test name
Test status
Simulation time 28698039 ps
CPU time 0.75 seconds
Started Jul 26 05:35:31 PM PDT 24
Finished Jul 26 05:35:32 PM PDT 24
Peak memory 206720 kb
Host smart-45ce52be-d5c4-48c8-9e86-8cafc8aad941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837905437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.837905437
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.3158327415
Short name T168
Test name
Test status
Simulation time 5150554720 ps
CPU time 34.8 seconds
Started Jul 26 05:35:33 PM PDT 24
Finished Jul 26 05:36:08 PM PDT 24
Peak memory 224756 kb
Host smart-b78433e4-abee-433e-8a74-2d7dcd083f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158327415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.3158327415
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.124692882
Short name T784
Test name
Test status
Simulation time 1595385883 ps
CPU time 22.38 seconds
Started Jul 26 05:35:34 PM PDT 24
Finished Jul 26 05:35:56 PM PDT 24
Peak memory 224720 kb
Host smart-6d6067b8-5c75-4316-b72c-48f2eea2245a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124692882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.124692882
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.2257678070
Short name T876
Test name
Test status
Simulation time 9194698106 ps
CPU time 112.27 seconds
Started Jul 26 05:35:31 PM PDT 24
Finished Jul 26 05:37:23 PM PDT 24
Peak memory 257600 kb
Host smart-9ec39a10-d73c-444c-bfec-8afc8c752d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257678070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.2257678070
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.315810402
Short name T274
Test name
Test status
Simulation time 6728236274 ps
CPU time 48.42 seconds
Started Jul 26 05:35:31 PM PDT 24
Finished Jul 26 05:36:20 PM PDT 24
Peak memory 224736 kb
Host smart-d3ada40e-8af0-49a7-a946-dfe45872b65a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315810402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.315810402
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.599338123
Short name T204
Test name
Test status
Simulation time 29461041765 ps
CPU time 199.78 seconds
Started Jul 26 05:35:33 PM PDT 24
Finished Jul 26 05:38:53 PM PDT 24
Peak memory 250420 kb
Host smart-8c8cf30f-7d45-44f4-85fe-8d7cb1099f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599338123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmds
.599338123
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.1763325832
Short name T189
Test name
Test status
Simulation time 854762466 ps
CPU time 4.91 seconds
Started Jul 26 05:35:31 PM PDT 24
Finished Jul 26 05:35:36 PM PDT 24
Peak memory 232876 kb
Host smart-8f3d4264-154f-403e-a89f-5f9147c7c45a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763325832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.1763325832
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.2128373902
Short name T478
Test name
Test status
Simulation time 126697972 ps
CPU time 2.5 seconds
Started Jul 26 05:35:33 PM PDT 24
Finished Jul 26 05:35:35 PM PDT 24
Peak memory 224672 kb
Host smart-b0f7f16b-562b-4b12-a258-9dc97651749e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128373902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.2128373902
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.2977893709
Short name T720
Test name
Test status
Simulation time 4084922341 ps
CPU time 12.18 seconds
Started Jul 26 05:35:36 PM PDT 24
Finished Jul 26 05:35:49 PM PDT 24
Peak memory 224708 kb
Host smart-c5800cf2-311c-43c1-8535-c97bd1758aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977893709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.2977893709
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.2631587411
Short name T758
Test name
Test status
Simulation time 1376750469 ps
CPU time 10.39 seconds
Started Jul 26 05:35:30 PM PDT 24
Finished Jul 26 05:35:40 PM PDT 24
Peak memory 232828 kb
Host smart-1f152ecc-0a22-4c07-b09d-2b2a89cfd8c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631587411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.2631587411
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.128941997
Short name T730
Test name
Test status
Simulation time 9917973866 ps
CPU time 6.33 seconds
Started Jul 26 05:35:31 PM PDT 24
Finished Jul 26 05:35:37 PM PDT 24
Peak memory 218692 kb
Host smart-a73c6947-24b4-4229-a34a-94071f391119
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=128941997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dire
ct.128941997
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.3415786033
Short name T515
Test name
Test status
Simulation time 5929324116 ps
CPU time 33.21 seconds
Started Jul 26 05:35:31 PM PDT 24
Finished Jul 26 05:36:04 PM PDT 24
Peak memory 216360 kb
Host smart-302f3d0e-373b-402d-a628-2dd487d14817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415786033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.3415786033
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.1275654919
Short name T363
Test name
Test status
Simulation time 41499165 ps
CPU time 0.7 seconds
Started Jul 26 05:35:32 PM PDT 24
Finished Jul 26 05:35:33 PM PDT 24
Peak memory 205784 kb
Host smart-bb3b8c58-7b41-4611-9a9a-cfd95539fecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275654919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.1275654919
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.456830171
Short name T67
Test name
Test status
Simulation time 104838504 ps
CPU time 4.43 seconds
Started Jul 26 05:35:32 PM PDT 24
Finished Jul 26 05:35:37 PM PDT 24
Peak memory 216332 kb
Host smart-d06ed99c-2a77-4b0a-9310-c26211fc9be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456830171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.456830171
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.2641049747
Short name T988
Test name
Test status
Simulation time 103893296 ps
CPU time 0.71 seconds
Started Jul 26 05:35:31 PM PDT 24
Finished Jul 26 05:35:32 PM PDT 24
Peak memory 206080 kb
Host smart-dda0ac75-27f3-453f-92d7-9f4ddb5659af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641049747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.2641049747
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.1570160612
Short name T242
Test name
Test status
Simulation time 604063204 ps
CPU time 4.47 seconds
Started Jul 26 05:35:34 PM PDT 24
Finished Jul 26 05:35:39 PM PDT 24
Peak memory 224700 kb
Host smart-3a4fe2b6-0ce2-4246-9172-09c1684a9f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570160612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.1570160612
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.3268054675
Short name T856
Test name
Test status
Simulation time 11460166 ps
CPU time 0.8 seconds
Started Jul 26 05:35:57 PM PDT 24
Finished Jul 26 05:35:58 PM PDT 24
Peak memory 204948 kb
Host smart-5bc85d30-21f7-4303-89e2-49c12a41d43c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268054675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
3268054675
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.1186583993
Short name T717
Test name
Test status
Simulation time 124092621 ps
CPU time 2.32 seconds
Started Jul 26 05:35:35 PM PDT 24
Finished Jul 26 05:35:37 PM PDT 24
Peak memory 232388 kb
Host smart-ebf6b7cd-7e21-4aa3-8594-19bfc9569c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186583993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.1186583993
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.660039014
Short name T463
Test name
Test status
Simulation time 52419642 ps
CPU time 0.8 seconds
Started Jul 26 05:35:31 PM PDT 24
Finished Jul 26 05:35:32 PM PDT 24
Peak memory 206684 kb
Host smart-e1265eac-4b44-4297-aab9-0af3ebe8abaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660039014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.660039014
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.2226204816
Short name T776
Test name
Test status
Simulation time 12516408772 ps
CPU time 89.14 seconds
Started Jul 26 05:35:54 PM PDT 24
Finished Jul 26 05:37:23 PM PDT 24
Peak memory 249288 kb
Host smart-5b010add-4142-4633-b21d-c1c15bf027d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226204816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.2226204816
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.3036143932
Short name T195
Test name
Test status
Simulation time 26883618683 ps
CPU time 205.91 seconds
Started Jul 26 05:35:55 PM PDT 24
Finished Jul 26 05:39:21 PM PDT 24
Peak memory 257400 kb
Host smart-97d53576-e833-4cc6-984c-1b46836e23d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036143932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.3036143932
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.24663113
Short name T248
Test name
Test status
Simulation time 475016217966 ps
CPU time 260.44 seconds
Started Jul 26 05:35:59 PM PDT 24
Finished Jul 26 05:40:20 PM PDT 24
Peak memory 264988 kb
Host smart-9d58fb7d-6e06-4d7d-ae84-2e9aef113273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24663113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idle.24663113
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.2083579713
Short name T275
Test name
Test status
Simulation time 1943445481 ps
CPU time 19.84 seconds
Started Jul 26 05:35:33 PM PDT 24
Finished Jul 26 05:35:53 PM PDT 24
Peak memory 240764 kb
Host smart-d950e4c1-a187-4f37-b518-45999108c498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083579713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.2083579713
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.2839496737
Short name T167
Test name
Test status
Simulation time 70930072117 ps
CPU time 478.21 seconds
Started Jul 26 05:35:35 PM PDT 24
Finished Jul 26 05:43:33 PM PDT 24
Peak memory 249752 kb
Host smart-d850a4ce-f94f-402d-8e93-5f93ee112cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839496737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmd
s.2839496737
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_intercept.2071579422
Short name T843
Test name
Test status
Simulation time 1449790618 ps
CPU time 12.87 seconds
Started Jul 26 05:35:34 PM PDT 24
Finished Jul 26 05:35:47 PM PDT 24
Peak memory 224596 kb
Host smart-4f11d9f2-315d-43d5-b7d1-ef13cd72afc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071579422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.2071579422
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.431288999
Short name T844
Test name
Test status
Simulation time 724085930 ps
CPU time 9.63 seconds
Started Jul 26 05:35:33 PM PDT 24
Finished Jul 26 05:35:43 PM PDT 24
Peak memory 233320 kb
Host smart-e8c8a225-ad7a-499d-8aca-5488af7f2657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431288999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.431288999
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.3204004469
Short name T907
Test name
Test status
Simulation time 789149187 ps
CPU time 7.12 seconds
Started Jul 26 05:35:34 PM PDT 24
Finished Jul 26 05:35:41 PM PDT 24
Peak memory 239264 kb
Host smart-6f1d0eb0-fff2-47a7-b815-b7547bcf99b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204004469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.3204004469
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.4194028233
Short name T796
Test name
Test status
Simulation time 427151832 ps
CPU time 3.53 seconds
Started Jul 26 05:35:32 PM PDT 24
Finished Jul 26 05:35:36 PM PDT 24
Peak memory 232780 kb
Host smart-f17bd796-49df-477f-aa8d-9c3337c558fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194028233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.4194028233
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.1755379900
Short name T479
Test name
Test status
Simulation time 226028224 ps
CPU time 4.55 seconds
Started Jul 26 05:35:53 PM PDT 24
Finished Jul 26 05:35:57 PM PDT 24
Peak memory 222576 kb
Host smart-1ba20237-4b5f-4b3a-88a3-a03b63f0fcb5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1755379900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.1755379900
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.2837463379
Short name T142
Test name
Test status
Simulation time 48045049 ps
CPU time 1.02 seconds
Started Jul 26 05:35:54 PM PDT 24
Finished Jul 26 05:35:55 PM PDT 24
Peak memory 207804 kb
Host smart-97b9f74d-b3ba-4909-a506-3fe92c2ab19b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837463379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.2837463379
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.385314451
Short name T787
Test name
Test status
Simulation time 715109323 ps
CPU time 3.47 seconds
Started Jul 26 05:35:34 PM PDT 24
Finished Jul 26 05:35:38 PM PDT 24
Peak memory 216652 kb
Host smart-2a6d7172-794c-4c62-ab35-fb1e78e92c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385314451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.385314451
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.2651345586
Short name T735
Test name
Test status
Simulation time 8714705594 ps
CPU time 21.14 seconds
Started Jul 26 05:35:33 PM PDT 24
Finished Jul 26 05:35:54 PM PDT 24
Peak memory 216412 kb
Host smart-fc7bf122-67e0-44d6-92af-656533a5d403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651345586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.2651345586
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.2832426128
Short name T289
Test name
Test status
Simulation time 74133856 ps
CPU time 1.25 seconds
Started Jul 26 05:35:32 PM PDT 24
Finished Jul 26 05:35:33 PM PDT 24
Peak memory 216440 kb
Host smart-24df8c95-0f87-4b0a-9872-da92eb0c1141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832426128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.2832426128
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.956270165
Short name T719
Test name
Test status
Simulation time 69837840 ps
CPU time 0.87 seconds
Started Jul 26 05:35:34 PM PDT 24
Finished Jul 26 05:35:35 PM PDT 24
Peak memory 207016 kb
Host smart-15bcea00-d1f0-4f8e-b0c4-f5432a02dfb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956270165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.956270165
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.654814426
Short name T628
Test name
Test status
Simulation time 508753897 ps
CPU time 5.71 seconds
Started Jul 26 05:35:31 PM PDT 24
Finished Jul 26 05:35:37 PM PDT 24
Peak memory 239088 kb
Host smart-15eeb7f9-cc40-46be-8eb3-5544c4f6efe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654814426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.654814426
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.1290724706
Short name T51
Test name
Test status
Simulation time 13871614 ps
CPU time 0.73 seconds
Started Jul 26 05:35:59 PM PDT 24
Finished Jul 26 05:36:00 PM PDT 24
Peak memory 204972 kb
Host smart-de12828f-0a6d-4ecf-bc7a-30dbbeb2e0de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290724706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
1290724706
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.1228827714
Short name T533
Test name
Test status
Simulation time 1405767334 ps
CPU time 9.47 seconds
Started Jul 26 05:35:56 PM PDT 24
Finished Jul 26 05:36:05 PM PDT 24
Peak memory 232828 kb
Host smart-38b5d4b6-57b2-4360-a6ba-8170d14a946b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228827714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.1228827714
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.2313202486
Short name T840
Test name
Test status
Simulation time 20733000 ps
CPU time 0.81 seconds
Started Jul 26 05:35:54 PM PDT 24
Finished Jul 26 05:35:55 PM PDT 24
Peak memory 206712 kb
Host smart-812bb556-8371-4b7f-a028-b18c20d4316f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313202486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.2313202486
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.3707498090
Short name T351
Test name
Test status
Simulation time 8999480635 ps
CPU time 96.13 seconds
Started Jul 26 05:35:56 PM PDT 24
Finished Jul 26 05:37:32 PM PDT 24
Peak memory 256324 kb
Host smart-18fe79a9-5f5b-4ae8-affe-06f4257a3fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707498090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.3707498090
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.988353704
Short name T71
Test name
Test status
Simulation time 36414547128 ps
CPU time 180.6 seconds
Started Jul 26 05:36:02 PM PDT 24
Finished Jul 26 05:39:02 PM PDT 24
Peak memory 253820 kb
Host smart-de4574aa-461f-4a0c-b793-7e7f4548a84d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988353704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.988353704
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.823989038
Short name T281
Test name
Test status
Simulation time 17957601379 ps
CPU time 125.01 seconds
Started Jul 26 05:35:59 PM PDT 24
Finished Jul 26 05:38:04 PM PDT 24
Peak memory 241176 kb
Host smart-faa860bc-1d6e-4002-a887-6ba66d49824e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823989038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idle
.823989038
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.944118581
Short name T570
Test name
Test status
Simulation time 438118512 ps
CPU time 5.14 seconds
Started Jul 26 05:35:57 PM PDT 24
Finished Jul 26 05:36:03 PM PDT 24
Peak memory 224912 kb
Host smart-dfebea1b-7067-4973-80ff-2cd954865544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944118581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.944118581
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.32077455
Short name T883
Test name
Test status
Simulation time 14218932602 ps
CPU time 108.67 seconds
Started Jul 26 05:35:55 PM PDT 24
Finished Jul 26 05:37:44 PM PDT 24
Peak memory 249336 kb
Host smart-46c8b42c-9905-4287-918a-26fc45fc71f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32077455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmds.32077455
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_intercept.1398754451
Short name T822
Test name
Test status
Simulation time 106686622 ps
CPU time 2.12 seconds
Started Jul 26 05:35:55 PM PDT 24
Finished Jul 26 05:35:57 PM PDT 24
Peak memory 223172 kb
Host smart-01ca5081-ed84-4839-acea-25b145898ecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398754451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.1398754451
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.1863109305
Short name T241
Test name
Test status
Simulation time 534738719 ps
CPU time 2.99 seconds
Started Jul 26 05:36:06 PM PDT 24
Finished Jul 26 05:36:09 PM PDT 24
Peak memory 224596 kb
Host smart-750fba18-e07e-4298-bc7b-909bd6d33ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863109305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.1863109305
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.3718819590
Short name T975
Test name
Test status
Simulation time 19288476532 ps
CPU time 16.22 seconds
Started Jul 26 05:35:54 PM PDT 24
Finished Jul 26 05:36:11 PM PDT 24
Peak memory 240496 kb
Host smart-8c814aa7-3f68-432b-b5bf-510f8469972c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718819590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.3718819590
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.2915922872
Short name T601
Test name
Test status
Simulation time 868730772 ps
CPU time 6.7 seconds
Started Jul 26 05:35:53 PM PDT 24
Finished Jul 26 05:36:00 PM PDT 24
Peak memory 224620 kb
Host smart-d75faead-e717-4f12-bd49-3ffaa6e13cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915922872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.2915922872
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.2781998724
Short name T461
Test name
Test status
Simulation time 920327635 ps
CPU time 10.65 seconds
Started Jul 26 05:36:01 PM PDT 24
Finished Jul 26 05:36:12 PM PDT 24
Peak memory 220632 kb
Host smart-55b90a4c-11ba-409b-be3d-4fde73bd62b2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2781998724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.2781998724
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.3539144662
Short name T420
Test name
Test status
Simulation time 46977260 ps
CPU time 0.98 seconds
Started Jul 26 05:35:59 PM PDT 24
Finished Jul 26 05:36:00 PM PDT 24
Peak memory 207704 kb
Host smart-98d929f5-0516-4734-a12d-0f521b790183
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539144662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.3539144662
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.2115282677
Short name T344
Test name
Test status
Simulation time 3756802015 ps
CPU time 19.97 seconds
Started Jul 26 05:35:53 PM PDT 24
Finished Jul 26 05:36:13 PM PDT 24
Peak memory 216424 kb
Host smart-82e31a54-a4d1-43b5-9634-22744ccae864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115282677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.2115282677
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.1898043049
Short name T365
Test name
Test status
Simulation time 3596019966 ps
CPU time 4.05 seconds
Started Jul 26 05:35:53 PM PDT 24
Finished Jul 26 05:35:57 PM PDT 24
Peak memory 216396 kb
Host smart-c6f9dd3a-5bf6-4f0a-b018-ef12ca5ab231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898043049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.1898043049
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.661373968
Short name T837
Test name
Test status
Simulation time 34914564 ps
CPU time 0.9 seconds
Started Jul 26 05:35:54 PM PDT 24
Finished Jul 26 05:35:55 PM PDT 24
Peak memory 207148 kb
Host smart-4de2b178-495b-4aae-acf8-c6a4c4452690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661373968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.661373968
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.2467020224
Short name T982
Test name
Test status
Simulation time 10090072 ps
CPU time 0.73 seconds
Started Jul 26 05:35:56 PM PDT 24
Finished Jul 26 05:35:57 PM PDT 24
Peak memory 205668 kb
Host smart-03ff7756-4b14-4eba-940c-019e3549b7e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467020224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.2467020224
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.1403845591
Short name T636
Test name
Test status
Simulation time 541070703 ps
CPU time 8.4 seconds
Started Jul 26 05:35:58 PM PDT 24
Finished Jul 26 05:36:07 PM PDT 24
Peak memory 233076 kb
Host smart-b4fb7424-32ae-490e-a6e1-778f8ef1fd50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403845591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.1403845591
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.1248125250
Short name T808
Test name
Test status
Simulation time 29277720 ps
CPU time 0.77 seconds
Started Jul 26 05:36:02 PM PDT 24
Finished Jul 26 05:36:03 PM PDT 24
Peak memory 204924 kb
Host smart-37b41177-277e-4548-bbd2-b51b14e0671f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248125250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
1248125250
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.3937033449
Short name T811
Test name
Test status
Simulation time 668371407 ps
CPU time 9.2 seconds
Started Jul 26 05:36:06 PM PDT 24
Finished Jul 26 05:36:15 PM PDT 24
Peak memory 224504 kb
Host smart-9b9f2a54-df2e-4329-b3a2-7bbffd687c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937033449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.3937033449
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.3242842209
Short name T313
Test name
Test status
Simulation time 27687489 ps
CPU time 0.79 seconds
Started Jul 26 05:35:59 PM PDT 24
Finished Jul 26 05:36:00 PM PDT 24
Peak memory 205644 kb
Host smart-7c7d8862-8bae-48b5-8e6f-0f92f49372e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242842209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.3242842209
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.2409757174
Short name T366
Test name
Test status
Simulation time 7231431387 ps
CPU time 45.01 seconds
Started Jul 26 05:36:00 PM PDT 24
Finished Jul 26 05:36:45 PM PDT 24
Peak memory 238084 kb
Host smart-f92be5ee-f27f-4094-a87d-a47f21e8245a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409757174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.2409757174
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.852921926
Short name T862
Test name
Test status
Simulation time 4604694254 ps
CPU time 39.68 seconds
Started Jul 26 05:36:01 PM PDT 24
Finished Jul 26 05:36:41 PM PDT 24
Peak memory 249320 kb
Host smart-441936a7-6922-4776-ad37-abfeba019f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852921926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.852921926
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.3370580958
Short name T261
Test name
Test status
Simulation time 116308174206 ps
CPU time 285.17 seconds
Started Jul 26 05:36:01 PM PDT 24
Finished Jul 26 05:40:47 PM PDT 24
Peak memory 265708 kb
Host smart-08524d75-1ccd-4efa-a18c-35733fe5880d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370580958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.3370580958
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.2070000855
Short name T361
Test name
Test status
Simulation time 353968101 ps
CPU time 4.16 seconds
Started Jul 26 05:36:02 PM PDT 24
Finished Jul 26 05:36:06 PM PDT 24
Peak memory 224648 kb
Host smart-5cc0cf92-bffd-4e7f-9d7a-b37a566bd44e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070000855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.2070000855
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.582982315
Short name T392
Test name
Test status
Simulation time 3292838962 ps
CPU time 18.78 seconds
Started Jul 26 05:36:00 PM PDT 24
Finished Jul 26 05:36:19 PM PDT 24
Peak memory 251636 kb
Host smart-a9469547-aaa2-4026-a0de-557cc21c65d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582982315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmds
.582982315
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_intercept.2558703527
Short name T188
Test name
Test status
Simulation time 500729146 ps
CPU time 4.97 seconds
Started Jul 26 05:36:03 PM PDT 24
Finished Jul 26 05:36:08 PM PDT 24
Peak memory 224640 kb
Host smart-6038a6db-3a26-4749-bbb5-20a885616107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558703527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.2558703527
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.757444178
Short name T238
Test name
Test status
Simulation time 10921863724 ps
CPU time 32.45 seconds
Started Jul 26 05:36:02 PM PDT 24
Finished Jul 26 05:36:35 PM PDT 24
Peak memory 240776 kb
Host smart-0a5b4c11-dc30-490a-99ea-8564a53eb815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757444178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.757444178
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.3357906167
Short name T502
Test name
Test status
Simulation time 971267864 ps
CPU time 3.14 seconds
Started Jul 26 05:36:00 PM PDT 24
Finished Jul 26 05:36:04 PM PDT 24
Peak memory 224628 kb
Host smart-5d0a7e52-9107-47e8-a455-3c3a27b8d5a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357906167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.3357906167
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.661407891
Short name T705
Test name
Test status
Simulation time 32341743066 ps
CPU time 26.01 seconds
Started Jul 26 05:35:56 PM PDT 24
Finished Jul 26 05:36:22 PM PDT 24
Peak memory 232828 kb
Host smart-69d7777b-fbec-46c4-987b-cd3d715f509f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661407891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.661407891
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.2657477776
Short name T948
Test name
Test status
Simulation time 3190029067 ps
CPU time 5.92 seconds
Started Jul 26 05:35:59 PM PDT 24
Finished Jul 26 05:36:05 PM PDT 24
Peak memory 219204 kb
Host smart-e70f5056-dcab-4998-b521-6dd99a118c4d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2657477776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.2657477776
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.1167692653
Short name T918
Test name
Test status
Simulation time 194001030 ps
CPU time 1.03 seconds
Started Jul 26 05:36:01 PM PDT 24
Finished Jul 26 05:36:02 PM PDT 24
Peak memory 206764 kb
Host smart-423f3257-30e0-4f4d-b7b7-398b64e85dc9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167692653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.1167692653
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.766509327
Short name T404
Test name
Test status
Simulation time 2227012084 ps
CPU time 5.19 seconds
Started Jul 26 05:36:01 PM PDT 24
Finished Jul 26 05:36:06 PM PDT 24
Peak memory 216432 kb
Host smart-68f17ead-0c69-4a47-9396-883c4cd3f30f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766509327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.766509327
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.1516446518
Short name T957
Test name
Test status
Simulation time 2013706815 ps
CPU time 7.3 seconds
Started Jul 26 05:35:57 PM PDT 24
Finished Jul 26 05:36:04 PM PDT 24
Peak memory 216404 kb
Host smart-a2157b0a-108e-4154-8037-a1a8f814b054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516446518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.1516446518
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.618824447
Short name T309
Test name
Test status
Simulation time 74433238 ps
CPU time 1.02 seconds
Started Jul 26 05:36:06 PM PDT 24
Finished Jul 26 05:36:07 PM PDT 24
Peak memory 207312 kb
Host smart-835a2104-8c6e-41fd-b3d8-f06bdee00d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618824447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.618824447
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.511069358
Short name T903
Test name
Test status
Simulation time 32118294 ps
CPU time 0.79 seconds
Started Jul 26 05:35:56 PM PDT 24
Finished Jul 26 05:35:57 PM PDT 24
Peak memory 205972 kb
Host smart-c9d05614-a6cd-4e69-bda1-b3594f777412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511069358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.511069358
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.2827063217
Short name T726
Test name
Test status
Simulation time 181743292 ps
CPU time 4.83 seconds
Started Jul 26 05:36:05 PM PDT 24
Finished Jul 26 05:36:10 PM PDT 24
Peak memory 232720 kb
Host smart-2e3a5915-bddc-416d-a1b0-7bb756035089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827063217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.2827063217
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.1186471120
Short name T549
Test name
Test status
Simulation time 11850805 ps
CPU time 0.73 seconds
Started Jul 26 05:33:00 PM PDT 24
Finished Jul 26 05:33:01 PM PDT 24
Peak memory 205888 kb
Host smart-1e09e5f4-7f8d-4fb6-9a5e-61d5e67ab152
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186471120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.1
186471120
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.840813890
Short name T716
Test name
Test status
Simulation time 11130692364 ps
CPU time 13 seconds
Started Jul 26 05:33:01 PM PDT 24
Finished Jul 26 05:33:14 PM PDT 24
Peak memory 233072 kb
Host smart-60bfc8de-f58a-4406-b02e-ac52c5ad4bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840813890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.840813890
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.1823177893
Short name T703
Test name
Test status
Simulation time 53006609 ps
CPU time 0.79 seconds
Started Jul 26 05:32:50 PM PDT 24
Finished Jul 26 05:32:51 PM PDT 24
Peak memory 205604 kb
Host smart-dfe93223-5f91-4645-a4c9-8abba078882e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823177893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.1823177893
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.3799987627
Short name T199
Test name
Test status
Simulation time 259181378449 ps
CPU time 128.92 seconds
Started Jul 26 05:33:02 PM PDT 24
Finished Jul 26 05:35:11 PM PDT 24
Peak memory 254352 kb
Host smart-0366499c-329f-4895-b0ee-4f3230e8762d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799987627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.3799987627
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.1630836033
Short name T573
Test name
Test status
Simulation time 81289115607 ps
CPU time 160.07 seconds
Started Jul 26 05:32:59 PM PDT 24
Finished Jul 26 05:35:39 PM PDT 24
Peak memory 250920 kb
Host smart-1afbd432-3438-443f-bca3-35aca665cfa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630836033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.1630836033
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.2727431984
Short name T971
Test name
Test status
Simulation time 119267021869 ps
CPU time 557.14 seconds
Started Jul 26 05:33:01 PM PDT 24
Finished Jul 26 05:42:19 PM PDT 24
Peak memory 255852 kb
Host smart-5ed86b55-58bf-45bd-9cc0-4bf520b17c3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727431984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.2727431984
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.1064379715
Short name T689
Test name
Test status
Simulation time 443456499 ps
CPU time 9.47 seconds
Started Jul 26 05:33:00 PM PDT 24
Finished Jul 26 05:33:10 PM PDT 24
Peak memory 232876 kb
Host smart-eff77abe-c9ab-4de9-881b-36a44f9ea4de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064379715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.1064379715
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.3211530555
Short name T933
Test name
Test status
Simulation time 66359840159 ps
CPU time 449.49 seconds
Started Jul 26 05:33:03 PM PDT 24
Finished Jul 26 05:40:32 PM PDT 24
Peak memory 267152 kb
Host smart-c4f91585-6cb4-4306-8864-40114e4d93ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211530555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds
.3211530555
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_intercept.4033427088
Short name T557
Test name
Test status
Simulation time 854522733 ps
CPU time 3.57 seconds
Started Jul 26 05:32:58 PM PDT 24
Finished Jul 26 05:33:02 PM PDT 24
Peak memory 224616 kb
Host smart-36598039-aa51-471b-960a-9368eb9e2d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033427088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.4033427088
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.1163898160
Short name T845
Test name
Test status
Simulation time 11689477287 ps
CPU time 16.27 seconds
Started Jul 26 05:33:01 PM PDT 24
Finished Jul 26 05:33:17 PM PDT 24
Peak memory 240596 kb
Host smart-bfa6f394-0aef-4b51-818f-fa773bf4f90e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163898160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.1163898160
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.324576978
Short name T625
Test name
Test status
Simulation time 11773850433 ps
CPU time 14.5 seconds
Started Jul 26 05:32:57 PM PDT 24
Finished Jul 26 05:33:12 PM PDT 24
Peak memory 224724 kb
Host smart-d1b441ab-6285-44f0-b6af-99ce208d7994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324576978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap.
324576978
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.949253453
Short name T237
Test name
Test status
Simulation time 9984152661 ps
CPU time 11.08 seconds
Started Jul 26 05:33:00 PM PDT 24
Finished Jul 26 05:33:11 PM PDT 24
Peak memory 232880 kb
Host smart-f2283bac-b68a-4bfa-8fed-6e500a20186d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949253453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.949253453
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.2685709197
Short name T352
Test name
Test status
Simulation time 4021715175 ps
CPU time 12.38 seconds
Started Jul 26 05:33:01 PM PDT 24
Finished Jul 26 05:33:14 PM PDT 24
Peak memory 220868 kb
Host smart-2bb267d3-2e2b-4434-bf4e-d5dad2b89b67
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2685709197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.2685709197
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.3418240100
Short name T397
Test name
Test status
Simulation time 6997808447 ps
CPU time 35.97 seconds
Started Jul 26 05:33:00 PM PDT 24
Finished Jul 26 05:33:36 PM PDT 24
Peak memory 216316 kb
Host smart-8771b11c-fb6f-4c40-ac08-b27d9415f279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418240100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.3418240100
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.3453370285
Short name T291
Test name
Test status
Simulation time 2360302795 ps
CPU time 4.48 seconds
Started Jul 26 05:32:49 PM PDT 24
Finished Jul 26 05:32:54 PM PDT 24
Peak memory 216420 kb
Host smart-f32d807a-c16f-4e2f-b0bb-37b43f52dd8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453370285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.3453370285
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.3656997935
Short name T434
Test name
Test status
Simulation time 12147360 ps
CPU time 0.72 seconds
Started Jul 26 05:32:59 PM PDT 24
Finished Jul 26 05:33:00 PM PDT 24
Peak memory 205712 kb
Host smart-7a69db95-e40a-4afd-9dc2-f7c64df230ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656997935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.3656997935
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.3261392110
Short name T691
Test name
Test status
Simulation time 149209767 ps
CPU time 0.98 seconds
Started Jul 26 05:33:02 PM PDT 24
Finished Jul 26 05:33:03 PM PDT 24
Peak memory 205980 kb
Host smart-8af378b9-0947-4cbf-af79-bbf0639af7db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261392110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.3261392110
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.4237190621
Short name T914
Test name
Test status
Simulation time 368375223 ps
CPU time 5.01 seconds
Started Jul 26 05:33:02 PM PDT 24
Finished Jul 26 05:33:07 PM PDT 24
Peak memory 224852 kb
Host smart-0a4823da-4951-4121-91c4-9f7c9347ad64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237190621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.4237190621
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.3543280719
Short name T620
Test name
Test status
Simulation time 40545180 ps
CPU time 0.79 seconds
Started Jul 26 05:33:00 PM PDT 24
Finished Jul 26 05:33:01 PM PDT 24
Peak memory 205448 kb
Host smart-c7b3f1f1-a919-4f02-b19b-87715426979c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543280719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.3
543280719
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.3586020068
Short name T829
Test name
Test status
Simulation time 40038726 ps
CPU time 2.35 seconds
Started Jul 26 05:33:00 PM PDT 24
Finished Jul 26 05:33:02 PM PDT 24
Peak memory 232764 kb
Host smart-b838065d-5d2c-4d1a-bad0-273c69650fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586020068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.3586020068
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.1757220752
Short name T731
Test name
Test status
Simulation time 38137494 ps
CPU time 0.92 seconds
Started Jul 26 05:33:02 PM PDT 24
Finished Jul 26 05:33:03 PM PDT 24
Peak memory 206712 kb
Host smart-b681ea23-a8b4-4211-9889-02bc93d81b14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757220752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.1757220752
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.3539614692
Short name T536
Test name
Test status
Simulation time 27086075376 ps
CPU time 42.58 seconds
Started Jul 26 05:33:02 PM PDT 24
Finished Jul 26 05:33:44 PM PDT 24
Peak memory 249352 kb
Host smart-c0b44166-d3a5-468f-9932-1becbcf9c9ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539614692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.3539614692
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.2962204394
Short name T483
Test name
Test status
Simulation time 244221268 ps
CPU time 4.47 seconds
Started Jul 26 05:33:01 PM PDT 24
Finished Jul 26 05:33:06 PM PDT 24
Peak memory 232832 kb
Host smart-7bb07cf6-a982-4a59-a1ea-3d5dc76b9cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962204394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.2962204394
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.2303677400
Short name T1010
Test name
Test status
Simulation time 144359041233 ps
CPU time 253.87 seconds
Started Jul 26 05:33:01 PM PDT 24
Finished Jul 26 05:37:15 PM PDT 24
Peak memory 249340 kb
Host smart-734d99fe-5852-4f59-b416-b318a7c9244b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303677400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds
.2303677400
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/6.spi_device_intercept.718463260
Short name T732
Test name
Test status
Simulation time 74891032 ps
CPU time 2.27 seconds
Started Jul 26 05:33:01 PM PDT 24
Finished Jul 26 05:33:04 PM PDT 24
Peak memory 223168 kb
Host smart-9d2aa67d-b310-4df4-9005-13ae55b15c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718463260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.718463260
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.3123868863
Short name T806
Test name
Test status
Simulation time 81068862854 ps
CPU time 93.19 seconds
Started Jul 26 05:33:00 PM PDT 24
Finished Jul 26 05:34:34 PM PDT 24
Peak memory 240436 kb
Host smart-cc109afc-a180-4a68-887d-d87a43708aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123868863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.3123868863
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.1410047414
Short name T231
Test name
Test status
Simulation time 1820581268 ps
CPU time 6.43 seconds
Started Jul 26 05:32:58 PM PDT 24
Finished Jul 26 05:33:05 PM PDT 24
Peak memory 232868 kb
Host smart-ce5b96e8-b123-451e-9542-9bf138f3e056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410047414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.1410047414
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.2202577225
Short name T357
Test name
Test status
Simulation time 4126838591 ps
CPU time 12.34 seconds
Started Jul 26 05:33:00 PM PDT 24
Finished Jul 26 05:33:12 PM PDT 24
Peak memory 252928 kb
Host smart-d92cb96f-d9ab-4d7d-89d1-c4e6b6e097bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202577225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.2202577225
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.3598236855
Short name T335
Test name
Test status
Simulation time 836091620 ps
CPU time 10.27 seconds
Started Jul 26 05:33:03 PM PDT 24
Finished Jul 26 05:33:13 PM PDT 24
Peak memory 222452 kb
Host smart-dd8ccea0-9479-4bc9-8cd9-5b01736ad153
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3598236855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.3598236855
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.1374405771
Short name T576
Test name
Test status
Simulation time 10355594871 ps
CPU time 59.82 seconds
Started Jul 26 05:33:00 PM PDT 24
Finished Jul 26 05:34:00 PM PDT 24
Peak memory 224668 kb
Host smart-7fc17ed5-89b4-46cb-ac84-554a22dc8f20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374405771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.1374405771
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.4282256356
Short name T584
Test name
Test status
Simulation time 3145850731 ps
CPU time 7.16 seconds
Started Jul 26 05:33:02 PM PDT 24
Finished Jul 26 05:33:09 PM PDT 24
Peak memory 216412 kb
Host smart-7a87c0cb-7fc0-48d1-a9eb-099a9d1a5b08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282256356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.4282256356
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.3652670264
Short name T602
Test name
Test status
Simulation time 3548396735 ps
CPU time 9.69 seconds
Started Jul 26 05:32:59 PM PDT 24
Finished Jul 26 05:33:09 PM PDT 24
Peak memory 216428 kb
Host smart-a4b53a4e-304b-4f17-925d-181ed96ed4cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652670264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.3652670264
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.3282594309
Short name T900
Test name
Test status
Simulation time 65143093 ps
CPU time 0.89 seconds
Started Jul 26 05:33:03 PM PDT 24
Finished Jul 26 05:33:04 PM PDT 24
Peak memory 207104 kb
Host smart-bdee6853-030f-4a96-8cf0-46885600dcad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282594309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.3282594309
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.3270692699
Short name T423
Test name
Test status
Simulation time 414307443 ps
CPU time 0.85 seconds
Started Jul 26 05:33:02 PM PDT 24
Finished Jul 26 05:33:03 PM PDT 24
Peak memory 206056 kb
Host smart-c69ee778-9ab3-4e04-a4e1-784029d9b131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270692699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.3270692699
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.537930328
Short name T375
Test name
Test status
Simulation time 12665425422 ps
CPU time 18.42 seconds
Started Jul 26 05:32:59 PM PDT 24
Finished Jul 26 05:33:18 PM PDT 24
Peak memory 224760 kb
Host smart-796f5c58-1c11-4d51-ae24-bcaab75a344c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537930328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.537930328
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.2023593375
Short name T391
Test name
Test status
Simulation time 34152361 ps
CPU time 0.75 seconds
Started Jul 26 05:33:01 PM PDT 24
Finished Jul 26 05:33:02 PM PDT 24
Peak memory 204984 kb
Host smart-b96f4307-7159-44d5-8140-01ff6f18e63f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023593375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.2
023593375
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.3370276457
Short name T471
Test name
Test status
Simulation time 32264791 ps
CPU time 2.49 seconds
Started Jul 26 05:33:01 PM PDT 24
Finished Jul 26 05:33:04 PM PDT 24
Peak memory 232832 kb
Host smart-60eba1fc-2264-4bf6-abfa-5ed1cc80e72a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370276457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.3370276457
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.862843672
Short name T487
Test name
Test status
Simulation time 284344797 ps
CPU time 0.77 seconds
Started Jul 26 05:33:00 PM PDT 24
Finished Jul 26 05:33:01 PM PDT 24
Peak memory 206712 kb
Host smart-e8d9ec61-7f1e-459f-b2e3-28c235d8a16e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862843672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.862843672
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.779648243
Short name T742
Test name
Test status
Simulation time 5695960608 ps
CPU time 55.41 seconds
Started Jul 26 05:33:03 PM PDT 24
Finished Jul 26 05:33:58 PM PDT 24
Peak memory 251096 kb
Host smart-4f9be614-b821-4cba-b7fc-605d88510039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779648243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.779648243
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.2707857488
Short name T282
Test name
Test status
Simulation time 11803181494 ps
CPU time 45.57 seconds
Started Jul 26 05:33:04 PM PDT 24
Finished Jul 26 05:33:49 PM PDT 24
Peak memory 239024 kb
Host smart-50e40884-5701-4b60-9d43-8261ac8e0191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707857488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.2707857488
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.3148247803
Short name T40
Test name
Test status
Simulation time 54435440483 ps
CPU time 135.33 seconds
Started Jul 26 05:33:05 PM PDT 24
Finished Jul 26 05:35:20 PM PDT 24
Peak memory 249276 kb
Host smart-764712c1-c8c7-41d8-9ccf-9f1c4242fcee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148247803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.3148247803
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.2086354348
Short name T276
Test name
Test status
Simulation time 2140121654 ps
CPU time 29.66 seconds
Started Jul 26 05:33:04 PM PDT 24
Finished Jul 26 05:33:34 PM PDT 24
Peak memory 233800 kb
Host smart-ebb91db4-f753-48df-9d12-53fda911590a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086354348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.2086354348
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.2174570933
Short name T260
Test name
Test status
Simulation time 135550395142 ps
CPU time 455.58 seconds
Started Jul 26 05:33:02 PM PDT 24
Finished Jul 26 05:40:37 PM PDT 24
Peak memory 271712 kb
Host smart-7f71a611-9e82-4a5a-a73c-d56a68271abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174570933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds
.2174570933
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.1982029845
Short name T373
Test name
Test status
Simulation time 212875529 ps
CPU time 4.95 seconds
Started Jul 26 05:33:03 PM PDT 24
Finished Jul 26 05:33:08 PM PDT 24
Peak memory 224520 kb
Host smart-6412d8f9-55cb-4d5b-aa80-47d7a27c233a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982029845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.1982029845
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.1490609125
Short name T949
Test name
Test status
Simulation time 366826161 ps
CPU time 3.69 seconds
Started Jul 26 05:32:59 PM PDT 24
Finished Jul 26 05:33:03 PM PDT 24
Peak memory 224668 kb
Host smart-baacf10d-ec4f-4bd2-9385-856e6b394984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490609125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.1490609125
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.4195956269
Short name T252
Test name
Test status
Simulation time 989504860 ps
CPU time 5.41 seconds
Started Jul 26 05:33:05 PM PDT 24
Finished Jul 26 05:33:11 PM PDT 24
Peak memory 233772 kb
Host smart-e8950f0d-a4d9-4fbf-9137-d4ede2e54009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195956269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.4195956269
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.1324012122
Short name T734
Test name
Test status
Simulation time 616881717 ps
CPU time 4.93 seconds
Started Jul 26 05:33:01 PM PDT 24
Finished Jul 26 05:33:06 PM PDT 24
Peak memory 224664 kb
Host smart-ab43bc72-01a5-4427-b955-41062546be26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324012122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.1324012122
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.3792423480
Short name T763
Test name
Test status
Simulation time 2469152752 ps
CPU time 9.6 seconds
Started Jul 26 05:32:58 PM PDT 24
Finished Jul 26 05:33:07 PM PDT 24
Peak memory 221792 kb
Host smart-edb2baec-b18f-4736-a4b1-eb4d88932e59
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3792423480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.3792423480
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.2029098735
Short name T222
Test name
Test status
Simulation time 133714811992 ps
CPU time 652.06 seconds
Started Jul 26 05:33:03 PM PDT 24
Finished Jul 26 05:43:55 PM PDT 24
Peak memory 271064 kb
Host smart-5d234dd7-5a43-489c-9a41-ed617070717a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029098735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.2029098735
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.422680965
Short name T499
Test name
Test status
Simulation time 44054891 ps
CPU time 0.7 seconds
Started Jul 26 05:33:04 PM PDT 24
Finished Jul 26 05:33:05 PM PDT 24
Peak memory 205716 kb
Host smart-60d233b6-5233-4abd-bc8f-23973cb3f5fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422680965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.422680965
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.4012065423
Short name T955
Test name
Test status
Simulation time 7973886601 ps
CPU time 11.55 seconds
Started Jul 26 05:33:03 PM PDT 24
Finished Jul 26 05:33:15 PM PDT 24
Peak memory 216480 kb
Host smart-82d047af-c23a-4128-bd7f-6cb94fbf1ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012065423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.4012065423
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.3132853373
Short name T513
Test name
Test status
Simulation time 35503935 ps
CPU time 1.24 seconds
Started Jul 26 05:33:00 PM PDT 24
Finished Jul 26 05:33:01 PM PDT 24
Peak memory 207944 kb
Host smart-38a93452-6efe-43dd-9c57-62bb43683752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132853373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.3132853373
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.3172822938
Short name T468
Test name
Test status
Simulation time 65380190 ps
CPU time 0.88 seconds
Started Jul 26 05:33:07 PM PDT 24
Finished Jul 26 05:33:08 PM PDT 24
Peak memory 205948 kb
Host smart-6477e56d-7d79-4e10-8110-750a3db9b735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172822938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.3172822938
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.1045347413
Short name T527
Test name
Test status
Simulation time 10348579525 ps
CPU time 10.6 seconds
Started Jul 26 05:32:58 PM PDT 24
Finished Jul 26 05:33:09 PM PDT 24
Peak memory 232920 kb
Host smart-1bd28a09-4828-42ca-8f59-896ce0e77778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045347413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.1045347413
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.710796740
Short name T318
Test name
Test status
Simulation time 50909742 ps
CPU time 0.73 seconds
Started Jul 26 05:33:16 PM PDT 24
Finished Jul 26 05:33:17 PM PDT 24
Peak memory 205220 kb
Host smart-40ce1628-e47f-4ec9-a796-ccaac00b419f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710796740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.710796740
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.3473038973
Short name T511
Test name
Test status
Simulation time 45663127 ps
CPU time 2.65 seconds
Started Jul 26 05:33:13 PM PDT 24
Finished Jul 26 05:33:16 PM PDT 24
Peak memory 232844 kb
Host smart-84390145-0e58-4114-8ca3-3e90b69bd9fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473038973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.3473038973
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.3002836226
Short name T943
Test name
Test status
Simulation time 15275517 ps
CPU time 0.76 seconds
Started Jul 26 05:33:02 PM PDT 24
Finished Jul 26 05:33:03 PM PDT 24
Peak memory 205916 kb
Host smart-5b43b1fa-7be1-43db-99b5-3be95b366082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002836226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.3002836226
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.4286450617
Short name T715
Test name
Test status
Simulation time 22573738694 ps
CPU time 79.63 seconds
Started Jul 26 05:33:12 PM PDT 24
Finished Jul 26 05:34:32 PM PDT 24
Peak memory 254048 kb
Host smart-d6bb89fb-9463-4593-ba9f-f2dec4cc36be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286450617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.4286450617
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.1377264531
Short name T789
Test name
Test status
Simulation time 5209620873 ps
CPU time 104.11 seconds
Started Jul 26 05:33:13 PM PDT 24
Finished Jul 26 05:34:57 PM PDT 24
Peak memory 267276 kb
Host smart-044e974f-a561-419e-ab1d-9258cf3665bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377264531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.1377264531
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.2401907882
Short name T613
Test name
Test status
Simulation time 40455889021 ps
CPU time 105.84 seconds
Started Jul 26 05:33:13 PM PDT 24
Finished Jul 26 05:34:59 PM PDT 24
Peak memory 238756 kb
Host smart-83d1690f-0bde-47e5-b376-d9922546dd73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401907882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.2401907882
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.1930241289
Short name T581
Test name
Test status
Simulation time 30652327519 ps
CPU time 91.15 seconds
Started Jul 26 05:33:18 PM PDT 24
Finished Jul 26 05:34:49 PM PDT 24
Peak memory 240532 kb
Host smart-cb9be7a0-933d-4344-aa25-f09ae89b7d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930241289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.1930241289
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.1133652554
Short name T828
Test name
Test status
Simulation time 12718783266 ps
CPU time 91.68 seconds
Started Jul 26 05:33:14 PM PDT 24
Finished Jul 26 05:34:46 PM PDT 24
Peak memory 249356 kb
Host smart-3233baf2-0d64-48da-b5ce-77f416d6905f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133652554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds
.1133652554
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/8.spi_device_intercept.200546070
Short name T793
Test name
Test status
Simulation time 345093090 ps
CPU time 4.19 seconds
Started Jul 26 05:33:15 PM PDT 24
Finished Jul 26 05:33:19 PM PDT 24
Peak memory 224668 kb
Host smart-4598b193-98bd-4702-b732-94d700f7a458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200546070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.200546070
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.2328380560
Short name T321
Test name
Test status
Simulation time 3493457409 ps
CPU time 14.97 seconds
Started Jul 26 05:33:15 PM PDT 24
Finished Jul 26 05:33:30 PM PDT 24
Peak memory 224736 kb
Host smart-e2a17a11-67c3-4d71-adc8-c1886bb10dc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328380560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.2328380560
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.1473241019
Short name T518
Test name
Test status
Simulation time 1565136520 ps
CPU time 6.57 seconds
Started Jul 26 05:33:10 PM PDT 24
Finished Jul 26 05:33:17 PM PDT 24
Peak memory 224608 kb
Host smart-76435917-0c0c-40c4-beac-ddc7624e9531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473241019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.1473241019
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.3328256108
Short name T771
Test name
Test status
Simulation time 1479922792 ps
CPU time 11.95 seconds
Started Jul 26 05:33:13 PM PDT 24
Finished Jul 26 05:33:25 PM PDT 24
Peak memory 232816 kb
Host smart-f4c22439-d7c8-4715-9647-f0792edb37ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328256108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.3328256108
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.249940036
Short name T870
Test name
Test status
Simulation time 5552326044 ps
CPU time 7.07 seconds
Started Jul 26 05:33:11 PM PDT 24
Finished Jul 26 05:33:19 PM PDT 24
Peak memory 221524 kb
Host smart-24ed425d-4df9-44ef-8087-258b2f51e937
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=249940036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_direc
t.249940036
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.1407794041
Short name T645
Test name
Test status
Simulation time 86566173141 ps
CPU time 476.2 seconds
Started Jul 26 05:33:12 PM PDT 24
Finished Jul 26 05:41:09 PM PDT 24
Peak memory 285816 kb
Host smart-1009efb4-09d2-4a27-9f83-3885b259d31f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407794041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.1407794041
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.3612515180
Short name T508
Test name
Test status
Simulation time 1113391052 ps
CPU time 16.2 seconds
Started Jul 26 05:33:02 PM PDT 24
Finished Jul 26 05:33:18 PM PDT 24
Peak memory 216372 kb
Host smart-ac28ed26-91dd-4705-b587-de3e62be571f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612515180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.3612515180
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.2218155585
Short name T568
Test name
Test status
Simulation time 1219197666 ps
CPU time 5.68 seconds
Started Jul 26 05:33:03 PM PDT 24
Finished Jul 26 05:33:08 PM PDT 24
Peak memory 216332 kb
Host smart-3ee3d750-4b48-40c3-97bc-b3940f14d31e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218155585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.2218155585
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.771573795
Short name T694
Test name
Test status
Simulation time 126237769 ps
CPU time 7.17 seconds
Started Jul 26 05:33:15 PM PDT 24
Finished Jul 26 05:33:23 PM PDT 24
Peak memory 216436 kb
Host smart-59d7f288-d781-42c7-8c85-48d64021a075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771573795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.771573795
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.2202555378
Short name T747
Test name
Test status
Simulation time 119838636 ps
CPU time 0.76 seconds
Started Jul 26 05:33:14 PM PDT 24
Finished Jul 26 05:33:15 PM PDT 24
Peak memory 205972 kb
Host smart-9d8477fe-fd7b-4c4d-ac2f-41c392ad40a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202555378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.2202555378
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.3858777592
Short name T435
Test name
Test status
Simulation time 5436587809 ps
CPU time 18.47 seconds
Started Jul 26 05:33:18 PM PDT 24
Finished Jul 26 05:33:36 PM PDT 24
Peak memory 224736 kb
Host smart-29a5580a-5480-4298-83ec-5fd1f1f0262c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858777592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.3858777592
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.2758928719
Short name T836
Test name
Test status
Simulation time 14279860 ps
CPU time 0.7 seconds
Started Jul 26 05:33:13 PM PDT 24
Finished Jul 26 05:33:14 PM PDT 24
Peak memory 204940 kb
Host smart-c849f48e-c99f-4560-96b3-8437b5b04c1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758928719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.2
758928719
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.2257244785
Short name T660
Test name
Test status
Simulation time 553054621 ps
CPU time 4.28 seconds
Started Jul 26 05:33:15 PM PDT 24
Finished Jul 26 05:33:19 PM PDT 24
Peak memory 232764 kb
Host smart-61d419eb-b4a7-4992-bd75-3a992eff7f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257244785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.2257244785
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.1159007952
Short name T455
Test name
Test status
Simulation time 178740560 ps
CPU time 0.76 seconds
Started Jul 26 05:33:13 PM PDT 24
Finished Jul 26 05:33:14 PM PDT 24
Peak memory 206708 kb
Host smart-6895ed94-71e4-48d4-ac8e-7c65742e2786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159007952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.1159007952
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.3776317153
Short name T817
Test name
Test status
Simulation time 6325188612 ps
CPU time 94.11 seconds
Started Jul 26 05:33:13 PM PDT 24
Finished Jul 26 05:34:48 PM PDT 24
Peak memory 253856 kb
Host smart-8a901676-37fd-42d9-9607-77d96d02648a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776317153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.3776317153
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.112294678
Short name T185
Test name
Test status
Simulation time 9061659020 ps
CPU time 101.73 seconds
Started Jul 26 05:33:15 PM PDT 24
Finished Jul 26 05:34:57 PM PDT 24
Peak memory 233136 kb
Host smart-85623c90-ab61-49fc-932b-2c44dcfd9f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112294678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.112294678
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.3477635476
Short name T355
Test name
Test status
Simulation time 309370109780 ps
CPU time 172.56 seconds
Started Jul 26 05:33:14 PM PDT 24
Finished Jul 26 05:36:07 PM PDT 24
Peak memory 251172 kb
Host smart-afe4de45-5694-42df-b30a-f53a108b86a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477635476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.3477635476
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.3220123953
Short name T389
Test name
Test status
Simulation time 84561235 ps
CPU time 2.73 seconds
Started Jul 26 05:33:16 PM PDT 24
Finished Jul 26 05:33:19 PM PDT 24
Peak memory 224676 kb
Host smart-5284e4d6-f586-4f42-88d4-142841818013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220123953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.3220123953
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.1516500369
Short name T364
Test name
Test status
Simulation time 2446712432 ps
CPU time 53.19 seconds
Started Jul 26 05:33:14 PM PDT 24
Finished Jul 26 05:34:07 PM PDT 24
Peak memory 256108 kb
Host smart-85d53925-0dac-45fd-b951-caa9e288d541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516500369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds
.1516500369
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.4174083997
Short name T539
Test name
Test status
Simulation time 11629888742 ps
CPU time 22.1 seconds
Started Jul 26 05:33:18 PM PDT 24
Finished Jul 26 05:33:40 PM PDT 24
Peak memory 224704 kb
Host smart-1ae5bcf9-c040-497b-b5f0-8a9cf1cc3f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174083997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.4174083997
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.2149955533
Short name T821
Test name
Test status
Simulation time 2477392938 ps
CPU time 32.14 seconds
Started Jul 26 05:33:11 PM PDT 24
Finished Jul 26 05:33:44 PM PDT 24
Peak memory 232736 kb
Host smart-0c1304a1-4139-43fe-82e9-13fe9fb9a660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149955533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.2149955533
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.2106703111
Short name T853
Test name
Test status
Simulation time 4287019929 ps
CPU time 6.73 seconds
Started Jul 26 05:33:13 PM PDT 24
Finished Jul 26 05:33:20 PM PDT 24
Peak memory 224560 kb
Host smart-054b84f3-c728-4d1e-a058-95e3f859c4e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106703111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.2106703111
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.3462603265
Short name T750
Test name
Test status
Simulation time 14157522906 ps
CPU time 24.42 seconds
Started Jul 26 05:33:17 PM PDT 24
Finished Jul 26 05:33:42 PM PDT 24
Peak memory 240548 kb
Host smart-a7f38806-b4bd-4336-b3d3-5f3ddd2f77b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462603265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.3462603265
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.4276728334
Short name T961
Test name
Test status
Simulation time 500643131 ps
CPU time 4.36 seconds
Started Jul 26 05:33:13 PM PDT 24
Finished Jul 26 05:33:17 PM PDT 24
Peak memory 222816 kb
Host smart-150bcf41-7bce-4919-bb9e-29d24cf1b877
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4276728334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.4276728334
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.1056016235
Short name T41
Test name
Test status
Simulation time 5814739084 ps
CPU time 70.87 seconds
Started Jul 26 05:33:18 PM PDT 24
Finished Jul 26 05:34:29 PM PDT 24
Peak memory 252780 kb
Host smart-a021bf8b-a29d-4611-b211-2cc6cc2ea6a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056016235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.1056016235
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.1460036963
Short name T595
Test name
Test status
Simulation time 10013926351 ps
CPU time 51.46 seconds
Started Jul 26 05:33:16 PM PDT 24
Finished Jul 26 05:34:08 PM PDT 24
Peak memory 219972 kb
Host smart-b7b7e338-f04e-4acc-af32-535901d3ee25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460036963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.1460036963
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.3448838677
Short name T779
Test name
Test status
Simulation time 46983852716 ps
CPU time 17.66 seconds
Started Jul 26 05:33:16 PM PDT 24
Finished Jul 26 05:33:33 PM PDT 24
Peak memory 216412 kb
Host smart-d200381d-39d2-476b-a15b-bc8b402b45c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448838677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.3448838677
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.4119662265
Short name T708
Test name
Test status
Simulation time 52453806 ps
CPU time 1.65 seconds
Started Jul 26 05:33:14 PM PDT 24
Finished Jul 26 05:33:16 PM PDT 24
Peak memory 216380 kb
Host smart-c3183947-6cc6-40c9-bb20-2185b026cd69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119662265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.4119662265
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.3407399103
Short name T433
Test name
Test status
Simulation time 42399197 ps
CPU time 0.76 seconds
Started Jul 26 05:33:13 PM PDT 24
Finished Jul 26 05:33:14 PM PDT 24
Peak memory 205964 kb
Host smart-28bd2f71-aba8-43e2-9834-1bf16aebf30c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407399103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.3407399103
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.2902541658
Short name T476
Test name
Test status
Simulation time 2989531402 ps
CPU time 4.72 seconds
Started Jul 26 05:33:14 PM PDT 24
Finished Jul 26 05:33:18 PM PDT 24
Peak memory 224648 kb
Host smart-bbc15048-5afd-4058-b773-9234deb1f6b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902541658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.2902541658
Directory /workspace/9.spi_device_upload/latest
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