Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2753045	1			T1	2567		T2	7		T3	1
all_values[1]	2753045	1			T1	2567		T2	7		T3	1
all_values[2]	2753045	1			T1	2567		T2	7		T3	1
all_values[3]	2753045	1			T1	2567		T2	7		T3	1
all_values[4]	2753045	1			T1	2567		T2	7		T3	1
all_values[5]	2753045	1			T1	2567		T2	7		T3	1
all_values[6]	2753045	1			T1	2567		T2	7		T3	1
all_values[7]	2753045	1			T1	2567		T2	7		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21742087

1

T1

20536

T2

56

T3

8

auto[1]

282273

1

T8

11

T16

52

T21

60

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21997930

1

T1

20536

T2

54

T3

8

auto[1]

26430

1

T2

2

T8

125

T16

48

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2678555	1			T1	2567		T2	7		T3	1
all_values[0]	auto[0]	auto[1]	11493	1			T8	46		T16	2		T18	79
all_values[0]	auto[1]	auto[0]	61874	1			T8	1		T16	3		T21	3
all_values[0]	auto[1]	auto[1]	1123	1			T8	3		T16	5		T21	2
all_values[1]	auto[0]	auto[0]	2713187	1			T1	2567		T2	7		T3	1
all_values[1]	auto[0]	auto[1]	7799	1			T8	47		T16	6		T18	79
all_values[1]	auto[1]	auto[0]	31476	1			T8	1		T16	2		T21	8
all_values[1]	auto[1]	auto[1]	583	1			T16	4		T21	1		T22	3
all_values[2]	auto[0]	auto[0]	2733967	1			T1	2567		T2	7		T3	1
all_values[2]	auto[0]	auto[1]	3152	1			T8	17		T16	3		T21	79
all_values[2]	auto[1]	auto[0]	15682	1			T16	4		T21	6		T22	6
all_values[2]	auto[1]	auto[1]	244	1			T8	1		T16	2		T21	5
all_values[3]	auto[0]	auto[0]	2699613	1			T1	2567		T2	7		T3	1
all_values[3]	auto[0]	auto[1]	197	1			T8	1		T16	5		T21	2
all_values[3]	auto[1]	auto[0]	53026	1			T8	1		T16	1		T21	7
all_values[3]	auto[1]	auto[1]	209	1			T8	3		T21	2		T22	10
all_values[4]	auto[0]	auto[0]	2737718	1			T1	2567		T2	5		T3	1
all_values[4]	auto[0]	auto[1]	225	1			T2	2		T8	2		T16	3
all_values[4]	auto[1]	auto[0]	14877	1			T16	6		T21	2		T22	8
all_values[4]	auto[1]	auto[1]	225	1			T16	2		T21	1		T22	8
all_values[5]	auto[0]	auto[0]	2745702	1			T1	2567		T2	7		T3	1
all_values[5]	auto[0]	auto[1]	206	1			T8	1		T16	2		T21	3
all_values[5]	auto[1]	auto[0]	6945	1			T16	8		T21	4		T22	5
all_values[5]	auto[1]	auto[1]	192	1			T16	2		T22	2		T27	2
all_values[6]	auto[0]	auto[0]	2722923	1			T1	2567		T2	7		T3	1
all_values[6]	auto[0]	auto[1]	200	1			T16	2		T21	1		T22	6
all_values[6]	auto[1]	auto[0]	29744	1			T16	2		T21	5		T22	5
all_values[6]	auto[1]	auto[1]	178	1			T8	1		T16	1		T21	3
all_values[7]	auto[0]	auto[0]	2686964	1			T1	2567		T2	7		T3	1
all_values[7]	auto[0]	auto[1]	186	1			T8	3		T16	4		T21	2
all_values[7]	auto[1]	auto[0]	65677	1			T16	5		T21	5		T22	6
all_values[7]	auto[1]	auto[1]	218	1			T16	5		T21	6		T22	5