Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	36511	1			T7	30		T8	127		T15	115
auto[SpiFlashAddrCfg]	8227	1			T2	3		T7	2		T8	40
auto[SpiFlashAddr3b]	9595	1			T2	2		T4	2		T8	41
auto[SpiFlashAddr4b]	8001	1			T2	1		T7	2		T8	35

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

35496

1

T2

6

T7

34

T8

142

auto[1]

26838

1

T4

2

T8

101

T13

20

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33550

1

T2

2

T4

2

T8

154

auto[1]

28784

1

T2

4

T7

34

T8

89

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	41398	1			T2	1		T4	2		T7	34
values[1]	1176	1			T8	6		T13	2		T17	11
values[2]	1561	1			T8	10		T15	4		T17	3
values[3]	1532	1			T8	8		T17	6		T36	4
values[4]	1473	1			T8	6		T15	2		T17	8
values[5]	1640	1			T2	3		T8	4		T17	9
values[6]	1621	1			T8	8		T15	2		T17	6
values[7]	1530	1			T2	1		T8	6		T13	2
values[8]	10403	1			T2	1		T8	44		T13	10

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31204

1

T4

2

T7

34

T13

20

auto[1]

31130

1

T2

6

T8

243

T17

330

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

58866

1

T2

6

T7

32

T8

224

write

3468

1

T4

2

T7

2

T8

19

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

20546

1

T2

5

T7

2

T8

87

valids[0x1]

41788

1

T2

1

T4

2

T7

32

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1728	1			T8	9		T17	9		T18	3
internal_process_ops[0x5a]	1603	1			T8	7		T17	9		T18	4
internal_process_ops[0x05]	21559	1			T7	30		T8	50		T15	115
internal_process_ops[0x35]	1777	1			T8	5		T17	9		T18	3
internal_process_ops[0x15]	1677	1			T8	11		T17	10		T18	4
internal_process_ops[0x03]	1039	1			T8	4		T13	2		T17	3
internal_process_ops[0x0b]	1125	1			T2	1		T8	2		T17	3
internal_process_ops[0x3b]	1147	1			T2	1		T8	6		T17	1
internal_process_ops[0x6b]	1153	1			T2	3		T8	3		T15	2
internal_process_ops[0xbb]	1098	1			T8	4		T17	3		T18	5
internal_process_ops[0xeb]	1125	1			T2	1		T8	3		T17	3

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

60663

1

T2

6

T7

34

T8

231

auto[1]

1671

1

T4

2

T8

12

T17

9

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

59831

1

T2

6

T4

2

T7

32

auto[1]

2503

1

T7

2

T8

7

T15

4

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10355

1

T7

30

T15

115

T18

43

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6346

1

T18

6

T101

2

T21

30

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2067

1

T15

6

T18

5

T21

17

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1947

1

T13

8

T18

9

T21

21

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2549

1

T15

2

T18

8

T20

6

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2296

1

T13

4

T18

11

T21

39

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2095

1

T7

2

T15

2

T18

11

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1904

1

T13

8

T18

4

T21

40

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

106

1

T21

3

T46

3

T27

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

83

1

T21

1

T37

2

T46

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

112

1

T37

3

T46

2

T27

4

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

116

1

T21

3

T48

2

T27

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

145

1

T7

2

T15

2

T46

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

98

1

T21

1

T37

1

T38

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

91

1

T37

2

T27

1

T38

6

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

102

1

T46

2

T49

1

T45

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

119

1

T18

4

T37

1

T27

6

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

93

1

T18

2

T38

4

T45

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

89

1

T46

1

T27

1

T38

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

106

1

T4

2

T47

2

T27

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

108

1

T15

2

T18

2

T21

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

88

1

T21

2

T37

2

T46

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

101

1

T21

1

T37

2

T46

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

88

1

T37

3

T46

2

T49

2

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

11396

1

T8

79

T17

74

T36

25

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7604

1

T8

46

T17

119

T36

8

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1699

1

T2

3

T8

17

T17

17

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1584

1

T8

17

T17

13

T36

11

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1955

1

T2

2

T8

16

T17

19

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1917

1

T8

18

T17

28

T36

5

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1618

1

T2

1

T8

19

T17

21

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1534

1

T8

12

T17

22

T36

4

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

98

1

T66

2

T165

2

T98

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

95

1

T36

1

T22

2

T51

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

100

1

T8

2

T17

1

T52

4

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

100

1

T17

2

T52

3

T66

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

126

1

T17

2

T36

3

T66

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

124

1

T8

3

T36

1

T52

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

127

1

T8

1

T36

2

T22

5

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

117

1

T8

2

T17

2

T52

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

130

1

T8

2

T17

1

T25

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

114

1

T8

3

T17

1

T36

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

111

1

T8

1

T36

2

T66

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

116

1

T8

1

T17

3

T52

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

118

1

T17

2

T22

3

T98

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

117

1

T8

3

T52

2

T22

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

116

1

T8

1

T17

2

T22

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

114

1

T17

1

T66

6

T165

1

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3925	1			T7	2		T13	4		T18	11
auto[0]	values[0]	valids[0x1]	15640	1			T4	2		T7	32		T13	2
auto[0]	values[1]	valids[0x1]	595	1			T13	2		T18	1		T21	5
auto[0]	values[2]	valids[0x0]	584	1			T18	3		T21	3		T37	3
auto[0]	values[2]	valids[0x1]	280	1			T15	4		T21	4		T37	4
auto[0]	values[3]	valids[0x0]	574	1			T21	8		T37	3		T46	3
auto[0]	values[3]	valids[0x1]	282	1			T21	5		T37	7		T46	3
auto[0]	values[4]	valids[0x0]	525	1			T15	2		T21	7		T37	5
auto[0]	values[4]	valids[0x1]	288	1			T18	1		T21	3		T37	1
auto[0]	values[5]	valids[0x0]	606	1			T18	3		T21	10		T37	10
auto[0]	values[5]	valids[0x1]	283	1			T18	2		T21	8		T37	4
auto[0]	values[6]	valids[0x0]	597	1			T15	2		T18	4		T21	4
auto[0]	values[6]	valids[0x1]	332	1			T21	3		T46	6		T27	11
auto[0]	values[7]	valids[0x0]	560	1			T13	2		T18	3		T21	9
auto[0]	values[7]	valids[0x1]	322	1			T18	3		T21	5		T37	5
auto[0]	values[8]	valids[0x0]	3670	1			T13	2		T15	2		T18	18
auto[0]	values[8]	valids[0x1]	2141	1			T13	8		T18	7		T20	6
auto[1]	values[0]	valids[0x0]	4321	1			T8	40		T17	45		T36	17
auto[1]	values[0]	valids[0x1]	17512	1			T2	1		T8	111		T17	176
auto[1]	values[1]	valids[0x1]	581	1			T8	6		T17	11		T36	2
auto[1]	values[2]	valids[0x0]	410	1			T8	7		T17	2		T19	2
auto[1]	values[2]	valids[0x1]	287	1			T8	3		T17	1		T36	1
auto[1]	values[3]	valids[0x0]	404	1			T8	4		T17	3		T36	1
auto[1]	values[3]	valids[0x1]	272	1			T8	4		T17	3		T36	3
auto[1]	values[4]	valids[0x0]	379	1			T17	5		T52	2		T22	1
auto[1]	values[4]	valids[0x1]	281	1			T8	6		T17	3		T22	4
auto[1]	values[5]	valids[0x0]	462	1			T2	3		T8	2		T17	9
auto[1]	values[5]	valids[0x1]	289	1			T8	2		T36	4		T52	3
auto[1]	values[6]	valids[0x0]	408	1			T8	6		T17	5		T36	5
auto[1]	values[6]	valids[0x1]	284	1			T8	2		T17	1		T19	1
auto[1]	values[7]	valids[0x0]	385	1			T2	1		T8	4		T17	2
auto[1]	values[7]	valids[0x1]	263	1			T8	2		T17	3		T52	6
auto[1]	values[8]	valids[0x0]	2736	1			T2	1		T8	24		T17	35
auto[1]	values[8]	valids[0x1]	1856	1			T8	20		T17	26		T36	8