Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3405800

1

T1

1

T2

1268

T4

1

auto[1]

36661

1

T7

30

T8

43

T15

115

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

862936

1

T1

1

T2

1268

T4

1

auto[1]

2579525

1

T7

30

T8

9747

T15

115

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	693120	1			T1	1		T2	476		T4	1
auto[524288:1048575]	449212	1			T8	1035		T17	3168		T19	2823
auto[1048576:1572863]	369335	1			T2	431		T8	5689		T17	1
auto[1572864:2097151]	396141	1			T5	1		T8	37		T17	537
auto[2097152:2621439]	399243	1			T8	404		T17	2822		T18	516
auto[2621440:3145727]	433513	1			T8	533		T17	772		T18	550
auto[3145728:3670015]	354627	1			T2	134		T8	2		T17	3711
auto[3670016:4194303]	347270	1			T2	227		T8	262		T17	3065

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2619007

1

T1

1

T2

234

T4

1

auto[1]

823454

1

T2

1034

T7

2

T8

4

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2921961

1

T1

1

T2

1268

T4

1

auto[1]

520500

1

T8

3771

T17

4935

T18

259

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	152960	1			T1	1		T2	476		T4	1
auto[0]	auto[0]	auto[0:524287]	auto[1]	442169	1			T7	2		T8	1846		T15	4
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	104778	1			T8	1		T17	4		T19	2823
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	272205	1			T17	2186		T21	9285		T46	389
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	97466	1			T2	431		T8	11		T18	2
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	209334	1			T8	2939		T21	2		T37	3538
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	108466	1			T5	1		T8	11		T17	5
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	228898	1			T8	13		T17	520		T18	2224
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	116787	1			T8	9		T17	11		T18	4
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	221929	1			T8	394		T17	2277		T18	512
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	118112	1			T8	7		T17	2		T18	8
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	246745	1			T8	515		T17	256		T18	260
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	83261	1			T2	134		T8	1		T17	2
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	212149	1			T17	777		T18	515		T21	2270
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	62057	1			T2	227		T8	3		T17	10
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	213455	1			T8	256		T17	2981		T18	512
auto[0]	auto[1]	auto[0:524287]	auto[0]	6261	1			T18	2		T21	8		T37	4
auto[0]	auto[1]	auto[0:524287]	auto[1]	86322	1			T21	257		T37	257		T46	2853
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	2686	1			T8	2		T17	2		T46	22
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	65744	1			T8	1032		T17	969		T21	256
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	708	1			T8	4		T17	1		T36	11
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	58122	1			T8	2716		T52	6		T22	1893
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	937	1			T17	2		T52	1		T22	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	54028	1			T21	256		T52	257		T22	384
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	589	1			T8	1		T17	3		T21	3
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	54119	1			T17	512		T21	819		T22	3
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	756	1			T17	2		T18	1		T36	5
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	62323	1			T17	512		T18	256		T36	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	1390	1			T8	1		T17	6		T21	2
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	53342	1			T17	2926		T21	257		T52	1
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	1276	1			T8	3		T37	4		T46	8
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	66426	1			T37	135		T22	5224		T51	1169
auto[1]	auto[0]	auto[0:524287]	auto[0]	546	1			T7	2		T15	4		T37	2
auto[1]	auto[0]	auto[0:524287]	auto[1]	4393	1			T7	28		T15	111		T37	13
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	439	1			T17	2		T21	1		T46	3
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	2352	1			T17	5		T52	16		T22	3
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	496	1			T8	3		T36	3		T46	6
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2587	1			T8	4		T52	2		T22	6
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	377	1			T8	1		T17	3		T21	2
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	2789	1			T8	12		T17	7		T37	8
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	465	1			T17	3		T36	9		T21	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	4672	1			T17	16		T21	5		T37	15
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	503	1			T8	2		T18	4		T21	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	3988	1			T8	9		T18	21		T37	51
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	432	1			T36	7		T21	1		T52	2
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	3552	1			T36	236		T21	1		T52	30
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	460	1			T17	6		T21	1		T37	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	3139	1			T17	68		T37	7		T46	4
auto[1]	auto[1]	auto[0:524287]	auto[0]	74	1			T21	1		T37	1		T52	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	395	1			T21	2		T37	5		T52	5
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	103	1			T46	3		T66	2		T165	3
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	905	1			T66	9		T165	31		T179	34
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	80	1			T8	1		T52	3		T22	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	542	1			T8	11		T52	22		T22	30
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	84	1			T52	1		T27	1		T99	3
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	562	1			T52	22		T27	2		T182	14
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	92	1			T27	1		T98	3		T99	5
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	590	1			T27	2		T98	8		T141	3
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	111	1			T36	8		T22	2		T66	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	975	1			T36	188		T22	5		T182	28
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	108	1			T21	1		T52	1		T22	2
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	393	1			T52	27		T22	24		T183	2
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	76	1			T37	2		T46	3		T22	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	381	1			T37	37		T22	22		T165	6

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	2077496	1			T1	1		T2	234		T4	1
auto[0]	auto[0]	auto[1]	813275	1			T2	1034		T8	2		T15	2
auto[0]	auto[1]	auto[0]	505635	1			T8	3759		T17	4935		T18	259
auto[0]	auto[1]	auto[1]	9394	1			T37	1		T52	4		T22	1
auto[1]	auto[0]	auto[0]	30536	1			T7	28		T8	30		T15	115
auto[1]	auto[0]	auto[1]	654	1			T7	2		T8	1		T17	9
auto[1]	auto[1]	auto[0]	5340	1			T8	11		T36	194		T21	4
auto[1]	auto[1]	auto[1]	131	1			T8	1		T36	2		T37	1