Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2753045	1			T1	2567		T2	7		T3	1
all_pins[1]	2753045	1			T1	2567		T2	7		T3	1
all_pins[2]	2753045	1			T1	2567		T2	7		T3	1
all_pins[3]	2753045	1			T1	2567		T2	7		T3	1
all_pins[4]	2753045	1			T1	2567		T2	7		T3	1
all_pins[5]	2753045	1			T1	2567		T2	7		T3	1
all_pins[6]	2753045	1			T1	2567		T2	7		T3	1
all_pins[7]	2753045	1			T1	2567		T2	7		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	21993445	1			T1	20536		T2	56		T3	8
values[0x1]	30915	1			T8	8		T16	21		T21	20
transitions[0x0=>0x1]	29459	1			T8	8		T16	18		T21	16
transitions[0x1=>0x0]	29467	1			T8	8		T16	18		T21	16

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2751837	1			T1	2567		T2	7		T3	1
all_pins[0]	values[0x1]	1208	1			T8	3		T16	5		T21	2
all_pins[0]	transitions[0x0=>0x1]	870	1			T8	3		T16	5		T21	2
all_pins[0]	transitions[0x1=>0x0]	274	1			T16	4		T21	1		T22	2
all_pins[1]	values[0x0]	2752433	1			T1	2567		T2	7		T3	1
all_pins[1]	values[0x1]	612	1			T16	4		T21	1		T22	3
all_pins[1]	transitions[0x0=>0x1]	528	1			T16	4		T21	1		T22	1
all_pins[1]	transitions[0x1=>0x0]	171	1			T8	1		T16	2		T21	5
all_pins[2]	values[0x0]	2752790	1			T1	2567		T2	7		T3	1
all_pins[2]	values[0x1]	255	1			T8	1		T16	2		T21	5
all_pins[2]	transitions[0x0=>0x1]	200	1			T8	1		T16	2		T21	4
all_pins[2]	transitions[0x1=>0x0]	154	1			T8	3		T21	1		T22	6
all_pins[3]	values[0x0]	2752836	1			T1	2567		T2	7		T3	1
all_pins[3]	values[0x1]	209	1			T8	3		T21	2		T22	10
all_pins[3]	transitions[0x0=>0x1]	153	1			T8	3		T21	2		T22	5
all_pins[3]	transitions[0x1=>0x0]	169	1			T16	2		T21	1		T22	3
all_pins[4]	values[0x0]	2752820	1			T1	2567		T2	7		T3	1
all_pins[4]	values[0x1]	225	1			T16	2		T21	1		T22	8
all_pins[4]	transitions[0x0=>0x1]	178	1			T16	2		T21	1		T22	8
all_pins[4]	transitions[0x1=>0x0]	1006	1			T16	2		T22	2		T27	2
all_pins[5]	values[0x0]	2751992	1			T1	2567		T2	7		T3	1
all_pins[5]	values[0x1]	1053	1			T16	2		T22	2		T27	2
all_pins[5]	transitions[0x0=>0x1]	282	1			T16	1		T22	2		T27	2
all_pins[5]	transitions[0x1=>0x0]	26364	1			T8	1		T21	3		T22	4
all_pins[6]	values[0x0]	2725910	1			T1	2567		T2	7		T3	1
all_pins[6]	values[0x1]	27135	1			T8	1		T16	1		T21	3
all_pins[6]	transitions[0x0=>0x1]	27086	1			T8	1		T16	1		T21	1
all_pins[6]	transitions[0x1=>0x0]	169	1			T16	5		T21	4		T22	5
all_pins[7]	values[0x0]	2752827	1			T1	2567		T2	7		T3	1
all_pins[7]	values[0x1]	218	1			T16	5		T21	6		T22	5
all_pins[7]	transitions[0x0=>0x1]	162	1			T16	3		T21	5		T22	3
all_pins[7]	transitions[0x1=>0x0]	1160	1			T8	3		T16	3		T21	1