Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17906

1

T7

34

T15

129

T18

75

auto[1]

13298

1

T4

2

T13

20

T18

30

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3852	1			T20	6		T37	71		T47	12
values[1]	4075	1			T18	45		T101	2		T21	67
values[2]	4033	1			T21	20		T46	20		T27	87
values[3]	4518	1			T13	20		T15	129		T18	40
values[4]	3605	1			T21	62		T37	67		T46	20
values[5]	3649	1			T21	20		T37	24		T46	20
values[6]	4150	1			T7	34		T21	42		T37	69
values[7]	3322	1			T4	2		T18	20		T21	20

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3750	1			T21	21		T37	51		T192	10
values[1]	4076	1			T15	129		T18	20		T21	42
values[2]	3843	1			T4	2		T13	20		T101	2
values[3]	3711	1			T18	40		T21	66		T37	53
values[4]	3918	1			T20	6		T21	63		T37	46
values[5]	4152	1			T18	45		T37	93		T47	12
values[6]	3445	1			T7	34		T21	22		T46	20
values[7]	4309	1			T21	43		T37	40		T46	60

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	230	1			T37	48		T179	12		T176	9
auto[0]	values[0]	values[1]	334	1			T37	11		T224	6		T227	2
auto[0]	values[0]	values[2]	211	1			T46	12		T27	8		T225	16
auto[0]	values[0]	values[3]	306	1			T141	13		T177	13		T184	26
auto[0]	values[0]	values[4]	298	1			T20	6		T27	74		T44	28
auto[0]	values[0]	values[5]	310	1			T38	16		T219	12		T228	17
auto[0]	values[0]	values[6]	214	1			T38	11		T45	14		T141	10
auto[0]	values[0]	values[7]	285	1			T38	7		T45	10		T179	18
auto[0]	values[1]	values[0]	345	1			T208	8		T180	112		T188	36
auto[0]	values[1]	values[1]	334	1			T46	14		T229	12		T188	21
auto[0]	values[1]	values[2]	202	1			T178	6		T172	12		T226	8
auto[0]	values[1]	values[3]	273	1			T21	31		T37	12		T133	41
auto[0]	values[1]	values[4]	345	1			T21	8		T27	124		T45	9
auto[0]	values[1]	values[5]	352	1			T18	41		T46	12		T49	7
auto[0]	values[1]	values[6]	299	1			T45	10		T133	10		T179	30
auto[0]	values[1]	values[7]	257	1			T46	2		T38	13		T133	23
auto[0]	values[2]	values[0]	331	1			T178	26		T133	11		T190	13
auto[0]	values[2]	values[1]	282	1			T87	8		T230	12		T231	4
auto[0]	values[2]	values[2]	293	1			T27	12		T232	12		T87	15
auto[0]	values[2]	values[3]	398	1			T180	101		T191	10		T193	11
auto[0]	values[2]	values[4]	389	1			T49	9		T87	11		T133	11
auto[0]	values[2]	values[5]	243	1			T87	47		T179	8		T94	12
auto[0]	values[2]	values[6]	200	1			T133	19		T177	7		T193	17
auto[0]	values[2]	values[7]	271	1			T21	13		T46	7		T27	56
auto[0]	values[3]	values[0]	259	1			T21	7		T27	14		T38	11
auto[0]	values[3]	values[1]	500	1			T15	129		T18	13		T38	18
auto[0]	values[3]	values[2]	254	1			T181	12		T210	14		T220	12
auto[0]	values[3]	values[3]	304	1			T18	9		T206	4		T172	12
auto[0]	values[3]	values[4]	176	1			T21	9		T37	16		T194	29
auto[0]	values[3]	values[5]	366	1			T37	7		T46	11		T45	10
auto[0]	values[3]	values[6]	246	1			T49	16		T178	13		T181	9
auto[0]	values[3]	values[7]	565	1			T21	15		T27	26		T190	10
auto[0]	values[4]	values[0]	186	1			T27	12		T178	14		T141	12
auto[0]	values[4]	values[1]	235	1			T21	13		T37	16		T49	11
auto[0]	values[4]	values[2]	191	1			T21	23		T87	5		T141	14
auto[0]	values[4]	values[3]	272	1			T179	11		T210	13		T233	14
auto[0]	values[4]	values[4]	370	1			T27	2		T32	13		T177	6
auto[0]	values[4]	values[5]	345	1			T46	8		T27	15		T87	10
auto[0]	values[4]	values[6]	219	1			T49	13		T194	15		T204	19
auto[0]	values[4]	values[7]	260	1			T140	22		T195	22		T177	13
auto[0]	values[5]	values[0]	192	1			T87	9		T32	16		T188	28
auto[0]	values[5]	values[1]	165	1			T38	15		T49	10		T179	15
auto[0]	values[5]	values[2]	326	1			T45	15		T87	42		T234	4
auto[0]	values[5]	values[3]	263	1			T235	8		T141	12		T176	14
auto[0]	values[5]	values[4]	246	1			T21	7		T27	24		T141	45
auto[0]	values[5]	values[5]	292	1			T37	12		T178	8		T141	9
auto[0]	values[5]	values[6]	215	1			T49	10		T178	11		T208	7
auto[0]	values[5]	values[7]	295	1			T46	13		T27	11		T236	4
auto[0]	values[6]	values[0]	350	1			T45	20		T178	16		T141	11
auto[0]	values[6]	values[1]	220	1			T21	13		T179	11		T181	13
auto[0]	values[6]	values[2]	238	1			T172	13		T193	15		T226	14
auto[0]	values[6]	values[3]	280	1			T46	17		T178	13		T181	13
auto[0]	values[6]	values[4]	210	1			T37	4		T237	2		T45	1
auto[0]	values[6]	values[5]	330	1			T37	5		T179	63		T238	2
auto[0]	values[6]	values[6]	257	1			T7	34		T21	12		T239	4
auto[0]	values[6]	values[7]	289	1			T27	26		T178	10		T141	9
auto[0]	values[7]	values[0]	200	1			T192	10		T27	11		T133	89
auto[0]	values[7]	values[1]	308	1			T38	14		T45	10		T87	15
auto[0]	values[7]	values[2]	222	1			T49	12		T141	12		T179	11
auto[0]	values[7]	values[3]	224	1			T18	12		T21	12		T27	29
auto[0]	values[7]	values[4]	292	1			T184	11		T240	14		T241	11
auto[0]	values[7]	values[5]	254	1			T242	22		T172	12		T186	24
auto[0]	values[7]	values[6]	229	1			T46	13		T87	12		T177	33
auto[0]	values[7]	values[7]	259	1			T37	20		T27	14		T38	8
auto[1]	values[0]	values[0]	121	1			T37	3		T179	22		T176	11
auto[1]	values[0]	values[1]	183	1			T37	9		T243	8		T160	5
auto[1]	values[0]	values[2]	270	1			T46	8		T27	12		T172	7
auto[1]	values[0]	values[3]	184	1			T141	9		T177	13		T184	10
auto[1]	values[0]	values[4]	135	1			T27	10		T87	8		T218	6
auto[1]	values[0]	values[5]	291	1			T47	12		T38	4		T219	8
auto[1]	values[0]	values[6]	282	1			T38	9		T45	6		T141	10
auto[1]	values[0]	values[7]	198	1			T38	13		T45	10		T179	2
auto[1]	values[1]	values[0]	355	1			T208	12		T180	9		T188	7
auto[1]	values[1]	values[1]	124	1			T46	6		T188	7		T193	11
auto[1]	values[1]	values[2]	114	1			T101	2		T178	14		T172	8
auto[1]	values[1]	values[3]	200	1			T21	15		T37	41		T133	6
auto[1]	values[1]	values[4]	229	1			T21	13		T27	25		T215	26
auto[1]	values[1]	values[5]	221	1			T18	4		T46	8		T49	13
auto[1]	values[1]	values[6]	175	1			T45	10		T133	14		T179	12
auto[1]	values[1]	values[7]	250	1			T46	18		T38	7		T133	17
auto[1]	values[2]	values[0]	221	1			T178	8		T133	35		T190	7
auto[1]	values[2]	values[1]	116	1			T87	12		T223	18		T188	7
auto[1]	values[2]	values[2]	275	1			T27	8		T87	5		T180	9
auto[1]	values[2]	values[3]	174	1			T100	22		T244	12		T180	8
auto[1]	values[2]	values[4]	366	1			T49	11		T87	17		T133	9
auto[1]	values[2]	values[5]	123	1			T87	13		T179	12		T208	1
auto[1]	values[2]	values[6]	220	1			T133	12		T177	13		T207	18
auto[1]	values[2]	values[7]	131	1			T21	7		T46	13		T27	11
auto[1]	values[3]	values[0]	343	1			T21	14		T27	6		T38	9
auto[1]	values[3]	values[1]	266	1			T18	7		T38	2		T133	30
auto[1]	values[3]	values[2]	269	1			T13	20		T181	8		T210	11
auto[1]	values[3]	values[3]	123	1			T18	11		T172	8		T219	11
auto[1]	values[3]	values[4]	206	1			T21	13		T37	10		T194	21
auto[1]	values[3]	values[5]	158	1			T37	13		T46	9		T45	10
auto[1]	values[3]	values[6]	155	1			T49	4		T178	7		T181	11
auto[1]	values[3]	values[7]	328	1			T21	8		T27	13		T190	10
auto[1]	values[4]	values[0]	208	1			T27	8		T178	6		T141	21
auto[1]	values[4]	values[1]	228	1			T21	9		T37	51		T49	9
auto[1]	values[4]	values[2]	186	1			T21	17		T87	54		T141	7
auto[1]	values[4]	values[3]	158	1			T179	10		T210	7		T245	9
auto[1]	values[4]	values[4]	240	1			T27	24		T201	8		T32	17
auto[1]	values[4]	values[5]	190	1			T46	12		T27	5		T87	10
auto[1]	values[4]	values[6]	209	1			T49	7		T194	7		T204	9
auto[1]	values[4]	values[7]	108	1			T177	8		T188	7		T185	10
auto[1]	values[5]	values[0]	139	1			T87	11		T32	5		T188	12
auto[1]	values[5]	values[1]	214	1			T38	5		T49	10		T179	10
auto[1]	values[5]	values[2]	350	1			T45	5		T87	11		T184	10
auto[1]	values[5]	values[3]	195	1			T141	10		T176	6		T221	15
auto[1]	values[5]	values[4]	126	1			T21	13		T27	28		T141	4
auto[1]	values[5]	values[5]	308	1			T37	12		T178	12		T137	10
auto[1]	values[5]	values[6]	133	1			T49	10		T178	16		T208	13
auto[1]	values[5]	values[7]	190	1			T46	7		T27	13		T133	14
auto[1]	values[6]	values[0]	207	1			T45	20		T178	11		T141	14
auto[1]	values[6]	values[1]	250	1			T21	7		T179	9		T181	7
auto[1]	values[6]	values[2]	296	1			T134	20		T172	7		T193	11
auto[1]	values[6]	values[3]	170	1			T46	23		T48	24		T178	7
auto[1]	values[6]	values[4]	171	1			T37	16		T45	19		T190	9
auto[1]	values[6]	values[5]	247	1			T37	44		T179	8		T177	8
auto[1]	values[6]	values[6]	201	1			T21	10		T141	7		T181	9
auto[1]	values[6]	values[7]	434	1			T27	14		T178	10		T141	11
auto[1]	values[7]	values[0]	63	1			T27	25		T133	5		T246	8
auto[1]	values[7]	values[1]	317	1			T38	6		T45	10		T87	58
auto[1]	values[7]	values[2]	146	1			T4	2		T49	8		T141	8
auto[1]	values[7]	values[3]	187	1			T18	8		T21	8		T27	14
auto[1]	values[7]	values[4]	119	1			T184	12		T241	9		T247	11
auto[1]	values[7]	values[5]	122	1			T172	8		T184	5		T248	12
auto[1]	values[7]	values[6]	191	1			T46	7		T87	8		T177	11
auto[1]	values[7]	values[7]	189	1			T37	20		T27	47		T38	12