Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	409	1			T18	1		T21	4		T37	2
auto[ReadAddrCrossIntoMailbox]	316	1			T18	1		T21	4		T37	2
auto[ReadAddrCrossOutOfMailbox]	315	1			T18	2		T21	5		T37	3
auto[ReadAddrCrossAllMailbox]	253	1			T18	3		T21	4		T37	1
auto[ReadAddrOutsideMailbox]	3688	1			T13	2		T15	2		T18	10

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2459

1

T13

1

T15

1

T18

8

auto[1]

2522

1

T13

1

T15

1

T18

9

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	763	1			T13	2		T18	1		T21	7
read_ops[0x0b]	844	1			T18	4		T20	6		T21	14
read_ops[0x3b]	855	1			T18	1		T21	11		T37	8
read_ops[0x6b]	857	1			T15	2		T18	5		T21	14
read_ops[0xbb]	830	1			T18	5		T21	7		T37	5
read_ops[0xeb]	832	1			T18	1		T21	13		T37	9

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	34	1			T27	1		T172	2		T208	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	32	1			T46	1		T45	1		T133	2
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	17	1			T46	1		T49	1		T179	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	30	1			T46	2		T27	1		T45	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	21	1			T181	1		T191	1		T245	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	26	1			T37	1		T46	1		T27	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T38	1		T141	1		T172	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T46	1		T49	1		T172	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	294	1			T13	1		T21	3		T37	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	276	1			T13	1		T18	1		T21	4
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	29	1			T222	2		T187	1		T194	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	39	1			T21	2		T46	2		T38	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	21	1			T38	1		T141	1		T179	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	36	1			T21	2		T178	2		T172	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	20	1			T188	1		T245	2		T249	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	21	1			T18	1		T37	1		T141	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	23	1			T27	1		T210	1		T184	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	22	1			T18	1		T21	2		T141	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	324	1			T18	1		T20	3		T21	2
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	309	1			T18	1		T20	3		T21	6
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	39	1			T21	1		T27	1		T49	2
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	28	1			T37	1		T218	1		T184	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	26	1			T46	1		T27	1		T38	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	32	1			T46	1		T27	1		T87	5
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	28	1			T21	1		T46	1		T49	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	23	1			T21	1		T46	1		T27	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T21	1		T38	1		T208	3
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	20	1			T37	1		T172	1		T177	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	332	1			T21	5		T37	4		T46	7
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	311	1			T18	1		T21	2		T37	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	29	1			T21	1		T222	1		T87	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	39	1			T38	1		T45	1		T222	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	24	1			T37	1		T141	1		T179	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	33	1			T45	1		T178	1		T210	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T37	1		T38	1		T141	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	29	1			T18	1		T21	1		T46	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T46	2		T250	1		T229	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	32	1			T21	1		T46	1		T27	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	317	1			T15	1		T18	3		T21	8
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	312	1			T15	1		T18	1		T21	3
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	36	1			T222	1		T179	1		T172	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	31	1			T222	1		T178	1		T220	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	23	1			T18	1		T87	1		T179	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	23	1			T21	1		T27	1		T181	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	35	1			T21	1		T179	1		T172	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	35	1			T27	1		T49	2		T178	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	23	1			T18	2		T38	1		T172	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	20	1			T45	1		T172	1		T208	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	283	1			T21	1		T37	2		T47	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	321	1			T18	2		T21	4		T37	3
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	40	1			T18	1		T46	1		T27	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	33	1			T37	1		T38	1		T49	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	26	1			T27	1		T49	1		T178	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	25	1			T21	1		T37	1		T46	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	27	1			T172	1		T210	1		T229	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	27	1			T21	1		T46	1		T38	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	21	1			T38	1		T178	1		T177	2
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	24	1			T46	1		T38	2		T45	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	292	1			T21	5		T37	2		T46	5
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	317	1			T21	6		T37	5		T192	1