Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4046	1			T18	20		T21	64		T37	40
values[1]	3354	1			T4	2		T7	34		T37	104
values[2]	4422	1			T18	45		T21	42		T37	87
values[3]	4065	1			T21	81		T37	20		T46	40
values[4]	3903	1			T15	129		T18	20		T20	6
values[5]	3998	1			T37	24		T27	81		T239	4
values[6]	3241	1			T18	20		T21	23		T37	95
values[7]	4175	1			T13	20		T101	2		T21	41

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3126	1			T21	42		T37	24		T27	40
values[1]	4842	1			T18	20		T20	6		T37	120
values[2]	3548	1			T21	22		T37	46		T27	125
values[3]	4649	1			T4	2		T15	129		T18	20
values[4]	4086	1			T21	40		T37	71		T47	12
values[5]	3390	1			T21	21		T37	20		T192	10
values[6]	3654	1			T7	34		T13	20		T18	20
values[7]	3909	1			T18	45		T21	87		T37	20

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30430

1

T7

34

T13

20

T15

129

auto[1]

774

1

T4

2

T18

2

T21

7

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	366	1			T181	20		T210	20		T184	23
auto[0]	values[0]	values[1]	436	1			T49	20		T180	90		T223	18
auto[0]	values[0]	values[2]	746	1			T21	21		T37	20		T179	21
auto[0]	values[0]	values[3]	574	1			T21	21		T46	19		T236	4
auto[0]	values[0]	values[4]	325	1			T46	20		T181	20		T210	20
auto[0]	values[0]	values[5]	650	1			T27	124		T133	24		T179	20
auto[0]	values[0]	values[6]	436	1			T18	20		T37	20		T46	18
auto[0]	values[0]	values[7]	437	1			T21	20		T27	20		T87	58
auto[0]	values[1]	values[0]	375	1			T232	12		T141	19		T177	20
auto[0]	values[1]	values[1]	654	1			T37	53		T238	2		T172	40
auto[0]	values[1]	values[2]	213	1			T45	16		T251	10		T190	20
auto[0]	values[1]	values[3]	451	1			T46	20		T27	20		T172	18
auto[0]	values[1]	values[4]	398	1			T37	50		T87	56		T179	19
auto[0]	values[1]	values[5]	286	1			T49	20		T178	20		T133	28
auto[0]	values[1]	values[6]	517	1			T7	34		T190	20		T172	20
auto[0]	values[1]	values[7]	354	1			T27	40		T178	20		T133	46
auto[0]	values[2]	values[0]	433	1			T21	21		T27	40		T179	55
auto[0]	values[2]	values[1]	677	1			T37	65		T87	20		T172	20
auto[0]	values[2]	values[2]	386	1			T184	60		T252	20		T228	19
auto[0]	values[2]	values[3]	569	1			T38	20		T242	22		T141	20
auto[0]	values[2]	values[4]	708	1			T47	10		T27	84		T210	25
auto[0]	values[2]	values[5]	455	1			T206	4		T225	16		T179	19
auto[0]	values[2]	values[6]	570	1			T21	20		T87	22		T141	24
auto[0]	values[2]	values[7]	520	1			T18	43		T37	20		T46	20
auto[0]	values[3]	values[0]	407	1			T38	19		T181	20		T208	20
auto[0]	values[3]	values[1]	644	1			T38	19		T133	66		T179	59
auto[0]	values[3]	values[2]	302	1			T27	22		T49	20		T83	8
auto[0]	values[3]	values[3]	505	1			T21	20		T46	20		T27	38
auto[0]	values[3]	values[4]	660	1			T21	20		T37	18		T46	20
auto[0]	values[3]	values[5]	427	1			T21	21		T48	22		T44	28
auto[0]	values[3]	values[6]	387	1			T87	50		T179	18		T208	20
auto[0]	values[3]	values[7]	624	1			T21	20		T237	2		T133	31
auto[0]	values[4]	values[0]	306	1			T224	6		T134	20		T219	20
auto[0]	values[4]	values[1]	433	1			T20	6		T46	19		T178	26
auto[0]	values[4]	values[2]	620	1			T27	20		T87	72		T234	4
auto[0]	values[4]	values[3]	750	1			T15	129		T18	20		T46	40
auto[0]	values[4]	values[4]	464	1			T21	20		T137	6		T172	20
auto[0]	values[4]	values[5]	377	1			T27	20		T32	20		T177	26
auto[0]	values[4]	values[6]	496	1			T100	22		T214	12		T193	24
auto[0]	values[4]	values[7]	369	1			T21	25		T133	20		T179	69
auto[0]	values[5]	values[0]	402	1			T37	23		T87	27		T133	38
auto[0]	values[5]	values[1]	661	1			T45	19		T141	25		T181	19
auto[0]	values[5]	values[2]	535	1			T27	20		T87	18		T210	20
auto[0]	values[5]	values[3]	570	1			T208	20		T253	16		T254	4
auto[0]	values[5]	values[4]	404	1			T38	40		T141	19		T190	20
auto[0]	values[5]	values[5]	386	1			T27	61		T239	4		T222	12
auto[0]	values[5]	values[6]	369	1			T38	17		T172	20		T177	22
auto[0]	values[5]	values[7]	582	1			T87	20		T179	23		T174	18
auto[0]	values[6]	values[0]	299	1			T227	2		T177	42		T194	22
auto[0]	values[6]	values[1]	671	1			T18	20		T27	44		T178	20
auto[0]	values[6]	values[2]	206	1			T37	26		T178	20		T190	20
auto[0]	values[6]	values[3]	517	1			T21	22		T37	47		T46	18
auto[0]	values[6]	values[4]	255	1			T45	18		T172	20		T195	22
auto[0]	values[6]	values[5]	311	1			T37	20		T192	10		T49	15
auto[0]	values[6]	values[6]	351	1			T49	38		T141	53		T219	47
auto[0]	values[6]	values[7]	532	1			T27	66		T45	39		T87	18
auto[0]	values[7]	values[0]	473	1			T21	18		T215	26		T141	23
auto[0]	values[7]	values[1]	545	1			T38	20		T87	51		T178	27
auto[0]	values[7]	values[2]	476	1			T27	62		T178	19		T208	98
auto[0]	values[7]	values[3]	607	1			T45	18		T210	43		T208	84
auto[0]	values[7]	values[4]	748	1			T177	42		T194	42		T184	21
auto[0]	values[7]	values[5]	402	1			T38	17		T201	6		T244	8
auto[0]	values[7]	values[6]	438	1			T13	20		T101	2		T178	18
auto[0]	values[7]	values[7]	383	1			T21	21		T49	20		T219	20
auto[1]	values[0]	values[0]	7	1			T184	3		T164	2		T255	2
auto[1]	values[0]	values[1]	4	1			T34	1		T256	2		T97	1
auto[1]	values[0]	values[2]	11	1			T21	1		T34	1		T54	1
auto[1]	values[0]	values[3]	16	1			T21	1		T46	1		T193	3
auto[1]	values[0]	values[4]	1	1			T208	1		-	-		-	-
auto[1]	values[0]	values[5]	15	1			T27	4		T208	2		T245	1
auto[1]	values[0]	values[6]	10	1			T46	2		T45	3		T199	1
auto[1]	values[0]	values[7]	12	1			T27	1		T87	2		T177	3
auto[1]	values[1]	values[0]	15	1			T141	1		T221	3		T203	4
auto[1]	values[1]	values[1]	19	1			T177	2		T252	1		T257	1
auto[1]	values[1]	values[2]	4	1			T45	4		-	-		-	-
auto[1]	values[1]	values[3]	13	1			T4	2		T172	2		T184	1
auto[1]	values[1]	values[4]	19	1			T37	1		T87	3		T179	1
auto[1]	values[1]	values[5]	10	1			T133	2		T54	1		T258	4
auto[1]	values[1]	values[6]	22	1			T193	2		T158	1		T245	3
auto[1]	values[1]	values[7]	4	1			T158	1		T259	1		T258	1
auto[1]	values[2]	values[0]	11	1			T21	1		T172	1		T177	1
auto[1]	values[2]	values[1]	12	1			T37	2		T184	1		T260	2
auto[1]	values[2]	values[2]	14	1			T184	2		T228	1		T261	1
auto[1]	values[2]	values[3]	9	1			T187	2		T180	1		T249	1
auto[1]	values[2]	values[4]	15	1			T47	2		T205	1		T180	2
auto[1]	values[2]	values[5]	12	1			T179	1		T241	1		T243	1
auto[1]	values[2]	values[6]	12	1			T87	1		T180	2		T185	1
auto[1]	values[2]	values[7]	19	1			T18	2		T45	2		T178	3
auto[1]	values[3]	values[0]	4	1			T38	1		T262	1		T263	2
auto[1]	values[3]	values[1]	19	1			T38	1		T133	1		T190	2
auto[1]	values[3]	values[2]	5	1			T27	1		T53	1		T264	1
auto[1]	values[3]	values[3]	23	1			T27	1		T38	3		T208	2
auto[1]	values[3]	values[4]	11	1			T37	2		T133	2		T241	1
auto[1]	values[3]	values[5]	13	1			T48	2		T141	2		T203	2
auto[1]	values[3]	values[6]	12	1			T179	2		T180	3		T252	1
auto[1]	values[3]	values[7]	22	1			T181	1		T32	5		T177	3
auto[1]	values[4]	values[0]	3	1			T265	1		T266	2		-	-
auto[1]	values[4]	values[1]	16	1			T46	1		T178	1		T32	3
auto[1]	values[4]	values[2]	9	1			T87	1		T172	1		T245	1
auto[1]	values[4]	values[3]	13	1			T54	1		T267	1		T266	4
auto[1]	values[4]	values[4]	17	1			T137	4		T187	1		T249	1
auto[1]	values[4]	values[5]	9	1			T268	6		T269	2		T270	1
auto[1]	values[4]	values[6]	10	1			T228	1		T158	1		T271	2
auto[1]	values[4]	values[7]	11	1			T21	1		T179	2		T218	1
auto[1]	values[5]	values[0]	8	1			T37	1		T87	1		T208	2
auto[1]	values[5]	values[1]	18	1			T45	1		T181	1		T177	3
auto[1]	values[5]	values[2]	9	1			T87	2		T188	2		T272	1
auto[1]	values[5]	values[3]	8	1			T54	1		T259	1		T273	1
auto[1]	values[5]	values[4]	19	1			T141	1		T248	4		T193	2
auto[1]	values[5]	values[5]	13	1			T228	1		T274	1		T163	2
auto[1]	values[5]	values[6]	5	1			T38	3		T185	2		-	-
auto[1]	values[5]	values[7]	9	1			T275	2		T34	1		T255	2
auto[1]	values[6]	values[0]	10	1			T177	3		T243	4		T273	1
auto[1]	values[6]	values[1]	10	1			T205	2		T187	1		T184	1
auto[1]	values[6]	values[2]	5	1			T226	1		T265	2		T258	1
auto[1]	values[6]	values[3]	20	1			T21	1		T37	2		T46	2
auto[1]	values[6]	values[4]	17	1			T45	2		T185	2		T276	6
auto[1]	values[6]	values[5]	9	1			T49	5		T203	1		T34	1
auto[1]	values[6]	values[6]	11	1			T49	2		T141	2		T219	3
auto[1]	values[6]	values[7]	17	1			T27	1		T45	1		T87	2
auto[1]	values[7]	values[0]	7	1			T21	2		T141	2		T177	2
auto[1]	values[7]	values[1]	23	1			T87	2		T249	2		T243	2
auto[1]	values[7]	values[2]	7	1			T178	1		T188	1		T226	2
auto[1]	values[7]	values[3]	4	1			T45	2		T161	1		T270	1
auto[1]	values[7]	values[4]	25	1			T194	4		T184	2		T204	2
auto[1]	values[7]	values[5]	15	1			T38	3		T201	2		T244	4
auto[1]	values[7]	values[6]	8	1			T178	2		T141	1		T208	2
auto[1]	values[7]	values[7]	14	1			T184	1		T271	2		T277	1