Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	867	1			T8	4		T16	14		T21	10
all_values[1]	867	1			T8	4		T16	14		T21	10
all_values[2]	867	1			T8	4		T16	14		T21	10
all_values[3]	867	1			T8	4		T16	14		T21	10
all_values[4]	867	1			T8	4		T16	14		T21	10
all_values[5]	867	1			T8	4		T16	14		T21	10
all_values[6]	867	1			T8	4		T16	14		T21	10
all_values[7]	867	1			T8	4		T16	14		T21	10

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3630

1

T8

23

T16

67

T21

42

auto[1]

3306

1

T8

9

T16

45

T21

38

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2689

1

T8

11

T16

53

T21

33

auto[1]

4247

1

T8

21

T16

59

T21

47

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3851

1

T8

22

T16

71

T21

46

auto[1]

3085

1

T8

10

T16

41

T21

34

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	184	1			T16	4		T21	4		T22	3
all_values[0]	auto[0]	auto[0]	auto[1]	64	1			T16	1		T22	1		T27	1
all_values[0]	auto[0]	auto[1]	auto[0]	142	1			T16	3		T21	1		T22	2
all_values[0]	auto[0]	auto[1]	auto[1]	90	1			T8	3		T16	1		T21	1
all_values[0]	auto[1]	auto[0]	auto[1]	196	1			T8	1		T16	2		T21	1
all_values[0]	auto[1]	auto[1]	auto[1]	191	1			T16	3		T21	3		T22	6
all_values[1]	auto[0]	auto[0]	auto[0]	178	1			T8	1		T21	4		T22	7
all_values[1]	auto[0]	auto[0]	auto[1]	70	1			T8	1		T16	3		T27	1
all_values[1]	auto[0]	auto[1]	auto[0]	135	1			T8	1		T21	4		T22	4
all_values[1]	auto[0]	auto[1]	auto[1]	98	1			T16	2		T21	1		T22	1
all_values[1]	auto[1]	auto[0]	auto[1]	210	1			T8	1		T16	8		T21	1
all_values[1]	auto[1]	auto[1]	auto[1]	176	1			T16	1		T22	3		T28	6
all_values[2]	auto[0]	auto[0]	auto[0]	178	1			T16	4		T21	1		T22	5
all_values[2]	auto[0]	auto[0]	auto[1]	64	1			T8	1		T16	1		T21	1
all_values[2]	auto[0]	auto[1]	auto[0]	145	1			T16	3		T21	1		T22	2
all_values[2]	auto[0]	auto[1]	auto[1]	102	1			T8	1		T16	1		T21	3
all_values[2]	auto[1]	auto[0]	auto[1]	184	1			T8	2		T16	1		T21	2
all_values[2]	auto[1]	auto[1]	auto[1]	194	1			T16	4		T21	2		T22	4
all_values[3]	auto[0]	auto[0]	auto[0]	176	1			T16	6		T21	2		T22	5
all_values[3]	auto[0]	auto[0]	auto[1]	82	1			T16	2		T21	1		T28	3
all_values[3]	auto[0]	auto[1]	auto[0]	141	1			T16	2		T21	3		T22	2
all_values[3]	auto[0]	auto[1]	auto[1]	79	1			T8	2		T22	5		T27	2
all_values[3]	auto[1]	auto[0]	auto[1]	214	1			T8	1		T16	4		T21	2
all_values[3]	auto[1]	auto[1]	auto[1]	175	1			T8	1		T21	2		T22	6
all_values[4]	auto[0]	auto[0]	auto[0]	157	1			T8	2		T16	4		T21	1
all_values[4]	auto[0]	auto[0]	auto[1]	95	1			T8	1		T16	1		T21	2
all_values[4]	auto[0]	auto[1]	auto[0]	127	1			T16	3		T21	1		T22	4
all_values[4]	auto[0]	auto[1]	auto[1]	97	1			T16	1		T22	1		T28	3
all_values[4]	auto[1]	auto[0]	auto[1]	195	1			T8	1		T16	3		T21	4
all_values[4]	auto[1]	auto[1]	auto[1]	196	1			T16	2		T21	2		T22	9
all_values[5]	auto[0]	auto[0]	auto[0]	253	1			T8	3		T16	4		T21	5
all_values[5]	auto[0]	auto[1]	auto[0]	216	1			T16	6		T21	2		T22	4
all_values[5]	auto[1]	auto[0]	auto[1]	200	1			T8	1		T16	2		T21	3
all_values[5]	auto[1]	auto[1]	auto[1]	198	1			T16	2		T22	3		T27	2
all_values[6]	auto[0]	auto[0]	auto[0]	187	1			T8	3		T16	9		T21	1
all_values[6]	auto[0]	auto[0]	auto[1]	74	1			T22	2		T28	2		T30	2
all_values[6]	auto[0]	auto[1]	auto[0]	148	1			T16	1		T21	2		T22	1
all_values[6]	auto[0]	auto[1]	auto[1]	71	1			T16	1		T21	1		T22	1
all_values[6]	auto[1]	auto[0]	auto[1]	208	1			T16	2		T21	5		T22	7
all_values[6]	auto[1]	auto[1]	auto[1]	179	1			T8	1		T16	1		T21	1
all_values[7]	auto[0]	auto[0]	auto[0]	187	1			T8	1		T16	1		T22	5
all_values[7]	auto[0]	auto[0]	auto[1]	82	1			T8	2		T16	2		T21	1
all_values[7]	auto[0]	auto[1]	auto[0]	135	1			T16	3		T21	1		T22	3
all_values[7]	auto[0]	auto[1]	auto[1]	94	1			T16	2		T21	2		T22	3
all_values[7]	auto[1]	auto[0]	auto[1]	192	1			T8	1		T16	3		T21	1
all_values[7]	auto[1]	auto[1]	auto[1]	177	1			T16	3		T21	5		T22	5

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal