Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1760

1

T1

3

T6

5

T8

2

auto[1]

1725

1

T1

1

T6

5

T8

3

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1917

1

T1

4

T8

4

T18

4

auto[1]

1568

1

T6

10

T8

1

T14

26

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2796

1

T1

2

T6

10

T8

4

auto[1]

689

1

T1

2

T8

1

T18

1

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	719	1			T6	1		T8	1		T14	5
valid[1]	703	1			T1	2		T6	1		T8	1
valid[2]	696	1			T6	3		T14	7		T23	8
valid[3]	691	1			T1	1		T6	2		T8	3
valid[4]	676	1			T1	1		T6	3		T14	4

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	136	1			T21	1		T22	1		T51	1
auto[0]	auto[0]	valid[0]	auto[1]	171	1			T14	3		T23	7		T24	2
auto[0]	auto[0]	valid[1]	auto[0]	123	1			T1	1		T21	1		T50	1
auto[0]	auto[0]	valid[1]	auto[1]	157	1			T6	1		T14	2		T23	2
auto[0]	auto[0]	valid[2]	auto[0]	121	1			T50	1		T22	4		T297	1
auto[0]	auto[0]	valid[2]	auto[1]	152	1			T6	2		T14	3		T23	6
auto[0]	auto[0]	valid[3]	auto[0]	111	1			T21	2		T22	2		T86	2
auto[0]	auto[0]	valid[3]	auto[1]	167	1			T8	1		T14	4		T23	4
auto[0]	auto[0]	valid[4]	auto[0]	121	1			T21	1		T27	1		T183	1
auto[0]	auto[0]	valid[4]	auto[1]	135	1			T6	2		T23	7		T24	2
auto[0]	auto[1]	valid[0]	auto[0]	127	1			T8	1		T18	1		T50	2
auto[0]	auto[1]	valid[0]	auto[1]	145	1			T6	1		T14	2		T23	6
auto[0]	auto[1]	valid[1]	auto[0]	123	1			T1	1		T8	1		T21	2
auto[0]	auto[1]	valid[1]	auto[1]	167	1			T14	1		T23	2		T24	1
auto[0]	auto[1]	valid[2]	auto[0]	121	1			T51	1		T297	1		T86	1
auto[0]	auto[1]	valid[2]	auto[1]	160	1			T6	1		T14	4		T23	2
auto[0]	auto[1]	valid[3]	auto[0]	115	1			T8	1		T18	1		T21	1
auto[0]	auto[1]	valid[3]	auto[1]	162	1			T6	2		T14	3		T23	2
auto[0]	auto[1]	valid[4]	auto[0]	130	1			T18	1		T21	1		T22	3
auto[0]	auto[1]	valid[4]	auto[1]	152	1			T6	1		T14	4		T23	3
auto[1]	auto[0]	valid[0]	auto[0]	76	1			T22	2		T183	1		T297	1
auto[1]	auto[0]	valid[1]	auto[0]	64	1			T66	1		T183	1		T294	1
auto[1]	auto[0]	valid[2]	auto[0]	80	1			T21	1		T22	1		T51	1
auto[1]	auto[0]	valid[3]	auto[0]	71	1			T1	1		T8	1		T21	1
auto[1]	auto[0]	valid[4]	auto[0]	75	1			T1	1		T18	1		T21	3
auto[1]	auto[1]	valid[0]	auto[0]	64	1			T21	2		T51	1		T141	1
auto[1]	auto[1]	valid[1]	auto[0]	69	1			T66	1		T178	1		T84	1
auto[1]	auto[1]	valid[2]	auto[0]	62	1			T21	1		T22	2		T86	1
auto[1]	auto[1]	valid[3]	auto[0]	65	1			T21	1		T22	1		T51	1
auto[1]	auto[1]	valid[4]	auto[0]	63	1			T21	1		T51	1		T297	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal