Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48033

1

T1

124

T8

53

T10

2

auto[1]

16236

1

T6

10

T8

19

T14

408

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

46967

1

T1

86

T6

10

T8

52

auto[1]

17302

1

T1

38

T8

20

T10

1

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	33018	1			T1	63		T6	10		T8	39
others[1]	5443	1			T1	12		T8	4		T14	38
others[2]	5323	1			T1	12		T8	4		T14	38
others[3]	6158	1			T1	9		T8	9		T14	29
interest[1]	3570	1			T1	8		T8	1		T14	26
interest[4]	21669	1			T1	42		T6	10		T8	27
interest[64]	10757	1			T1	20		T8	15		T14	67

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	15754	1			T1	47		T8	16		T10	1
auto[0]	auto[0]	others[1]	2611	1			T1	6		T8	2		T18	6
auto[0]	auto[0]	others[2]	2542	1			T1	7		T8	1		T18	3
auto[0]	auto[0]	others[3]	2955	1			T1	7		T8	6		T18	3
auto[0]	auto[0]	interest[1]	1717	1			T1	5		T18	5		T21	14
auto[0]	auto[0]	interest[4]	10257	1			T1	31		T8	11		T10	1
auto[0]	auto[0]	interest[64]	5152	1			T1	14		T8	8		T18	7
auto[0]	auto[1]	others[0]	8380	1			T6	10		T8	12		T14	210
auto[0]	auto[1]	others[1]	1365	1			T8	2		T14	38		T23	44
auto[0]	auto[1]	others[2]	1357	1			T8	1		T14	38		T23	37
auto[0]	auto[1]	others[3]	1521	1			T8	1		T14	29		T23	54
auto[0]	auto[1]	interest[1]	887	1			T14	26		T23	20		T24	7
auto[0]	auto[1]	interest[4]	5610	1			T6	10		T8	9		T14	139
auto[0]	auto[1]	interest[64]	2726	1			T8	3		T14	67		T23	74
auto[1]	auto[0]	others[0]	8884	1			T1	16		T8	11		T10	1
auto[1]	auto[0]	others[1]	1467	1			T1	6		T18	2		T21	13
auto[1]	auto[0]	others[2]	1424	1			T1	5		T8	2		T18	3
auto[1]	auto[0]	others[3]	1682	1			T1	2		T8	2		T18	1
auto[1]	auto[0]	interest[1]	966	1			T1	3		T8	1		T18	1
auto[1]	auto[0]	interest[4]	5802	1			T1	11		T8	7		T10	1
auto[1]	auto[0]	interest[64]	2879	1			T1	6		T8	4		T18	4

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal