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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.04 98.38 94.02 98.62 89.36 97.21 95.45 99.26


Total test records in report: 1131
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T1021 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1530140898 Jul 27 05:28:13 PM PDT 24 Jul 27 05:28:26 PM PDT 24 638128487 ps
T1022 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3560908991 Jul 27 05:28:23 PM PDT 24 Jul 27 05:28:27 PM PDT 24 113047680 ps
T1023 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2972067219 Jul 27 05:28:37 PM PDT 24 Jul 27 05:28:41 PM PDT 24 493916408 ps
T1024 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.2856195691 Jul 27 05:28:41 PM PDT 24 Jul 27 05:28:42 PM PDT 24 14709807 ps
T128 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.2790099292 Jul 27 05:28:34 PM PDT 24 Jul 27 05:28:36 PM PDT 24 139079792 ps
T111 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3862589996 Jul 27 05:28:13 PM PDT 24 Jul 27 05:28:16 PM PDT 24 43239672 ps
T129 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.298605457 Jul 27 05:28:11 PM PDT 24 Jul 27 05:28:25 PM PDT 24 2010506607 ps
T1025 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3614359653 Jul 27 05:28:22 PM PDT 24 Jul 27 05:28:25 PM PDT 24 133819275 ps
T114 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.74070457 Jul 27 05:28:26 PM PDT 24 Jul 27 05:28:31 PM PDT 24 759467780 ps
T1026 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.342048520 Jul 27 05:28:23 PM PDT 24 Jul 27 05:28:24 PM PDT 24 27700125 ps
T1027 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2969101861 Jul 27 05:28:01 PM PDT 24 Jul 27 05:28:02 PM PDT 24 23165801 ps
T156 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2827363000 Jul 27 05:28:17 PM PDT 24 Jul 27 05:28:19 PM PDT 24 78229317 ps
T157 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.207428133 Jul 27 05:28:26 PM PDT 24 Jul 27 05:28:30 PM PDT 24 413909091 ps
T130 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1840981481 Jul 27 05:28:34 PM PDT 24 Jul 27 05:28:35 PM PDT 24 41822201 ps
T1028 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.777195725 Jul 27 05:28:44 PM PDT 24 Jul 27 05:28:44 PM PDT 24 138195463 ps
T1029 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.3108240490 Jul 27 05:28:24 PM PDT 24 Jul 27 05:28:25 PM PDT 24 14140477 ps
T131 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2097824903 Jul 27 05:28:32 PM PDT 24 Jul 27 05:28:35 PM PDT 24 118127971 ps
T1030 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.1965872956 Jul 27 05:28:42 PM PDT 24 Jul 27 05:28:43 PM PDT 24 37855739 ps
T168 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.3563461107 Jul 27 05:28:36 PM PDT 24 Jul 27 05:28:56 PM PDT 24 579813376 ps
T1031 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.3034939482 Jul 27 05:28:43 PM PDT 24 Jul 27 05:28:44 PM PDT 24 13290804 ps
T113 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.1740871222 Jul 27 05:28:15 PM PDT 24 Jul 27 05:28:19 PM PDT 24 160665181 ps
T1032 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3851907854 Jul 27 05:28:32 PM PDT 24 Jul 27 05:28:34 PM PDT 24 285961417 ps
T1033 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.748960185 Jul 27 05:28:14 PM PDT 24 Jul 27 05:28:17 PM PDT 24 419859972 ps
T1034 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2812318394 Jul 27 05:28:35 PM PDT 24 Jul 27 05:28:36 PM PDT 24 12686381 ps
T167 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.4018196899 Jul 27 05:28:33 PM PDT 24 Jul 27 05:28:53 PM PDT 24 871980938 ps
T1035 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1579508731 Jul 27 05:28:26 PM PDT 24 Jul 27 05:28:28 PM PDT 24 32699850 ps
T1036 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3935893593 Jul 27 05:28:00 PM PDT 24 Jul 27 05:28:02 PM PDT 24 133190158 ps
T1037 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.1695757643 Jul 27 05:28:45 PM PDT 24 Jul 27 05:28:46 PM PDT 24 64260407 ps
T1038 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2254291201 Jul 27 05:28:30 PM PDT 24 Jul 27 05:28:32 PM PDT 24 265657450 ps
T1039 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3650884490 Jul 27 05:28:12 PM PDT 24 Jul 27 05:28:13 PM PDT 24 165549075 ps
T1040 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.2905761498 Jul 27 05:28:32 PM PDT 24 Jul 27 05:28:37 PM PDT 24 502520788 ps
T1041 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.477218977 Jul 27 05:28:16 PM PDT 24 Jul 27 05:28:17 PM PDT 24 37877336 ps
T132 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3080352985 Jul 27 05:28:21 PM PDT 24 Jul 27 05:28:24 PM PDT 24 185012235 ps
T169 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1737309546 Jul 27 05:28:35 PM PDT 24 Jul 27 05:28:44 PM PDT 24 1868561598 ps
T88 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3070743674 Jul 27 05:28:16 PM PDT 24 Jul 27 05:28:17 PM PDT 24 58017833 ps
T89 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2790350861 Jul 27 05:28:13 PM PDT 24 Jul 27 05:28:14 PM PDT 24 35014283 ps
T1042 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.553960190 Jul 27 05:28:25 PM PDT 24 Jul 27 05:28:27 PM PDT 24 26338526 ps
T1043 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.515200241 Jul 27 05:28:42 PM PDT 24 Jul 27 05:28:43 PM PDT 24 53157583 ps
T1044 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.380652712 Jul 27 05:28:33 PM PDT 24 Jul 27 05:28:35 PM PDT 24 62107462 ps
T1045 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.1847121646 Jul 27 05:28:12 PM PDT 24 Jul 27 05:28:13 PM PDT 24 48147905 ps
T1046 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.867108907 Jul 27 05:28:24 PM PDT 24 Jul 27 05:28:27 PM PDT 24 317567703 ps
T110 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.4242543287 Jul 27 05:28:15 PM PDT 24 Jul 27 05:28:32 PM PDT 24 1639278447 ps
T1047 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2745648973 Jul 27 05:28:36 PM PDT 24 Jul 27 05:28:40 PM PDT 24 162922088 ps
T170 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.3213156307 Jul 27 05:28:34 PM PDT 24 Jul 27 05:28:47 PM PDT 24 788087488 ps
T1048 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.3219578643 Jul 27 05:28:43 PM PDT 24 Jul 27 05:28:44 PM PDT 24 15910966 ps
T1049 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.2863842788 Jul 27 05:28:35 PM PDT 24 Jul 27 05:28:36 PM PDT 24 14401165 ps
T90 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2243803290 Jul 27 05:28:15 PM PDT 24 Jul 27 05:28:17 PM PDT 24 23102123 ps
T1050 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.934083133 Jul 27 05:28:41 PM PDT 24 Jul 27 05:28:42 PM PDT 24 13760300 ps
T115 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.4272295912 Jul 27 05:28:11 PM PDT 24 Jul 27 05:28:15 PM PDT 24 336326449 ps
T1051 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.270016441 Jul 27 05:28:15 PM PDT 24 Jul 27 05:28:18 PM PDT 24 218682070 ps
T1052 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.2391732569 Jul 27 05:28:23 PM PDT 24 Jul 27 05:28:36 PM PDT 24 212517777 ps
T1053 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.4264276007 Jul 27 05:28:26 PM PDT 24 Jul 27 05:28:29 PM PDT 24 83915557 ps
T1054 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1258642513 Jul 27 05:28:41 PM PDT 24 Jul 27 05:28:42 PM PDT 24 55781475 ps
T1055 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1148792742 Jul 27 05:27:58 PM PDT 24 Jul 27 05:28:25 PM PDT 24 25860033860 ps
T1056 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.1956748461 Jul 27 05:28:36 PM PDT 24 Jul 27 05:28:40 PM PDT 24 121385667 ps
T1057 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2151200049 Jul 27 05:28:12 PM PDT 24 Jul 27 05:28:14 PM PDT 24 196811819 ps
T1058 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.3458145276 Jul 27 05:28:42 PM PDT 24 Jul 27 05:28:43 PM PDT 24 52173324 ps
T1059 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2661609420 Jul 27 05:28:23 PM PDT 24 Jul 27 05:28:27 PM PDT 24 64500310 ps
T1060 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2836933124 Jul 27 05:28:26 PM PDT 24 Jul 27 05:28:30 PM PDT 24 147433734 ps
T1061 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.964721937 Jul 27 05:28:14 PM PDT 24 Jul 27 05:28:16 PM PDT 24 45361473 ps
T1062 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.3836664804 Jul 27 05:28:38 PM PDT 24 Jul 27 05:28:40 PM PDT 24 293448193 ps
T1063 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.1852927255 Jul 27 05:28:12 PM PDT 24 Jul 27 05:28:28 PM PDT 24 2506734689 ps
T1064 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.3513805673 Jul 27 05:28:24 PM PDT 24 Jul 27 05:28:25 PM PDT 24 14971842 ps
T1065 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1807160280 Jul 27 05:28:11 PM PDT 24 Jul 27 05:28:14 PM PDT 24 1000738261 ps
T1066 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2001690296 Jul 27 05:28:43 PM PDT 24 Jul 27 05:28:46 PM PDT 24 152817363 ps
T1067 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.719499368 Jul 27 05:28:15 PM PDT 24 Jul 27 05:28:18 PM PDT 24 228001856 ps
T1068 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1936041287 Jul 27 05:28:15 PM PDT 24 Jul 27 05:28:17 PM PDT 24 56974523 ps
T1069 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.4232427218 Jul 27 05:28:46 PM PDT 24 Jul 27 05:28:47 PM PDT 24 28231316 ps
T1070 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.4262584228 Jul 27 05:28:33 PM PDT 24 Jul 27 05:28:35 PM PDT 24 83480435 ps
T1071 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.4187945076 Jul 27 05:28:40 PM PDT 24 Jul 27 05:28:41 PM PDT 24 12721919 ps
T1072 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2638817514 Jul 27 05:28:22 PM PDT 24 Jul 27 05:28:26 PM PDT 24 60620335 ps
T1073 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.1032424634 Jul 27 05:28:43 PM PDT 24 Jul 27 05:28:44 PM PDT 24 16469679 ps
T1074 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2569350892 Jul 27 05:28:14 PM PDT 24 Jul 27 05:28:27 PM PDT 24 2394162133 ps
T1075 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3840500404 Jul 27 05:28:42 PM PDT 24 Jul 27 05:28:43 PM PDT 24 19401832 ps
T1076 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.4281787436 Jul 27 05:28:01 PM PDT 24 Jul 27 05:28:03 PM PDT 24 73406967 ps
T1077 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1750894251 Jul 27 05:28:38 PM PDT 24 Jul 27 05:29:00 PM PDT 24 1112598455 ps
T1078 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.438682746 Jul 27 05:28:23 PM PDT 24 Jul 27 05:28:27 PM PDT 24 533769218 ps
T1079 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.2168453791 Jul 27 05:28:26 PM PDT 24 Jul 27 05:28:29 PM PDT 24 334222297 ps
T1080 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.275507243 Jul 27 05:28:20 PM PDT 24 Jul 27 05:28:43 PM PDT 24 1650330593 ps
T1081 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.4032620707 Jul 27 05:28:16 PM PDT 24 Jul 27 05:28:17 PM PDT 24 11026017 ps
T1082 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.1705608744 Jul 27 05:28:15 PM PDT 24 Jul 27 05:28:15 PM PDT 24 10197082 ps
T1083 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1133379111 Jul 27 05:28:41 PM PDT 24 Jul 27 05:28:41 PM PDT 24 12316722 ps
T1084 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3673626607 Jul 27 05:28:33 PM PDT 24 Jul 27 05:28:37 PM PDT 24 490395629 ps
T1085 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2296779877 Jul 27 05:28:33 PM PDT 24 Jul 27 05:28:36 PM PDT 24 200866554 ps
T1086 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1716301597 Jul 27 05:28:15 PM PDT 24 Jul 27 05:28:15 PM PDT 24 14018695 ps
T1087 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.1162007969 Jul 27 05:28:41 PM PDT 24 Jul 27 05:28:42 PM PDT 24 26645424 ps
T1088 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.410442308 Jul 27 05:28:43 PM PDT 24 Jul 27 05:28:44 PM PDT 24 14405677 ps
T1089 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.4165933167 Jul 27 05:28:15 PM PDT 24 Jul 27 05:28:31 PM PDT 24 2650771824 ps
T1090 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.2755680472 Jul 27 05:28:16 PM PDT 24 Jul 27 05:28:17 PM PDT 24 30191204 ps
T1091 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.914941938 Jul 27 05:28:21 PM PDT 24 Jul 27 05:28:22 PM PDT 24 23648811 ps
T1092 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.84649276 Jul 27 05:28:42 PM PDT 24 Jul 27 05:28:43 PM PDT 24 98468030 ps
T1093 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.1921845303 Jul 27 05:28:41 PM PDT 24 Jul 27 05:28:42 PM PDT 24 11565922 ps
T1094 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.784356268 Jul 27 05:28:37 PM PDT 24 Jul 27 05:28:42 PM PDT 24 140210048 ps
T1095 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.25125911 Jul 27 05:28:33 PM PDT 24 Jul 27 05:28:34 PM PDT 24 50551467 ps
T1096 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.3337968641 Jul 27 05:28:16 PM PDT 24 Jul 27 05:28:16 PM PDT 24 159364071 ps
T1097 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.422266929 Jul 27 05:28:24 PM PDT 24 Jul 27 05:28:25 PM PDT 24 26178516 ps
T1098 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.253964547 Jul 27 05:28:25 PM PDT 24 Jul 27 05:28:28 PM PDT 24 113988423 ps
T1099 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.3326543434 Jul 27 05:28:41 PM PDT 24 Jul 27 05:28:43 PM PDT 24 27208584 ps
T1100 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1352061516 Jul 27 05:28:43 PM PDT 24 Jul 27 05:28:45 PM PDT 24 21140335 ps
T1101 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.4019408853 Jul 27 05:28:48 PM PDT 24 Jul 27 05:28:49 PM PDT 24 55282215 ps
T1102 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2528316626 Jul 27 05:28:13 PM PDT 24 Jul 27 05:28:14 PM PDT 24 35637596 ps
T1103 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.4058178754 Jul 27 05:28:33 PM PDT 24 Jul 27 05:28:34 PM PDT 24 122255919 ps
T1104 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.2753881961 Jul 27 05:28:34 PM PDT 24 Jul 27 05:28:39 PM PDT 24 155601931 ps
T1105 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2423838256 Jul 27 05:28:13 PM PDT 24 Jul 27 05:28:15 PM PDT 24 152251406 ps
T1106 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2766818975 Jul 27 05:28:23 PM PDT 24 Jul 27 05:28:24 PM PDT 24 38848018 ps
T1107 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3483252605 Jul 27 05:27:57 PM PDT 24 Jul 27 05:27:59 PM PDT 24 243908374 ps
T1108 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.128310502 Jul 27 05:28:34 PM PDT 24 Jul 27 05:28:38 PM PDT 24 212625326 ps
T1109 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.531912836 Jul 27 05:28:12 PM PDT 24 Jul 27 05:28:26 PM PDT 24 197137257 ps
T1110 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2261468374 Jul 27 05:28:44 PM PDT 24 Jul 27 05:28:45 PM PDT 24 53318275 ps
T1111 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.1356568057 Jul 27 05:28:29 PM PDT 24 Jul 27 05:28:45 PM PDT 24 2946206974 ps
T1112 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1606825063 Jul 27 05:28:15 PM PDT 24 Jul 27 05:28:28 PM PDT 24 1240396067 ps
T1113 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.1468244598 Jul 27 05:28:39 PM PDT 24 Jul 27 05:28:40 PM PDT 24 46469230 ps
T1114 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1611086918 Jul 27 05:28:34 PM PDT 24 Jul 27 05:28:34 PM PDT 24 12840503 ps
T1115 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.1601452756 Jul 27 05:28:14 PM PDT 24 Jul 27 05:28:38 PM PDT 24 5231200702 ps
T1116 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.441622236 Jul 27 05:28:41 PM PDT 24 Jul 27 05:28:41 PM PDT 24 55243249 ps
T1117 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.4214363794 Jul 27 05:28:33 PM PDT 24 Jul 27 05:28:36 PM PDT 24 162338576 ps
T1118 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1707737675 Jul 27 05:28:34 PM PDT 24 Jul 27 05:28:41 PM PDT 24 571879396 ps
T1119 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3547194462 Jul 27 05:28:38 PM PDT 24 Jul 27 05:28:39 PM PDT 24 20176033 ps
T1120 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.3813267730 Jul 27 05:28:41 PM PDT 24 Jul 27 05:28:42 PM PDT 24 17410681 ps
T1121 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.597279998 Jul 27 05:28:22 PM PDT 24 Jul 27 05:28:43 PM PDT 24 1676175992 ps
T1122 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.4189910664 Jul 27 05:28:12 PM PDT 24 Jul 27 05:28:13 PM PDT 24 158253530 ps
T1123 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.264472504 Jul 27 05:28:15 PM PDT 24 Jul 27 05:28:18 PM PDT 24 197752260 ps
T109 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.637464979 Jul 27 05:28:25 PM PDT 24 Jul 27 05:28:45 PM PDT 24 835949380 ps
T1124 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.930267217 Jul 27 05:28:33 PM PDT 24 Jul 27 05:28:34 PM PDT 24 217525309 ps
T1125 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.2391425303 Jul 27 05:28:24 PM PDT 24 Jul 27 05:28:25 PM PDT 24 18501356 ps
T1126 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.1599395817 Jul 27 05:28:41 PM PDT 24 Jul 27 05:28:42 PM PDT 24 34112836 ps
T1127 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.1676416697 Jul 27 05:28:14 PM PDT 24 Jul 27 05:28:16 PM PDT 24 62448884 ps
T1128 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.112733539 Jul 27 05:28:15 PM PDT 24 Jul 27 05:28:28 PM PDT 24 678711670 ps
T1129 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.76600008 Jul 27 05:28:01 PM PDT 24 Jul 27 05:28:06 PM PDT 24 268318361 ps
T1130 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.83018146 Jul 27 05:28:12 PM PDT 24 Jul 27 05:28:34 PM PDT 24 1008376499 ps
T1131 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.4252670031 Jul 27 05:28:25 PM PDT 24 Jul 27 05:28:26 PM PDT 24 26131413 ps

Test location /workspace/coverage/default/49.spi_device_stress_all.353045628
Short name T8
Test name
Test status
Simulation time 79014852313 ps
CPU time 287.1 seconds
Started Jul 27 05:34:43 PM PDT 24
Finished Jul 27 05:39:30 PM PDT 24
Peak memory 256036 kb
Host smart-b615984d-7e8b-489b-a1f7-a64f96598a3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353045628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stres
s_all.353045628
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.2894061402
Short name T21
Test name
Test status
Simulation time 136063141020 ps
CPU time 569.39 seconds
Started Jul 27 05:33:57 PM PDT 24
Finished Jul 27 05:43:26 PM PDT 24
Peak memory 263296 kb
Host smart-72271809-f363-4c20-8772-a35b6d9754d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894061402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.2894061402
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.2286088600
Short name T23
Test name
Test status
Simulation time 51654757483 ps
CPU time 24.12 seconds
Started Jul 27 05:31:11 PM PDT 24
Finished Jul 27 05:31:36 PM PDT 24
Peak memory 216344 kb
Host smart-fc1c3293-e1c2-4ed6-89c1-70a780609f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286088600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.2286088600
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.4195505747
Short name T177
Test name
Test status
Simulation time 469547709069 ps
CPU time 1074.07 seconds
Started Jul 27 05:33:12 PM PDT 24
Finished Jul 27 05:51:07 PM PDT 24
Peak memory 281732 kb
Host smart-da3ac5d3-bd51-4565-a5d8-8f708b23c0b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195505747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.4195505747
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1847978596
Short name T102
Test name
Test status
Simulation time 4997045815 ps
CPU time 21.74 seconds
Started Jul 27 05:28:16 PM PDT 24
Finished Jul 27 05:28:38 PM PDT 24
Peak memory 215448 kb
Host smart-0b7ed34d-e8da-4c87-b33d-28be559f483f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847978596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.1847978596
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.1133610374
Short name T27
Test name
Test status
Simulation time 60255870697 ps
CPU time 503.56 seconds
Started Jul 27 05:34:54 PM PDT 24
Finished Jul 27 05:43:18 PM PDT 24
Peak memory 285040 kb
Host smart-3b82cb73-120d-43db-8b7b-7bbf029b0bbe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133610374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.1133610374
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.4228968572
Short name T72
Test name
Test status
Simulation time 15841873 ps
CPU time 0.78 seconds
Started Jul 27 05:31:02 PM PDT 24
Finished Jul 27 05:31:03 PM PDT 24
Peak memory 216408 kb
Host smart-1db8ffa0-48c6-406f-810a-2fbc9e7699f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228968572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.4228968572
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.891412826
Short name T178
Test name
Test status
Simulation time 36139946603 ps
CPU time 159.69 seconds
Started Jul 27 05:33:45 PM PDT 24
Finished Jul 27 05:36:24 PM PDT 24
Peak memory 266632 kb
Host smart-2a4f42f2-a1de-4695-ae05-f5b2eea097cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891412826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idle
.891412826
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.1907870327
Short name T180
Test name
Test status
Simulation time 27870799046 ps
CPU time 158.43 seconds
Started Jul 27 05:32:06 PM PDT 24
Finished Jul 27 05:34:45 PM PDT 24
Peak memory 273860 kb
Host smart-37740a4c-f5da-4997-931d-1d6fc84c45b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907870327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.1907870327
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.1491467079
Short name T37
Test name
Test status
Simulation time 37616085355 ps
CPU time 288.96 seconds
Started Jul 27 05:32:57 PM PDT 24
Finished Jul 27 05:37:46 PM PDT 24
Peak memory 263832 kb
Host smart-85462810-dfe2-455f-b480-68b98f3c5c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491467079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.1491467079
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.1140383839
Short name T179
Test name
Test status
Simulation time 8858141103 ps
CPU time 128.44 seconds
Started Jul 27 05:32:50 PM PDT 24
Finished Jul 27 05:34:59 PM PDT 24
Peak memory 257556 kb
Host smart-4d498945-5718-4b6e-8f75-00b02b84ebec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140383839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.1140383839
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3768817778
Short name T71
Test name
Test status
Simulation time 1552359944 ps
CPU time 4.5 seconds
Started Jul 27 05:28:24 PM PDT 24
Finished Jul 27 05:28:29 PM PDT 24
Peak memory 215816 kb
Host smart-f160e210-28f3-4a4e-8ebf-8325acd0c233
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768817778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
3768817778
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.691065353
Short name T29
Test name
Test status
Simulation time 350103942 ps
CPU time 1.17 seconds
Started Jul 27 05:31:09 PM PDT 24
Finished Jul 27 05:31:10 PM PDT 24
Peak memory 235868 kb
Host smart-39e5e80e-af0d-46f4-be76-8425af151ed8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691065353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.691065353
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.455562025
Short name T2
Test name
Test status
Simulation time 315890349 ps
CPU time 9.46 seconds
Started Jul 27 05:31:00 PM PDT 24
Finished Jul 27 05:31:10 PM PDT 24
Peak memory 224660 kb
Host smart-8b59c3bf-abf4-4970-ad61-d4caebfdd3a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455562025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.455562025
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.825989213
Short name T193
Test name
Test status
Simulation time 106086741373 ps
CPU time 968.31 seconds
Started Jul 27 05:33:58 PM PDT 24
Finished Jul 27 05:50:06 PM PDT 24
Peak memory 281312 kb
Host smart-334f75d9-c3e9-45c9-873e-dba98db5f615
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825989213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stres
s_all.825989213
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.4047484969
Short name T45
Test name
Test status
Simulation time 163227414538 ps
CPU time 310.88 seconds
Started Jul 27 05:31:12 PM PDT 24
Finished Jul 27 05:36:23 PM PDT 24
Peak memory 265700 kb
Host smart-31e577b8-aebd-4a51-9daa-8588f021a403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047484969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds
.4047484969
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.1225486532
Short name T66
Test name
Test status
Simulation time 11140810828 ps
CPU time 98.53 seconds
Started Jul 27 05:33:16 PM PDT 24
Finished Jul 27 05:34:55 PM PDT 24
Peak memory 253064 kb
Host smart-27a2d57e-ca4a-4825-b8b5-67566c5d1d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225486532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.1225486532
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.298605457
Short name T129
Test name
Test status
Simulation time 2010506607 ps
CPU time 14.02 seconds
Started Jul 27 05:28:11 PM PDT 24
Finished Jul 27 05:28:25 PM PDT 24
Peak memory 207060 kb
Host smart-9e818f2e-e177-41ba-b830-089e67422c07
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298605457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_aliasing.298605457
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.83186970
Short name T184
Test name
Test status
Simulation time 74649012922 ps
CPU time 365.46 seconds
Started Jul 27 05:32:03 PM PDT 24
Finished Jul 27 05:38:09 PM PDT 24
Peak memory 269828 kb
Host smart-636e859e-a0a8-4641-949c-b59aef60e233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83186970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.83186970
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.2637511148
Short name T54
Test name
Test status
Simulation time 387935467389 ps
CPU time 739.77 seconds
Started Jul 27 05:33:09 PM PDT 24
Finished Jul 27 05:45:29 PM PDT 24
Peak memory 273920 kb
Host smart-616dc2a0-fea5-49fe-a998-0cd152742764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637511148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.2637511148
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.1722939445
Short name T183
Test name
Test status
Simulation time 32585964441 ps
CPU time 88.1 seconds
Started Jul 27 05:32:20 PM PDT 24
Finished Jul 27 05:33:48 PM PDT 24
Peak memory 256172 kb
Host smart-45d9c33c-1150-4758-a8f2-343fc90f1770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722939445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.1722939445
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.893287311
Short name T38
Test name
Test status
Simulation time 4099485609 ps
CPU time 71.41 seconds
Started Jul 27 05:34:49 PM PDT 24
Finished Jul 27 05:36:01 PM PDT 24
Peak memory 265588 kb
Host smart-11049fcd-f0c7-4a98-8368-91ccde77a73e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893287311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmds
.893287311
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.1921658760
Short name T249
Test name
Test status
Simulation time 205798710000 ps
CPU time 467.44 seconds
Started Jul 27 05:31:12 PM PDT 24
Finished Jul 27 05:39:00 PM PDT 24
Peak memory 262500 kb
Host smart-a06a92f2-d24d-4831-881d-fd42570193c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921658760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.1921658760
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.1700351098
Short name T286
Test name
Test status
Simulation time 10844657479 ps
CPU time 67.24 seconds
Started Jul 27 05:31:23 PM PDT 24
Finished Jul 27 05:32:30 PM PDT 24
Peak memory 238968 kb
Host smart-4076a56b-7cdc-4327-b9cb-a9584ea5e348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700351098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.1700351098
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.4085479004
Short name T208
Test name
Test status
Simulation time 388309410056 ps
CPU time 210.34 seconds
Started Jul 27 05:31:03 PM PDT 24
Finished Jul 27 05:34:33 PM PDT 24
Peak memory 273184 kb
Host smart-ffa00424-e3ab-4388-9cb8-e9e1e894e623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085479004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.4085479004
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.3038891702
Short name T328
Test name
Test status
Simulation time 23419501 ps
CPU time 0.77 seconds
Started Jul 27 05:31:00 PM PDT 24
Finished Jul 27 05:31:01 PM PDT 24
Peak memory 205528 kb
Host smart-ed693d7b-5c5b-4f0b-9068-478dd03b5fed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038891702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.3
038891702
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.2357175820
Short name T164
Test name
Test status
Simulation time 5772126555 ps
CPU time 101.25 seconds
Started Jul 27 05:32:59 PM PDT 24
Finished Jul 27 05:34:41 PM PDT 24
Peak memory 249268 kb
Host smart-33ce69fb-062c-4248-9f10-959e7fb8d0aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357175820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.2357175820
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.1186827361
Short name T221
Test name
Test status
Simulation time 316645713676 ps
CPU time 809.35 seconds
Started Jul 27 05:33:34 PM PDT 24
Finished Jul 27 05:47:04 PM PDT 24
Peak memory 273960 kb
Host smart-cf3cb6a0-a530-4788-ad8b-033d677cc839
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186827361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.1186827361
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.1927319490
Short name T133
Test name
Test status
Simulation time 77919896071 ps
CPU time 320.99 seconds
Started Jul 27 05:32:03 PM PDT 24
Finished Jul 27 05:37:24 PM PDT 24
Peak memory 265684 kb
Host smart-34aa73b3-be87-4561-9bef-fa7ceaed25b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927319490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.1927319490
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.1184721193
Short name T97
Test name
Test status
Simulation time 42544656675 ps
CPU time 484.55 seconds
Started Jul 27 05:32:05 PM PDT 24
Finished Jul 27 05:40:10 PM PDT 24
Peak memory 268856 kb
Host smart-1aeeb953-5c77-4081-ae6e-e4be223523c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184721193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.1184721193
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.264554258
Short name T19
Test name
Test status
Simulation time 3675116950 ps
CPU time 50.25 seconds
Started Jul 27 05:32:20 PM PDT 24
Finished Jul 27 05:33:10 PM PDT 24
Peak memory 237488 kb
Host smart-123320f5-2f85-4b49-8e36-6b9abc3a527c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264554258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.264554258
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.2131394888
Short name T258
Test name
Test status
Simulation time 47321427875 ps
CPU time 197.44 seconds
Started Jul 27 05:32:27 PM PDT 24
Finished Jul 27 05:35:44 PM PDT 24
Peak memory 263604 kb
Host smart-c40d77c9-9145-45c6-8fdc-2aa726f33d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131394888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.2131394888
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.498402650
Short name T270
Test name
Test status
Simulation time 67606838704 ps
CPU time 518.08 seconds
Started Jul 27 05:32:28 PM PDT 24
Finished Jul 27 05:41:06 PM PDT 24
Peak memory 265688 kb
Host smart-ca2befb8-bc59-43fd-8ef0-b3bec13fea80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498402650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idle
.498402650
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.3451941363
Short name T34
Test name
Test status
Simulation time 80095306275 ps
CPU time 658.62 seconds
Started Jul 27 05:34:14 PM PDT 24
Finished Jul 27 05:45:13 PM PDT 24
Peak memory 267028 kb
Host smart-cd890dd3-1cd6-405f-b06e-f0359f2b7c1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451941363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.3451941363
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.1740871222
Short name T113
Test name
Test status
Simulation time 160665181 ps
CPU time 3.73 seconds
Started Jul 27 05:28:15 PM PDT 24
Finished Jul 27 05:28:19 PM PDT 24
Peak memory 215476 kb
Host smart-d53acb81-4464-444d-938a-90d97c6d80a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740871222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.1
740871222
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.3563461107
Short name T168
Test name
Test status
Simulation time 579813376 ps
CPU time 19.64 seconds
Started Jul 27 05:28:36 PM PDT 24
Finished Jul 27 05:28:56 PM PDT 24
Peak memory 215856 kb
Host smart-2343a3e8-7e52-470a-ab29-55c0e7fa5d67
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563461107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.3563461107
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.1414508234
Short name T284
Test name
Test status
Simulation time 1159994001 ps
CPU time 20.31 seconds
Started Jul 27 05:32:59 PM PDT 24
Finished Jul 27 05:33:20 PM PDT 24
Peak memory 235884 kb
Host smart-5ebf4fd7-c588-4df4-8911-7fb1862afeef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414508234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.1414508234
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.821162056
Short name T171
Test name
Test status
Simulation time 279454032 ps
CPU time 19.08 seconds
Started Jul 27 05:28:31 PM PDT 24
Finished Jul 27 05:28:50 PM PDT 24
Peak memory 215328 kb
Host smart-9204b151-8fb2-459a-a398-74c47a0877d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821162056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device
_tl_intg_err.821162056
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.757929126
Short name T564
Test name
Test status
Simulation time 233426566262 ps
CPU time 370.49 seconds
Started Jul 27 05:31:08 PM PDT 24
Finished Jul 27 05:37:19 PM PDT 24
Peak memory 269680 kb
Host smart-206d4eb3-05bf-49e5-b4e0-2945f683ed01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757929126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle.
757929126
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.3549741165
Short name T172
Test name
Test status
Simulation time 1129347705988 ps
CPU time 531.04 seconds
Started Jul 27 05:30:59 PM PDT 24
Finished Jul 27 05:39:50 PM PDT 24
Peak memory 267984 kb
Host smart-99e88a20-444f-40a3-92ab-782047e50c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549741165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds
.3549741165
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.1186851197
Short name T158
Test name
Test status
Simulation time 5712097124 ps
CPU time 85.26 seconds
Started Jul 27 05:31:12 PM PDT 24
Finished Jul 27 05:32:38 PM PDT 24
Peak memory 249396 kb
Host smart-df687f8d-6f6e-492c-8586-f90b078d6ef7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186851197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.1186851197
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.1773810983
Short name T293
Test name
Test status
Simulation time 1044134666 ps
CPU time 9.55 seconds
Started Jul 27 05:31:52 PM PDT 24
Finished Jul 27 05:32:02 PM PDT 24
Peak memory 216384 kb
Host smart-1898c604-2e6a-45c3-9313-acdcb993ff82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773810983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.1773810983
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.3868772366
Short name T99
Test name
Test status
Simulation time 137766897555 ps
CPU time 245.53 seconds
Started Jul 27 05:32:19 PM PDT 24
Finished Jul 27 05:36:25 PM PDT 24
Peak memory 254016 kb
Host smart-ae1679ed-cfaa-43dd-9859-59ad5c5cb641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868772366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmd
s.3868772366
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.3531860384
Short name T198
Test name
Test status
Simulation time 11185122872 ps
CPU time 66.71 seconds
Started Jul 27 05:33:09 PM PDT 24
Finished Jul 27 05:34:17 PM PDT 24
Peak memory 255528 kb
Host smart-03bbf8d8-b3de-4075-afa9-a97a1b5bb7e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531860384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.3531860384
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.945840935
Short name T265
Test name
Test status
Simulation time 23769967415 ps
CPU time 211.67 seconds
Started Jul 27 05:34:13 PM PDT 24
Finished Jul 27 05:37:45 PM PDT 24
Peak memory 255288 kb
Host smart-7da3bd7e-85ff-476e-9b3d-79354c7fb577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945840935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.945840935
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_intercept.371349298
Short name T721
Test name
Test status
Simulation time 755773102 ps
CPU time 4.68 seconds
Started Jul 27 05:31:53 PM PDT 24
Finished Jul 27 05:31:58 PM PDT 24
Peak memory 224668 kb
Host smart-91b6a9e5-088d-4cc8-8198-4ac0b9035450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371349298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.371349298
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.3032491947
Short name T236
Test name
Test status
Simulation time 1243563072 ps
CPU time 8.26 seconds
Started Jul 27 05:32:15 PM PDT 24
Finished Jul 27 05:32:23 PM PDT 24
Peak memory 224652 kb
Host smart-fedcad2b-da9b-48bc-ab4f-84799a2f8984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032491947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.3032491947
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2243803290
Short name T90
Test name
Test status
Simulation time 23102123 ps
CPU time 1.38 seconds
Started Jul 27 05:28:15 PM PDT 24
Finished Jul 27 05:28:17 PM PDT 24
Peak memory 207028 kb
Host smart-091da118-c479-46cc-94ab-ef0dda390871
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243803290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.2243803290
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.76600008
Short name T1129
Test name
Test status
Simulation time 268318361 ps
CPU time 4.84 seconds
Started Jul 27 05:28:01 PM PDT 24
Finished Jul 27 05:28:06 PM PDT 24
Peak memory 215568 kb
Host smart-9f661f04-87e8-480a-8b30-da52099675fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76600008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.76600008
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.4242543287
Short name T110
Test name
Test status
Simulation time 1639278447 ps
CPU time 17.37 seconds
Started Jul 27 05:28:15 PM PDT 24
Finished Jul 27 05:28:32 PM PDT 24
Peak memory 215444 kb
Host smart-5f48d7c4-1ee5-4255-8e6d-ede3ee5793db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242543287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.4242543287
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.637464979
Short name T109
Test name
Test status
Simulation time 835949380 ps
CPU time 19.82 seconds
Started Jul 27 05:28:25 PM PDT 24
Finished Jul 27 05:28:45 PM PDT 24
Peak memory 215528 kb
Host smart-331d0af6-d82a-400e-8d6e-964cc5baaa6f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637464979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device
_tl_intg_err.637464979
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.531912836
Short name T1109
Test name
Test status
Simulation time 197137257 ps
CPU time 13.45 seconds
Started Jul 27 05:28:12 PM PDT 24
Finished Jul 27 05:28:26 PM PDT 24
Peak memory 215300 kb
Host smart-80f989d7-9046-4e6e-a761-bd201bf1fd90
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531912836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_aliasing.531912836
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1148792742
Short name T1055
Test name
Test status
Simulation time 25860033860 ps
CPU time 27.01 seconds
Started Jul 27 05:27:58 PM PDT 24
Finished Jul 27 05:28:25 PM PDT 24
Peak memory 207288 kb
Host smart-04710782-d694-411c-ada8-4a2eeec36e03
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148792742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.1148792742
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2969101861
Short name T1027
Test name
Test status
Simulation time 23165801 ps
CPU time 1.02 seconds
Started Jul 27 05:28:01 PM PDT 24
Finished Jul 27 05:28:02 PM PDT 24
Peak memory 206996 kb
Host smart-ec3d9043-d9b6-4922-b4aa-01414752b017
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969101861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.2969101861
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3935893593
Short name T1036
Test name
Test status
Simulation time 133190158 ps
CPU time 2.05 seconds
Started Jul 27 05:28:00 PM PDT 24
Finished Jul 27 05:28:02 PM PDT 24
Peak memory 216524 kb
Host smart-fdbb4e3f-44c4-4db3-860e-eba02e6d1953
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935893593 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.3935893593
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.4281787436
Short name T1076
Test name
Test status
Simulation time 73406967 ps
CPU time 2.33 seconds
Started Jul 27 05:28:01 PM PDT 24
Finished Jul 27 05:28:03 PM PDT 24
Peak memory 215452 kb
Host smart-dc6c8f13-bb3f-4d92-960d-b008ce3ed1c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281787436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.4
281787436
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.1847121646
Short name T1045
Test name
Test status
Simulation time 48147905 ps
CPU time 0.74 seconds
Started Jul 27 05:28:12 PM PDT 24
Finished Jul 27 05:28:13 PM PDT 24
Peak memory 203812 kb
Host smart-73d9b3b8-9ca1-4009-8d61-8abf4c51f71f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847121646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.1
847121646
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3483252605
Short name T1107
Test name
Test status
Simulation time 243908374 ps
CPU time 1.81 seconds
Started Jul 27 05:27:57 PM PDT 24
Finished Jul 27 05:27:59 PM PDT 24
Peak memory 215400 kb
Host smart-2417dac9-3890-4fc3-9ca1-b5c3ec31ad8f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483252605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.3483252605
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.1705608744
Short name T1082
Test name
Test status
Simulation time 10197082 ps
CPU time 0.67 seconds
Started Jul 27 05:28:15 PM PDT 24
Finished Jul 27 05:28:15 PM PDT 24
Peak memory 203728 kb
Host smart-ecd6c049-5800-4c06-a78b-0817fb67b3c6
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705608744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.1705608744
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.719499368
Short name T1067
Test name
Test status
Simulation time 228001856 ps
CPU time 2.93 seconds
Started Jul 27 05:28:15 PM PDT 24
Finished Jul 27 05:28:18 PM PDT 24
Peak memory 215372 kb
Host smart-52cff8c5-6851-47a7-a0c9-98467f14c70f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719499368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sp
i_device_same_csr_outstanding.719499368
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.112733539
Short name T1128
Test name
Test status
Simulation time 678711670 ps
CPU time 12.83 seconds
Started Jul 27 05:28:15 PM PDT 24
Finished Jul 27 05:28:28 PM PDT 24
Peak memory 215424 kb
Host smart-9a1536ae-44ad-40be-813f-10e167ed2d57
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112733539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_bit_bash.112733539
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.748960185
Short name T1033
Test name
Test status
Simulation time 419859972 ps
CPU time 2.84 seconds
Started Jul 27 05:28:14 PM PDT 24
Finished Jul 27 05:28:17 PM PDT 24
Peak memory 217868 kb
Host smart-af7378c9-5dae-451c-88ca-c549ba5678f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748960185 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.748960185
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.1728201883
Short name T121
Test name
Test status
Simulation time 67103029 ps
CPU time 2.01 seconds
Started Jul 27 05:28:13 PM PDT 24
Finished Jul 27 05:28:15 PM PDT 24
Peak memory 215400 kb
Host smart-0e3f9625-e307-46ec-ad4b-47455ab2f0c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728201883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.1
728201883
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3650884490
Short name T1039
Test name
Test status
Simulation time 165549075 ps
CPU time 0.73 seconds
Started Jul 27 05:28:12 PM PDT 24
Finished Jul 27 05:28:13 PM PDT 24
Peak memory 204148 kb
Host smart-c69b9503-dcd1-4cae-a0ce-87702570dec1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650884490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.3
650884490
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.1226443147
Short name T123
Test name
Test status
Simulation time 19384181 ps
CPU time 1.26 seconds
Started Jul 27 05:28:11 PM PDT 24
Finished Jul 27 05:28:12 PM PDT 24
Peak memory 215216 kb
Host smart-67ebf368-1f5d-45b6-b78e-5119f90092fb
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226443147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.1226443147
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.477218977
Short name T1041
Test name
Test status
Simulation time 37877336 ps
CPU time 0.69 seconds
Started Jul 27 05:28:16 PM PDT 24
Finished Jul 27 05:28:17 PM PDT 24
Peak memory 204132 kb
Host smart-540e0c2e-2fcc-4fb9-8f42-94797fc90884
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477218977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem
_walk.477218977
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.270016441
Short name T1051
Test name
Test status
Simulation time 218682070 ps
CPU time 3.32 seconds
Started Jul 27 05:28:15 PM PDT 24
Finished Jul 27 05:28:18 PM PDT 24
Peak memory 215388 kb
Host smart-73671af8-27c5-44ba-8de4-c5fdbf34ccfe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270016441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sp
i_device_same_csr_outstanding.270016441
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2569350892
Short name T1074
Test name
Test status
Simulation time 2394162133 ps
CPU time 12.91 seconds
Started Jul 27 05:28:14 PM PDT 24
Finished Jul 27 05:28:27 PM PDT 24
Peak memory 215984 kb
Host smart-54617bcd-23ba-4717-87aa-56b53b437de3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569350892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.2569350892
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.867108907
Short name T1046
Test name
Test status
Simulation time 317567703 ps
CPU time 2.52 seconds
Started Jul 27 05:28:24 PM PDT 24
Finished Jul 27 05:28:27 PM PDT 24
Peak memory 216936 kb
Host smart-1d52e5ed-1454-4da9-826c-fa36d15d787c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867108907 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.867108907
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3080352985
Short name T132
Test name
Test status
Simulation time 185012235 ps
CPU time 2.48 seconds
Started Jul 27 05:28:21 PM PDT 24
Finished Jul 27 05:28:24 PM PDT 24
Peak memory 215408 kb
Host smart-52f2d67d-79f3-4b2d-81b5-78277d821a5b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080352985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
3080352985
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.3513805673
Short name T1064
Test name
Test status
Simulation time 14971842 ps
CPU time 0.69 seconds
Started Jul 27 05:28:24 PM PDT 24
Finished Jul 27 05:28:25 PM PDT 24
Peak memory 203912 kb
Host smart-b26d1453-e9ed-4f70-b21c-3f69c41372f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513805673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
3513805673
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.3643558428
Short name T1017
Test name
Test status
Simulation time 229824181 ps
CPU time 1.9 seconds
Started Jul 27 05:28:24 PM PDT 24
Finished Jul 27 05:28:26 PM PDT 24
Peak memory 215452 kb
Host smart-6382f920-54d1-41dd-b231-f9bda39126bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643558428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.3643558428
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.2168453791
Short name T1079
Test name
Test status
Simulation time 334222297 ps
CPU time 2.51 seconds
Started Jul 27 05:28:26 PM PDT 24
Finished Jul 27 05:28:29 PM PDT 24
Peak memory 215468 kb
Host smart-b9318582-35ce-4e23-b42c-6e7d740f50e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168453791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
2168453791
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.2391732569
Short name T1052
Test name
Test status
Simulation time 212517777 ps
CPU time 12.52 seconds
Started Jul 27 05:28:23 PM PDT 24
Finished Jul 27 05:28:36 PM PDT 24
Peak memory 215288 kb
Host smart-1f5146b3-aeea-4d35-bcab-8446e4c6156a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391732569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.2391732569
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3614359653
Short name T1025
Test name
Test status
Simulation time 133819275 ps
CPU time 2.61 seconds
Started Jul 27 05:28:22 PM PDT 24
Finished Jul 27 05:28:25 PM PDT 24
Peak memory 217036 kb
Host smart-80cffdc4-fdd3-4e7e-9425-397ffedfaae9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614359653 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.3614359653
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.353717634
Short name T122
Test name
Test status
Simulation time 83321265 ps
CPU time 1.7 seconds
Started Jul 27 05:28:22 PM PDT 24
Finished Jul 27 05:28:23 PM PDT 24
Peak memory 207236 kb
Host smart-49d79b09-c0cf-49b4-9043-6ffd11c92ec5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353717634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.353717634
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.342048520
Short name T1026
Test name
Test status
Simulation time 27700125 ps
CPU time 0.72 seconds
Started Jul 27 05:28:23 PM PDT 24
Finished Jul 27 05:28:24 PM PDT 24
Peak memory 203772 kb
Host smart-b8f33208-b19f-465a-9519-f8bc5cd91dcc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342048520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.342048520
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.553960190
Short name T1042
Test name
Test status
Simulation time 26338526 ps
CPU time 1.77 seconds
Started Jul 27 05:28:25 PM PDT 24
Finished Jul 27 05:28:27 PM PDT 24
Peak memory 215360 kb
Host smart-1b97c01b-7d1d-4ecc-9e70-2f758b26331c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553960190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.s
pi_device_same_csr_outstanding.553960190
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.2615648720
Short name T116
Test name
Test status
Simulation time 205082600 ps
CPU time 3.77 seconds
Started Jul 27 05:28:33 PM PDT 24
Finished Jul 27 05:28:37 PM PDT 24
Peak memory 217388 kb
Host smart-74205b92-e935-4dc5-801c-df836413e4d7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615648720 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.2615648720
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2766818975
Short name T1106
Test name
Test status
Simulation time 38848018 ps
CPU time 1.35 seconds
Started Jul 27 05:28:23 PM PDT 24
Finished Jul 27 05:28:24 PM PDT 24
Peak memory 207152 kb
Host smart-269939bc-d549-4b58-940c-53dca7fe56a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766818975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
2766818975
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.60025603
Short name T1015
Test name
Test status
Simulation time 14032183 ps
CPU time 0.72 seconds
Started Jul 27 05:28:24 PM PDT 24
Finished Jul 27 05:28:25 PM PDT 24
Peak memory 204188 kb
Host smart-8c8867ea-62e6-467b-bf0d-4f57aef88077
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60025603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.60025603
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3851907854
Short name T1032
Test name
Test status
Simulation time 285961417 ps
CPU time 1.7 seconds
Started Jul 27 05:28:32 PM PDT 24
Finished Jul 27 05:28:34 PM PDT 24
Peak memory 215412 kb
Host smart-0f2a804a-5496-467e-883c-158619ea1d16
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851907854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.3851907854
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3381393752
Short name T108
Test name
Test status
Simulation time 276086925 ps
CPU time 2.43 seconds
Started Jul 27 05:28:24 PM PDT 24
Finished Jul 27 05:28:27 PM PDT 24
Peak memory 215504 kb
Host smart-478ddf36-4a2a-4eff-af7c-9946ce130894
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381393752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
3381393752
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.275507243
Short name T1080
Test name
Test status
Simulation time 1650330593 ps
CPU time 23.45 seconds
Started Jul 27 05:28:20 PM PDT 24
Finished Jul 27 05:28:43 PM PDT 24
Peak memory 215576 kb
Host smart-32296f03-1c4d-48bb-b30a-3ce6836579a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275507243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device
_tl_intg_err.275507243
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.4192375146
Short name T103
Test name
Test status
Simulation time 159193461 ps
CPU time 3.93 seconds
Started Jul 27 05:28:38 PM PDT 24
Finished Jul 27 05:28:42 PM PDT 24
Peak memory 218240 kb
Host smart-e0ebd0f8-d9f2-4d5a-9b4b-aeb80a4757c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192375146 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.4192375146
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.4262584228
Short name T1070
Test name
Test status
Simulation time 83480435 ps
CPU time 2.39 seconds
Started Jul 27 05:28:33 PM PDT 24
Finished Jul 27 05:28:35 PM PDT 24
Peak memory 207252 kb
Host smart-f70ea942-4cbb-42a6-b645-39c54e6f4467
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262584228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
4262584228
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.4058178754
Short name T1103
Test name
Test status
Simulation time 122255919 ps
CPU time 0.74 seconds
Started Jul 27 05:28:33 PM PDT 24
Finished Jul 27 05:28:34 PM PDT 24
Peak memory 204252 kb
Host smart-b50ad6be-f58c-4641-aedf-adf3947a4420
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058178754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
4058178754
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.128310502
Short name T1108
Test name
Test status
Simulation time 212625326 ps
CPU time 3.81 seconds
Started Jul 27 05:28:34 PM PDT 24
Finished Jul 27 05:28:38 PM PDT 24
Peak memory 215484 kb
Host smart-4de33ac0-db27-4255-abdd-8c64452cb634
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128310502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.s
pi_device_same_csr_outstanding.128310502
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.784356268
Short name T1094
Test name
Test status
Simulation time 140210048 ps
CPU time 4.85 seconds
Started Jul 27 05:28:37 PM PDT 24
Finished Jul 27 05:28:42 PM PDT 24
Peak memory 216640 kb
Host smart-cc709472-a281-4f89-92bb-4d5fd28696c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784356268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.784356268
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.4018196899
Short name T167
Test name
Test status
Simulation time 871980938 ps
CPU time 20.22 seconds
Started Jul 27 05:28:33 PM PDT 24
Finished Jul 27 05:28:53 PM PDT 24
Peak memory 217240 kb
Host smart-e8200085-9054-4130-9f1d-427035e00037
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018196899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.4018196899
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2745648973
Short name T1047
Test name
Test status
Simulation time 162922088 ps
CPU time 4.06 seconds
Started Jul 27 05:28:36 PM PDT 24
Finished Jul 27 05:28:40 PM PDT 24
Peak memory 218436 kb
Host smart-3cc62a93-77a9-4f2a-aff2-d7e05d77d4bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745648973 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.2745648973
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.2790099292
Short name T128
Test name
Test status
Simulation time 139079792 ps
CPU time 2.48 seconds
Started Jul 27 05:28:34 PM PDT 24
Finished Jul 27 05:28:36 PM PDT 24
Peak memory 215416 kb
Host smart-7f3108a3-b5f0-4a31-a530-923e8296c7b2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790099292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
2790099292
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2812318394
Short name T1034
Test name
Test status
Simulation time 12686381 ps
CPU time 0.74 seconds
Started Jul 27 05:28:35 PM PDT 24
Finished Jul 27 05:28:36 PM PDT 24
Peak memory 203908 kb
Host smart-6d2a6dc4-364f-48bb-97d3-11b5f18ecc13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812318394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
2812318394
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.683522287
Short name T1014
Test name
Test status
Simulation time 26586214 ps
CPU time 1.72 seconds
Started Jul 27 05:28:35 PM PDT 24
Finished Jul 27 05:28:37 PM PDT 24
Peak memory 215388 kb
Host smart-16e8e72b-1c0b-4617-be12-4680c5b46745
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683522287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.s
pi_device_same_csr_outstanding.683522287
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.3836664804
Short name T1062
Test name
Test status
Simulation time 293448193 ps
CPU time 1.96 seconds
Started Jul 27 05:28:38 PM PDT 24
Finished Jul 27 05:28:40 PM PDT 24
Peak memory 215440 kb
Host smart-78fcbca7-3fb6-4563-a80b-fe334cde2b88
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836664804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
3836664804
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2254291201
Short name T1038
Test name
Test status
Simulation time 265657450 ps
CPU time 1.86 seconds
Started Jul 27 05:28:30 PM PDT 24
Finished Jul 27 05:28:32 PM PDT 24
Peak memory 216488 kb
Host smart-a58f3bc6-1bfe-4df7-89c1-8ab06f04a04a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254291201 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.2254291201
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.3054942535
Short name T127
Test name
Test status
Simulation time 28635807 ps
CPU time 1.72 seconds
Started Jul 27 05:28:38 PM PDT 24
Finished Jul 27 05:28:39 PM PDT 24
Peak memory 215312 kb
Host smart-6df7d70d-d52b-46dd-8928-91d95198af9f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054942535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
3054942535
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.25125911
Short name T1095
Test name
Test status
Simulation time 50551467 ps
CPU time 0.72 seconds
Started Jul 27 05:28:33 PM PDT 24
Finished Jul 27 05:28:34 PM PDT 24
Peak memory 203868 kb
Host smart-a4b27cdd-19f7-4e0c-90f8-15a40df11458
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25125911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.25125911
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.4214363794
Short name T1117
Test name
Test status
Simulation time 162338576 ps
CPU time 2.97 seconds
Started Jul 27 05:28:33 PM PDT 24
Finished Jul 27 05:28:36 PM PDT 24
Peak memory 215520 kb
Host smart-5a19558e-ad30-4292-bb36-19bec2dc07d6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214363794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.4214363794
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.1956748461
Short name T1056
Test name
Test status
Simulation time 121385667 ps
CPU time 3.22 seconds
Started Jul 27 05:28:36 PM PDT 24
Finished Jul 27 05:28:40 PM PDT 24
Peak memory 215396 kb
Host smart-af322d98-8729-468c-8da3-c3b1cf90609f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956748461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
1956748461
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.3213156307
Short name T170
Test name
Test status
Simulation time 788087488 ps
CPU time 12.72 seconds
Started Jul 27 05:28:34 PM PDT 24
Finished Jul 27 05:28:47 PM PDT 24
Peak memory 215456 kb
Host smart-ac8ad0da-974c-47b7-a57c-cf99af323c3d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213156307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.3213156307
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3673626607
Short name T1084
Test name
Test status
Simulation time 490395629 ps
CPU time 3.89 seconds
Started Jul 27 05:28:33 PM PDT 24
Finished Jul 27 05:28:37 PM PDT 24
Peak memory 217364 kb
Host smart-9e56d2b7-caa2-4926-bd7b-0391b548d974
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673626607 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.3673626607
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2097824903
Short name T131
Test name
Test status
Simulation time 118127971 ps
CPU time 2.83 seconds
Started Jul 27 05:28:32 PM PDT 24
Finished Jul 27 05:28:35 PM PDT 24
Peak memory 207196 kb
Host smart-8236760e-b8e8-4888-89d0-adfbc5673dee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097824903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
2097824903
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3547194462
Short name T1119
Test name
Test status
Simulation time 20176033 ps
CPU time 0.7 seconds
Started Jul 27 05:28:38 PM PDT 24
Finished Jul 27 05:28:39 PM PDT 24
Peak memory 203844 kb
Host smart-a6460045-f321-484d-b682-d1c783d3d6f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547194462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
3547194462
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.2905761498
Short name T1040
Test name
Test status
Simulation time 502520788 ps
CPU time 4.35 seconds
Started Jul 27 05:28:32 PM PDT 24
Finished Jul 27 05:28:37 PM PDT 24
Peak memory 215500 kb
Host smart-8466a9ef-312d-43da-a3ec-4c4ee9895ec9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905761498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.2905761498
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.380652712
Short name T1044
Test name
Test status
Simulation time 62107462 ps
CPU time 1.73 seconds
Started Jul 27 05:28:33 PM PDT 24
Finished Jul 27 05:28:35 PM PDT 24
Peak memory 216468 kb
Host smart-5749bf13-1aeb-4936-ae3a-c447b273f0bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380652712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.380652712
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1750894251
Short name T1077
Test name
Test status
Simulation time 1112598455 ps
CPU time 21.96 seconds
Started Jul 27 05:28:38 PM PDT 24
Finished Jul 27 05:29:00 PM PDT 24
Peak memory 215484 kb
Host smart-5a368ef1-5542-4b92-aff2-99216ed304e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750894251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.1750894251
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.930267217
Short name T1124
Test name
Test status
Simulation time 217525309 ps
CPU time 1.67 seconds
Started Jul 27 05:28:33 PM PDT 24
Finished Jul 27 05:28:34 PM PDT 24
Peak memory 215360 kb
Host smart-dfc39dc5-58f1-4782-8a79-b7ca57f7381b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930267217 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.930267217
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1840981481
Short name T130
Test name
Test status
Simulation time 41822201 ps
CPU time 1.45 seconds
Started Jul 27 05:28:34 PM PDT 24
Finished Jul 27 05:28:35 PM PDT 24
Peak memory 215484 kb
Host smart-96f77eff-4deb-4203-98ae-6ccc20157294
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840981481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
1840981481
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.2863842788
Short name T1049
Test name
Test status
Simulation time 14401165 ps
CPU time 0.72 seconds
Started Jul 27 05:28:35 PM PDT 24
Finished Jul 27 05:28:36 PM PDT 24
Peak memory 203912 kb
Host smart-e32b0bec-d5de-4d73-954c-eb9608570766
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863842788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
2863842788
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3663724658
Short name T146
Test name
Test status
Simulation time 143901932 ps
CPU time 3.1 seconds
Started Jul 27 05:28:38 PM PDT 24
Finished Jul 27 05:28:41 PM PDT 24
Peak memory 216000 kb
Host smart-ae5b3b85-4154-4b74-9984-18b660498bd4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663724658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.3663724658
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.2503924283
Short name T69
Test name
Test status
Simulation time 68440608 ps
CPU time 5.3 seconds
Started Jul 27 05:28:37 PM PDT 24
Finished Jul 27 05:28:42 PM PDT 24
Peak memory 215472 kb
Host smart-6732b9fe-a1bb-4f0a-92af-572efeee01fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503924283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
2503924283
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2972067219
Short name T1023
Test name
Test status
Simulation time 493916408 ps
CPU time 3.74 seconds
Started Jul 27 05:28:37 PM PDT 24
Finished Jul 27 05:28:41 PM PDT 24
Peak memory 217480 kb
Host smart-2f572154-b155-46f3-a11a-a38c8d697537
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972067219 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.2972067219
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1179815095
Short name T126
Test name
Test status
Simulation time 183875481 ps
CPU time 2.88 seconds
Started Jul 27 05:28:33 PM PDT 24
Finished Jul 27 05:28:36 PM PDT 24
Peak memory 215660 kb
Host smart-0e99d576-fcae-4404-aeb4-c2db2570ea8a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179815095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
1179815095
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1611086918
Short name T1114
Test name
Test status
Simulation time 12840503 ps
CPU time 0.78 seconds
Started Jul 27 05:28:34 PM PDT 24
Finished Jul 27 05:28:34 PM PDT 24
Peak memory 203844 kb
Host smart-1dc4cfc3-2203-47fc-84f3-a7ed6f417e82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611086918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
1611086918
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2515366675
Short name T147
Test name
Test status
Simulation time 116462675 ps
CPU time 1.83 seconds
Started Jul 27 05:28:32 PM PDT 24
Finished Jul 27 05:28:34 PM PDT 24
Peak memory 215432 kb
Host smart-6d24d761-941f-46aa-afb4-b18edf0385ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515366675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.2515366675
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.2753881961
Short name T1104
Test name
Test status
Simulation time 155601931 ps
CPU time 4.43 seconds
Started Jul 27 05:28:34 PM PDT 24
Finished Jul 27 05:28:39 PM PDT 24
Peak memory 215408 kb
Host smart-8a49cbe7-28d6-4e22-9cd5-b59141ab86b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753881961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
2753881961
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1737309546
Short name T169
Test name
Test status
Simulation time 1868561598 ps
CPU time 8.65 seconds
Started Jul 27 05:28:35 PM PDT 24
Finished Jul 27 05:28:44 PM PDT 24
Peak memory 215304 kb
Host smart-d9ddc345-4298-4526-920e-c86a0f9be3e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737309546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.1737309546
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2001690296
Short name T1066
Test name
Test status
Simulation time 152817363 ps
CPU time 2.63 seconds
Started Jul 27 05:28:43 PM PDT 24
Finished Jul 27 05:28:46 PM PDT 24
Peak memory 217212 kb
Host smart-98e16b65-6148-4790-a193-6a2e1366b555
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001690296 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.2001690296
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1352061516
Short name T1100
Test name
Test status
Simulation time 21140335 ps
CPU time 1.54 seconds
Started Jul 27 05:28:43 PM PDT 24
Finished Jul 27 05:28:45 PM PDT 24
Peak memory 215364 kb
Host smart-5c056994-e7db-4293-ac49-38383256ee18
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352061516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
1352061516
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2261468374
Short name T1110
Test name
Test status
Simulation time 53318275 ps
CPU time 0.71 seconds
Started Jul 27 05:28:44 PM PDT 24
Finished Jul 27 05:28:45 PM PDT 24
Peak memory 204220 kb
Host smart-ccc6db01-fb16-433e-a748-34a166ec45eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261468374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
2261468374
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.3326543434
Short name T1099
Test name
Test status
Simulation time 27208584 ps
CPU time 1.86 seconds
Started Jul 27 05:28:41 PM PDT 24
Finished Jul 27 05:28:43 PM PDT 24
Peak memory 215432 kb
Host smart-91208a67-f989-40ec-a70c-0de99824b4a5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326543434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.3326543434
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2296779877
Short name T1085
Test name
Test status
Simulation time 200866554 ps
CPU time 2.72 seconds
Started Jul 27 05:28:33 PM PDT 24
Finished Jul 27 05:28:36 PM PDT 24
Peak memory 216552 kb
Host smart-206245cc-410a-43a8-80c8-fad1843b0a3b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296779877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
2296779877
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1707737675
Short name T1118
Test name
Test status
Simulation time 571879396 ps
CPU time 6.97 seconds
Started Jul 27 05:28:34 PM PDT 24
Finished Jul 27 05:28:41 PM PDT 24
Peak memory 215448 kb
Host smart-407e73ec-75ff-4243-9047-15986b50e9f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707737675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.1707737675
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2121675887
Short name T124
Test name
Test status
Simulation time 4766705792 ps
CPU time 24.97 seconds
Started Jul 27 05:28:17 PM PDT 24
Finished Jul 27 05:28:42 PM PDT 24
Peak memory 215496 kb
Host smart-83d0fe71-c44f-419f-bf12-178d91714f54
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121675887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.2121675887
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1606825063
Short name T1112
Test name
Test status
Simulation time 1240396067 ps
CPU time 13.31 seconds
Started Jul 27 05:28:15 PM PDT 24
Finished Jul 27 05:28:28 PM PDT 24
Peak memory 207108 kb
Host smart-1e254bdb-c488-4810-8dc0-bc03702660fc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606825063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.1606825063
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2790350861
Short name T89
Test name
Test status
Simulation time 35014283 ps
CPU time 1.26 seconds
Started Jul 27 05:28:13 PM PDT 24
Finished Jul 27 05:28:14 PM PDT 24
Peak memory 217476 kb
Host smart-75266088-ae2c-4dd1-94f1-0bd6ef09419b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790350861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.2790350861
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1936041287
Short name T1068
Test name
Test status
Simulation time 56974523 ps
CPU time 1.94 seconds
Started Jul 27 05:28:15 PM PDT 24
Finished Jul 27 05:28:17 PM PDT 24
Peak memory 215724 kb
Host smart-7b783b69-a764-465a-9916-52d2266cc8d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936041287 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.1936041287
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2423838256
Short name T1105
Test name
Test status
Simulation time 152251406 ps
CPU time 1.35 seconds
Started Jul 27 05:28:13 PM PDT 24
Finished Jul 27 05:28:15 PM PDT 24
Peak memory 215436 kb
Host smart-cbb35204-b76f-4678-bb97-77441318910d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423838256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.2
423838256
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.3337968641
Short name T1096
Test name
Test status
Simulation time 159364071 ps
CPU time 0.76 seconds
Started Jul 27 05:28:16 PM PDT 24
Finished Jul 27 05:28:16 PM PDT 24
Peak memory 203848 kb
Host smart-95b57390-1e7f-47e1-8ce7-d9fca8b53b95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337968641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.3
337968641
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2528316626
Short name T1102
Test name
Test status
Simulation time 35637596 ps
CPU time 1.17 seconds
Started Jul 27 05:28:13 PM PDT 24
Finished Jul 27 05:28:14 PM PDT 24
Peak memory 215352 kb
Host smart-bcd376d3-9511-4b76-87d8-ad633c13e5fb
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528316626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.2528316626
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.2010872482
Short name T1011
Test name
Test status
Simulation time 30007617 ps
CPU time 0.7 seconds
Started Jul 27 05:28:15 PM PDT 24
Finished Jul 27 05:28:16 PM PDT 24
Peak memory 203792 kb
Host smart-4a007b53-d8bf-423b-a421-934b555b02a4
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010872482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.2010872482
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3547801017
Short name T149
Test name
Test status
Simulation time 78242431 ps
CPU time 1.93 seconds
Started Jul 27 05:28:12 PM PDT 24
Finished Jul 27 05:28:14 PM PDT 24
Peak memory 215408 kb
Host smart-b8542706-1556-4a8f-8ae0-18669f73cf4e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547801017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.3547801017
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3862589996
Short name T111
Test name
Test status
Simulation time 43239672 ps
CPU time 2.65 seconds
Started Jul 27 05:28:13 PM PDT 24
Finished Jul 27 05:28:16 PM PDT 24
Peak memory 216504 kb
Host smart-9baec858-9a60-4367-b32b-a20399a7de54
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862589996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.3
862589996
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.3236382777
Short name T70
Test name
Test status
Simulation time 110207937 ps
CPU time 6.95 seconds
Started Jul 27 05:28:11 PM PDT 24
Finished Jul 27 05:28:18 PM PDT 24
Peak memory 215476 kb
Host smart-d88af862-7009-47b0-adc8-ed5d94297c60
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236382777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.3236382777
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.1921845303
Short name T1093
Test name
Test status
Simulation time 11565922 ps
CPU time 0.72 seconds
Started Jul 27 05:28:41 PM PDT 24
Finished Jul 27 05:28:42 PM PDT 24
Peak memory 203948 kb
Host smart-dc7eb11a-d1e2-49dc-8bc0-62a73957ba0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921845303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
1921845303
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.1965872956
Short name T1030
Test name
Test status
Simulation time 37855739 ps
CPU time 0.71 seconds
Started Jul 27 05:28:42 PM PDT 24
Finished Jul 27 05:28:43 PM PDT 24
Peak memory 204248 kb
Host smart-ff85af97-ddc0-470b-960d-c629627fc06a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965872956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
1965872956
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3840500404
Short name T1075
Test name
Test status
Simulation time 19401832 ps
CPU time 0.79 seconds
Started Jul 27 05:28:42 PM PDT 24
Finished Jul 27 05:28:43 PM PDT 24
Peak memory 204204 kb
Host smart-3132748b-4f2d-45fe-a33b-8718df7ed578
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840500404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
3840500404
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.5748374
Short name T1013
Test name
Test status
Simulation time 211598850 ps
CPU time 0.74 seconds
Started Jul 27 05:28:41 PM PDT 24
Finished Jul 27 05:28:42 PM PDT 24
Peak memory 203936 kb
Host smart-80c36625-f3d6-4aa9-b0a5-bff9325139bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5748374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.5748374
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1258642513
Short name T1054
Test name
Test status
Simulation time 55781475 ps
CPU time 0.7 seconds
Started Jul 27 05:28:41 PM PDT 24
Finished Jul 27 05:28:42 PM PDT 24
Peak memory 204160 kb
Host smart-ff317dd3-1d14-4835-9129-ae3e4b8df260
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258642513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
1258642513
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.84649276
Short name T1092
Test name
Test status
Simulation time 98468030 ps
CPU time 0.73 seconds
Started Jul 27 05:28:42 PM PDT 24
Finished Jul 27 05:28:43 PM PDT 24
Peak memory 203908 kb
Host smart-ff606cdd-1346-4fcd-8f36-ff547e6acacd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84649276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.84649276
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.3458145276
Short name T1058
Test name
Test status
Simulation time 52173324 ps
CPU time 0.77 seconds
Started Jul 27 05:28:42 PM PDT 24
Finished Jul 27 05:28:43 PM PDT 24
Peak memory 203832 kb
Host smart-277a9358-803d-4bf7-b2ca-f48325e638d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458145276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
3458145276
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.4187945076
Short name T1071
Test name
Test status
Simulation time 12721919 ps
CPU time 0.71 seconds
Started Jul 27 05:28:40 PM PDT 24
Finished Jul 27 05:28:41 PM PDT 24
Peak memory 203856 kb
Host smart-bc2ae312-ac2d-43de-a6d9-3766fbb44f05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187945076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
4187945076
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.515200241
Short name T1043
Test name
Test status
Simulation time 53157583 ps
CPU time 0.75 seconds
Started Jul 27 05:28:42 PM PDT 24
Finished Jul 27 05:28:43 PM PDT 24
Peak memory 203936 kb
Host smart-33129253-379d-4f86-a83d-796d46182b07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515200241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.515200241
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2285976781
Short name T1008
Test name
Test status
Simulation time 30835624 ps
CPU time 0.71 seconds
Started Jul 27 05:28:45 PM PDT 24
Finished Jul 27 05:28:46 PM PDT 24
Peak memory 203828 kb
Host smart-a22c6fd8-ad48-41f0-8304-63394ee7e80a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285976781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
2285976781
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.1852927255
Short name T1063
Test name
Test status
Simulation time 2506734689 ps
CPU time 15.9 seconds
Started Jul 27 05:28:12 PM PDT 24
Finished Jul 27 05:28:28 PM PDT 24
Peak memory 207184 kb
Host smart-b66c2069-5d83-4bce-bce3-38a22cba40d2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852927255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.1852927255
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1530140898
Short name T1021
Test name
Test status
Simulation time 638128487 ps
CPU time 13.01 seconds
Started Jul 27 05:28:13 PM PDT 24
Finished Jul 27 05:28:26 PM PDT 24
Peak memory 207232 kb
Host smart-5fd51aa5-f404-4b54-b119-508909b275a7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530140898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.1530140898
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3070743674
Short name T88
Test name
Test status
Simulation time 58017833 ps
CPU time 1.27 seconds
Started Jul 27 05:28:16 PM PDT 24
Finished Jul 27 05:28:17 PM PDT 24
Peak memory 215316 kb
Host smart-8316fa20-160d-4f8d-8d16-c51490a71fa3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070743674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.3070743674
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2151200049
Short name T1057
Test name
Test status
Simulation time 196811819 ps
CPU time 1.89 seconds
Started Jul 27 05:28:12 PM PDT 24
Finished Jul 27 05:28:14 PM PDT 24
Peak memory 215412 kb
Host smart-2a99704b-1d1d-44c6-b577-d9ef085f5e5e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151200049 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.2151200049
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.264472504
Short name T1123
Test name
Test status
Simulation time 197752260 ps
CPU time 2.59 seconds
Started Jul 27 05:28:15 PM PDT 24
Finished Jul 27 05:28:18 PM PDT 24
Peak memory 207224 kb
Host smart-682c278d-60d9-40f6-898b-8eab8f62bd3b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264472504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.264472504
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.2755680472
Short name T1090
Test name
Test status
Simulation time 30191204 ps
CPU time 0.75 seconds
Started Jul 27 05:28:16 PM PDT 24
Finished Jul 27 05:28:17 PM PDT 24
Peak memory 203840 kb
Host smart-ec401af1-1e35-4a13-b30e-cdc7d6a6f609
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755680472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.2
755680472
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.1676416697
Short name T1127
Test name
Test status
Simulation time 62448884 ps
CPU time 2.21 seconds
Started Jul 27 05:28:14 PM PDT 24
Finished Jul 27 05:28:16 PM PDT 24
Peak memory 215416 kb
Host smart-e6bc2e7e-dbf2-48c8-8a84-55b07d5ef198
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676416697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.1676416697
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1716301597
Short name T1086
Test name
Test status
Simulation time 14018695 ps
CPU time 0.68 seconds
Started Jul 27 05:28:15 PM PDT 24
Finished Jul 27 05:28:15 PM PDT 24
Peak memory 204220 kb
Host smart-c9a2c4c8-2700-4285-8146-419e8a681b31
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716301597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.1716301597
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1502423346
Short name T1018
Test name
Test status
Simulation time 794526051 ps
CPU time 4.48 seconds
Started Jul 27 05:28:13 PM PDT 24
Finished Jul 27 05:28:17 PM PDT 24
Peak memory 215412 kb
Host smart-3f7e02ef-b03e-4f51-9b4d-1f7b87db4a3d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502423346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.1502423346
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.3336688611
Short name T106
Test name
Test status
Simulation time 130253549 ps
CPU time 3.45 seconds
Started Jul 27 05:28:15 PM PDT 24
Finished Jul 27 05:28:19 PM PDT 24
Peak memory 215804 kb
Host smart-d23f3292-962a-497e-87e1-10e0ed1905ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336688611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.3
336688611
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.217650145
Short name T1016
Test name
Test status
Simulation time 15931074 ps
CPU time 0.8 seconds
Started Jul 27 05:28:43 PM PDT 24
Finished Jul 27 05:28:44 PM PDT 24
Peak memory 203920 kb
Host smart-e975aa3d-9ebb-49c1-97b4-50a2d783609b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217650145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.217650145
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.934083133
Short name T1050
Test name
Test status
Simulation time 13760300 ps
CPU time 0.72 seconds
Started Jul 27 05:28:41 PM PDT 24
Finished Jul 27 05:28:42 PM PDT 24
Peak memory 204248 kb
Host smart-d9b2dff8-e217-47e4-826b-40d56f587c90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934083133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.934083133
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.3219578643
Short name T1048
Test name
Test status
Simulation time 15910966 ps
CPU time 0.75 seconds
Started Jul 27 05:28:43 PM PDT 24
Finished Jul 27 05:28:44 PM PDT 24
Peak memory 203916 kb
Host smart-be5cfb2e-e370-40ee-9bfe-d88a0a97c2a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219578643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
3219578643
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.1599395817
Short name T1126
Test name
Test status
Simulation time 34112836 ps
CPU time 0.66 seconds
Started Jul 27 05:28:41 PM PDT 24
Finished Jul 27 05:28:42 PM PDT 24
Peak memory 203936 kb
Host smart-84f98948-ae6f-4c3f-b218-90f9fb5ae27d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599395817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
1599395817
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.2856195691
Short name T1024
Test name
Test status
Simulation time 14709807 ps
CPU time 0.73 seconds
Started Jul 27 05:28:41 PM PDT 24
Finished Jul 27 05:28:42 PM PDT 24
Peak memory 203916 kb
Host smart-c35c668c-c81b-4322-af1a-fd271b5553f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856195691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
2856195691
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.1032424634
Short name T1073
Test name
Test status
Simulation time 16469679 ps
CPU time 0.78 seconds
Started Jul 27 05:28:43 PM PDT 24
Finished Jul 27 05:28:44 PM PDT 24
Peak memory 203816 kb
Host smart-87a4709c-ecd2-40a3-a28c-9cf1e6577f28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032424634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
1032424634
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.1162007969
Short name T1087
Test name
Test status
Simulation time 26645424 ps
CPU time 0.73 seconds
Started Jul 27 05:28:41 PM PDT 24
Finished Jul 27 05:28:42 PM PDT 24
Peak memory 203944 kb
Host smart-ef7dac3e-5756-41b7-8f19-76043bc83f49
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162007969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
1162007969
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.441622236
Short name T1116
Test name
Test status
Simulation time 55243249 ps
CPU time 0.75 seconds
Started Jul 27 05:28:41 PM PDT 24
Finished Jul 27 05:28:41 PM PDT 24
Peak memory 204228 kb
Host smart-b71918fe-98a3-4953-aaff-e1bd48e7c624
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441622236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.441622236
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.3034939482
Short name T1031
Test name
Test status
Simulation time 13290804 ps
CPU time 0.7 seconds
Started Jul 27 05:28:43 PM PDT 24
Finished Jul 27 05:28:44 PM PDT 24
Peak memory 203928 kb
Host smart-4e566ef2-9606-49e7-b11c-bd280aab0894
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034939482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
3034939482
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.410442308
Short name T1088
Test name
Test status
Simulation time 14405677 ps
CPU time 0.7 seconds
Started Jul 27 05:28:43 PM PDT 24
Finished Jul 27 05:28:44 PM PDT 24
Peak memory 204192 kb
Host smart-2b26c84d-3700-434c-922a-3cda2a59ddea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410442308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.410442308
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.2190394680
Short name T1009
Test name
Test status
Simulation time 450605492 ps
CPU time 15.32 seconds
Started Jul 27 05:28:17 PM PDT 24
Finished Jul 27 05:28:32 PM PDT 24
Peak memory 215432 kb
Host smart-f1bbf067-ed4b-4c15-9207-638d0c177305
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190394680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.2190394680
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.1601452756
Short name T1115
Test name
Test status
Simulation time 5231200702 ps
CPU time 24.48 seconds
Started Jul 27 05:28:14 PM PDT 24
Finished Jul 27 05:28:38 PM PDT 24
Peak memory 207256 kb
Host smart-4e6b899d-3b3c-4f28-8393-536ae6e259d1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601452756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.1601452756
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.4189910664
Short name T1122
Test name
Test status
Simulation time 158253530 ps
CPU time 1.38 seconds
Started Jul 27 05:28:12 PM PDT 24
Finished Jul 27 05:28:13 PM PDT 24
Peak memory 217452 kb
Host smart-51630fd6-612d-4d45-b83e-b72d392ea17d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189910664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.4189910664
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1008164732
Short name T118
Test name
Test status
Simulation time 179721828 ps
CPU time 3.46 seconds
Started Jul 27 05:28:13 PM PDT 24
Finished Jul 27 05:28:17 PM PDT 24
Peak memory 218136 kb
Host smart-ad5fa466-8289-43ad-9518-ed0d336b5385
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008164732 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.1008164732
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1807160280
Short name T1065
Test name
Test status
Simulation time 1000738261 ps
CPU time 2.33 seconds
Started Jul 27 05:28:11 PM PDT 24
Finished Jul 27 05:28:14 PM PDT 24
Peak memory 215428 kb
Host smart-c86cf18e-2f92-44ed-97e2-6962be6baa65
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807160280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.1
807160280
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3471329176
Short name T1012
Test name
Test status
Simulation time 17201079 ps
CPU time 0.76 seconds
Started Jul 27 05:28:13 PM PDT 24
Finished Jul 27 05:28:14 PM PDT 24
Peak memory 203904 kb
Host smart-fda09125-c518-4b90-a0d0-5932eaec02bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471329176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.3
471329176
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.964721937
Short name T1061
Test name
Test status
Simulation time 45361473 ps
CPU time 1.73 seconds
Started Jul 27 05:28:14 PM PDT 24
Finished Jul 27 05:28:16 PM PDT 24
Peak memory 215344 kb
Host smart-264e034f-9200-4ae2-9004-653cd3a7441e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964721937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_
device_mem_partial_access.964721937
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.4032620707
Short name T1081
Test name
Test status
Simulation time 11026017 ps
CPU time 0.71 seconds
Started Jul 27 05:28:16 PM PDT 24
Finished Jul 27 05:28:17 PM PDT 24
Peak memory 203912 kb
Host smart-6bb66543-afe5-4837-a252-27a808e22ae0
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032620707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.4032620707
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2827363000
Short name T156
Test name
Test status
Simulation time 78229317 ps
CPU time 1.97 seconds
Started Jul 27 05:28:17 PM PDT 24
Finished Jul 27 05:28:19 PM PDT 24
Peak memory 207100 kb
Host smart-a68543c7-7da7-49f9-8ddf-d44b5b9c600c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827363000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.2827363000
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.1580754621
Short name T107
Test name
Test status
Simulation time 57933233 ps
CPU time 1.87 seconds
Started Jul 27 05:28:17 PM PDT 24
Finished Jul 27 05:28:19 PM PDT 24
Peak memory 215564 kb
Host smart-97013043-8318-4c6c-b466-b14456aca2b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580754621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.1
580754621
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.83018146
Short name T1130
Test name
Test status
Simulation time 1008376499 ps
CPU time 21.79 seconds
Started Jul 27 05:28:12 PM PDT 24
Finished Jul 27 05:28:34 PM PDT 24
Peak memory 215912 kb
Host smart-42ca7bb8-178f-4878-9524-e6f1c882d705
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83018146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_t
l_intg_err.83018146
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.4232427218
Short name T1069
Test name
Test status
Simulation time 28231316 ps
CPU time 0.78 seconds
Started Jul 27 05:28:46 PM PDT 24
Finished Jul 27 05:28:47 PM PDT 24
Peak memory 204148 kb
Host smart-9a40d687-d2e7-4877-9041-02f8238e3576
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232427218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
4232427218
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.3709903728
Short name T1020
Test name
Test status
Simulation time 60213122 ps
CPU time 0.77 seconds
Started Jul 27 05:28:43 PM PDT 24
Finished Jul 27 05:28:44 PM PDT 24
Peak memory 203920 kb
Host smart-56704aca-5846-4b7f-a704-bbff14dd7681
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709903728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
3709903728
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.1468244598
Short name T1113
Test name
Test status
Simulation time 46469230 ps
CPU time 0.73 seconds
Started Jul 27 05:28:39 PM PDT 24
Finished Jul 27 05:28:40 PM PDT 24
Peak memory 204124 kb
Host smart-b8832a0d-b04e-4076-84ed-748045de1473
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468244598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
1468244598
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.3821593053
Short name T1010
Test name
Test status
Simulation time 16002513 ps
CPU time 0.78 seconds
Started Jul 27 05:28:43 PM PDT 24
Finished Jul 27 05:28:43 PM PDT 24
Peak memory 203900 kb
Host smart-2e79ec7f-c6b1-48a5-9974-786618996799
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821593053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
3821593053
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1133379111
Short name T1083
Test name
Test status
Simulation time 12316722 ps
CPU time 0.67 seconds
Started Jul 27 05:28:41 PM PDT 24
Finished Jul 27 05:28:41 PM PDT 24
Peak memory 203936 kb
Host smart-1260f302-c8a9-4164-8a96-f6d3e7207492
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133379111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
1133379111
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.777195725
Short name T1028
Test name
Test status
Simulation time 138195463 ps
CPU time 0.74 seconds
Started Jul 27 05:28:44 PM PDT 24
Finished Jul 27 05:28:44 PM PDT 24
Peak memory 203880 kb
Host smart-b631d1d5-8bdc-45c5-91de-ee8c73fbc824
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777195725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.777195725
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.3813267730
Short name T1120
Test name
Test status
Simulation time 17410681 ps
CPU time 0.75 seconds
Started Jul 27 05:28:41 PM PDT 24
Finished Jul 27 05:28:42 PM PDT 24
Peak memory 204176 kb
Host smart-a99984d9-74e7-462e-8812-21c1b43bf4a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813267730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
3813267730
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.1695757643
Short name T1037
Test name
Test status
Simulation time 64260407 ps
CPU time 0.76 seconds
Started Jul 27 05:28:45 PM PDT 24
Finished Jul 27 05:28:46 PM PDT 24
Peak memory 203840 kb
Host smart-5abf33ea-4a0f-4f20-91e9-8fb603878953
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695757643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
1695757643
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.1118837977
Short name T1019
Test name
Test status
Simulation time 43977107 ps
CPU time 0.73 seconds
Started Jul 27 05:28:49 PM PDT 24
Finished Jul 27 05:28:50 PM PDT 24
Peak memory 204136 kb
Host smart-9edfe181-9b32-49d3-9e74-c4fd4848a944
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118837977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
1118837977
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.4019408853
Short name T1101
Test name
Test status
Simulation time 55282215 ps
CPU time 0.75 seconds
Started Jul 27 05:28:48 PM PDT 24
Finished Jul 27 05:28:49 PM PDT 24
Peak memory 204160 kb
Host smart-637a0c2d-811b-43b5-ad62-f2e65a52b3cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019408853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
4019408853
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.438682746
Short name T1078
Test name
Test status
Simulation time 533769218 ps
CPU time 3.61 seconds
Started Jul 27 05:28:23 PM PDT 24
Finished Jul 27 05:28:27 PM PDT 24
Peak memory 217576 kb
Host smart-19573160-c36a-4549-ba2b-723e92807c33
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438682746 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.438682746
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.524318429
Short name T120
Test name
Test status
Simulation time 58601433 ps
CPU time 1.2 seconds
Started Jul 27 05:28:23 PM PDT 24
Finished Jul 27 05:28:24 PM PDT 24
Peak memory 207152 kb
Host smart-8a2223a9-a779-4e7f-9812-6bfe0c9d3a02
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524318429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.524318429
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3150035643
Short name T1007
Test name
Test status
Simulation time 13336916 ps
CPU time 0.78 seconds
Started Jul 27 05:28:16 PM PDT 24
Finished Jul 27 05:28:17 PM PDT 24
Peak memory 203924 kb
Host smart-ab1521c4-14b7-4115-8d4f-9dc5c04651a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150035643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.3
150035643
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.3006111253
Short name T155
Test name
Test status
Simulation time 148517760 ps
CPU time 3.38 seconds
Started Jul 27 05:28:24 PM PDT 24
Finished Jul 27 05:28:28 PM PDT 24
Peak memory 215372 kb
Host smart-7d00d42f-3f3a-42eb-856c-6b9e76d3a78a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006111253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.3006111253
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.4272295912
Short name T115
Test name
Test status
Simulation time 336326449 ps
CPU time 3.72 seconds
Started Jul 27 05:28:11 PM PDT 24
Finished Jul 27 05:28:15 PM PDT 24
Peak memory 219732 kb
Host smart-3675052f-2f91-4a85-87bd-0f41fda47635
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272295912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.4
272295912
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.4165933167
Short name T1089
Test name
Test status
Simulation time 2650771824 ps
CPU time 15.79 seconds
Started Jul 27 05:28:15 PM PDT 24
Finished Jul 27 05:28:31 PM PDT 24
Peak memory 215976 kb
Host smart-0d51098d-f93c-4543-887f-13d5605327ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165933167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.4165933167
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2643512756
Short name T117
Test name
Test status
Simulation time 501439708 ps
CPU time 1.77 seconds
Started Jul 27 05:28:23 PM PDT 24
Finished Jul 27 05:28:25 PM PDT 24
Peak memory 215476 kb
Host smart-0d049528-5384-420a-a2ed-bd89375594d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643512756 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.2643512756
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1579508731
Short name T1035
Test name
Test status
Simulation time 32699850 ps
CPU time 2.04 seconds
Started Jul 27 05:28:26 PM PDT 24
Finished Jul 27 05:28:28 PM PDT 24
Peak memory 207312 kb
Host smart-8ae29486-4141-4738-a48a-7cec1e46543e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579508731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.1
579508731
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.914941938
Short name T1091
Test name
Test status
Simulation time 23648811 ps
CPU time 0.67 seconds
Started Jul 27 05:28:21 PM PDT 24
Finished Jul 27 05:28:22 PM PDT 24
Peak memory 203872 kb
Host smart-65c32004-860d-4218-9a4f-76559de98e75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914941938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.914941938
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.4252670031
Short name T1131
Test name
Test status
Simulation time 26131413 ps
CPU time 1.64 seconds
Started Jul 27 05:28:25 PM PDT 24
Finished Jul 27 05:28:26 PM PDT 24
Peak memory 215380 kb
Host smart-0dc7bacb-aab9-48b6-a555-19828e32f762
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252670031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.4252670031
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2971179217
Short name T112
Test name
Test status
Simulation time 123142340 ps
CPU time 2.15 seconds
Started Jul 27 05:28:24 PM PDT 24
Finished Jul 27 05:28:26 PM PDT 24
Peak memory 215664 kb
Host smart-df39440b-174b-40d9-a339-77325b276e14
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971179217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.2
971179217
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.2828895706
Short name T104
Test name
Test status
Simulation time 376013003 ps
CPU time 19.02 seconds
Started Jul 27 05:28:29 PM PDT 24
Finished Jul 27 05:28:48 PM PDT 24
Peak memory 215540 kb
Host smart-2e08ffac-c3f4-4f28-9ab0-2a517942b653
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828895706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.2828895706
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3560908991
Short name T1022
Test name
Test status
Simulation time 113047680 ps
CPU time 3.88 seconds
Started Jul 27 05:28:23 PM PDT 24
Finished Jul 27 05:28:27 PM PDT 24
Peak memory 218116 kb
Host smart-607170d0-3132-40a8-8fe3-c344ccaa0a46
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560908991 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.3560908991
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.4264276007
Short name T1053
Test name
Test status
Simulation time 83915557 ps
CPU time 2.22 seconds
Started Jul 27 05:28:26 PM PDT 24
Finished Jul 27 05:28:29 PM PDT 24
Peak memory 215460 kb
Host smart-68481c60-f0ee-45f3-97b0-28724c38dd64
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264276007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.4
264276007
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.2391425303
Short name T1125
Test name
Test status
Simulation time 18501356 ps
CPU time 0.78 seconds
Started Jul 27 05:28:24 PM PDT 24
Finished Jul 27 05:28:25 PM PDT 24
Peak memory 203888 kb
Host smart-162ab05c-f1b4-4c14-a9ac-4ce90e7358de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391425303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.2
391425303
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.2308623444
Short name T148
Test name
Test status
Simulation time 157195765 ps
CPU time 2.69 seconds
Started Jul 27 05:28:29 PM PDT 24
Finished Jul 27 05:28:32 PM PDT 24
Peak memory 215448 kb
Host smart-15ef02d2-c070-464b-8e5a-6383e8a72853
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308623444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.2308623444
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.74070457
Short name T114
Test name
Test status
Simulation time 759467780 ps
CPU time 4.72 seconds
Started Jul 27 05:28:26 PM PDT 24
Finished Jul 27 05:28:31 PM PDT 24
Peak memory 215540 kb
Host smart-b3e3c6be-b7bc-4bd7-87bf-6d69d84ddf3d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74070457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.74070457
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.1356568057
Short name T1111
Test name
Test status
Simulation time 2946206974 ps
CPU time 15.64 seconds
Started Jul 27 05:28:29 PM PDT 24
Finished Jul 27 05:28:45 PM PDT 24
Peak memory 215468 kb
Host smart-70d68c2e-0a3d-4c0c-afcd-6c263a58287a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356568057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.1356568057
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2661609420
Short name T1059
Test name
Test status
Simulation time 64500310 ps
CPU time 3.85 seconds
Started Jul 27 05:28:23 PM PDT 24
Finished Jul 27 05:28:27 PM PDT 24
Peak memory 217908 kb
Host smart-e3bf0f76-27d4-451b-8b86-4fe34c53606f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661609420 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.2661609420
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.2760134467
Short name T154
Test name
Test status
Simulation time 51677776 ps
CPU time 1.45 seconds
Started Jul 27 05:28:24 PM PDT 24
Finished Jul 27 05:28:25 PM PDT 24
Peak memory 207052 kb
Host smart-3b607e17-a03a-4f1d-a43a-94c9791f223c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760134467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.2
760134467
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.3108240490
Short name T1029
Test name
Test status
Simulation time 14140477 ps
CPU time 0.7 seconds
Started Jul 27 05:28:24 PM PDT 24
Finished Jul 27 05:28:25 PM PDT 24
Peak memory 204228 kb
Host smart-139e1a31-662a-4159-9501-b5866c7b0b8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108240490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.3
108240490
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2638817514
Short name T1072
Test name
Test status
Simulation time 60620335 ps
CPU time 3.65 seconds
Started Jul 27 05:28:22 PM PDT 24
Finished Jul 27 05:28:26 PM PDT 24
Peak memory 215376 kb
Host smart-a2be7209-6657-4cc1-8069-0c32b07f6982
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638817514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.2638817514
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.253964547
Short name T1098
Test name
Test status
Simulation time 113988423 ps
CPU time 3.01 seconds
Started Jul 27 05:28:25 PM PDT 24
Finished Jul 27 05:28:28 PM PDT 24
Peak memory 216516 kb
Host smart-8523abda-e7f4-40cb-9590-b117157d8b75
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253964547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.253964547
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.597279998
Short name T1121
Test name
Test status
Simulation time 1676175992 ps
CPU time 20.55 seconds
Started Jul 27 05:28:22 PM PDT 24
Finished Jul 27 05:28:43 PM PDT 24
Peak memory 215660 kb
Host smart-a89d3f58-88bd-4ac0-aa9e-03813df455ff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597279998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_
tl_intg_err.597279998
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2836933124
Short name T1060
Test name
Test status
Simulation time 147433734 ps
CPU time 3.49 seconds
Started Jul 27 05:28:26 PM PDT 24
Finished Jul 27 05:28:30 PM PDT 24
Peak memory 217416 kb
Host smart-9b7feb10-3936-4b47-b983-5079fa47b18f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836933124 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.2836933124
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.123514452
Short name T125
Test name
Test status
Simulation time 94786739 ps
CPU time 1.86 seconds
Started Jul 27 05:28:23 PM PDT 24
Finished Jul 27 05:28:25 PM PDT 24
Peak memory 215500 kb
Host smart-40e6ef16-4311-4701-be8f-022f76833b24
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123514452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.123514452
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.422266929
Short name T1097
Test name
Test status
Simulation time 26178516 ps
CPU time 0.72 seconds
Started Jul 27 05:28:24 PM PDT 24
Finished Jul 27 05:28:25 PM PDT 24
Peak memory 203912 kb
Host smart-c38211c2-3dda-4145-9501-c9103ba25935
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422266929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.422266929
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.207428133
Short name T157
Test name
Test status
Simulation time 413909091 ps
CPU time 4.41 seconds
Started Jul 27 05:28:26 PM PDT 24
Finished Jul 27 05:28:30 PM PDT 24
Peak memory 215456 kb
Host smart-6fd8db18-caa4-4734-8c0e-6e71abd054b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207428133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sp
i_device_same_csr_outstanding.207428133
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.3846366223
Short name T105
Test name
Test status
Simulation time 27707824 ps
CPU time 1.97 seconds
Started Jul 27 05:28:28 PM PDT 24
Finished Jul 27 05:28:30 PM PDT 24
Peak memory 215544 kb
Host smart-1039128e-d4f0-473e-9a69-bea6d0441f2f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846366223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.3
846366223
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.3540154511
Short name T166
Test name
Test status
Simulation time 1584889215 ps
CPU time 18.52 seconds
Started Jul 27 05:28:22 PM PDT 24
Finished Jul 27 05:28:40 PM PDT 24
Peak memory 215428 kb
Host smart-8de59dfb-f2d3-4593-9db5-3672a3976df1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540154511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.3540154511
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.2033209245
Short name T511
Test name
Test status
Simulation time 1681585459 ps
CPU time 4.53 seconds
Started Jul 27 05:30:59 PM PDT 24
Finished Jul 27 05:31:04 PM PDT 24
Peak memory 232864 kb
Host smart-eb368c45-6d9b-4431-bfa2-4b1250451e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033209245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.2033209245
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.648239533
Short name T531
Test name
Test status
Simulation time 36644917 ps
CPU time 0.78 seconds
Started Jul 27 05:31:04 PM PDT 24
Finished Jul 27 05:31:05 PM PDT 24
Peak memory 207000 kb
Host smart-6105e989-eb9a-42c1-9b01-205eb046cd5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648239533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.648239533
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.1750083810
Short name T51
Test name
Test status
Simulation time 28354318388 ps
CPU time 108.35 seconds
Started Jul 27 05:31:00 PM PDT 24
Finished Jul 27 05:32:48 PM PDT 24
Peak memory 249328 kb
Host smart-4bda2cab-c0e6-4c78-a5bc-8790bbd28a35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750083810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.1750083810
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.2739091152
Short name T33
Test name
Test status
Simulation time 20942401494 ps
CPU time 198.75 seconds
Started Jul 27 05:31:01 PM PDT 24
Finished Jul 27 05:34:20 PM PDT 24
Peak memory 250296 kb
Host smart-7b565373-3cac-44d2-a564-2296cb16c06f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739091152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.2739091152
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.1934062288
Short name T543
Test name
Test status
Simulation time 2850906759 ps
CPU time 21.25 seconds
Started Jul 27 05:31:01 PM PDT 24
Finished Jul 27 05:31:23 PM PDT 24
Peak memory 233100 kb
Host smart-4a215b56-85a1-4108-990e-50c823f2d971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934062288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.1934062288
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.625411108
Short name T588
Test name
Test status
Simulation time 4321648432 ps
CPU time 62.77 seconds
Started Jul 27 05:31:03 PM PDT 24
Finished Jul 27 05:32:06 PM PDT 24
Peak memory 255388 kb
Host smart-0056e823-9506-4e31-b656-2593495ed6f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625411108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds.
625411108
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_intercept.993022240
Short name T847
Test name
Test status
Simulation time 233401879 ps
CPU time 4.55 seconds
Started Jul 27 05:31:03 PM PDT 24
Finished Jul 27 05:31:07 PM PDT 24
Peak memory 232740 kb
Host smart-bfc76f8f-4d6f-4b02-a711-9036f18f48b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993022240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.993022240
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.1079447456
Short name T698
Test name
Test status
Simulation time 295646330 ps
CPU time 2.28 seconds
Started Jul 27 05:31:01 PM PDT 24
Finished Jul 27 05:31:04 PM PDT 24
Peak memory 224592 kb
Host smart-d098ef89-8a9e-47f1-98be-9355c052872d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079447456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.1079447456
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.1857671261
Short name T625
Test name
Test status
Simulation time 65176542063 ps
CPU time 18.7 seconds
Started Jul 27 05:31:01 PM PDT 24
Finished Jul 27 05:31:20 PM PDT 24
Peak memory 239560 kb
Host smart-4fee9520-1b0c-44cc-acc7-b428f4049500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857671261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.1857671261
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.951414772
Short name T321
Test name
Test status
Simulation time 72776409 ps
CPU time 2.29 seconds
Started Jul 27 05:30:57 PM PDT 24
Finished Jul 27 05:31:00 PM PDT 24
Peak memory 224280 kb
Host smart-b07a47d7-c47e-45f7-ba88-1cdf1934dab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951414772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.951414772
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.3652771229
Short name T402
Test name
Test status
Simulation time 211736075 ps
CPU time 3.46 seconds
Started Jul 27 05:30:58 PM PDT 24
Finished Jul 27 05:31:01 PM PDT 24
Peak memory 219392 kb
Host smart-335ae859-2057-4aa1-a666-fec828cdb3e6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3652771229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.3652771229
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.1868678954
Short name T73
Test name
Test status
Simulation time 129267993 ps
CPU time 0.95 seconds
Started Jul 27 05:30:59 PM PDT 24
Finished Jul 27 05:31:01 PM PDT 24
Peak memory 235752 kb
Host smart-8b637749-b415-4c18-9139-f3166b24c58d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868678954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.1868678954
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.3307643800
Short name T519
Test name
Test status
Simulation time 2050575505 ps
CPU time 32.94 seconds
Started Jul 27 05:31:00 PM PDT 24
Finished Jul 27 05:31:33 PM PDT 24
Peak memory 257344 kb
Host smart-71692788-459c-4a80-b83f-4fddcd9f8053
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307643800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.3307643800
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.860659900
Short name T539
Test name
Test status
Simulation time 533633416 ps
CPU time 9.23 seconds
Started Jul 27 05:31:00 PM PDT 24
Finished Jul 27 05:31:09 PM PDT 24
Peak memory 216596 kb
Host smart-66120a0d-7311-4408-8f96-8b23407d4525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860659900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.860659900
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.3807221917
Short name T795
Test name
Test status
Simulation time 1561919121 ps
CPU time 5.44 seconds
Started Jul 27 05:31:04 PM PDT 24
Finished Jul 27 05:31:10 PM PDT 24
Peak memory 216320 kb
Host smart-4eb34fbe-067c-41c6-9205-838b9a35ef6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807221917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.3807221917
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.2471684982
Short name T299
Test name
Test status
Simulation time 37592571 ps
CPU time 1.1 seconds
Started Jul 27 05:31:00 PM PDT 24
Finished Jul 27 05:31:02 PM PDT 24
Peak memory 207064 kb
Host smart-85438ffb-2c03-4007-b9ed-61a97de5a293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471684982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.2471684982
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.2998053928
Short name T399
Test name
Test status
Simulation time 33105912 ps
CPU time 0.87 seconds
Started Jul 27 05:31:02 PM PDT 24
Finished Jul 27 05:31:03 PM PDT 24
Peak memory 206396 kb
Host smart-47e6f743-aa37-49d8-a264-dc843fa87e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998053928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.2998053928
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.754753084
Short name T934
Test name
Test status
Simulation time 5700199353 ps
CPU time 22.59 seconds
Started Jul 27 05:30:58 PM PDT 24
Finished Jul 27 05:31:21 PM PDT 24
Peak memory 240900 kb
Host smart-ce1553d6-313f-4c66-b012-53fb50e40ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754753084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.754753084
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.2453865096
Short name T911
Test name
Test status
Simulation time 41265161 ps
CPU time 0.74 seconds
Started Jul 27 05:31:14 PM PDT 24
Finished Jul 27 05:31:15 PM PDT 24
Peak memory 205508 kb
Host smart-83d91f5e-c708-4ff6-b92e-01758c980b2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453865096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.2
453865096
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.3864312523
Short name T741
Test name
Test status
Simulation time 631665266 ps
CPU time 4.09 seconds
Started Jul 27 05:31:01 PM PDT 24
Finished Jul 27 05:31:06 PM PDT 24
Peak memory 232772 kb
Host smart-e74d040c-fcf2-4606-915a-314088e65697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864312523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.3864312523
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.1580080639
Short name T685
Test name
Test status
Simulation time 16292098 ps
CPU time 0.79 seconds
Started Jul 27 05:31:03 PM PDT 24
Finished Jul 27 05:31:04 PM PDT 24
Peak memory 205680 kb
Host smart-dd9281da-05a3-41e8-8ccd-d5f66d8e67e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580080639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.1580080639
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.3309471318
Short name T226
Test name
Test status
Simulation time 60826488328 ps
CPU time 119.06 seconds
Started Jul 27 05:31:01 PM PDT 24
Finished Jul 27 05:33:01 PM PDT 24
Peak memory 251440 kb
Host smart-e96a806e-9455-4af5-8ea6-9c9f591fd3c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309471318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.3309471318
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.706366588
Short name T822
Test name
Test status
Simulation time 12687890419 ps
CPU time 141.21 seconds
Started Jul 27 05:31:11 PM PDT 24
Finished Jul 27 05:33:32 PM PDT 24
Peak memory 265760 kb
Host smart-2bb9c460-27e8-41bb-a9ab-579c6d060f5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706366588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.706366588
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_intercept.4034688580
Short name T702
Test name
Test status
Simulation time 1269828918 ps
CPU time 5.87 seconds
Started Jul 27 05:30:59 PM PDT 24
Finished Jul 27 05:31:05 PM PDT 24
Peak memory 224668 kb
Host smart-96b9c254-94e6-4b98-a24c-8f095b554dc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034688580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.4034688580
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.1178323372
Short name T627
Test name
Test status
Simulation time 6652367780 ps
CPU time 52.11 seconds
Started Jul 27 05:31:02 PM PDT 24
Finished Jul 27 05:31:54 PM PDT 24
Peak memory 224636 kb
Host smart-ec805111-5ada-415a-aa86-998dc9ad1321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178323372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.1178323372
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.3612262215
Short name T906
Test name
Test status
Simulation time 1668669194 ps
CPU time 3.56 seconds
Started Jul 27 05:31:01 PM PDT 24
Finished Jul 27 05:31:05 PM PDT 24
Peak memory 232672 kb
Host smart-81ac9b3f-ade9-4147-b770-48d5c6a19b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612262215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.3612262215
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.144678745
Short name T560
Test name
Test status
Simulation time 5999691847 ps
CPU time 14.49 seconds
Started Jul 27 05:31:03 PM PDT 24
Finished Jul 27 05:31:17 PM PDT 24
Peak memory 232796 kb
Host smart-63e33a33-c23b-48a2-b38e-2adba5dd9c2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144678745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.144678745
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.3684156508
Short name T505
Test name
Test status
Simulation time 303805314 ps
CPU time 4.48 seconds
Started Jul 27 05:30:59 PM PDT 24
Finished Jul 27 05:31:04 PM PDT 24
Peak memory 222840 kb
Host smart-4507bbd8-346f-4f78-ba2c-c009c9e9be33
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3684156508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.3684156508
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.4292932144
Short name T792
Test name
Test status
Simulation time 55222639799 ps
CPU time 20.32 seconds
Started Jul 27 05:31:00 PM PDT 24
Finished Jul 27 05:31:20 PM PDT 24
Peak memory 216784 kb
Host smart-73fb6573-4845-4ee6-99f8-febfcf89a81c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292932144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.4292932144
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.3991348325
Short name T745
Test name
Test status
Simulation time 1616806250 ps
CPU time 9.33 seconds
Started Jul 27 05:30:59 PM PDT 24
Finished Jul 27 05:31:08 PM PDT 24
Peak memory 216292 kb
Host smart-647265c1-90f1-45ff-9cf1-fa76307b6d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991348325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.3991348325
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.3055783223
Short name T340
Test name
Test status
Simulation time 118189565 ps
CPU time 1.55 seconds
Started Jul 27 05:31:02 PM PDT 24
Finished Jul 27 05:31:03 PM PDT 24
Peak memory 216412 kb
Host smart-31876b18-b967-4226-af2a-0ae0fe4597fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055783223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.3055783223
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.2664592444
Short name T502
Test name
Test status
Simulation time 150458417 ps
CPU time 0.86 seconds
Started Jul 27 05:30:58 PM PDT 24
Finished Jul 27 05:30:59 PM PDT 24
Peak memory 207104 kb
Host smart-95b0b0b3-abd9-4aea-a181-84a617f5871d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664592444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.2664592444
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.2467843572
Short name T362
Test name
Test status
Simulation time 2346028934 ps
CPU time 6.92 seconds
Started Jul 27 05:30:59 PM PDT 24
Finished Jul 27 05:31:06 PM PDT 24
Peak memory 232824 kb
Host smart-6487995f-6b1f-465e-a6f3-63a61540fd2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467843572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.2467843572
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.3925343999
Short name T912
Test name
Test status
Simulation time 30912604 ps
CPU time 0.68 seconds
Started Jul 27 05:31:51 PM PDT 24
Finished Jul 27 05:31:52 PM PDT 24
Peak memory 205880 kb
Host smart-35ca817f-5f8f-4544-9c64-31a0c87538a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925343999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
3925343999
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.347933157
Short name T613
Test name
Test status
Simulation time 966428035 ps
CPU time 11.74 seconds
Started Jul 27 05:31:53 PM PDT 24
Finished Jul 27 05:32:05 PM PDT 24
Peak memory 232848 kb
Host smart-c6a31f37-bbb3-4508-85ce-6e9d244a485d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347933157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.347933157
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.526943938
Short name T304
Test name
Test status
Simulation time 128464275 ps
CPU time 0.8 seconds
Started Jul 27 05:31:52 PM PDT 24
Finished Jul 27 05:31:53 PM PDT 24
Peak memory 206580 kb
Host smart-79695b77-342e-4be7-bcb8-892cdbdbd2d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526943938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.526943938
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.2843214644
Short name T165
Test name
Test status
Simulation time 28425109542 ps
CPU time 108.34 seconds
Started Jul 27 05:31:52 PM PDT 24
Finished Jul 27 05:33:40 PM PDT 24
Peak memory 252152 kb
Host smart-ef88d0ee-7459-4aff-b275-74330dd97e73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843214644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.2843214644
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.3132967967
Short name T392
Test name
Test status
Simulation time 11975110960 ps
CPU time 63.31 seconds
Started Jul 27 05:31:52 PM PDT 24
Finished Jul 27 05:32:55 PM PDT 24
Peak memory 249368 kb
Host smart-b2598539-10d3-4d5f-b0e1-cc8ffccef7a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132967967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.3132967967
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.2876779012
Short name T145
Test name
Test status
Simulation time 3414808405 ps
CPU time 85.59 seconds
Started Jul 27 05:31:56 PM PDT 24
Finished Jul 27 05:33:21 PM PDT 24
Peak memory 262396 kb
Host smart-ecc1f88f-af1f-4a96-b84f-e64a284f29e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876779012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.2876779012
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.2918585847
Short name T454
Test name
Test status
Simulation time 1050403018 ps
CPU time 18.57 seconds
Started Jul 27 05:31:52 PM PDT 24
Finished Jul 27 05:32:11 PM PDT 24
Peak memory 232888 kb
Host smart-d26b1d32-7f86-49a7-8b01-14a6e0ab5126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918585847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.2918585847
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.3083055699
Short name T785
Test name
Test status
Simulation time 40799415967 ps
CPU time 295.78 seconds
Started Jul 27 05:31:52 PM PDT 24
Finished Jul 27 05:36:48 PM PDT 24
Peak memory 273320 kb
Host smart-0178e7f4-1b12-40bc-a0a8-b60191cdf9e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083055699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmd
s.3083055699
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.4146486249
Short name T522
Test name
Test status
Simulation time 2693899106 ps
CPU time 18.32 seconds
Started Jul 27 05:31:55 PM PDT 24
Finished Jul 27 05:32:14 PM PDT 24
Peak memory 241048 kb
Host smart-d32c0e39-655d-46cb-ba1b-fea036d5c979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146486249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.4146486249
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.1307123515
Short name T914
Test name
Test status
Simulation time 2994668159 ps
CPU time 10.92 seconds
Started Jul 27 05:31:52 PM PDT 24
Finished Jul 27 05:32:03 PM PDT 24
Peak memory 224720 kb
Host smart-06f6ef78-e7c8-44dc-a2de-2e6c85ba1302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307123515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.1307123515
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.3853381464
Short name T666
Test name
Test status
Simulation time 6499034059 ps
CPU time 9.16 seconds
Started Jul 27 05:31:53 PM PDT 24
Finished Jul 27 05:32:02 PM PDT 24
Peak memory 238280 kb
Host smart-f110fe73-ab55-4a95-adcd-5ec928cb9608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853381464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.3853381464
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.1995393543
Short name T479
Test name
Test status
Simulation time 85573289 ps
CPU time 3.75 seconds
Started Jul 27 05:31:54 PM PDT 24
Finished Jul 27 05:31:57 PM PDT 24
Peak memory 218972 kb
Host smart-c13859af-771b-4b51-8ae4-8cb162b52be7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1995393543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.1995393543
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.2539155524
Short name T720
Test name
Test status
Simulation time 81596932455 ps
CPU time 154.73 seconds
Started Jul 27 05:31:54 PM PDT 24
Finished Jul 27 05:34:29 PM PDT 24
Peak memory 241204 kb
Host smart-bbfaf4c1-bc0e-4385-b604-7689ec07e229
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539155524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.2539155524
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.1995824818
Short name T375
Test name
Test status
Simulation time 27138850086 ps
CPU time 14.53 seconds
Started Jul 27 05:31:56 PM PDT 24
Finished Jul 27 05:32:10 PM PDT 24
Peak memory 216352 kb
Host smart-ffc67b5c-5111-44d1-8696-040b1fc0d334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995824818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.1995824818
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.3023694215
Short name T905
Test name
Test status
Simulation time 73395214 ps
CPU time 0.97 seconds
Started Jul 27 05:31:53 PM PDT 24
Finished Jul 27 05:31:54 PM PDT 24
Peak memory 207492 kb
Host smart-39ee1419-7fa4-4caa-8165-4e3f558d04ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023694215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.3023694215
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.4221556554
Short name T1001
Test name
Test status
Simulation time 79884303 ps
CPU time 0.78 seconds
Started Jul 27 05:31:55 PM PDT 24
Finished Jul 27 05:31:56 PM PDT 24
Peak memory 206008 kb
Host smart-c9c851e0-9862-4c59-b8d3-de8cbe30422c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221556554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.4221556554
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.2249969207
Short name T217
Test name
Test status
Simulation time 259663332 ps
CPU time 3.37 seconds
Started Jul 27 05:31:52 PM PDT 24
Finished Jul 27 05:31:56 PM PDT 24
Peak memory 232848 kb
Host smart-76ee4ef3-a413-43cd-b704-56ccb6eee1dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249969207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.2249969207
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.44299543
Short name T896
Test name
Test status
Simulation time 14292645 ps
CPU time 0.74 seconds
Started Jul 27 05:32:05 PM PDT 24
Finished Jul 27 05:32:06 PM PDT 24
Peak memory 205068 kb
Host smart-6fe95bd8-0a14-4c46-a3c3-61fcb2a8a62b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44299543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.44299543
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.3196782105
Short name T373
Test name
Test status
Simulation time 33153859 ps
CPU time 2.62 seconds
Started Jul 27 05:32:06 PM PDT 24
Finished Jul 27 05:32:09 PM PDT 24
Peak memory 232760 kb
Host smart-c24ce928-d479-470a-8de2-ed308691ed6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196782105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.3196782105
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.4163495002
Short name T858
Test name
Test status
Simulation time 60924652 ps
CPU time 0.77 seconds
Started Jul 27 05:31:52 PM PDT 24
Finished Jul 27 05:31:53 PM PDT 24
Peak memory 206632 kb
Host smart-348c9e01-f2ba-45ee-a1c1-aa358855e77a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163495002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.4163495002
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.3513171214
Short name T971
Test name
Test status
Simulation time 21513510608 ps
CPU time 74.55 seconds
Started Jul 27 05:32:05 PM PDT 24
Finished Jul 27 05:33:20 PM PDT 24
Peak memory 249312 kb
Host smart-a1378db4-cc67-49fc-be8c-969333de1fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513171214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.3513171214
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.112868590
Short name T263
Test name
Test status
Simulation time 14427676956 ps
CPU time 93.73 seconds
Started Jul 27 05:32:07 PM PDT 24
Finished Jul 27 05:33:41 PM PDT 24
Peak memory 256344 kb
Host smart-a8872dd9-52fb-4fe3-8dff-606de211bbae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112868590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.112868590
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.266230722
Short name T882
Test name
Test status
Simulation time 177129965 ps
CPU time 4 seconds
Started Jul 27 05:32:03 PM PDT 24
Finished Jul 27 05:32:07 PM PDT 24
Peak memory 224640 kb
Host smart-fce2ceff-389b-4943-9571-e33f7fb8583c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266230722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.266230722
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.2166947825
Short name T46
Test name
Test status
Simulation time 37270146635 ps
CPU time 287.71 seconds
Started Jul 27 05:32:06 PM PDT 24
Finished Jul 27 05:36:54 PM PDT 24
Peak memory 256972 kb
Host smart-61135b1d-bea5-45d7-bab2-5c5e13dc0e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166947825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmd
s.2166947825
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_intercept.1352978362
Short name T310
Test name
Test status
Simulation time 596287616 ps
CPU time 3.76 seconds
Started Jul 27 05:31:55 PM PDT 24
Finished Jul 27 05:31:58 PM PDT 24
Peak memory 232876 kb
Host smart-dfe01e72-db97-41e2-a3f1-998a476de41a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352978362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.1352978362
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.2437552356
Short name T425
Test name
Test status
Simulation time 53980838342 ps
CPU time 97.02 seconds
Started Jul 27 05:31:51 PM PDT 24
Finished Jul 27 05:33:28 PM PDT 24
Peak memory 249212 kb
Host smart-91c9bbca-0d0a-4dbe-a1bd-c01cea8c0418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437552356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.2437552356
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.2330757253
Short name T540
Test name
Test status
Simulation time 1233819370 ps
CPU time 6.54 seconds
Started Jul 27 05:31:54 PM PDT 24
Finished Jul 27 05:32:01 PM PDT 24
Peak memory 232788 kb
Host smart-941d3ecb-d6d1-4e25-84b4-de4a28e25dff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330757253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.2330757253
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.2053467154
Short name T209
Test name
Test status
Simulation time 67203146588 ps
CPU time 23.12 seconds
Started Jul 27 05:31:54 PM PDT 24
Finished Jul 27 05:32:17 PM PDT 24
Peak memory 232836 kb
Host smart-02f87977-a945-4ad9-af24-7d4d74354d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053467154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.2053467154
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.4168589133
Short name T150
Test name
Test status
Simulation time 966949709 ps
CPU time 9.29 seconds
Started Jul 27 05:32:04 PM PDT 24
Finished Jul 27 05:32:14 PM PDT 24
Peak memory 220440 kb
Host smart-b96acedd-c646-43b3-a94e-f6dc4dd035e2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4168589133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.4168589133
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.1586444886
Short name T541
Test name
Test status
Simulation time 19023276414 ps
CPU time 34.06 seconds
Started Jul 27 05:31:53 PM PDT 24
Finished Jul 27 05:32:28 PM PDT 24
Peak memory 220576 kb
Host smart-dea469af-4e3b-4b79-9984-95c088a8d49f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586444886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.1586444886
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.3730996508
Short name T586
Test name
Test status
Simulation time 26872869 ps
CPU time 0.76 seconds
Started Jul 27 05:31:50 PM PDT 24
Finished Jul 27 05:31:51 PM PDT 24
Peak memory 205800 kb
Host smart-15d3b43d-355a-422a-bf6f-49b74c7c71af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730996508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.3730996508
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.1354677547
Short name T941
Test name
Test status
Simulation time 24982259 ps
CPU time 0.91 seconds
Started Jul 27 05:31:52 PM PDT 24
Finished Jul 27 05:31:53 PM PDT 24
Peak memory 207028 kb
Host smart-07f023a3-a26c-40da-9dc0-8876b1f25210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354677547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.1354677547
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.611172387
Short name T946
Test name
Test status
Simulation time 151577901 ps
CPU time 0.78 seconds
Started Jul 27 05:31:54 PM PDT 24
Finished Jul 27 05:31:55 PM PDT 24
Peak memory 206044 kb
Host smart-e7ce5fd8-1238-4830-ae22-e578074a825a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611172387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.611172387
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.977822308
Short name T551
Test name
Test status
Simulation time 447455722 ps
CPU time 3.09 seconds
Started Jul 27 05:32:04 PM PDT 24
Finished Jul 27 05:32:07 PM PDT 24
Peak memory 232856 kb
Host smart-10b8620e-ed95-413c-bd8d-9e761a5da61b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977822308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.977822308
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.561023103
Short name T656
Test name
Test status
Simulation time 36534062 ps
CPU time 0.74 seconds
Started Jul 27 05:32:06 PM PDT 24
Finished Jul 27 05:32:07 PM PDT 24
Peak memory 205868 kb
Host smart-a4e89f2d-133c-4cd1-861d-6efb26ce596d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561023103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.561023103
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.2538964858
Short name T862
Test name
Test status
Simulation time 7803336310 ps
CPU time 13.88 seconds
Started Jul 27 05:32:05 PM PDT 24
Finished Jul 27 05:32:19 PM PDT 24
Peak memory 232812 kb
Host smart-27bb1ade-572d-48d9-8346-f11ade18863e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538964858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.2538964858
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.2705348999
Short name T928
Test name
Test status
Simulation time 35753774 ps
CPU time 0.77 seconds
Started Jul 27 05:32:05 PM PDT 24
Finished Jul 27 05:32:07 PM PDT 24
Peak memory 206572 kb
Host smart-7315077d-acb0-45dd-a73f-983412c36266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705348999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.2705348999
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.2871139920
Short name T211
Test name
Test status
Simulation time 1654635659 ps
CPU time 28.41 seconds
Started Jul 27 05:32:06 PM PDT 24
Finished Jul 27 05:32:35 PM PDT 24
Peak memory 252248 kb
Host smart-c7f3ae48-7dbd-4c7d-84aa-6153d8ded575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871139920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.2871139920
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.135232254
Short name T628
Test name
Test status
Simulation time 1222337336 ps
CPU time 7.32 seconds
Started Jul 27 05:32:04 PM PDT 24
Finished Jul 27 05:32:11 PM PDT 24
Peak memory 217516 kb
Host smart-4ada76cf-76a0-4af7-9c14-b6178c46c3fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135232254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.135232254
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.733786949
Short name T397
Test name
Test status
Simulation time 27986044096 ps
CPU time 147.72 seconds
Started Jul 27 05:32:04 PM PDT 24
Finished Jul 27 05:34:32 PM PDT 24
Peak memory 252496 kb
Host smart-dbef6996-cb9d-455d-8872-2238d725bde1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733786949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idle
.733786949
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.1838587402
Short name T942
Test name
Test status
Simulation time 1247966387 ps
CPU time 14.81 seconds
Started Jul 27 05:32:02 PM PDT 24
Finished Jul 27 05:32:17 PM PDT 24
Peak memory 233920 kb
Host smart-9a63be00-82d9-45fe-9756-6139ff22a2e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838587402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.1838587402
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.727969374
Short name T36
Test name
Test status
Simulation time 6909947792 ps
CPU time 25.78 seconds
Started Jul 27 05:32:04 PM PDT 24
Finished Jul 27 05:32:30 PM PDT 24
Peak memory 235532 kb
Host smart-93b14e1d-74de-417c-acb0-fe889b37e59b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727969374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmds
.727969374
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_intercept.2334233039
Short name T827
Test name
Test status
Simulation time 1162664075 ps
CPU time 12.97 seconds
Started Jul 27 05:32:05 PM PDT 24
Finished Jul 27 05:32:18 PM PDT 24
Peak memory 224624 kb
Host smart-dcc66c31-c26b-4606-a6b8-3767cf2a94be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334233039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.2334233039
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.2195287653
Short name T383
Test name
Test status
Simulation time 25992144374 ps
CPU time 30.63 seconds
Started Jul 27 05:32:04 PM PDT 24
Finished Jul 27 05:32:35 PM PDT 24
Peak memory 232848 kb
Host smart-70ea8454-81f1-4752-9b0d-66c9a74fce3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195287653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.2195287653
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.3940522356
Short name T276
Test name
Test status
Simulation time 3226237836 ps
CPU time 15.76 seconds
Started Jul 27 05:32:03 PM PDT 24
Finished Jul 27 05:32:19 PM PDT 24
Peak memory 241020 kb
Host smart-44c5762f-d271-4200-b3fc-b96dfcfe867e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940522356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.3940522356
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.1168685237
Short name T607
Test name
Test status
Simulation time 132017519 ps
CPU time 2.48 seconds
Started Jul 27 05:32:05 PM PDT 24
Finished Jul 27 05:32:08 PM PDT 24
Peak memory 232768 kb
Host smart-4a975c09-13aa-4eb1-850e-23c4b691e44d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168685237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.1168685237
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.2180787389
Short name T629
Test name
Test status
Simulation time 1737859961 ps
CPU time 8.99 seconds
Started Jul 27 05:32:03 PM PDT 24
Finished Jul 27 05:32:12 PM PDT 24
Peak memory 219000 kb
Host smart-b67696e1-7d2a-47c9-b465-106bafacc117
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2180787389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.2180787389
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.3685234041
Short name T953
Test name
Test status
Simulation time 54665107 ps
CPU time 1.08 seconds
Started Jul 27 05:32:03 PM PDT 24
Finished Jul 27 05:32:05 PM PDT 24
Peak memory 207316 kb
Host smart-22a325fe-5988-40dc-9c67-3a27826b6c83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685234041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.3685234041
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.1833751789
Short name T341
Test name
Test status
Simulation time 39815803 ps
CPU time 0.75 seconds
Started Jul 27 05:32:04 PM PDT 24
Finished Jul 27 05:32:05 PM PDT 24
Peak memory 205824 kb
Host smart-06c4a5f8-0e97-4720-b149-ba63387702ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833751789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.1833751789
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.1224467004
Short name T24
Test name
Test status
Simulation time 643536579 ps
CPU time 2.35 seconds
Started Jul 27 05:32:03 PM PDT 24
Finished Jul 27 05:32:05 PM PDT 24
Peak memory 216460 kb
Host smart-22e6001f-1c37-4568-9a52-e2d0bceeb0d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224467004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.1224467004
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.4086558305
Short name T712
Test name
Test status
Simulation time 37690078 ps
CPU time 0.72 seconds
Started Jul 27 05:32:10 PM PDT 24
Finished Jul 27 05:32:10 PM PDT 24
Peak memory 205688 kb
Host smart-0104bc07-5d6d-4fed-ac26-697c4e0d405a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086558305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.4086558305
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.2208168698
Short name T919
Test name
Test status
Simulation time 46174264 ps
CPU time 0.91 seconds
Started Jul 27 05:32:06 PM PDT 24
Finished Jul 27 05:32:07 PM PDT 24
Peak memory 206984 kb
Host smart-e37b1eb2-7250-4015-84f6-d6cf64c77b3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208168698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.2208168698
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.2041639590
Short name T239
Test name
Test status
Simulation time 1940652161 ps
CPU time 5.79 seconds
Started Jul 27 05:32:03 PM PDT 24
Finished Jul 27 05:32:09 PM PDT 24
Peak memory 232836 kb
Host smart-274c5366-95a9-445f-a150-918f820ec5e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041639590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.2041639590
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.1953183961
Short name T695
Test name
Test status
Simulation time 187908117 ps
CPU time 0.78 seconds
Started Jul 27 05:32:05 PM PDT 24
Finished Jul 27 05:32:07 PM PDT 24
Peak memory 205484 kb
Host smart-02f223b1-02f4-4fb3-8be0-68abc77809a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953183961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
1953183961
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.4255414657
Short name T701
Test name
Test status
Simulation time 114184408 ps
CPU time 2.36 seconds
Started Jul 27 05:32:05 PM PDT 24
Finished Jul 27 05:32:07 PM PDT 24
Peak memory 232472 kb
Host smart-abc706a9-539c-43fe-a26a-a100f1304e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255414657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.4255414657
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.877334920
Short name T312
Test name
Test status
Simulation time 15243346 ps
CPU time 0.82 seconds
Started Jul 27 05:32:03 PM PDT 24
Finished Jul 27 05:32:04 PM PDT 24
Peak memory 205964 kb
Host smart-34a83339-1130-469f-ae6c-e8c613fe65c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877334920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.877334920
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.1871982914
Short name T973
Test name
Test status
Simulation time 79565420422 ps
CPU time 259.53 seconds
Started Jul 27 05:32:03 PM PDT 24
Finished Jul 27 05:36:23 PM PDT 24
Peak memory 257332 kb
Host smart-c38bf585-f665-44c3-9207-ddb4b684613a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871982914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.1871982914
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.2833636812
Short name T605
Test name
Test status
Simulation time 17271336319 ps
CPU time 107.62 seconds
Started Jul 27 05:32:07 PM PDT 24
Finished Jul 27 05:33:55 PM PDT 24
Peak memory 255160 kb
Host smart-dc126512-bf39-4176-8c72-75ee0cc43e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833636812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.2833636812
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.4253743034
Short name T280
Test name
Test status
Simulation time 2399443759 ps
CPU time 19.52 seconds
Started Jul 27 05:32:04 PM PDT 24
Finished Jul 27 05:32:24 PM PDT 24
Peak memory 225600 kb
Host smart-69217f59-48c5-403d-a148-9aa022c131e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253743034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.4253743034
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.3011546860
Short name T268
Test name
Test status
Simulation time 2909179246 ps
CPU time 75.87 seconds
Started Jul 27 05:32:05 PM PDT 24
Finished Jul 27 05:33:22 PM PDT 24
Peak memory 265416 kb
Host smart-65820143-bf8f-4e3b-9856-2f37987028d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011546860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmd
s.3011546860
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_intercept.4270228106
Short name T615
Test name
Test status
Simulation time 1201405364 ps
CPU time 13.98 seconds
Started Jul 27 05:32:02 PM PDT 24
Finished Jul 27 05:32:16 PM PDT 24
Peak memory 232704 kb
Host smart-17fe161b-8ecf-40dc-9412-ebcbb684f756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270228106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.4270228106
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.3787754911
Short name T817
Test name
Test status
Simulation time 33230569517 ps
CPU time 81.38 seconds
Started Jul 27 05:32:05 PM PDT 24
Finished Jul 27 05:33:26 PM PDT 24
Peak memory 232876 kb
Host smart-1f3d3ab3-3089-4a4c-b8c9-40baef0ca399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787754911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.3787754911
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.3540977235
Short name T348
Test name
Test status
Simulation time 130415956 ps
CPU time 2.4 seconds
Started Jul 27 05:32:05 PM PDT 24
Finished Jul 27 05:32:08 PM PDT 24
Peak memory 224548 kb
Host smart-1174ee21-801b-415d-81cc-02a526e1f543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540977235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.3540977235
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.4225900397
Short name T409
Test name
Test status
Simulation time 617993062 ps
CPU time 6.27 seconds
Started Jul 27 05:32:05 PM PDT 24
Finished Jul 27 05:32:11 PM PDT 24
Peak memory 232816 kb
Host smart-dde321db-b07c-4557-be17-3802921a7e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225900397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.4225900397
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.676674333
Short name T41
Test name
Test status
Simulation time 3043438056 ps
CPU time 10.97 seconds
Started Jul 27 05:32:07 PM PDT 24
Finished Jul 27 05:32:18 PM PDT 24
Peak memory 222896 kb
Host smart-de7184aa-fc11-488b-bc89-d96c82c3cab4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=676674333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dire
ct.676674333
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.3961757560
Short name T750
Test name
Test status
Simulation time 8070364838 ps
CPU time 13.84 seconds
Started Jul 27 05:32:03 PM PDT 24
Finished Jul 27 05:32:17 PM PDT 24
Peak memory 216476 kb
Host smart-6d441ad1-a0a3-4aa9-8118-38732af0633b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961757560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.3961757560
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.3092109744
Short name T417
Test name
Test status
Simulation time 1161259829 ps
CPU time 1.92 seconds
Started Jul 27 05:32:03 PM PDT 24
Finished Jul 27 05:32:05 PM PDT 24
Peak memory 207952 kb
Host smart-7e17e00d-bfee-4953-99f9-a672525b96de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092109744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.3092109744
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.3807358215
Short name T796
Test name
Test status
Simulation time 444475375 ps
CPU time 5.02 seconds
Started Jul 27 05:32:06 PM PDT 24
Finished Jul 27 05:32:11 PM PDT 24
Peak memory 216260 kb
Host smart-1a6fe585-b64d-48b5-8ec6-42f1a8de9356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807358215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.3807358215
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.3926767167
Short name T638
Test name
Test status
Simulation time 15669491 ps
CPU time 0.73 seconds
Started Jul 27 05:32:06 PM PDT 24
Finished Jul 27 05:32:07 PM PDT 24
Peak memory 206092 kb
Host smart-949ebf56-62ac-4f3e-9da9-73400f77bffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926767167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.3926767167
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.3231160305
Short name T192
Test name
Test status
Simulation time 3036326102 ps
CPU time 12.99 seconds
Started Jul 27 05:32:05 PM PDT 24
Finished Jul 27 05:32:18 PM PDT 24
Peak memory 233064 kb
Host smart-35307dad-a46d-434d-a4ba-f6535f4acaac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231160305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.3231160305
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.2342649316
Short name T938
Test name
Test status
Simulation time 11479316 ps
CPU time 0.69 seconds
Started Jul 27 05:32:08 PM PDT 24
Finished Jul 27 05:32:09 PM PDT 24
Peak memory 204968 kb
Host smart-58dcf5ab-06fd-468f-9050-961ccd35db29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342649316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
2342649316
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.1165607572
Short name T231
Test name
Test status
Simulation time 72901249 ps
CPU time 2.67 seconds
Started Jul 27 05:32:07 PM PDT 24
Finished Jul 27 05:32:09 PM PDT 24
Peak memory 232780 kb
Host smart-e080f704-d453-4b1b-b7ce-51a3fe0803d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165607572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.1165607572
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.2473004979
Short name T753
Test name
Test status
Simulation time 14819233 ps
CPU time 0.77 seconds
Started Jul 27 05:32:05 PM PDT 24
Finished Jul 27 05:32:06 PM PDT 24
Peak memory 205672 kb
Host smart-a8d2ba18-d7f2-41b5-af06-05583026d28b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473004979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.2473004979
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.2379861017
Short name T647
Test name
Test status
Simulation time 12561581882 ps
CPU time 46.25 seconds
Started Jul 27 05:32:08 PM PDT 24
Finished Jul 27 05:32:54 PM PDT 24
Peak memory 257456 kb
Host smart-2ffe706a-1c6d-40e7-a8b3-a6950f2f30ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379861017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.2379861017
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.2402371846
Short name T202
Test name
Test status
Simulation time 5011560962 ps
CPU time 65.83 seconds
Started Jul 27 05:32:09 PM PDT 24
Finished Jul 27 05:33:15 PM PDT 24
Peak memory 250196 kb
Host smart-b0f2155d-4127-4edb-b2ac-757d52306b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402371846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.2402371846
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.1924580405
Short name T298
Test name
Test status
Simulation time 2082142416 ps
CPU time 48.86 seconds
Started Jul 27 05:32:07 PM PDT 24
Finished Jul 27 05:32:56 PM PDT 24
Peak memory 249932 kb
Host smart-0ed0b5d7-a1ca-4403-b72c-b9fa143b3ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924580405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.1924580405
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.2673426743
Short name T548
Test name
Test status
Simulation time 652125485 ps
CPU time 13.83 seconds
Started Jul 27 05:32:05 PM PDT 24
Finished Jul 27 05:32:19 PM PDT 24
Peak memory 248756 kb
Host smart-b7dc00bd-3211-4fa6-ae15-ffd7d885a5cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673426743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.2673426743
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.502262870
Short name T257
Test name
Test status
Simulation time 646424588 ps
CPU time 12.07 seconds
Started Jul 27 05:32:04 PM PDT 24
Finished Jul 27 05:32:17 PM PDT 24
Peak memory 232868 kb
Host smart-4b2dea0c-5219-4f13-93d4-9164597e8e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502262870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmds
.502262870
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_intercept.1055130738
Short name T814
Test name
Test status
Simulation time 886685803 ps
CPU time 5.04 seconds
Started Jul 27 05:32:07 PM PDT 24
Finished Jul 27 05:32:12 PM PDT 24
Peak memory 232776 kb
Host smart-7f02411f-0c6c-4a54-9241-3099682791a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055130738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.1055130738
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.1617491638
Short name T1002
Test name
Test status
Simulation time 22568701767 ps
CPU time 15.5 seconds
Started Jul 27 05:32:07 PM PDT 24
Finished Jul 27 05:32:23 PM PDT 24
Peak memory 238956 kb
Host smart-77190b41-ae66-4658-9cd2-744affd730c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617491638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.1617491638
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.2695440396
Short name T499
Test name
Test status
Simulation time 3446077349 ps
CPU time 6.62 seconds
Started Jul 27 05:32:07 PM PDT 24
Finished Jul 27 05:32:14 PM PDT 24
Peak memory 233592 kb
Host smart-4710755d-7b8f-47b7-8fe7-6149ea8f4f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695440396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.2695440396
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.4037654736
Short name T825
Test name
Test status
Simulation time 865357549 ps
CPU time 4.82 seconds
Started Jul 27 05:32:07 PM PDT 24
Finished Jul 27 05:32:12 PM PDT 24
Peak memory 224532 kb
Host smart-42972200-dc78-4f73-9693-f8a1964a35d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037654736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.4037654736
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.2454403933
Short name T988
Test name
Test status
Simulation time 478214427 ps
CPU time 3.25 seconds
Started Jul 27 05:32:08 PM PDT 24
Finished Jul 27 05:32:11 PM PDT 24
Peak memory 221012 kb
Host smart-ecb3262c-c11d-4ad4-9f4f-ce3cc0b967c4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2454403933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.2454403933
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.575700549
Short name T908
Test name
Test status
Simulation time 25147217877 ps
CPU time 289.08 seconds
Started Jul 27 05:32:08 PM PDT 24
Finished Jul 27 05:36:57 PM PDT 24
Peak memory 265780 kb
Host smart-dec2135b-1953-42c8-a382-69ec948f0dc8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575700549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stres
s_all.575700549
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.3731727069
Short name T523
Test name
Test status
Simulation time 46881401795 ps
CPU time 31.09 seconds
Started Jul 27 05:32:06 PM PDT 24
Finished Jul 27 05:32:37 PM PDT 24
Peak memory 216480 kb
Host smart-b2cf2914-af10-49c1-af73-359295f29587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731727069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.3731727069
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.3725592643
Short name T336
Test name
Test status
Simulation time 5244835513 ps
CPU time 16.04 seconds
Started Jul 27 05:32:04 PM PDT 24
Finished Jul 27 05:32:20 PM PDT 24
Peak memory 216480 kb
Host smart-3fb8efd3-13c6-4c51-96ae-5a8d400e2512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725592643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.3725592643
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.2058643654
Short name T856
Test name
Test status
Simulation time 21994908 ps
CPU time 1.29 seconds
Started Jul 27 05:32:05 PM PDT 24
Finished Jul 27 05:32:07 PM PDT 24
Peak memory 216416 kb
Host smart-ad504845-c6fd-44f6-8171-20cea6c564c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058643654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.2058643654
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.4074318966
Short name T840
Test name
Test status
Simulation time 29483687 ps
CPU time 0.67 seconds
Started Jul 27 05:32:07 PM PDT 24
Finished Jul 27 05:32:08 PM PDT 24
Peak memory 205628 kb
Host smart-09e4fe5f-d4d0-46d1-87ec-c31efc1ba326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074318966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.4074318966
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.520805415
Short name T61
Test name
Test status
Simulation time 134914000122 ps
CPU time 21.24 seconds
Started Jul 27 05:32:05 PM PDT 24
Finished Jul 27 05:32:27 PM PDT 24
Peak memory 224684 kb
Host smart-681da6e1-9443-4837-bc62-316d44ddae70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520805415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.520805415
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.3360343381
Short name T496
Test name
Test status
Simulation time 19122374 ps
CPU time 0.73 seconds
Started Jul 27 05:32:15 PM PDT 24
Finished Jul 27 05:32:16 PM PDT 24
Peak memory 205552 kb
Host smart-680915f6-79ba-4c53-851d-987ae578ca19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360343381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
3360343381
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.1243350186
Short name T423
Test name
Test status
Simulation time 1632816923 ps
CPU time 4.56 seconds
Started Jul 27 05:32:20 PM PDT 24
Finished Jul 27 05:32:25 PM PDT 24
Peak memory 224568 kb
Host smart-fe0c5ccc-d501-4183-9cc5-df7ea3bf8878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243350186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.1243350186
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.4217369518
Short name T332
Test name
Test status
Simulation time 63529729 ps
CPU time 0.76 seconds
Started Jul 27 05:32:03 PM PDT 24
Finished Jul 27 05:32:04 PM PDT 24
Peak memory 205680 kb
Host smart-12173cd8-4fa5-4f86-86bc-01e3eed29e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217369518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.4217369518
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.2735640651
Short name T358
Test name
Test status
Simulation time 42793350681 ps
CPU time 78.94 seconds
Started Jul 27 05:32:16 PM PDT 24
Finished Jul 27 05:33:35 PM PDT 24
Peak memory 249264 kb
Host smart-23546472-6fc1-42ad-bd89-54953b889e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735640651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.2735640651
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.2926257307
Short name T791
Test name
Test status
Simulation time 28544201771 ps
CPU time 106.17 seconds
Started Jul 27 05:32:16 PM PDT 24
Finished Jul 27 05:34:02 PM PDT 24
Peak memory 257452 kb
Host smart-c3e381e3-0b19-4402-81b7-77efec285313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926257307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.2926257307
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_intercept.416356526
Short name T652
Test name
Test status
Simulation time 4638375125 ps
CPU time 16.56 seconds
Started Jul 27 05:32:16 PM PDT 24
Finished Jul 27 05:32:32 PM PDT 24
Peak memory 232892 kb
Host smart-e7435dcd-5318-4675-a8ce-3bf17ab86f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416356526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.416356526
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.668246379
Short name T646
Test name
Test status
Simulation time 8834910363 ps
CPU time 24.23 seconds
Started Jul 27 05:32:15 PM PDT 24
Finished Jul 27 05:32:39 PM PDT 24
Peak memory 232900 kb
Host smart-cab46424-de0b-4aad-9753-76ac076249ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668246379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swap
.668246379
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.1420382386
Short name T371
Test name
Test status
Simulation time 14214284821 ps
CPU time 11.22 seconds
Started Jul 27 05:32:17 PM PDT 24
Finished Jul 27 05:32:28 PM PDT 24
Peak memory 232896 kb
Host smart-f5650114-2810-4956-9fcf-7e56dc772972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420382386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.1420382386
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.2774952302
Short name T386
Test name
Test status
Simulation time 10944491578 ps
CPU time 11.9 seconds
Started Jul 27 05:32:12 PM PDT 24
Finished Jul 27 05:32:24 PM PDT 24
Peak memory 219524 kb
Host smart-339b0b2d-4b57-4a47-b252-378c4e1ff314
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2774952302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.2774952302
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.2834356180
Short name T55
Test name
Test status
Simulation time 310681859465 ps
CPU time 393.68 seconds
Started Jul 27 05:32:17 PM PDT 24
Finished Jul 27 05:38:51 PM PDT 24
Peak memory 269872 kb
Host smart-c89c1105-22d7-4cb7-81b9-53e30f30b356
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834356180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.2834356180
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.1167594214
Short name T84
Test name
Test status
Simulation time 1682341912 ps
CPU time 25.86 seconds
Started Jul 27 05:32:15 PM PDT 24
Finished Jul 27 05:32:41 PM PDT 24
Peak memory 216308 kb
Host smart-341e5ccc-c611-4b5f-9efa-e8f2d0aefe96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167594214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.1167594214
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.3059283519
Short name T781
Test name
Test status
Simulation time 12269206 ps
CPU time 0.73 seconds
Started Jul 27 05:32:15 PM PDT 24
Finished Jul 27 05:32:16 PM PDT 24
Peak memory 205692 kb
Host smart-65281147-68b8-43d3-9c40-e7b4eef23309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059283519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.3059283519
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.1838969016
Short name T561
Test name
Test status
Simulation time 32277194 ps
CPU time 1 seconds
Started Jul 27 05:32:17 PM PDT 24
Finished Jul 27 05:32:18 PM PDT 24
Peak memory 207984 kb
Host smart-60c869ef-ffa3-4029-9208-cdd04a6b8e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838969016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.1838969016
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.2922653960
Short name T622
Test name
Test status
Simulation time 128905695 ps
CPU time 0.74 seconds
Started Jul 27 05:32:13 PM PDT 24
Finished Jul 27 05:32:14 PM PDT 24
Peak memory 206068 kb
Host smart-576669ef-7eba-4423-b173-2cc1987a7d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922653960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.2922653960
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.294883160
Short name T240
Test name
Test status
Simulation time 11561653202 ps
CPU time 11.1 seconds
Started Jul 27 05:32:18 PM PDT 24
Finished Jul 27 05:32:29 PM PDT 24
Peak memory 224604 kb
Host smart-6ab9d88e-e47c-44e0-bfca-119ae5d51865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294883160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.294883160
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.2072196647
Short name T851
Test name
Test status
Simulation time 44514745 ps
CPU time 0.76 seconds
Started Jul 27 05:32:14 PM PDT 24
Finished Jul 27 05:32:15 PM PDT 24
Peak memory 204912 kb
Host smart-e97774c4-5c43-4800-a251-22025efcebff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072196647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
2072196647
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.3915827520
Short name T994
Test name
Test status
Simulation time 131906098 ps
CPU time 2.7 seconds
Started Jul 27 05:32:22 PM PDT 24
Finished Jul 27 05:32:25 PM PDT 24
Peak memory 232792 kb
Host smart-7f7011e9-60c2-46e0-a7de-fb2786a46903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915827520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.3915827520
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.1753827113
Short name T529
Test name
Test status
Simulation time 13787790 ps
CPU time 0.79 seconds
Started Jul 27 05:32:20 PM PDT 24
Finished Jul 27 05:32:21 PM PDT 24
Peak memory 206720 kb
Host smart-9b13c4f7-9961-44f9-98a9-e5583612a084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753827113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.1753827113
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.3749376552
Short name T830
Test name
Test status
Simulation time 58937844918 ps
CPU time 127.55 seconds
Started Jul 27 05:32:19 PM PDT 24
Finished Jul 27 05:34:27 PM PDT 24
Peak memory 256532 kb
Host smart-b6cc3a98-bafa-4e1a-8fd6-0a0bf59f2bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749376552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.3749376552
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.3283787637
Short name T787
Test name
Test status
Simulation time 10125599523 ps
CPU time 67.96 seconds
Started Jul 27 05:32:14 PM PDT 24
Finished Jul 27 05:33:22 PM PDT 24
Peak memory 234796 kb
Host smart-e28e2325-ab7f-44b7-a9e3-929b1eaf8f96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283787637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.3283787637
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.2375153132
Short name T739
Test name
Test status
Simulation time 3865542574 ps
CPU time 54.16 seconds
Started Jul 27 05:32:23 PM PDT 24
Finished Jul 27 05:33:17 PM PDT 24
Peak memory 249476 kb
Host smart-4f297490-909a-4129-b580-70d6a2205eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375153132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.2375153132
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.1777575977
Short name T5
Test name
Test status
Simulation time 119610097 ps
CPU time 2.62 seconds
Started Jul 27 05:32:16 PM PDT 24
Finished Jul 27 05:32:19 PM PDT 24
Peak memory 233080 kb
Host smart-e73bc7fd-bbd4-44ba-86e0-1990eafba92c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777575977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.1777575977
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.1591863355
Short name T924
Test name
Test status
Simulation time 60640629871 ps
CPU time 189.06 seconds
Started Jul 27 05:32:17 PM PDT 24
Finished Jul 27 05:35:26 PM PDT 24
Peak memory 249740 kb
Host smart-93683f67-9ec2-453d-8e54-e432b5fa25a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591863355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmd
s.1591863355
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_intercept.851303375
Short name T816
Test name
Test status
Simulation time 2020109876 ps
CPU time 23.12 seconds
Started Jul 27 05:32:15 PM PDT 24
Finished Jul 27 05:32:38 PM PDT 24
Peak memory 232776 kb
Host smart-bee30fec-246f-49a9-9e43-8280e0c94f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851303375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.851303375
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.4017494464
Short name T670
Test name
Test status
Simulation time 670343600 ps
CPU time 5.14 seconds
Started Jul 27 05:32:15 PM PDT 24
Finished Jul 27 05:32:20 PM PDT 24
Peak memory 232768 kb
Host smart-19da1c5c-27e9-45c6-8b13-f0eb8a93a104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017494464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.4017494464
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.3656243237
Short name T927
Test name
Test status
Simulation time 2514120557 ps
CPU time 9.66 seconds
Started Jul 27 05:32:16 PM PDT 24
Finished Jul 27 05:32:25 PM PDT 24
Peak memory 224652 kb
Host smart-a80e871c-74b0-46ce-b7f0-4eaecd93e548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656243237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.3656243237
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.2253722108
Short name T410
Test name
Test status
Simulation time 32308758039 ps
CPU time 17.87 seconds
Started Jul 27 05:32:14 PM PDT 24
Finished Jul 27 05:32:32 PM PDT 24
Peak memory 232872 kb
Host smart-0f9dd1b7-ca92-40ec-ba88-87f17a9f37bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253722108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.2253722108
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.97277542
Short name T453
Test name
Test status
Simulation time 1197161811 ps
CPU time 9.64 seconds
Started Jul 27 05:32:15 PM PDT 24
Finished Jul 27 05:32:25 PM PDT 24
Peak memory 222228 kb
Host smart-fa718ba9-7b14-4fd0-8f53-d5924d3d06ca
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=97277542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_direc
t.97277542
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.100203867
Short name T643
Test name
Test status
Simulation time 40150976071 ps
CPU time 93.63 seconds
Started Jul 27 05:32:17 PM PDT 24
Finished Jul 27 05:33:51 PM PDT 24
Peak memory 252880 kb
Host smart-2e7b4140-a2cb-46e0-8bc3-a1b1e1654a97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100203867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stres
s_all.100203867
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.1661517612
Short name T981
Test name
Test status
Simulation time 6633978973 ps
CPU time 35.7 seconds
Started Jul 27 05:32:21 PM PDT 24
Finished Jul 27 05:32:57 PM PDT 24
Peak memory 216476 kb
Host smart-83d6c75c-7a0e-4fa6-94b7-3c389ea42246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661517612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.1661517612
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.3345012589
Short name T630
Test name
Test status
Simulation time 992509181 ps
CPU time 2.83 seconds
Started Jul 27 05:32:16 PM PDT 24
Finished Jul 27 05:32:19 PM PDT 24
Peak memory 216280 kb
Host smart-2228556f-9dc1-4a18-bae3-7e6374d311e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345012589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.3345012589
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.2270641055
Short name T482
Test name
Test status
Simulation time 102588157 ps
CPU time 1.77 seconds
Started Jul 27 05:32:13 PM PDT 24
Finished Jul 27 05:32:15 PM PDT 24
Peak memory 216360 kb
Host smart-c12860c7-19c7-48f0-ac9f-a300a5d7bbd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270641055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.2270641055
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.2056949576
Short name T440
Test name
Test status
Simulation time 36524734 ps
CPU time 0.89 seconds
Started Jul 27 05:32:14 PM PDT 24
Finished Jul 27 05:32:15 PM PDT 24
Peak memory 206084 kb
Host smart-c6cd744a-e458-4ccb-b4be-2df80c5f0129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056949576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.2056949576
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.2543022408
Short name T616
Test name
Test status
Simulation time 2021599912 ps
CPU time 5.06 seconds
Started Jul 27 05:32:13 PM PDT 24
Finished Jul 27 05:32:18 PM PDT 24
Peak memory 232820 kb
Host smart-3d495a2f-99fd-4f9f-a9e8-6f25a6330cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543022408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.2543022408
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.2261751845
Short name T68
Test name
Test status
Simulation time 12196754 ps
CPU time 0.71 seconds
Started Jul 27 05:32:14 PM PDT 24
Finished Jul 27 05:32:15 PM PDT 24
Peak memory 205436 kb
Host smart-9d84ca41-1459-4cc7-a747-8db2a18d655c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261751845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
2261751845
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.3108484787
Short name T365
Test name
Test status
Simulation time 2205154796 ps
CPU time 3.42 seconds
Started Jul 27 05:32:29 PM PDT 24
Finished Jul 27 05:32:32 PM PDT 24
Peak memory 232808 kb
Host smart-31ebecec-6372-47c9-beb5-eaa3dc930a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108484787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.3108484787
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.2992066046
Short name T843
Test name
Test status
Simulation time 183993144 ps
CPU time 0.82 seconds
Started Jul 27 05:32:14 PM PDT 24
Finished Jul 27 05:32:15 PM PDT 24
Peak memory 206700 kb
Host smart-c5a2ff9d-9d4d-4418-9685-c44d85c4e814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992066046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.2992066046
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.1931903661
Short name T823
Test name
Test status
Simulation time 401517145 ps
CPU time 5.99 seconds
Started Jul 27 05:32:18 PM PDT 24
Finished Jul 27 05:32:24 PM PDT 24
Peak memory 235220 kb
Host smart-79abe838-c2aa-46d9-b405-17da4935facd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931903661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.1931903661
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.1803801656
Short name T246
Test name
Test status
Simulation time 22577290581 ps
CPU time 105.56 seconds
Started Jul 27 05:32:21 PM PDT 24
Finished Jul 27 05:34:06 PM PDT 24
Peak memory 254872 kb
Host smart-dcff1ccb-c59d-44cc-abba-b0de74881958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803801656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.1803801656
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.2179089817
Short name T800
Test name
Test status
Simulation time 8178444973 ps
CPU time 73.75 seconds
Started Jul 27 05:32:14 PM PDT 24
Finished Jul 27 05:33:28 PM PDT 24
Peak memory 249280 kb
Host smart-986a9979-8318-4f93-87be-bf4aded44e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179089817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.2179089817
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.1169290070
Short name T77
Test name
Test status
Simulation time 2574380373 ps
CPU time 7.01 seconds
Started Jul 27 05:32:18 PM PDT 24
Finished Jul 27 05:32:25 PM PDT 24
Peak memory 232840 kb
Host smart-9f9a10e0-d7c9-4376-be50-2865bf4168be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169290070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.1169290070
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.2178335871
Short name T65
Test name
Test status
Simulation time 30552019250 ps
CPU time 59.66 seconds
Started Jul 27 05:32:18 PM PDT 24
Finished Jul 27 05:33:18 PM PDT 24
Peak memory 237752 kb
Host smart-691db522-9bb7-43c6-9818-f456bdf8915d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178335871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmd
s.2178335871
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_intercept.451079864
Short name T725
Test name
Test status
Simulation time 2200054435 ps
CPU time 4.91 seconds
Started Jul 27 05:32:16 PM PDT 24
Finished Jul 27 05:32:21 PM PDT 24
Peak memory 232924 kb
Host smart-0a30490e-7234-4a96-86cd-ac9a0c0d79e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451079864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.451079864
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.1824310651
Short name T422
Test name
Test status
Simulation time 1493409635 ps
CPU time 6.55 seconds
Started Jul 27 05:32:16 PM PDT 24
Finished Jul 27 05:32:23 PM PDT 24
Peak memory 224648 kb
Host smart-dc9d787e-e945-4881-a635-2ba811bac1ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824310651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.1824310651
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.3330651206
Short name T895
Test name
Test status
Simulation time 223549040 ps
CPU time 3.34 seconds
Started Jul 27 05:32:22 PM PDT 24
Finished Jul 27 05:32:25 PM PDT 24
Peak memory 232840 kb
Host smart-7b251f33-7ce0-47b0-bc91-777763c3aa57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330651206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.3330651206
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.333532766
Short name T617
Test name
Test status
Simulation time 13130664829 ps
CPU time 9.11 seconds
Started Jul 27 05:32:22 PM PDT 24
Finished Jul 27 05:32:31 PM PDT 24
Peak memory 237696 kb
Host smart-b8ebaf18-c62e-48f1-84dc-70dc837bd20b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333532766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.333532766
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.3964339364
Short name T907
Test name
Test status
Simulation time 2220634486 ps
CPU time 10.14 seconds
Started Jul 27 05:32:16 PM PDT 24
Finished Jul 27 05:32:26 PM PDT 24
Peak memory 220620 kb
Host smart-5b9479a9-4ddb-44ed-871a-710915e98a52
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3964339364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.3964339364
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.1748901038
Short name T961
Test name
Test status
Simulation time 65731128251 ps
CPU time 361.82 seconds
Started Jul 27 05:32:16 PM PDT 24
Finished Jul 27 05:38:18 PM PDT 24
Peak memory 273584 kb
Host smart-b3ff97dd-4436-46a5-bf70-c6e30207d965
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748901038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.1748901038
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.1587625735
Short name T580
Test name
Test status
Simulation time 2264085157 ps
CPU time 15.34 seconds
Started Jul 27 05:32:18 PM PDT 24
Finished Jul 27 05:32:33 PM PDT 24
Peak memory 219460 kb
Host smart-016987b4-d5a9-480f-9351-490332f780c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587625735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.1587625735
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.3502281520
Short name T361
Test name
Test status
Simulation time 18730173610 ps
CPU time 14.34 seconds
Started Jul 27 05:32:19 PM PDT 24
Finished Jul 27 05:32:33 PM PDT 24
Peak memory 217360 kb
Host smart-ed470089-ed82-49d0-94b1-8cd3cbccd1fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502281520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.3502281520
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.2433930049
Short name T854
Test name
Test status
Simulation time 30905933 ps
CPU time 1.27 seconds
Started Jul 27 05:32:20 PM PDT 24
Finished Jul 27 05:32:22 PM PDT 24
Peak memory 216400 kb
Host smart-ff49c436-e9a5-4641-a0d4-2ae17b42d8be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433930049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.2433930049
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.1729071288
Short name T723
Test name
Test status
Simulation time 55700519 ps
CPU time 0.86 seconds
Started Jul 27 05:32:15 PM PDT 24
Finished Jul 27 05:32:16 PM PDT 24
Peak memory 206000 kb
Host smart-93a69322-0602-4902-9e1d-7785094dd14d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729071288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.1729071288
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.1218941518
Short name T1006
Test name
Test status
Simulation time 765230071 ps
CPU time 4.61 seconds
Started Jul 27 05:32:16 PM PDT 24
Finished Jul 27 05:32:20 PM PDT 24
Peak memory 232808 kb
Host smart-40536d54-65e5-4dc5-be91-5d5b3c76f075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218941518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.1218941518
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.1585618643
Short name T372
Test name
Test status
Simulation time 17176800 ps
CPU time 0.72 seconds
Started Jul 27 05:32:28 PM PDT 24
Finished Jul 27 05:32:28 PM PDT 24
Peak memory 205484 kb
Host smart-3ab95fe9-b3b0-4439-9148-46b84fa0c611
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585618643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
1585618643
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.3333319336
Short name T322
Test name
Test status
Simulation time 416431943 ps
CPU time 6.45 seconds
Started Jul 27 05:32:20 PM PDT 24
Finished Jul 27 05:32:26 PM PDT 24
Peak memory 232784 kb
Host smart-e21c823e-169a-4da5-b6b6-3398e3187cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333319336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.3333319336
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.4082258341
Short name T503
Test name
Test status
Simulation time 58742301 ps
CPU time 0.8 seconds
Started Jul 27 05:32:17 PM PDT 24
Finished Jul 27 05:32:18 PM PDT 24
Peak memory 206720 kb
Host smart-e1094cd5-2a6c-4d4b-a3e2-f1e3c2ba25c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082258341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.4082258341
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.1209984569
Short name T200
Test name
Test status
Simulation time 1747642361 ps
CPU time 42.13 seconds
Started Jul 27 05:32:26 PM PDT 24
Finished Jul 27 05:33:08 PM PDT 24
Peak memory 250456 kb
Host smart-0698e739-0cbc-43a7-be61-6e77faa2a12b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209984569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.1209984569
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.786920730
Short name T820
Test name
Test status
Simulation time 55431241525 ps
CPU time 122.11 seconds
Started Jul 27 05:32:27 PM PDT 24
Finished Jul 27 05:34:30 PM PDT 24
Peak memory 241396 kb
Host smart-123c6326-f008-4591-be03-00dc9ebda318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786920730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idle
.786920730
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.2515178138
Short name T283
Test name
Test status
Simulation time 1398467457 ps
CPU time 8.16 seconds
Started Jul 27 05:32:20 PM PDT 24
Finished Jul 27 05:32:28 PM PDT 24
Peak memory 240952 kb
Host smart-99e327be-e3f5-4cff-a339-52e6472fe01f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515178138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.2515178138
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.3038528928
Short name T243
Test name
Test status
Simulation time 11812370643 ps
CPU time 80.16 seconds
Started Jul 27 05:32:22 PM PDT 24
Finished Jul 27 05:33:42 PM PDT 24
Peak memory 256760 kb
Host smart-e79e3339-fc36-4b0f-9b22-365708d3c107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038528928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmd
s.3038528928
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/18.spi_device_intercept.3189890528
Short name T762
Test name
Test status
Simulation time 1354865978 ps
CPU time 5.98 seconds
Started Jul 27 05:32:20 PM PDT 24
Finished Jul 27 05:32:26 PM PDT 24
Peak memory 232728 kb
Host smart-1b28a68b-9f41-421e-b1ac-cd1eaef61770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189890528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.3189890528
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.3111329146
Short name T972
Test name
Test status
Simulation time 96899309 ps
CPU time 2.55 seconds
Started Jul 27 05:32:22 PM PDT 24
Finished Jul 27 05:32:25 PM PDT 24
Peak memory 232520 kb
Host smart-3645f577-d344-4fc1-826c-fc607ae11d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111329146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.3111329146
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.1873666489
Short name T385
Test name
Test status
Simulation time 8346415748 ps
CPU time 7.5 seconds
Started Jul 27 05:32:21 PM PDT 24
Finished Jul 27 05:32:29 PM PDT 24
Peak memory 232900 kb
Host smart-0e4ee0c1-cdf9-4671-83ed-6d4e9b618f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873666489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.1873666489
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.607714480
Short name T481
Test name
Test status
Simulation time 3009351749 ps
CPU time 7.09 seconds
Started Jul 27 05:32:20 PM PDT 24
Finished Jul 27 05:32:27 PM PDT 24
Peak memory 232824 kb
Host smart-d95907e0-2514-4a1a-88b6-78648417335e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607714480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.607714480
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.1827195481
Short name T960
Test name
Test status
Simulation time 93916471 ps
CPU time 3.88 seconds
Started Jul 27 05:32:26 PM PDT 24
Finished Jul 27 05:32:30 PM PDT 24
Peak memory 223336 kb
Host smart-b0f6b8f7-89ce-44af-9c13-fb18e9775fb9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1827195481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.1827195481
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.2168002471
Short name T160
Test name
Test status
Simulation time 5616575484 ps
CPU time 57.23 seconds
Started Jul 27 05:32:34 PM PDT 24
Finished Jul 27 05:33:31 PM PDT 24
Peak memory 255852 kb
Host smart-ad5f8848-4cc7-4081-bf38-02c1b152b8f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168002471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.2168002471
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.4170219068
Short name T292
Test name
Test status
Simulation time 1372630769 ps
CPU time 7.86 seconds
Started Jul 27 05:32:20 PM PDT 24
Finished Jul 27 05:32:27 PM PDT 24
Peak memory 216220 kb
Host smart-cf3088cb-76a2-4513-a498-48f85b5e86ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170219068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.4170219068
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.1360001438
Short name T672
Test name
Test status
Simulation time 708805941 ps
CPU time 1.24 seconds
Started Jul 27 05:32:19 PM PDT 24
Finished Jul 27 05:32:20 PM PDT 24
Peak memory 207800 kb
Host smart-b7f58c61-6ad9-445f-a4bf-ff7f207494e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360001438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.1360001438
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.624398978
Short name T374
Test name
Test status
Simulation time 437722900 ps
CPU time 1.03 seconds
Started Jul 27 05:32:26 PM PDT 24
Finished Jul 27 05:32:27 PM PDT 24
Peak memory 207404 kb
Host smart-114b80ff-d114-4b7a-8025-d7da9d5ee71f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624398978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.624398978
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.2427400934
Short name T546
Test name
Test status
Simulation time 19236865 ps
CPU time 0.78 seconds
Started Jul 27 05:32:20 PM PDT 24
Finished Jul 27 05:32:21 PM PDT 24
Peak memory 206100 kb
Host smart-8afcb821-816e-441e-96d8-3099557db054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427400934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.2427400934
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.1673568191
Short name T7
Test name
Test status
Simulation time 301595034 ps
CPU time 2.44 seconds
Started Jul 27 05:32:30 PM PDT 24
Finished Jul 27 05:32:33 PM PDT 24
Peak memory 232852 kb
Host smart-b50dffc2-76e0-49dc-8cd5-f8264ae1b38f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673568191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.1673568191
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.2532974122
Short name T758
Test name
Test status
Simulation time 13875763 ps
CPU time 0.72 seconds
Started Jul 27 05:32:35 PM PDT 24
Finished Jul 27 05:32:36 PM PDT 24
Peak memory 205868 kb
Host smart-760f615a-261e-4514-83a1-76b40d1ac2cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532974122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
2532974122
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.2505936028
Short name T484
Test name
Test status
Simulation time 7457620730 ps
CPU time 9.52 seconds
Started Jul 27 05:32:28 PM PDT 24
Finished Jul 27 05:32:38 PM PDT 24
Peak memory 232872 kb
Host smart-22939ec4-6759-4ca6-8bd1-9407af0f2123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505936028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.2505936028
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.1789758928
Short name T534
Test name
Test status
Simulation time 17794412 ps
CPU time 0.77 seconds
Started Jul 27 05:32:27 PM PDT 24
Finished Jul 27 05:32:27 PM PDT 24
Peak memory 207024 kb
Host smart-37a7e70e-f9ae-4af6-95ea-8b5b4ee7f9cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789758928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.1789758928
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.2166183712
Short name T990
Test name
Test status
Simulation time 33641777763 ps
CPU time 237.73 seconds
Started Jul 27 05:32:29 PM PDT 24
Finished Jul 27 05:36:27 PM PDT 24
Peak memory 253560 kb
Host smart-b4870a39-953d-4e13-9f37-42eb2f2726b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166183712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.2166183712
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.3672828150
Short name T175
Test name
Test status
Simulation time 80122144458 ps
CPU time 155.95 seconds
Started Jul 27 05:32:27 PM PDT 24
Finished Jul 27 05:35:04 PM PDT 24
Peak memory 249312 kb
Host smart-870144b3-451b-4394-80c1-6e5871715c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672828150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.3672828150
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.137883761
Short name T388
Test name
Test status
Simulation time 25518564788 ps
CPU time 233.66 seconds
Started Jul 27 05:32:27 PM PDT 24
Finished Jul 27 05:36:21 PM PDT 24
Peak memory 254564 kb
Host smart-92e8c6e8-0508-4d46-985c-584b2bee5d60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137883761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idle
.137883761
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.1821180015
Short name T497
Test name
Test status
Simulation time 179214109 ps
CPU time 2.85 seconds
Started Jul 27 05:32:30 PM PDT 24
Finished Jul 27 05:32:33 PM PDT 24
Peak memory 232808 kb
Host smart-6535eeea-373d-4ed6-ba2c-ae4a378cd300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821180015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.1821180015
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.1029167972
Short name T444
Test name
Test status
Simulation time 66992645767 ps
CPU time 249.15 seconds
Started Jul 27 05:32:31 PM PDT 24
Finished Jul 27 05:36:40 PM PDT 24
Peak memory 253160 kb
Host smart-d1676aac-861f-4ee9-8ded-37c0fac1d1c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029167972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmd
s.1029167972
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_intercept.3780527412
Short name T224
Test name
Test status
Simulation time 2612620041 ps
CPU time 20.04 seconds
Started Jul 27 05:32:35 PM PDT 24
Finished Jul 27 05:32:56 PM PDT 24
Peak memory 219044 kb
Host smart-8e0b5c29-af12-4aec-90b3-7c3e06558996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780527412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.3780527412
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.672995588
Short name T918
Test name
Test status
Simulation time 3331555300 ps
CPU time 24.16 seconds
Started Jul 27 05:32:27 PM PDT 24
Finished Jul 27 05:32:51 PM PDT 24
Peak memory 224704 kb
Host smart-85c3dbb1-aa2e-4c8b-8e98-d84c4895fe12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672995588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.672995588
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.355956862
Short name T101
Test name
Test status
Simulation time 345259255 ps
CPU time 3.64 seconds
Started Jul 27 05:32:26 PM PDT 24
Finished Jul 27 05:32:30 PM PDT 24
Peak memory 232876 kb
Host smart-e62bd0f3-d7f6-4482-897f-ef2a6a5cfdad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355956862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swap
.355956862
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.3007836042
Short name T514
Test name
Test status
Simulation time 6728479698 ps
CPU time 22.46 seconds
Started Jul 27 05:32:27 PM PDT 24
Finished Jul 27 05:32:49 PM PDT 24
Peak memory 248892 kb
Host smart-8e91576f-40d0-4517-ab37-1fd0d3954f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007836042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.3007836042
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.1433874082
Short name T849
Test name
Test status
Simulation time 1313111783 ps
CPU time 4.53 seconds
Started Jul 27 05:32:27 PM PDT 24
Finished Jul 27 05:32:31 PM PDT 24
Peak memory 220512 kb
Host smart-6e5b4d6d-05e6-4eae-8cf6-ed2740f17b37
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1433874082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.1433874082
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.1680908112
Short name T161
Test name
Test status
Simulation time 30170018132 ps
CPU time 114.68 seconds
Started Jul 27 05:32:28 PM PDT 24
Finished Jul 27 05:34:23 PM PDT 24
Peak memory 252316 kb
Host smart-b8a5ca33-26a1-4160-a0da-f09027874c56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680908112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.1680908112
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.2709775712
Short name T554
Test name
Test status
Simulation time 8114233511 ps
CPU time 17.51 seconds
Started Jul 27 05:32:27 PM PDT 24
Finished Jul 27 05:32:45 PM PDT 24
Peak memory 216476 kb
Host smart-68047865-ac56-4c41-a703-2fe4f9850fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709775712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.2709775712
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.3977800408
Short name T437
Test name
Test status
Simulation time 7035152348 ps
CPU time 22.29 seconds
Started Jul 27 05:32:32 PM PDT 24
Finished Jul 27 05:32:54 PM PDT 24
Peak memory 216480 kb
Host smart-6ed04da0-ff5e-41fc-b0c1-4e211d830980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977800408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.3977800408
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.3889535090
Short name T821
Test name
Test status
Simulation time 168736596 ps
CPU time 1.32 seconds
Started Jul 27 05:32:26 PM PDT 24
Finished Jul 27 05:32:28 PM PDT 24
Peak memory 216348 kb
Host smart-ec714bdf-f291-448c-b43e-1bc69c4d011c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889535090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.3889535090
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.3242007201
Short name T983
Test name
Test status
Simulation time 159423321 ps
CPU time 0.96 seconds
Started Jul 27 05:32:27 PM PDT 24
Finished Jul 27 05:32:29 PM PDT 24
Peak memory 206012 kb
Host smart-fc353214-6d70-4960-9986-7f4eef1f0568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242007201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.3242007201
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.2099340191
Short name T461
Test name
Test status
Simulation time 32821315604 ps
CPU time 16.69 seconds
Started Jul 27 05:32:37 PM PDT 24
Finished Jul 27 05:32:54 PM PDT 24
Peak memory 232856 kb
Host smart-7d717858-fcd9-4078-83e8-adda12a41df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099340191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.2099340191
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.408932377
Short name T859
Test name
Test status
Simulation time 12064668 ps
CPU time 0.69 seconds
Started Jul 27 05:31:08 PM PDT 24
Finished Jul 27 05:31:09 PM PDT 24
Peak memory 205596 kb
Host smart-910be743-324e-4b17-9783-670fb1413f48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408932377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.408932377
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.2598264709
Short name T619
Test name
Test status
Simulation time 234370035 ps
CPU time 2.79 seconds
Started Jul 27 05:31:08 PM PDT 24
Finished Jul 27 05:31:11 PM PDT 24
Peak memory 232876 kb
Host smart-800b34e3-14e4-4cf6-be8a-ac4b0130159d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598264709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.2598264709
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.2150737331
Short name T435
Test name
Test status
Simulation time 20864236 ps
CPU time 0.79 seconds
Started Jul 27 05:31:12 PM PDT 24
Finished Jul 27 05:31:13 PM PDT 24
Peak memory 206596 kb
Host smart-c563abb4-4f40-4a05-8fe5-328587c4eca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150737331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.2150737331
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.2903444401
Short name T182
Test name
Test status
Simulation time 10494663253 ps
CPU time 111.41 seconds
Started Jul 27 05:31:07 PM PDT 24
Finished Jul 27 05:32:59 PM PDT 24
Peak memory 263520 kb
Host smart-57d66220-4787-4eb7-bb92-27091993aebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903444401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.2903444401
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.703093085
Short name T806
Test name
Test status
Simulation time 86136344387 ps
CPU time 182.42 seconds
Started Jul 27 05:31:10 PM PDT 24
Finished Jul 27 05:34:12 PM PDT 24
Peak memory 250928 kb
Host smart-e4a0f180-553e-45f0-8f1f-55c540d7efe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703093085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.703093085
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.517429785
Short name T746
Test name
Test status
Simulation time 52127143994 ps
CPU time 95.76 seconds
Started Jul 27 05:31:13 PM PDT 24
Finished Jul 27 05:32:49 PM PDT 24
Peak memory 250968 kb
Host smart-3504acd5-12e5-4a57-99c9-ccdbda24e99d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517429785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle.
517429785
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.3732293298
Short name T986
Test name
Test status
Simulation time 479140633 ps
CPU time 6.04 seconds
Started Jul 27 05:31:12 PM PDT 24
Finished Jul 27 05:31:18 PM PDT 24
Peak memory 224508 kb
Host smart-748faab5-abc8-4451-ae31-48bc1934ef5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732293298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.3732293298
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.1622485673
Short name T923
Test name
Test status
Simulation time 55493688313 ps
CPU time 94.77 seconds
Started Jul 27 05:31:12 PM PDT 24
Finished Jul 27 05:32:47 PM PDT 24
Peak memory 265588 kb
Host smart-7941c26f-0904-41e7-b710-4428d9ce52e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622485673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds
.1622485673
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_intercept.1873643974
Short name T668
Test name
Test status
Simulation time 316444534 ps
CPU time 2.63 seconds
Started Jul 27 05:31:11 PM PDT 24
Finished Jul 27 05:31:14 PM PDT 24
Peak memory 224604 kb
Host smart-b21bbcac-f3da-4bcf-aa86-6be0485a2a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873643974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.1873643974
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.2691944866
Short name T594
Test name
Test status
Simulation time 1581871345 ps
CPU time 14.02 seconds
Started Jul 27 05:31:10 PM PDT 24
Finished Jul 27 05:31:24 PM PDT 24
Peak memory 240888 kb
Host smart-4183aed2-c1b6-4f36-a18c-ed83fb5394ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691944866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.2691944866
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.3491361156
Short name T568
Test name
Test status
Simulation time 5797471744 ps
CPU time 5.45 seconds
Started Jul 27 05:31:13 PM PDT 24
Finished Jul 27 05:31:19 PM PDT 24
Peak memory 232868 kb
Host smart-1bae0212-7a68-4587-af6d-d77aa760ec97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491361156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.3491361156
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.2067938668
Short name T703
Test name
Test status
Simulation time 332361945 ps
CPU time 6.68 seconds
Started Jul 27 05:31:12 PM PDT 24
Finished Jul 27 05:31:19 PM PDT 24
Peak memory 232672 kb
Host smart-b40033e3-6d56-45bf-9f84-cba6214ccfc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067938668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.2067938668
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.2960840973
Short name T669
Test name
Test status
Simulation time 2116862127 ps
CPU time 21.68 seconds
Started Jul 27 05:31:12 PM PDT 24
Finished Jul 27 05:31:34 PM PDT 24
Peak memory 222028 kb
Host smart-4bd376a0-9ab0-4a9d-b061-88f7687cf017
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2960840973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.2960840973
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.3635428328
Short name T74
Test name
Test status
Simulation time 275324633 ps
CPU time 1.1 seconds
Started Jul 27 05:31:10 PM PDT 24
Finished Jul 27 05:31:11 PM PDT 24
Peak memory 236440 kb
Host smart-1bf846ff-c23a-478a-a392-ca2ce8d8f2bf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635428328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.3635428328
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.3373671457
Short name T557
Test name
Test status
Simulation time 14776843737 ps
CPU time 22.45 seconds
Started Jul 27 05:31:06 PM PDT 24
Finished Jul 27 05:31:29 PM PDT 24
Peak memory 216448 kb
Host smart-347679ea-8473-4249-93aa-391e9e15f013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373671457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.3373671457
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.2254477434
Short name T58
Test name
Test status
Simulation time 13307745 ps
CPU time 0.71 seconds
Started Jul 27 05:31:09 PM PDT 24
Finished Jul 27 05:31:10 PM PDT 24
Peak memory 205784 kb
Host smart-d23b356f-606b-4a2e-b5aa-4967a0a584bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254477434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.2254477434
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.4081956088
Short name T658
Test name
Test status
Simulation time 151796329 ps
CPU time 2.42 seconds
Started Jul 27 05:31:11 PM PDT 24
Finished Jul 27 05:31:14 PM PDT 24
Peak memory 216280 kb
Host smart-39fd8f0c-7a54-44e8-bd2b-556a4a669378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081956088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.4081956088
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.977167396
Short name T633
Test name
Test status
Simulation time 103340764 ps
CPU time 0.82 seconds
Started Jul 27 05:31:11 PM PDT 24
Finished Jul 27 05:31:12 PM PDT 24
Peak memory 206076 kb
Host smart-810d3a6b-ee50-42d4-ab81-9eeda3f12766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977167396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.977167396
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.2975446060
Short name T411
Test name
Test status
Simulation time 24357707118 ps
CPU time 25.07 seconds
Started Jul 27 05:31:14 PM PDT 24
Finished Jul 27 05:31:39 PM PDT 24
Peak memory 241748 kb
Host smart-a0257984-ccad-43f8-bd9e-e6a8ddb4e00d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975446060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.2975446060
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.2825666174
Short name T504
Test name
Test status
Simulation time 59572689 ps
CPU time 0.71 seconds
Started Jul 27 05:32:35 PM PDT 24
Finished Jul 27 05:32:35 PM PDT 24
Peak memory 205868 kb
Host smart-75863e70-2fbf-42d6-9ea6-7120c1fcceb1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825666174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
2825666174
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.2964996025
Short name T574
Test name
Test status
Simulation time 124846950 ps
CPU time 2.6 seconds
Started Jul 27 05:32:28 PM PDT 24
Finished Jul 27 05:32:31 PM PDT 24
Peak memory 232504 kb
Host smart-af394652-5e13-446a-bf1a-2a2269da7a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964996025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.2964996025
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.796476766
Short name T813
Test name
Test status
Simulation time 14347470 ps
CPU time 0.77 seconds
Started Jul 27 05:32:26 PM PDT 24
Finished Jul 27 05:32:27 PM PDT 24
Peak memory 206664 kb
Host smart-8927e6b2-b750-4e8f-ad4e-f6d6df8e8fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796476766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.796476766
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.2043300589
Short name T17
Test name
Test status
Simulation time 62664804046 ps
CPU time 208.96 seconds
Started Jul 27 05:32:27 PM PDT 24
Finished Jul 27 05:35:56 PM PDT 24
Peak memory 250384 kb
Host smart-1d0ca576-50af-4b0e-b88b-e3ba051a5497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043300589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.2043300589
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.2293840971
Short name T35
Test name
Test status
Simulation time 29733267522 ps
CPU time 95.6 seconds
Started Jul 27 05:32:29 PM PDT 24
Finished Jul 27 05:34:05 PM PDT 24
Peak memory 265352 kb
Host smart-f4b7113b-0563-4983-a716-0bc9b44a668a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293840971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.2293840971
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.1087299857
Short name T579
Test name
Test status
Simulation time 6108525723 ps
CPU time 26.42 seconds
Started Jul 27 05:32:26 PM PDT 24
Finished Jul 27 05:32:52 PM PDT 24
Peak memory 232808 kb
Host smart-c2560f15-ca38-4e35-9db0-d330d29410f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087299857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.1087299857
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.3627463290
Short name T810
Test name
Test status
Simulation time 22402917478 ps
CPU time 97.28 seconds
Started Jul 27 05:32:29 PM PDT 24
Finished Jul 27 05:34:07 PM PDT 24
Peak memory 249308 kb
Host smart-f5433830-2e8a-4cf0-8149-3f51f03e0e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627463290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmd
s.3627463290
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_intercept.90060076
Short name T197
Test name
Test status
Simulation time 2025215354 ps
CPU time 22.42 seconds
Started Jul 27 05:32:27 PM PDT 24
Finished Jul 27 05:32:50 PM PDT 24
Peak memory 224600 kb
Host smart-a85d43e1-d86e-4498-972e-be197c6459f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90060076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.90060076
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.2702107891
Short name T828
Test name
Test status
Simulation time 714870752 ps
CPU time 2.29 seconds
Started Jul 27 05:32:34 PM PDT 24
Finished Jul 27 05:32:37 PM PDT 24
Peak memory 223244 kb
Host smart-1b4489f1-286d-4b5a-9ae0-a4b95d435d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702107891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.2702107891
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.105636963
Short name T657
Test name
Test status
Simulation time 12913348257 ps
CPU time 11.06 seconds
Started Jul 27 05:32:35 PM PDT 24
Finished Jul 27 05:32:47 PM PDT 24
Peak memory 224708 kb
Host smart-130c0678-b514-4368-aa9d-1b548a61f26b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105636963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swap
.105636963
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.2368398171
Short name T916
Test name
Test status
Simulation time 14047703566 ps
CPU time 14.11 seconds
Started Jul 27 05:32:29 PM PDT 24
Finished Jul 27 05:32:43 PM PDT 24
Peak memory 241032 kb
Host smart-3b9e7ebc-a96d-49b2-845c-e2664cf00573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368398171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.2368398171
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.2476267139
Short name T434
Test name
Test status
Simulation time 4507314887 ps
CPU time 9.99 seconds
Started Jul 27 05:32:31 PM PDT 24
Finished Jul 27 05:32:41 PM PDT 24
Peak memory 219256 kb
Host smart-399a012d-a182-4b8f-bc80-aa7e34cd4ee0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2476267139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.2476267139
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.2549681799
Short name T162
Test name
Test status
Simulation time 10378871971 ps
CPU time 13.58 seconds
Started Jul 27 05:32:26 PM PDT 24
Finished Jul 27 05:32:40 PM PDT 24
Peak memory 217744 kb
Host smart-25c7495d-4254-4316-90f6-ffb6d41c6a50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549681799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.2549681799
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.901726046
Short name T480
Test name
Test status
Simulation time 3263125309 ps
CPU time 24.29 seconds
Started Jul 27 05:32:32 PM PDT 24
Finished Jul 27 05:32:56 PM PDT 24
Peak memory 216420 kb
Host smart-3578f2cf-5235-4a8b-af17-61d0ea48b44d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901726046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.901726046
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.1764073071
Short name T308
Test name
Test status
Simulation time 19402267124 ps
CPU time 22.41 seconds
Started Jul 27 05:32:27 PM PDT 24
Finished Jul 27 05:32:49 PM PDT 24
Peak memory 216480 kb
Host smart-bf2c7f5a-3725-403a-9c70-ed062d746b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764073071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.1764073071
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.1449417996
Short name T524
Test name
Test status
Simulation time 64869266 ps
CPU time 1.62 seconds
Started Jul 27 05:32:26 PM PDT 24
Finished Jul 27 05:32:28 PM PDT 24
Peak memory 216328 kb
Host smart-1568269a-1447-4bba-82f0-375479e4c3a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449417996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.1449417996
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.3041851576
Short name T550
Test name
Test status
Simulation time 96341284 ps
CPU time 0.76 seconds
Started Jul 27 05:32:27 PM PDT 24
Finished Jul 27 05:32:28 PM PDT 24
Peak memory 206052 kb
Host smart-be2c0f89-1bc4-4447-92ba-0d39ad217056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041851576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.3041851576
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.825912105
Short name T408
Test name
Test status
Simulation time 7650207959 ps
CPU time 22.58 seconds
Started Jul 27 05:32:27 PM PDT 24
Finished Jul 27 05:32:50 PM PDT 24
Peak memory 232916 kb
Host smart-ec7307d8-f6a2-492a-b546-75391d1cd346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825912105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.825912105
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.3958083635
Short name T363
Test name
Test status
Simulation time 13891564 ps
CPU time 0.75 seconds
Started Jul 27 05:32:38 PM PDT 24
Finished Jul 27 05:32:38 PM PDT 24
Peak memory 205424 kb
Host smart-04316e6a-9eca-412a-9d48-c26abc0d938f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958083635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
3958083635
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.986866027
Short name T477
Test name
Test status
Simulation time 386891949 ps
CPU time 3.97 seconds
Started Jul 27 05:32:38 PM PDT 24
Finished Jul 27 05:32:42 PM PDT 24
Peak memory 232776 kb
Host smart-6788780f-8bd2-43fc-968b-b542d41d8a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986866027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.986866027
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.1219924125
Short name T884
Test name
Test status
Simulation time 33618605 ps
CPU time 0.75 seconds
Started Jul 27 05:32:28 PM PDT 24
Finished Jul 27 05:32:29 PM PDT 24
Peak memory 205644 kb
Host smart-6234af34-6899-4665-8eb4-a368c377b414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219924125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.1219924125
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.895450308
Short name T450
Test name
Test status
Simulation time 30295325706 ps
CPU time 108.97 seconds
Started Jul 27 05:32:39 PM PDT 24
Finished Jul 27 05:34:28 PM PDT 24
Peak memory 253792 kb
Host smart-fbeac64a-54f6-42c4-9c7e-6dffe3397dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895450308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.895450308
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.3164251756
Short name T809
Test name
Test status
Simulation time 5056873580 ps
CPU time 48.32 seconds
Started Jul 27 05:32:41 PM PDT 24
Finished Jul 27 05:33:29 PM PDT 24
Peak memory 248924 kb
Host smart-2b38adb3-f30b-4144-bbf3-f57b8370ecd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164251756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.3164251756
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.925670593
Short name T948
Test name
Test status
Simulation time 9837731436 ps
CPU time 73.6 seconds
Started Jul 27 05:32:39 PM PDT 24
Finished Jul 27 05:33:52 PM PDT 24
Peak memory 251476 kb
Host smart-4c811463-8c86-4157-be12-37fc14f45773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925670593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idle
.925670593
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.1562906805
Short name T832
Test name
Test status
Simulation time 4041447824 ps
CPU time 60.66 seconds
Started Jul 27 05:32:37 PM PDT 24
Finished Jul 27 05:33:38 PM PDT 24
Peak memory 236584 kb
Host smart-dd4d11e6-8df7-4c40-ae6e-6f6614b65120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562906805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.1562906805
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.3679241363
Short name T255
Test name
Test status
Simulation time 58394609794 ps
CPU time 399.33 seconds
Started Jul 27 05:32:34 PM PDT 24
Finished Jul 27 05:39:14 PM PDT 24
Peak memory 264208 kb
Host smart-fa4f11e2-7808-425a-92fd-e2320aa65026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679241363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmd
s.3679241363
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_intercept.37875883
Short name T595
Test name
Test status
Simulation time 106380171 ps
CPU time 2.85 seconds
Started Jul 27 05:32:39 PM PDT 24
Finished Jul 27 05:32:42 PM PDT 24
Peak memory 224604 kb
Host smart-78755a15-c70b-47b0-bb21-af7e5e04f5ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37875883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.37875883
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.2758701932
Short name T441
Test name
Test status
Simulation time 496579097 ps
CPU time 6.12 seconds
Started Jul 27 05:32:37 PM PDT 24
Finished Jul 27 05:32:43 PM PDT 24
Peak memory 238788 kb
Host smart-287ba144-a54b-42e7-aa6c-850356b2a033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758701932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.2758701932
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.1821450471
Short name T573
Test name
Test status
Simulation time 56090278 ps
CPU time 2.61 seconds
Started Jul 27 05:32:40 PM PDT 24
Finished Jul 27 05:32:42 PM PDT 24
Peak memory 232500 kb
Host smart-a3d6b5e9-1e7b-4464-b018-f96048b530a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821450471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.1821450471
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.3237777278
Short name T380
Test name
Test status
Simulation time 4065539060 ps
CPU time 13.51 seconds
Started Jul 27 05:32:37 PM PDT 24
Finished Jul 27 05:32:51 PM PDT 24
Peak memory 224732 kb
Host smart-2aab93ef-14ec-4209-9869-45f74cedac65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237777278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.3237777278
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.315827430
Short name T527
Test name
Test status
Simulation time 92531531 ps
CPU time 4.15 seconds
Started Jul 27 05:32:39 PM PDT 24
Finished Jul 27 05:32:43 PM PDT 24
Peak memory 222760 kb
Host smart-85cf3457-697d-43ea-b5e4-25b1f5cdc807
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=315827430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dire
ct.315827430
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.3700582198
Short name T275
Test name
Test status
Simulation time 46486583011 ps
CPU time 477 seconds
Started Jul 27 05:32:39 PM PDT 24
Finished Jul 27 05:40:37 PM PDT 24
Peak memory 265676 kb
Host smart-a1b4233a-c88f-4cb0-9a0c-c66f33d841e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700582198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.3700582198
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.3334700823
Short name T761
Test name
Test status
Simulation time 17244870529 ps
CPU time 26.27 seconds
Started Jul 27 05:32:29 PM PDT 24
Finished Jul 27 05:32:55 PM PDT 24
Peak memory 216392 kb
Host smart-613efc7f-1672-432f-8e37-f59a913ab5a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334700823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.3334700823
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.14834470
Short name T991
Test name
Test status
Simulation time 2690137237 ps
CPU time 4.3 seconds
Started Jul 27 05:32:28 PM PDT 24
Finished Jul 27 05:32:32 PM PDT 24
Peak memory 216400 kb
Host smart-f3fc10a7-32a9-4d3d-a1f6-8acbc252fe52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14834470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.14834470
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.1047983497
Short name T10
Test name
Test status
Simulation time 25157538 ps
CPU time 0.75 seconds
Started Jul 27 05:32:29 PM PDT 24
Finished Jul 27 05:32:29 PM PDT 24
Peak memory 206012 kb
Host smart-e484b733-e016-49b5-aa35-1c97f6ded6b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047983497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.1047983497
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.3493882081
Short name T356
Test name
Test status
Simulation time 61436981 ps
CPU time 0.76 seconds
Started Jul 27 05:32:28 PM PDT 24
Finished Jul 27 05:32:29 PM PDT 24
Peak memory 206024 kb
Host smart-c7c41f7c-a5a2-4f0a-936d-a712ffbac0f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493882081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.3493882081
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.798872782
Short name T235
Test name
Test status
Simulation time 7662695620 ps
CPU time 26 seconds
Started Jul 27 05:32:39 PM PDT 24
Finished Jul 27 05:33:05 PM PDT 24
Peak memory 249028 kb
Host smart-4ba8503e-5d28-4de4-b37f-5f2872704881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798872782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.798872782
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.2125009720
Short name T691
Test name
Test status
Simulation time 14794400 ps
CPU time 0.74 seconds
Started Jul 27 05:32:36 PM PDT 24
Finished Jul 27 05:32:37 PM PDT 24
Peak memory 204972 kb
Host smart-e85cd545-55d7-4bd8-bdc6-557ea334b2d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125009720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
2125009720
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.1634241160
Short name T254
Test name
Test status
Simulation time 218591223 ps
CPU time 4.37 seconds
Started Jul 27 05:32:41 PM PDT 24
Finished Jul 27 05:32:45 PM PDT 24
Peak memory 232812 kb
Host smart-9988db7c-0f7a-4d70-9abd-5c5954fa847d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634241160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.1634241160
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.1765757159
Short name T900
Test name
Test status
Simulation time 67933480 ps
CPU time 0.77 seconds
Started Jul 27 05:32:38 PM PDT 24
Finished Jul 27 05:32:39 PM PDT 24
Peak memory 206636 kb
Host smart-6bc44945-c983-4a0a-b8e6-dd60227d83d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765757159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.1765757159
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.3766045065
Short name T999
Test name
Test status
Simulation time 16501950162 ps
CPU time 62.75 seconds
Started Jul 27 05:32:38 PM PDT 24
Finished Jul 27 05:33:41 PM PDT 24
Peak memory 235288 kb
Host smart-ffb2adaf-e09e-4bad-a428-41e0eb9d871e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766045065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.3766045065
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.2049964916
Short name T185
Test name
Test status
Simulation time 25770029208 ps
CPU time 242.3 seconds
Started Jul 27 05:32:37 PM PDT 24
Finished Jul 27 05:36:39 PM PDT 24
Peak memory 255944 kb
Host smart-030cc215-e2a2-4c1f-a227-5e5ec2f38e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049964916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.2049964916
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.1990689668
Short name T901
Test name
Test status
Simulation time 52072324502 ps
CPU time 69.88 seconds
Started Jul 27 05:32:38 PM PDT 24
Finished Jul 27 05:33:48 PM PDT 24
Peak memory 223888 kb
Host smart-2fc1fe3d-ba6a-42ae-be70-20f3649079a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990689668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.1990689668
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.3513719458
Short name T279
Test name
Test status
Simulation time 2854976253 ps
CPU time 13.13 seconds
Started Jul 27 05:32:36 PM PDT 24
Finished Jul 27 05:32:49 PM PDT 24
Peak memory 249312 kb
Host smart-731478c4-f697-4091-bc45-25a0206167ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513719458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.3513719458
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.3958771916
Short name T894
Test name
Test status
Simulation time 725837911 ps
CPU time 15.87 seconds
Started Jul 27 05:32:38 PM PDT 24
Finished Jul 27 05:32:54 PM PDT 24
Peak memory 240976 kb
Host smart-c705a28a-e2c1-4e2a-8cfd-6cae7d34ebb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958771916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmd
s.3958771916
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_intercept.1797937664
Short name T790
Test name
Test status
Simulation time 100090655 ps
CPU time 2.34 seconds
Started Jul 27 05:32:39 PM PDT 24
Finished Jul 27 05:32:42 PM PDT 24
Peak memory 232488 kb
Host smart-bc630f9a-482f-41a4-9eb7-ed5987c46ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797937664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.1797937664
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.2138543305
Short name T802
Test name
Test status
Simulation time 26551343094 ps
CPU time 68.31 seconds
Started Jul 27 05:32:37 PM PDT 24
Finished Jul 27 05:33:46 PM PDT 24
Peak memory 232936 kb
Host smart-41b6a1c6-a65a-4fbe-bd68-b4b54a6a7e4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138543305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.2138543305
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.192939118
Short name T655
Test name
Test status
Simulation time 12571346733 ps
CPU time 10.64 seconds
Started Jul 27 05:32:37 PM PDT 24
Finished Jul 27 05:32:47 PM PDT 24
Peak memory 234212 kb
Host smart-acdb4fa8-0bf4-4544-8c63-15a9be45c302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192939118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swap
.192939118
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.1905134896
Short name T577
Test name
Test status
Simulation time 355075368 ps
CPU time 3.23 seconds
Started Jul 27 05:32:36 PM PDT 24
Finished Jul 27 05:32:39 PM PDT 24
Peak memory 232752 kb
Host smart-8a7d4348-fbbf-4d34-aa4c-82866880d2fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905134896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.1905134896
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.3111976116
Short name T367
Test name
Test status
Simulation time 382730025 ps
CPU time 4.35 seconds
Started Jul 27 05:32:40 PM PDT 24
Finished Jul 27 05:32:44 PM PDT 24
Peak memory 220532 kb
Host smart-c0bdd2bc-6388-4ea3-ae91-b6a44be0f4b7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3111976116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.3111976116
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.1350230004
Short name T291
Test name
Test status
Simulation time 192168658945 ps
CPU time 385.23 seconds
Started Jul 27 05:32:38 PM PDT 24
Finished Jul 27 05:39:03 PM PDT 24
Peak memory 265720 kb
Host smart-b6f660d0-8bc1-452a-8a6c-45b05fe7233c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350230004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.1350230004
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.1006571323
Short name T285
Test name
Test status
Simulation time 732606397 ps
CPU time 3.78 seconds
Started Jul 27 05:32:38 PM PDT 24
Finished Jul 27 05:32:42 PM PDT 24
Peak memory 216592 kb
Host smart-9aa2d177-b211-4c93-a9b3-44823bdb3a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006571323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.1006571323
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.3566061727
Short name T463
Test name
Test status
Simulation time 6121310036 ps
CPU time 5.24 seconds
Started Jul 27 05:32:35 PM PDT 24
Finished Jul 27 05:32:41 PM PDT 24
Peak memory 216412 kb
Host smart-ac60e2aa-725e-4141-9a80-f9f0b0772a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566061727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.3566061727
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.1155298989
Short name T682
Test name
Test status
Simulation time 24335743 ps
CPU time 0.85 seconds
Started Jul 27 05:32:37 PM PDT 24
Finished Jul 27 05:32:38 PM PDT 24
Peak memory 206676 kb
Host smart-c538670c-ff9a-4f9d-a876-c8c31d61fe99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155298989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.1155298989
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.2706601368
Short name T632
Test name
Test status
Simulation time 12481642 ps
CPU time 0.74 seconds
Started Jul 27 05:32:39 PM PDT 24
Finished Jul 27 05:32:39 PM PDT 24
Peak memory 206048 kb
Host smart-8444615f-4c51-4a79-912c-879fe0fa553c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706601368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.2706601368
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.3646387806
Short name T678
Test name
Test status
Simulation time 6144471130 ps
CPU time 23.48 seconds
Started Jul 27 05:32:38 PM PDT 24
Finished Jul 27 05:33:01 PM PDT 24
Peak memory 241136 kb
Host smart-886255bf-37df-4693-8a33-e6f1a47e6561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646387806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.3646387806
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.3233386910
Short name T910
Test name
Test status
Simulation time 33623968 ps
CPU time 0.69 seconds
Started Jul 27 05:32:47 PM PDT 24
Finished Jul 27 05:32:48 PM PDT 24
Peak memory 204984 kb
Host smart-bcf20f90-fd39-4af7-ba7c-34fd0f9b01fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233386910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
3233386910
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.3533355185
Short name T606
Test name
Test status
Simulation time 296422201 ps
CPU time 6.9 seconds
Started Jul 27 05:32:48 PM PDT 24
Finished Jul 27 05:32:55 PM PDT 24
Peak memory 224580 kb
Host smart-2cc2537f-14f3-430a-a98f-1abc09c2e74d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533355185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.3533355185
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.2060534437
Short name T421
Test name
Test status
Simulation time 18207154 ps
CPU time 0.8 seconds
Started Jul 27 05:32:37 PM PDT 24
Finished Jul 27 05:32:38 PM PDT 24
Peak memory 206676 kb
Host smart-a86ea8c5-01fa-48f6-ac3f-cb69642229e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060534437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.2060534437
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.1214515317
Short name T902
Test name
Test status
Simulation time 7717708029 ps
CPU time 32.61 seconds
Started Jul 27 05:32:46 PM PDT 24
Finished Jul 27 05:33:18 PM PDT 24
Peak memory 249548 kb
Host smart-95835bce-0bb2-4d91-8257-24eeb0647780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214515317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.1214515317
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.2163931391
Short name T287
Test name
Test status
Simulation time 72295684498 ps
CPU time 138.32 seconds
Started Jul 27 05:32:46 PM PDT 24
Finished Jul 27 05:35:05 PM PDT 24
Peak memory 251588 kb
Host smart-dbe47f0c-0e7c-4486-b144-7ef9bccd85d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163931391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.2163931391
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.4040529630
Short name T153
Test name
Test status
Simulation time 5827599194 ps
CPU time 19.4 seconds
Started Jul 27 05:32:47 PM PDT 24
Finished Jul 27 05:33:07 PM PDT 24
Peak memory 241080 kb
Host smart-7d1e6abd-1581-4f07-bbde-808f86dd50a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040529630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.4040529630
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.3546615033
Short name T844
Test name
Test status
Simulation time 1617356044 ps
CPU time 34.04 seconds
Started Jul 27 05:32:45 PM PDT 24
Finished Jul 27 05:33:20 PM PDT 24
Peak memory 251504 kb
Host smart-2cb0dfc2-6429-4344-908e-21f595b955e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546615033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmd
s.3546615033
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_intercept.2878208741
Short name T253
Test name
Test status
Simulation time 1638289105 ps
CPU time 6.2 seconds
Started Jul 27 05:32:47 PM PDT 24
Finished Jul 27 05:32:53 PM PDT 24
Peak memory 232864 kb
Host smart-07a9d78a-1a8a-446a-80b1-e3f3623c4dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878208741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.2878208741
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.975858932
Short name T510
Test name
Test status
Simulation time 6471524427 ps
CPU time 69.12 seconds
Started Jul 27 05:32:47 PM PDT 24
Finished Jul 27 05:33:56 PM PDT 24
Peak memory 227992 kb
Host smart-ae6d009d-b2b7-4d01-a286-34733d67a402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975858932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.975858932
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.1409730079
Short name T865
Test name
Test status
Simulation time 260264756 ps
CPU time 5.47 seconds
Started Jul 27 05:32:38 PM PDT 24
Finished Jul 27 05:32:44 PM PDT 24
Peak memory 224528 kb
Host smart-872a092c-8864-43ab-967e-ca083de23073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409730079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.1409730079
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.2831311203
Short name T921
Test name
Test status
Simulation time 2492733578 ps
CPU time 6.02 seconds
Started Jul 27 05:32:37 PM PDT 24
Finished Jul 27 05:32:43 PM PDT 24
Peak memory 232868 kb
Host smart-8b7ce414-5f93-49a3-bed0-96f9dcc943b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831311203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.2831311203
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.764698847
Short name T357
Test name
Test status
Simulation time 151686806 ps
CPU time 3.77 seconds
Started Jul 27 05:32:50 PM PDT 24
Finished Jul 27 05:32:53 PM PDT 24
Peak memory 223200 kb
Host smart-ab38eaf3-0985-4cf6-aec0-27baf102dde8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=764698847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dire
ct.764698847
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.479831901
Short name T259
Test name
Test status
Simulation time 17421192707 ps
CPU time 127.28 seconds
Started Jul 27 05:32:48 PM PDT 24
Finished Jul 27 05:34:55 PM PDT 24
Peak memory 266584 kb
Host smart-07935dde-1873-4716-bad4-3b3429a6227d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479831901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stres
s_all.479831901
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.885114254
Short name T770
Test name
Test status
Simulation time 662435228 ps
CPU time 6.25 seconds
Started Jul 27 05:32:37 PM PDT 24
Finished Jul 27 05:32:44 PM PDT 24
Peak memory 216592 kb
Host smart-c7305567-c0ee-44d5-8809-76ba62bd4659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885114254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.885114254
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.2630591124
Short name T888
Test name
Test status
Simulation time 588840778 ps
CPU time 2.36 seconds
Started Jul 27 05:32:36 PM PDT 24
Finished Jul 27 05:32:38 PM PDT 24
Peak memory 216248 kb
Host smart-7ff80849-bba5-4f17-9513-9ceedbe13d26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630591124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.2630591124
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.3994837007
Short name T760
Test name
Test status
Simulation time 86258301 ps
CPU time 1.21 seconds
Started Jul 27 05:32:38 PM PDT 24
Finished Jul 27 05:32:39 PM PDT 24
Peak memory 207556 kb
Host smart-9454d2fe-9faf-4bf3-84dc-5cc85ef1c56c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994837007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.3994837007
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.584090255
Short name T6
Test name
Test status
Simulation time 115027613 ps
CPU time 0.81 seconds
Started Jul 27 05:32:36 PM PDT 24
Finished Jul 27 05:32:37 PM PDT 24
Peak memory 206076 kb
Host smart-2d88dc38-4e46-4cf4-9f5f-bdb5dc7ec416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584090255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.584090255
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.926714913
Short name T676
Test name
Test status
Simulation time 1019220714 ps
CPU time 4.44 seconds
Started Jul 27 05:32:47 PM PDT 24
Finished Jul 27 05:32:51 PM PDT 24
Peak memory 224580 kb
Host smart-78a8f72f-6ff7-4616-8c6b-e6e5a8cf5940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926714913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.926714913
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.1332491832
Short name T64
Test name
Test status
Simulation time 50204320 ps
CPU time 0.73 seconds
Started Jul 27 05:32:48 PM PDT 24
Finished Jul 27 05:32:49 PM PDT 24
Peak memory 205520 kb
Host smart-f41cc5c7-89b6-4528-b02b-e0399f9e1638
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332491832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
1332491832
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.3438036959
Short name T391
Test name
Test status
Simulation time 1100908366 ps
CPU time 8.52 seconds
Started Jul 27 05:32:47 PM PDT 24
Finished Jul 27 05:32:56 PM PDT 24
Peak memory 232716 kb
Host smart-edd38c5f-c820-43d5-8adf-cb2a09f6c62e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438036959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.3438036959
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.2801212338
Short name T3
Test name
Test status
Simulation time 15815317 ps
CPU time 0.79 seconds
Started Jul 27 05:32:50 PM PDT 24
Finished Jul 27 05:32:51 PM PDT 24
Peak memory 206916 kb
Host smart-62da6c04-fceb-408e-818d-0b7ee6c4a484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801212338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.2801212338
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.834207088
Short name T262
Test name
Test status
Simulation time 26898970788 ps
CPU time 93.07 seconds
Started Jul 27 05:32:46 PM PDT 24
Finished Jul 27 05:34:19 PM PDT 24
Peak memory 254156 kb
Host smart-d9e7eec0-8bce-4402-ba08-67a82ae04ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834207088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.834207088
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.3893688179
Short name T194
Test name
Test status
Simulation time 44917608048 ps
CPU time 95.42 seconds
Started Jul 27 05:32:51 PM PDT 24
Finished Jul 27 05:34:27 PM PDT 24
Peak memory 256136 kb
Host smart-49183c17-fbba-4463-8508-5eca880af883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893688179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.3893688179
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.3814215326
Short name T562
Test name
Test status
Simulation time 11152713716 ps
CPU time 25.17 seconds
Started Jul 27 05:32:46 PM PDT 24
Finished Jul 27 05:33:11 PM PDT 24
Peak memory 224708 kb
Host smart-940ab71b-53ea-4f27-b58a-7fb4789b9b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814215326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.3814215326
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.2101851102
Short name T642
Test name
Test status
Simulation time 1447307731 ps
CPU time 25.39 seconds
Started Jul 27 05:32:45 PM PDT 24
Finished Jul 27 05:33:10 PM PDT 24
Peak memory 224672 kb
Host smart-8881ee52-6298-4d3c-9247-6ca90d081b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101851102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.2101851102
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.2975757036
Short name T256
Test name
Test status
Simulation time 48191617352 ps
CPU time 204.6 seconds
Started Jul 27 05:32:47 PM PDT 24
Finished Jul 27 05:36:11 PM PDT 24
Peak memory 265588 kb
Host smart-1925e06d-4bcf-467c-b2dc-8ce865d435dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975757036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmd
s.2975757036
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/24.spi_device_intercept.1149940064
Short name T863
Test name
Test status
Simulation time 1450692569 ps
CPU time 7.62 seconds
Started Jul 27 05:32:48 PM PDT 24
Finished Jul 27 05:32:56 PM PDT 24
Peak memory 232844 kb
Host smart-1e1cf41e-e97a-421f-bf3c-cc54e88f71a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149940064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.1149940064
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.3368406042
Short name T920
Test name
Test status
Simulation time 3931272668 ps
CPU time 43.13 seconds
Started Jul 27 05:32:48 PM PDT 24
Finished Jul 27 05:33:32 PM PDT 24
Peak memory 240804 kb
Host smart-789de665-60bb-46d9-8fac-076113046bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368406042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.3368406042
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.1651706524
Short name T100
Test name
Test status
Simulation time 1688909828 ps
CPU time 10.88 seconds
Started Jul 27 05:32:47 PM PDT 24
Finished Jul 27 05:32:58 PM PDT 24
Peak memory 249196 kb
Host smart-6989fc06-d883-4d3f-8999-761a825c7271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651706524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.1651706524
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.2593303695
Short name T415
Test name
Test status
Simulation time 6530615090 ps
CPU time 7.16 seconds
Started Jul 27 05:32:51 PM PDT 24
Finished Jul 27 05:32:58 PM PDT 24
Peak memory 232820 kb
Host smart-a387bff1-897e-4261-b0fa-3b235f20e4a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593303695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.2593303695
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.2591382487
Short name T697
Test name
Test status
Simulation time 5577014399 ps
CPU time 5.84 seconds
Started Jul 27 05:32:47 PM PDT 24
Finished Jul 27 05:32:53 PM PDT 24
Peak memory 219020 kb
Host smart-e25fec43-7814-461f-9dad-5088cad9fd2e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2591382487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.2591382487
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.3175143382
Short name T891
Test name
Test status
Simulation time 3582883314 ps
CPU time 51.87 seconds
Started Jul 27 05:32:46 PM PDT 24
Finished Jul 27 05:33:38 PM PDT 24
Peak memory 248708 kb
Host smart-b1e8e309-979e-4ce8-af24-d1f1ab37778a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175143382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.3175143382
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.2160953636
Short name T290
Test name
Test status
Simulation time 6459427654 ps
CPU time 10.62 seconds
Started Jul 27 05:32:47 PM PDT 24
Finished Jul 27 05:32:58 PM PDT 24
Peak memory 220524 kb
Host smart-775fb34e-432e-4d43-9331-ede157fc59b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160953636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.2160953636
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.3784424130
Short name T955
Test name
Test status
Simulation time 2018152880 ps
CPU time 7.01 seconds
Started Jul 27 05:32:50 PM PDT 24
Finished Jul 27 05:32:57 PM PDT 24
Peak memory 216356 kb
Host smart-2a229c89-552a-4dd4-96c9-2b53a353d4d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784424130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.3784424130
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.1935085873
Short name T947
Test name
Test status
Simulation time 57310978 ps
CPU time 1.58 seconds
Started Jul 27 05:32:48 PM PDT 24
Finished Jul 27 05:32:50 PM PDT 24
Peak memory 216412 kb
Host smart-addc4e62-9669-4202-82e0-548bd7b877f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935085873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.1935085873
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.4064083741
Short name T405
Test name
Test status
Simulation time 102104382 ps
CPU time 1 seconds
Started Jul 27 05:32:46 PM PDT 24
Finished Jul 27 05:32:47 PM PDT 24
Peak memory 206296 kb
Host smart-d7bd9bc3-0dea-462e-8654-bb3c1411c0d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064083741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.4064083741
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.2685424825
Short name T696
Test name
Test status
Simulation time 967065801 ps
CPU time 3.24 seconds
Started Jul 27 05:32:47 PM PDT 24
Finished Jul 27 05:32:51 PM PDT 24
Peak memory 236676 kb
Host smart-ce0c3e66-bd43-49c8-bf67-5fa744c7aa5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685424825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.2685424825
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.2732947356
Short name T873
Test name
Test status
Simulation time 22423950 ps
CPU time 0.7 seconds
Started Jul 27 05:33:00 PM PDT 24
Finished Jul 27 05:33:01 PM PDT 24
Peak memory 204996 kb
Host smart-285e476f-8bd3-49d1-9ae4-77f5f7c08058
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732947356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
2732947356
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.2173524464
Short name T648
Test name
Test status
Simulation time 2002707131 ps
CPU time 5.16 seconds
Started Jul 27 05:32:47 PM PDT 24
Finished Jul 27 05:32:53 PM PDT 24
Peak memory 232740 kb
Host smart-266d8ed4-7254-4c6a-9120-62e68ba95876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173524464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.2173524464
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.2134195751
Short name T306
Test name
Test status
Simulation time 41891528 ps
CPU time 0.78 seconds
Started Jul 27 05:32:48 PM PDT 24
Finished Jul 27 05:32:49 PM PDT 24
Peak memory 206708 kb
Host smart-6a353516-82e3-4f44-9a89-a2df5069ed4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134195751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.2134195751
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.1714036414
Short name T173
Test name
Test status
Simulation time 42420689032 ps
CPU time 139.98 seconds
Started Jul 27 05:32:52 PM PDT 24
Finished Jul 27 05:35:12 PM PDT 24
Peak memory 249304 kb
Host smart-8fadd573-e31c-4f6c-9635-59cff4fc311c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714036414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.1714036414
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.1992206665
Short name T935
Test name
Test status
Simulation time 24699258112 ps
CPU time 61.41 seconds
Started Jul 27 05:32:58 PM PDT 24
Finished Jul 27 05:33:59 PM PDT 24
Peak memory 241124 kb
Host smart-a50859c0-503d-4c90-9048-bdd410261e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992206665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.1992206665
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.3330083851
Short name T904
Test name
Test status
Simulation time 36569206017 ps
CPU time 79.01 seconds
Started Jul 27 05:32:56 PM PDT 24
Finished Jul 27 05:34:16 PM PDT 24
Peak memory 240712 kb
Host smart-70b41d42-44a1-4d15-ba3e-664684a80254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330083851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.3330083851
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.1087416850
Short name T451
Test name
Test status
Simulation time 180791459 ps
CPU time 6.96 seconds
Started Jul 27 05:32:48 PM PDT 24
Finished Jul 27 05:32:56 PM PDT 24
Peak memory 232736 kb
Host smart-5675e77b-6cc3-4618-bcec-0386bb69610c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087416850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.1087416850
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.596075445
Short name T754
Test name
Test status
Simulation time 60525232866 ps
CPU time 136.23 seconds
Started Jul 27 05:32:48 PM PDT 24
Finished Jul 27 05:35:05 PM PDT 24
Peak memory 255768 kb
Host smart-e9a88718-eb0e-484c-8fc8-add55d071a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596075445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmds
.596075445
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_intercept.4198343242
Short name T845
Test name
Test status
Simulation time 859152409 ps
CPU time 10.89 seconds
Started Jul 27 05:32:47 PM PDT 24
Finished Jul 27 05:32:58 PM PDT 24
Peak memory 229040 kb
Host smart-4a62ee02-88ac-4c39-a13e-6635ae2da56e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198343242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.4198343242
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.3817297318
Short name T667
Test name
Test status
Simulation time 856106231 ps
CPU time 13.31 seconds
Started Jul 27 05:32:46 PM PDT 24
Finished Jul 27 05:32:59 PM PDT 24
Peak memory 234076 kb
Host smart-b9fe4000-ba27-49e1-9444-035b24c736f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817297318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.3817297318
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.2182590558
Short name T251
Test name
Test status
Simulation time 400871285 ps
CPU time 7.42 seconds
Started Jul 27 05:32:50 PM PDT 24
Finished Jul 27 05:32:57 PM PDT 24
Peak memory 232848 kb
Host smart-207c392f-6e38-41da-b298-54c37232d525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182590558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.2182590558
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.1266343945
Short name T234
Test name
Test status
Simulation time 485190655 ps
CPU time 3.93 seconds
Started Jul 27 05:32:47 PM PDT 24
Finished Jul 27 05:32:51 PM PDT 24
Peak memory 224600 kb
Host smart-f0e2e7f8-8adc-4698-ae5f-dcd848954b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266343945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.1266343945
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.4000385791
Short name T152
Test name
Test status
Simulation time 1560202641 ps
CPU time 6.78 seconds
Started Jul 27 05:32:50 PM PDT 24
Finished Jul 27 05:32:57 PM PDT 24
Peak memory 218896 kb
Host smart-3cfe0561-d36b-49ae-a2ff-2eea4e8063f6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4000385791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.4000385791
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.2893005160
Short name T969
Test name
Test status
Simulation time 15926516773 ps
CPU time 148.97 seconds
Started Jul 27 05:32:57 PM PDT 24
Finished Jul 27 05:35:26 PM PDT 24
Peak memory 256776 kb
Host smart-09e1750b-61a5-4309-bc2e-63fd7a3baefc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893005160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.2893005160
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.1655219123
Short name T368
Test name
Test status
Simulation time 4740527741 ps
CPU time 17.52 seconds
Started Jul 27 05:32:48 PM PDT 24
Finished Jul 27 05:33:06 PM PDT 24
Peak memory 216412 kb
Host smart-c2a5a85e-68d4-4b56-89b6-4b9a8e816474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655219123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.1655219123
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.3181604764
Short name T735
Test name
Test status
Simulation time 1727995440 ps
CPU time 2.83 seconds
Started Jul 27 05:32:48 PM PDT 24
Finished Jul 27 05:32:51 PM PDT 24
Peak memory 216320 kb
Host smart-131efe04-3524-46d4-ba1a-1172e7d55925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181604764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.3181604764
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.2524712838
Short name T824
Test name
Test status
Simulation time 53528402 ps
CPU time 1.19 seconds
Started Jul 27 05:32:46 PM PDT 24
Finished Jul 27 05:32:48 PM PDT 24
Peak memory 207368 kb
Host smart-306871fc-b04e-4502-93bc-d67f932e3d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524712838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.2524712838
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.3363765438
Short name T314
Test name
Test status
Simulation time 321443030 ps
CPU time 0.79 seconds
Started Jul 27 05:32:48 PM PDT 24
Finished Jul 27 05:32:49 PM PDT 24
Peak memory 206000 kb
Host smart-853a5317-5e54-4104-aa7a-d01e4e3afaa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363765438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.3363765438
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.3208346060
Short name T412
Test name
Test status
Simulation time 181535020 ps
CPU time 4.79 seconds
Started Jul 27 05:32:47 PM PDT 24
Finished Jul 27 05:32:52 PM PDT 24
Peak memory 224584 kb
Host smart-bca61dc1-ef57-49bb-92e6-efd36e611878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208346060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.3208346060
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.3649321026
Short name T318
Test name
Test status
Simulation time 17085248 ps
CPU time 0.71 seconds
Started Jul 27 05:32:59 PM PDT 24
Finished Jul 27 05:32:59 PM PDT 24
Peak memory 205796 kb
Host smart-0fada53b-82fc-4851-9173-aafc565179f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649321026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
3649321026
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.2036625208
Short name T233
Test name
Test status
Simulation time 666365890 ps
CPU time 4.93 seconds
Started Jul 27 05:32:58 PM PDT 24
Finished Jul 27 05:33:03 PM PDT 24
Peak memory 232764 kb
Host smart-9280609b-d41a-435e-a43c-ca5969db1cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036625208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.2036625208
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.2985737472
Short name T305
Test name
Test status
Simulation time 21942021 ps
CPU time 0.75 seconds
Started Jul 27 05:32:58 PM PDT 24
Finished Jul 27 05:32:59 PM PDT 24
Peak memory 205672 kb
Host smart-dbdac444-0097-48bd-9217-dc2533925bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985737472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.2985737472
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.2174276582
Short name T449
Test name
Test status
Simulation time 13460089872 ps
CPU time 63.44 seconds
Started Jul 27 05:32:57 PM PDT 24
Finished Jul 27 05:34:01 PM PDT 24
Peak memory 241056 kb
Host smart-97e4675f-8438-40ef-9bf8-3c239cdf8718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174276582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.2174276582
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.1971636232
Short name T18
Test name
Test status
Simulation time 3288403070 ps
CPU time 52.51 seconds
Started Jul 27 05:32:58 PM PDT 24
Finished Jul 27 05:33:50 PM PDT 24
Peak memory 249372 kb
Host smart-ab131d8c-f68c-4ba3-96d0-fb168b659678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971636232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.1971636232
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.2887170542
Short name T39
Test name
Test status
Simulation time 12882610724 ps
CPU time 34.15 seconds
Started Jul 27 05:33:00 PM PDT 24
Finished Jul 27 05:33:34 PM PDT 24
Peak memory 232928 kb
Host smart-20c49da1-b32a-46d8-ae6c-b159b32e840d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887170542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.2887170542
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.921728553
Short name T212
Test name
Test status
Simulation time 30273364050 ps
CPU time 211.75 seconds
Started Jul 27 05:33:00 PM PDT 24
Finished Jul 27 05:36:32 PM PDT 24
Peak memory 255828 kb
Host smart-a5b92769-f861-4038-b975-5f22954ca676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921728553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmds
.921728553
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_intercept.56116971
Short name T637
Test name
Test status
Simulation time 7158442237 ps
CPU time 23.93 seconds
Started Jul 27 05:32:57 PM PDT 24
Finished Jul 27 05:33:21 PM PDT 24
Peak memory 224948 kb
Host smart-1aa734e5-6f2f-44f7-b000-985c831b0113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56116971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.56116971
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.4101558890
Short name T20
Test name
Test status
Simulation time 634360459 ps
CPU time 6.88 seconds
Started Jul 27 05:32:59 PM PDT 24
Finished Jul 27 05:33:06 PM PDT 24
Peak memory 232732 kb
Host smart-9a9a5fe6-80f8-4e25-9cbd-31f77122a928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101558890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.4101558890
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.2385303848
Short name T673
Test name
Test status
Simulation time 114234157 ps
CPU time 2.38 seconds
Started Jul 27 05:32:58 PM PDT 24
Finished Jul 27 05:33:00 PM PDT 24
Peak memory 232544 kb
Host smart-3aa90861-03fb-41eb-b0d8-10b518e27fe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385303848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.2385303848
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.2312596406
Short name T833
Test name
Test status
Simulation time 2026790648 ps
CPU time 11.04 seconds
Started Jul 27 05:33:02 PM PDT 24
Finished Jul 27 05:33:13 PM PDT 24
Peak memory 232664 kb
Host smart-fe387cae-746d-4bd6-9666-696b40d0cc3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312596406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.2312596406
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.3255062888
Short name T452
Test name
Test status
Simulation time 2449295328 ps
CPU time 12.3 seconds
Started Jul 27 05:32:59 PM PDT 24
Finished Jul 27 05:33:12 PM PDT 24
Peak memory 220484 kb
Host smart-b41448bb-13ef-4516-810c-ff27846f8d72
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3255062888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.3255062888
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.2930923290
Short name T593
Test name
Test status
Simulation time 29466210128 ps
CPU time 34.01 seconds
Started Jul 27 05:32:56 PM PDT 24
Finished Jul 27 05:33:31 PM PDT 24
Peak memory 216392 kb
Host smart-15afb16c-25c6-45af-9a35-8d09b58dd1a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930923290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.2930923290
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.482503574
Short name T93
Test name
Test status
Simulation time 4290509955 ps
CPU time 6.03 seconds
Started Jul 27 05:32:58 PM PDT 24
Finished Jul 27 05:33:04 PM PDT 24
Peak memory 216340 kb
Host smart-e92119c8-5025-457e-9c75-d106526acb53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482503574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.482503574
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.1467548266
Short name T903
Test name
Test status
Simulation time 119716629 ps
CPU time 2.15 seconds
Started Jul 27 05:32:58 PM PDT 24
Finished Jul 27 05:33:00 PM PDT 24
Peak memory 216360 kb
Host smart-f7b085df-c327-4575-8ddd-95bf0913594f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467548266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.1467548266
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.2328587795
Short name T818
Test name
Test status
Simulation time 73786838 ps
CPU time 0.77 seconds
Started Jul 27 05:33:01 PM PDT 24
Finished Jul 27 05:33:01 PM PDT 24
Peak memory 205968 kb
Host smart-ffff7b9a-7438-4217-aa8a-b3689ee94cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328587795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.2328587795
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.1316837995
Short name T15
Test name
Test status
Simulation time 870244272 ps
CPU time 12.43 seconds
Started Jul 27 05:33:00 PM PDT 24
Finished Jul 27 05:33:13 PM PDT 24
Peak memory 252296 kb
Host smart-06bf0ce7-c3e7-4493-8b71-c42f65b1250c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316837995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.1316837995
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.1242132453
Short name T309
Test name
Test status
Simulation time 43912142 ps
CPU time 0.71 seconds
Started Jul 27 05:32:59 PM PDT 24
Finished Jul 27 05:33:00 PM PDT 24
Peak memory 205516 kb
Host smart-3da024ae-74ae-4695-a865-4f6a4f654178
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242132453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
1242132453
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.2377408681
Short name T94
Test name
Test status
Simulation time 1562901885 ps
CPU time 14.05 seconds
Started Jul 27 05:32:58 PM PDT 24
Finished Jul 27 05:33:12 PM PDT 24
Peak memory 232860 kb
Host smart-ea3ec400-0824-4e05-b6ac-121b1983a4a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377408681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.2377408681
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.968748400
Short name T300
Test name
Test status
Simulation time 47507877 ps
CPU time 0.75 seconds
Started Jul 27 05:32:59 PM PDT 24
Finished Jul 27 05:33:00 PM PDT 24
Peak memory 205700 kb
Host smart-2324753a-c500-4eac-bc07-071beb502694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968748400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.968748400
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.2944787006
Short name T330
Test name
Test status
Simulation time 21787153 ps
CPU time 0.78 seconds
Started Jul 27 05:32:57 PM PDT 24
Finished Jul 27 05:32:58 PM PDT 24
Peak memory 215880 kb
Host smart-9da811e6-1364-4484-a844-ef219f8e6c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944787006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.2944787006
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.1608972486
Short name T933
Test name
Test status
Simulation time 9637101047 ps
CPU time 45.18 seconds
Started Jul 27 05:33:02 PM PDT 24
Finished Jul 27 05:33:47 PM PDT 24
Peak memory 235248 kb
Host smart-5551476a-73df-4cf8-b116-248a98fc289d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608972486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.1608972486
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.5473916
Short name T571
Test name
Test status
Simulation time 52174379704 ps
CPU time 389.86 seconds
Started Jul 27 05:32:58 PM PDT 24
Finished Jul 27 05:39:28 PM PDT 24
Peak memory 249288 kb
Host smart-00cf929e-de24-402d-8a21-593b1e5ea2a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5473916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idle.5473916
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.3289923171
Short name T448
Test name
Test status
Simulation time 12727708 ps
CPU time 0.75 seconds
Started Jul 27 05:32:59 PM PDT 24
Finished Jul 27 05:33:00 PM PDT 24
Peak memory 215860 kb
Host smart-0e56b2be-8ffb-4e2a-bd9f-b1f773e6e207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289923171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmd
s.3289923171
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_intercept.4259440576
Short name T302
Test name
Test status
Simulation time 52606987 ps
CPU time 2.11 seconds
Started Jul 27 05:32:58 PM PDT 24
Finished Jul 27 05:33:00 PM PDT 24
Peak memory 223976 kb
Host smart-45d17491-544c-4275-b11d-b9b54f05a220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259440576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.4259440576
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.520821192
Short name T803
Test name
Test status
Simulation time 36896386 ps
CPU time 2.39 seconds
Started Jul 27 05:32:58 PM PDT 24
Finished Jul 27 05:33:01 PM PDT 24
Peak memory 232688 kb
Host smart-097b0403-27e6-4cec-b27e-509495f0fe58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520821192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.520821192
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.4247321419
Short name T634
Test name
Test status
Simulation time 94007263 ps
CPU time 2.94 seconds
Started Jul 27 05:33:00 PM PDT 24
Finished Jul 27 05:33:03 PM PDT 24
Peak memory 232768 kb
Host smart-ae4cb954-40d9-403b-8e99-98675e029372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247321419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.4247321419
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.2574531988
Short name T837
Test name
Test status
Simulation time 984473867 ps
CPU time 8.14 seconds
Started Jul 27 05:32:58 PM PDT 24
Finished Jul 27 05:33:06 PM PDT 24
Peak memory 249192 kb
Host smart-76de4b3d-a01c-4688-bc9a-0cfcf1774d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574531988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.2574531988
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.2250611950
Short name T495
Test name
Test status
Simulation time 769082350 ps
CPU time 4.58 seconds
Started Jul 27 05:32:59 PM PDT 24
Finished Jul 27 05:33:04 PM PDT 24
Peak memory 223740 kb
Host smart-9ee7f9ef-7bc6-4a7f-869e-6306207529b4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2250611950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.2250611950
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.4210510518
Short name T163
Test name
Test status
Simulation time 33579833498 ps
CPU time 350.75 seconds
Started Jul 27 05:33:00 PM PDT 24
Finished Jul 27 05:38:51 PM PDT 24
Peak memory 269576 kb
Host smart-82b151be-a427-435e-af80-ebe55c0b51f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210510518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.4210510518
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.620381452
Short name T737
Test name
Test status
Simulation time 481270161 ps
CPU time 2.64 seconds
Started Jul 27 05:32:56 PM PDT 24
Finished Jul 27 05:32:59 PM PDT 24
Peak memory 216588 kb
Host smart-09dd649a-a218-403e-8135-94a08df509aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620381452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.620381452
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.2303963884
Short name T951
Test name
Test status
Simulation time 8896706147 ps
CPU time 10.33 seconds
Started Jul 27 05:32:58 PM PDT 24
Finished Jul 27 05:33:08 PM PDT 24
Peak memory 216472 kb
Host smart-159b1ecd-b7f8-4eb7-9b86-01abf0f4994f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303963884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.2303963884
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.2155525749
Short name T490
Test name
Test status
Simulation time 251145805 ps
CPU time 1.5 seconds
Started Jul 27 05:32:57 PM PDT 24
Finished Jul 27 05:32:59 PM PDT 24
Peak memory 208208 kb
Host smart-708625c0-64b8-432d-bfbe-ef6362e96e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155525749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.2155525749
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.2617418469
Short name T469
Test name
Test status
Simulation time 72933876 ps
CPU time 0.9 seconds
Started Jul 27 05:32:59 PM PDT 24
Finished Jul 27 05:33:00 PM PDT 24
Peak memory 206052 kb
Host smart-d66d904f-266f-4715-8470-cbef4c9a4e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617418469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.2617418469
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.993888124
Short name T631
Test name
Test status
Simulation time 875845290 ps
CPU time 7.38 seconds
Started Jul 27 05:32:58 PM PDT 24
Finished Jul 27 05:33:06 PM PDT 24
Peak memory 232800 kb
Host smart-48f73ad0-a526-41e1-8a40-5caca5d69da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993888124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.993888124
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.1791689490
Short name T880
Test name
Test status
Simulation time 208136115 ps
CPU time 0.74 seconds
Started Jul 27 05:33:11 PM PDT 24
Finished Jul 27 05:33:11 PM PDT 24
Peak memory 205524 kb
Host smart-88314d31-da45-46af-a778-8dd70c0b69e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791689490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
1791689490
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.1647666992
Short name T730
Test name
Test status
Simulation time 288672705 ps
CPU time 2.93 seconds
Started Jul 27 05:33:12 PM PDT 24
Finished Jul 27 05:33:15 PM PDT 24
Peak memory 232796 kb
Host smart-67bae203-1e00-4326-aee9-d397f28c372a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647666992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.1647666992
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.3304290628
Short name T570
Test name
Test status
Simulation time 49111161 ps
CPU time 0.79 seconds
Started Jul 27 05:33:01 PM PDT 24
Finished Jul 27 05:33:01 PM PDT 24
Peak memory 206592 kb
Host smart-b2fe8334-a287-4189-abfa-eaa3b508e1ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304290628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.3304290628
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.4014491466
Short name T756
Test name
Test status
Simulation time 7795051653 ps
CPU time 33.2 seconds
Started Jul 27 05:33:13 PM PDT 24
Finished Jul 27 05:33:46 PM PDT 24
Peak memory 249316 kb
Host smart-72d0ed5c-ed47-4f56-a6fe-cb11b6844ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014491466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.4014491466
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.3958808743
Short name T962
Test name
Test status
Simulation time 121650817329 ps
CPU time 195.37 seconds
Started Jul 27 05:33:10 PM PDT 24
Finished Jul 27 05:36:25 PM PDT 24
Peak memory 250516 kb
Host smart-735ebbfa-1481-424d-9403-6c67c4de46e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958808743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.3958808743
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.1095557897
Short name T272
Test name
Test status
Simulation time 139982713678 ps
CPU time 262.26 seconds
Started Jul 27 05:33:14 PM PDT 24
Finished Jul 27 05:37:36 PM PDT 24
Peak memory 249576 kb
Host smart-b1935d67-3b4a-4959-94f7-797054c3d0b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095557897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.1095557897
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.2032153366
Short name T278
Test name
Test status
Simulation time 432115202 ps
CPU time 14.24 seconds
Started Jul 27 05:33:08 PM PDT 24
Finished Jul 27 05:33:22 PM PDT 24
Peak memory 240016 kb
Host smart-5b1cb41d-350b-4d88-8ded-24ecd51058c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032153366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.2032153366
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.3780111520
Short name T576
Test name
Test status
Simulation time 25137179 ps
CPU time 0.74 seconds
Started Jul 27 05:33:16 PM PDT 24
Finished Jul 27 05:33:17 PM PDT 24
Peak memory 215844 kb
Host smart-6196d78e-9b92-46ee-883c-abade39b40ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780111520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmd
s.3780111520
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.8419104
Short name T62
Test name
Test status
Simulation time 480213022 ps
CPU time 4.41 seconds
Started Jul 27 05:33:12 PM PDT 24
Finished Jul 27 05:33:16 PM PDT 24
Peak memory 232764 kb
Host smart-e94fae4d-b6f8-4403-800e-219369655f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8419104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.8419104
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.3105952358
Short name T917
Test name
Test status
Simulation time 1007843832 ps
CPU time 8.19 seconds
Started Jul 27 05:33:16 PM PDT 24
Finished Jul 27 05:33:24 PM PDT 24
Peak memory 219152 kb
Host smart-2dd42b03-0bb3-4ee6-9e6d-ef2bd0e19c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105952358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.3105952358
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.3239372269
Short name T772
Test name
Test status
Simulation time 5963901930 ps
CPU time 10.48 seconds
Started Jul 27 05:33:08 PM PDT 24
Finished Jul 27 05:33:18 PM PDT 24
Peak memory 232856 kb
Host smart-eac0646b-9ed4-48e0-874a-68cba3db190e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239372269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.3239372269
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.584387866
Short name T752
Test name
Test status
Simulation time 1798635205 ps
CPU time 6.78 seconds
Started Jul 27 05:33:13 PM PDT 24
Finished Jul 27 05:33:20 PM PDT 24
Peak memory 232908 kb
Host smart-fdec00bc-3568-466f-90be-5814974e7507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584387866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.584387866
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.3596527879
Short name T424
Test name
Test status
Simulation time 378627112 ps
CPU time 5.29 seconds
Started Jul 27 05:33:19 PM PDT 24
Finished Jul 27 05:33:24 PM PDT 24
Peak memory 223004 kb
Host smart-684570ff-ae14-4a27-a136-2e21cc579bc7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3596527879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.3596527879
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.2860666506
Short name T487
Test name
Test status
Simulation time 333367878 ps
CPU time 1.16 seconds
Started Jul 27 05:33:09 PM PDT 24
Finished Jul 27 05:33:10 PM PDT 24
Peak memory 207256 kb
Host smart-4c5849a6-64a0-4dc5-921e-56503d5068d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860666506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.2860666506
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.3442376581
Short name T401
Test name
Test status
Simulation time 7113837956 ps
CPU time 22.55 seconds
Started Jul 27 05:33:18 PM PDT 24
Finished Jul 27 05:33:40 PM PDT 24
Peak memory 216340 kb
Host smart-c2b336f3-5341-41ac-a901-5d3315d14085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442376581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.3442376581
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.1554612076
Short name T465
Test name
Test status
Simulation time 1175600734 ps
CPU time 7.82 seconds
Started Jul 27 05:33:12 PM PDT 24
Finished Jul 27 05:33:20 PM PDT 24
Peak memory 216260 kb
Host smart-2cca5693-b509-4087-9180-8b23a3d8e8b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554612076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.1554612076
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.664486271
Short name T457
Test name
Test status
Simulation time 704057401 ps
CPU time 3.36 seconds
Started Jul 27 05:33:09 PM PDT 24
Finished Jul 27 05:33:12 PM PDT 24
Peak memory 216412 kb
Host smart-c3cdb456-d54a-419b-9cc6-6d5df7b60ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664486271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.664486271
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.1267523702
Short name T966
Test name
Test status
Simulation time 395859035 ps
CPU time 1 seconds
Started Jul 27 05:33:08 PM PDT 24
Finished Jul 27 05:33:09 PM PDT 24
Peak memory 207112 kb
Host smart-3c39e02b-1b8e-4954-8e10-1254fff4d090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267523702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.1267523702
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.2633160773
Short name T342
Test name
Test status
Simulation time 6701003466 ps
CPU time 14.59 seconds
Started Jul 27 05:33:13 PM PDT 24
Finished Jul 27 05:33:28 PM PDT 24
Peak memory 249224 kb
Host smart-2ec7f2e9-8c77-425d-9140-60e3bf77cf5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633160773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.2633160773
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.2092327057
Short name T950
Test name
Test status
Simulation time 15425874 ps
CPU time 0.71 seconds
Started Jul 27 05:33:16 PM PDT 24
Finished Jul 27 05:33:17 PM PDT 24
Peak memory 204908 kb
Host smart-a9c71ccb-da1c-4689-a5e9-1531d9993dfe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092327057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
2092327057
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.327799046
Short name T331
Test name
Test status
Simulation time 926898918 ps
CPU time 4.68 seconds
Started Jul 27 05:33:13 PM PDT 24
Finished Jul 27 05:33:18 PM PDT 24
Peak memory 224524 kb
Host smart-bca06ca1-f06f-4d16-b5cf-d94f8504ea65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327799046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.327799046
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.3648971045
Short name T804
Test name
Test status
Simulation time 37086758 ps
CPU time 0.78 seconds
Started Jul 27 05:33:09 PM PDT 24
Finished Jul 27 05:33:10 PM PDT 24
Peak memory 206996 kb
Host smart-3c8a540f-278a-4d1f-87c2-11a65a99747f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648971045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.3648971045
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.3762015765
Short name T693
Test name
Test status
Simulation time 444234203 ps
CPU time 3.04 seconds
Started Jul 27 05:33:15 PM PDT 24
Finished Jul 27 05:33:18 PM PDT 24
Peak memory 224588 kb
Host smart-d784dc98-b512-4558-aa81-aeaffa5949bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762015765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.3762015765
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.12314811
Short name T968
Test name
Test status
Simulation time 1110403138 ps
CPU time 8.24 seconds
Started Jul 27 05:33:12 PM PDT 24
Finished Jul 27 05:33:21 PM PDT 24
Peak memory 235176 kb
Host smart-b5c3be06-f174-4b2f-8344-ba20381d6c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12314811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmds.12314811
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_intercept.3596587172
Short name T436
Test name
Test status
Simulation time 670196142 ps
CPU time 9.54 seconds
Started Jul 27 05:33:10 PM PDT 24
Finished Jul 27 05:33:20 PM PDT 24
Peak memory 219868 kb
Host smart-02e4c53f-da43-465f-ba61-71a8777c5a65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596587172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.3596587172
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.1042853379
Short name T343
Test name
Test status
Simulation time 1623937132 ps
CPU time 13.78 seconds
Started Jul 27 05:33:09 PM PDT 24
Finished Jul 27 05:33:24 PM PDT 24
Peak memory 240816 kb
Host smart-550b5101-689c-4ce1-9809-21927c264b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042853379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.1042853379
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.1054727516
Short name T620
Test name
Test status
Simulation time 1575008310 ps
CPU time 8.69 seconds
Started Jul 27 05:33:12 PM PDT 24
Finished Jul 27 05:33:21 PM PDT 24
Peak memory 224608 kb
Host smart-b5f3cc33-9b24-4622-85f2-4b41e0803cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054727516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.1054727516
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.429205761
Short name T688
Test name
Test status
Simulation time 16148677703 ps
CPU time 12.96 seconds
Started Jul 27 05:33:16 PM PDT 24
Finished Jul 27 05:33:29 PM PDT 24
Peak memory 232908 kb
Host smart-68468cad-8e0f-44d3-a349-c940a8432c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429205761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.429205761
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.1764528532
Short name T767
Test name
Test status
Simulation time 2055218898 ps
CPU time 6.46 seconds
Started Jul 27 05:33:11 PM PDT 24
Finished Jul 27 05:33:17 PM PDT 24
Peak memory 219188 kb
Host smart-b7f05ec3-4fe3-491f-8d07-a7e1a34fc20a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1764528532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.1764528532
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.8514461
Short name T387
Test name
Test status
Simulation time 3184456554 ps
CPU time 12.49 seconds
Started Jul 27 05:33:12 PM PDT 24
Finished Jul 27 05:33:25 PM PDT 24
Peak memory 216544 kb
Host smart-6aa16d57-4807-4d85-9859-c0158d3e84d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8514461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.8514461
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.4253052241
Short name T679
Test name
Test status
Simulation time 8509541574 ps
CPU time 13.93 seconds
Started Jul 27 05:33:19 PM PDT 24
Finished Jul 27 05:33:33 PM PDT 24
Peak memory 216368 kb
Host smart-dbe1ef69-c1d0-4a6b-a41c-a8fbc5179575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253052241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.4253052241
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.3824248862
Short name T370
Test name
Test status
Simulation time 54282390 ps
CPU time 1.22 seconds
Started Jul 27 05:33:09 PM PDT 24
Finished Jul 27 05:33:11 PM PDT 24
Peak memory 207900 kb
Host smart-b4290dff-86ca-40e3-98d4-0b3dc3a3810f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824248862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.3824248862
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.3016143029
Short name T521
Test name
Test status
Simulation time 11589336 ps
CPU time 0.71 seconds
Started Jul 27 05:33:09 PM PDT 24
Finished Jul 27 05:33:10 PM PDT 24
Peak memory 206068 kb
Host smart-21cfbd41-7800-4b1c-afad-002e8a43aedd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016143029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.3016143029
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.2137896058
Short name T724
Test name
Test status
Simulation time 596328744 ps
CPU time 10.32 seconds
Started Jul 27 05:33:09 PM PDT 24
Finished Jul 27 05:33:19 PM PDT 24
Peak memory 249256 kb
Host smart-f238b17d-9255-46cc-810d-7d12e83b6f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137896058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.2137896058
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.4216317390
Short name T489
Test name
Test status
Simulation time 14056037 ps
CPU time 0.72 seconds
Started Jul 27 05:31:12 PM PDT 24
Finished Jul 27 05:31:12 PM PDT 24
Peak memory 205544 kb
Host smart-ccaa653b-b2cf-4678-b80f-e159e3088d64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216317390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.4
216317390
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.3083736626
Short name T237
Test name
Test status
Simulation time 575360893 ps
CPU time 5.42 seconds
Started Jul 27 05:31:09 PM PDT 24
Finished Jul 27 05:31:15 PM PDT 24
Peak memory 224672 kb
Host smart-66f6173f-9c50-40a5-a3e4-62a884e57724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083736626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.3083736626
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.4231890459
Short name T786
Test name
Test status
Simulation time 15617454 ps
CPU time 0.77 seconds
Started Jul 27 05:31:13 PM PDT 24
Finished Jul 27 05:31:14 PM PDT 24
Peak memory 205888 kb
Host smart-c4a98ab7-d649-4928-84c2-cfe7cedfaa28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231890459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.4231890459
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.1168127106
Short name T757
Test name
Test status
Simulation time 34035509315 ps
CPU time 276.94 seconds
Started Jul 27 05:31:12 PM PDT 24
Finished Jul 27 05:35:49 PM PDT 24
Peak memory 265700 kb
Host smart-ac82c703-78b9-483e-9d4c-31e75971c279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168127106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.1168127106
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.3506111800
Short name T478
Test name
Test status
Simulation time 4950956740 ps
CPU time 13.36 seconds
Started Jul 27 05:31:09 PM PDT 24
Finished Jul 27 05:31:22 PM PDT 24
Peak memory 237064 kb
Host smart-3cf683b0-6f16-4f81-8658-c8e63318b62c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506111800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.3506111800
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.2206273984
Short name T471
Test name
Test status
Simulation time 33533867420 ps
CPU time 89.02 seconds
Started Jul 27 05:31:11 PM PDT 24
Finished Jul 27 05:32:41 PM PDT 24
Peak memory 256984 kb
Host smart-1f48b216-9cdb-4b6c-9cae-7a9e583ad8e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206273984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.2206273984
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.953358411
Short name T355
Test name
Test status
Simulation time 165980034 ps
CPU time 4.37 seconds
Started Jul 27 05:31:09 PM PDT 24
Finished Jul 27 05:31:14 PM PDT 24
Peak memory 224640 kb
Host smart-a8da4f7f-e07c-4ec4-a6d9-ff440bed8b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953358411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.953358411
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_intercept.3146423273
Short name T777
Test name
Test status
Simulation time 1147107423 ps
CPU time 9.55 seconds
Started Jul 27 05:31:12 PM PDT 24
Finished Jul 27 05:31:21 PM PDT 24
Peak memory 224668 kb
Host smart-87f02ddf-79f3-4917-87ad-27ed1875f9ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146423273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.3146423273
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.2659079842
Short name T476
Test name
Test status
Simulation time 2115803742 ps
CPU time 25.11 seconds
Started Jul 27 05:31:08 PM PDT 24
Finished Jul 27 05:31:33 PM PDT 24
Peak memory 249048 kb
Host smart-7e64d2f2-24bb-4075-a691-98e675ded914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659079842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.2659079842
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.1584040299
Short name T624
Test name
Test status
Simulation time 110380419655 ps
CPU time 26.64 seconds
Started Jul 27 05:31:14 PM PDT 24
Finished Jul 27 05:31:41 PM PDT 24
Peak memory 232836 kb
Host smart-16786354-12f6-49b5-95f1-5196d80cd7d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584040299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.1584040299
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.2798441786
Short name T687
Test name
Test status
Simulation time 1660285487 ps
CPU time 12.51 seconds
Started Jul 27 05:31:12 PM PDT 24
Finished Jul 27 05:31:24 PM PDT 24
Peak memory 240536 kb
Host smart-31d9ad1f-663a-4c27-849f-51edffac9485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798441786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.2798441786
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.3923605040
Short name T899
Test name
Test status
Simulation time 422453229 ps
CPU time 4.32 seconds
Started Jul 27 05:31:10 PM PDT 24
Finished Jul 27 05:31:15 PM PDT 24
Peak memory 223272 kb
Host smart-c4a12c84-fae5-4797-8eeb-cbe26793c435
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3923605040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.3923605040
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.1764614679
Short name T75
Test name
Test status
Simulation time 164997100 ps
CPU time 1.12 seconds
Started Jul 27 05:31:14 PM PDT 24
Finished Jul 27 05:31:16 PM PDT 24
Peak memory 235884 kb
Host smart-d13647b1-0e4c-4c42-a9e5-f0f4f28892ad
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764614679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.1764614679
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.3184159702
Short name T53
Test name
Test status
Simulation time 461235429101 ps
CPU time 1021.11 seconds
Started Jul 27 05:31:12 PM PDT 24
Finished Jul 27 05:48:13 PM PDT 24
Peak memory 265640 kb
Host smart-a60a2063-562d-46ad-91c1-b5481d01964a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184159702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.3184159702
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.1842454040
Short name T848
Test name
Test status
Simulation time 1021486045 ps
CPU time 8.84 seconds
Started Jul 27 05:31:10 PM PDT 24
Finished Jul 27 05:31:19 PM PDT 24
Peak memory 216704 kb
Host smart-9f02af33-60d2-4279-813c-88b9eb81e123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842454040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.1842454040
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.2334855331
Short name T780
Test name
Test status
Simulation time 54170434 ps
CPU time 1.51 seconds
Started Jul 27 05:31:09 PM PDT 24
Finished Jul 27 05:31:11 PM PDT 24
Peak memory 208112 kb
Host smart-4b8a09d9-fb12-429d-9c17-846bf588c019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334855331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.2334855331
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.275276728
Short name T323
Test name
Test status
Simulation time 32945172 ps
CPU time 0.71 seconds
Started Jul 27 05:31:09 PM PDT 24
Finished Jul 27 05:31:10 PM PDT 24
Peak memory 206076 kb
Host smart-a2485ff4-762d-4ce3-a09d-c29bd7c5c390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275276728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.275276728
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.3767350592
Short name T488
Test name
Test status
Simulation time 899345234 ps
CPU time 7.24 seconds
Started Jul 27 05:31:14 PM PDT 24
Finished Jul 27 05:31:21 PM PDT 24
Peak memory 249016 kb
Host smart-62f79d7e-ca1d-4f97-bdde-fe2839d17a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767350592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.3767350592
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.2815412869
Short name T533
Test name
Test status
Simulation time 13212954 ps
CPU time 0.72 seconds
Started Jul 27 05:33:19 PM PDT 24
Finished Jul 27 05:33:20 PM PDT 24
Peak memory 204900 kb
Host smart-e2b94303-66c3-4fd9-8438-47ce370a2e05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815412869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
2815412869
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.2800222904
Short name T654
Test name
Test status
Simulation time 879917780 ps
CPU time 2.89 seconds
Started Jul 27 05:33:09 PM PDT 24
Finished Jul 27 05:33:12 PM PDT 24
Peak memory 232796 kb
Host smart-55ddded0-c3d5-4d70-8541-70d684775e16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800222904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.2800222904
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.694762392
Short name T975
Test name
Test status
Simulation time 47293039 ps
CPU time 0.81 seconds
Started Jul 27 05:33:14 PM PDT 24
Finished Jul 27 05:33:15 PM PDT 24
Peak memory 206016 kb
Host smart-eb4503be-3b5c-46e2-91a7-9a97b1956700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694762392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.694762392
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.1520639771
Short name T779
Test name
Test status
Simulation time 13100051000 ps
CPU time 86.74 seconds
Started Jul 27 05:33:13 PM PDT 24
Finished Jul 27 05:34:40 PM PDT 24
Peak memory 249304 kb
Host smart-104530b3-8c7e-41d7-848c-e7a4fc6aeea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520639771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.1520639771
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.1319343511
Short name T538
Test name
Test status
Simulation time 47891777888 ps
CPU time 125.87 seconds
Started Jul 27 05:33:13 PM PDT 24
Finished Jul 27 05:35:19 PM PDT 24
Peak memory 253216 kb
Host smart-ff46c3de-d8c7-4d6a-944e-a4ae786e19f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319343511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.1319343511
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.58217466
Short name T87
Test name
Test status
Simulation time 549256232340 ps
CPU time 411.67 seconds
Started Jul 27 05:33:11 PM PDT 24
Finished Jul 27 05:40:03 PM PDT 24
Peak memory 267512 kb
Host smart-0de0f2fb-dc74-4a29-a6a7-c5748fdac43f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58217466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idle.58217466
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.2939923266
Short name T135
Test name
Test status
Simulation time 155180066 ps
CPU time 6.73 seconds
Started Jul 27 05:33:10 PM PDT 24
Finished Jul 27 05:33:17 PM PDT 24
Peak memory 232816 kb
Host smart-b1510447-45dd-4af6-9bd2-d7cfe78f5e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939923266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.2939923266
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.2058603648
Short name T187
Test name
Test status
Simulation time 11951742310 ps
CPU time 40.78 seconds
Started Jul 27 05:33:10 PM PDT 24
Finished Jul 27 05:33:51 PM PDT 24
Peak memory 249256 kb
Host smart-87087bf0-9d5f-4b81-a2c7-9e44dc11ac66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058603648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmd
s.2058603648
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/30.spi_device_intercept.276571422
Short name T874
Test name
Test status
Simulation time 13254804207 ps
CPU time 13.95 seconds
Started Jul 27 05:33:21 PM PDT 24
Finished Jul 27 05:33:35 PM PDT 24
Peak memory 232776 kb
Host smart-2997a716-749b-4e88-ad4e-8855b8e3fe9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276571422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.276571422
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.4137487195
Short name T875
Test name
Test status
Simulation time 680969319 ps
CPU time 6.42 seconds
Started Jul 27 05:33:13 PM PDT 24
Finished Jul 27 05:33:19 PM PDT 24
Peak memory 224524 kb
Host smart-01e6ada6-6040-4de1-b72e-6899ce0daaec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137487195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.4137487195
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.694661398
Short name T48
Test name
Test status
Simulation time 1584039908 ps
CPU time 9.83 seconds
Started Jul 27 05:33:19 PM PDT 24
Finished Jul 27 05:33:29 PM PDT 24
Peak memory 224528 kb
Host smart-9c3d6779-2093-43bd-84f7-3ab76778ff0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694661398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swap
.694661398
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.32888296
Short name T545
Test name
Test status
Simulation time 1956125113 ps
CPU time 3.22 seconds
Started Jul 27 05:33:13 PM PDT 24
Finished Jul 27 05:33:16 PM PDT 24
Peak memory 232852 kb
Host smart-eb602d09-c488-4764-8fba-c88118b918e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32888296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.32888296
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.1244453765
Short name T765
Test name
Test status
Simulation time 1481826272 ps
CPU time 6.7 seconds
Started Jul 27 05:33:15 PM PDT 24
Finished Jul 27 05:33:22 PM PDT 24
Peak memory 218920 kb
Host smart-dadfba3e-bbc3-4d4c-a795-8a3a543a7033
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1244453765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.1244453765
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.3595797833
Short name T247
Test name
Test status
Simulation time 90462707876 ps
CPU time 873.76 seconds
Started Jul 27 05:33:15 PM PDT 24
Finished Jul 27 05:47:49 PM PDT 24
Peak memory 273564 kb
Host smart-89f0f46e-d71a-4e1c-ba3a-cc1199cca4c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595797833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.3595797833
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.3707648461
Short name T731
Test name
Test status
Simulation time 58431330 ps
CPU time 0.71 seconds
Started Jul 27 05:33:09 PM PDT 24
Finished Jul 27 05:33:10 PM PDT 24
Peak memory 205812 kb
Host smart-90ad75c7-2cd1-410f-8b84-370737550a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707648461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.3707648461
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.3225179000
Short name T749
Test name
Test status
Simulation time 20981852494 ps
CPU time 13.3 seconds
Started Jul 27 05:33:12 PM PDT 24
Finished Jul 27 05:33:26 PM PDT 24
Peak memory 216592 kb
Host smart-64bac81c-f76d-45fe-a4f8-e104d4c39d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225179000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.3225179000
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.2992431587
Short name T885
Test name
Test status
Simulation time 662017472 ps
CPU time 5.62 seconds
Started Jul 27 05:33:09 PM PDT 24
Finished Jul 27 05:33:16 PM PDT 24
Peak memory 216372 kb
Host smart-a2da4432-efd3-4f28-be91-1b3425e70420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992431587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.2992431587
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.4135525816
Short name T805
Test name
Test status
Simulation time 118749889 ps
CPU time 0.93 seconds
Started Jul 27 05:33:09 PM PDT 24
Finished Jul 27 05:33:11 PM PDT 24
Peak memory 206000 kb
Host smart-25ce983a-7d4f-46ad-9096-351be8ab6ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135525816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.4135525816
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.3741376828
Short name T603
Test name
Test status
Simulation time 1050306350 ps
CPU time 3.02 seconds
Started Jul 27 05:33:09 PM PDT 24
Finished Jul 27 05:33:13 PM PDT 24
Peak memory 232800 kb
Host smart-e765d4a2-09a1-4991-b4f8-33ee564f82db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741376828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.3741376828
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.1440915931
Short name T649
Test name
Test status
Simulation time 16822370 ps
CPU time 0.72 seconds
Started Jul 27 05:33:20 PM PDT 24
Finished Jul 27 05:33:21 PM PDT 24
Peak memory 204932 kb
Host smart-e8116514-c50c-4a8b-8af9-506f24c3119f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440915931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
1440915931
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.211608241
Short name T404
Test name
Test status
Simulation time 149111717 ps
CPU time 3.34 seconds
Started Jul 27 05:33:21 PM PDT 24
Finished Jul 27 05:33:25 PM PDT 24
Peak memory 232840 kb
Host smart-0be13d03-49f1-47d9-8e6d-14eaf2cc3d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211608241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.211608241
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.709231239
Short name T446
Test name
Test status
Simulation time 47669192 ps
CPU time 0.84 seconds
Started Jul 27 05:33:12 PM PDT 24
Finished Jul 27 05:33:13 PM PDT 24
Peak memory 206712 kb
Host smart-530a5172-89aa-485e-ad76-06c34e018e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709231239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.709231239
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.430238357
Short name T269
Test name
Test status
Simulation time 99297114787 ps
CPU time 190.9 seconds
Started Jul 27 05:33:21 PM PDT 24
Finished Jul 27 05:36:32 PM PDT 24
Peak memory 257244 kb
Host smart-3192a5f8-1cfe-4fee-ae12-a6ecb0719e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430238357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.430238357
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.577569354
Short name T141
Test name
Test status
Simulation time 92783764808 ps
CPU time 829.71 seconds
Started Jul 27 05:33:22 PM PDT 24
Finished Jul 27 05:47:12 PM PDT 24
Peak memory 273792 kb
Host smart-519d524c-e956-4b46-a4e0-64515a338dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577569354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.577569354
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.3269897437
Short name T491
Test name
Test status
Simulation time 84607855320 ps
CPU time 127.5 seconds
Started Jul 27 05:33:20 PM PDT 24
Finished Jul 27 05:35:28 PM PDT 24
Peak memory 256400 kb
Host smart-7fb2b691-c96d-40b6-a49e-16556ab6d739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269897437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.3269897437
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.1622485305
Short name T334
Test name
Test status
Simulation time 195950885 ps
CPU time 5.24 seconds
Started Jul 27 05:33:24 PM PDT 24
Finished Jul 27 05:33:29 PM PDT 24
Peak memory 224668 kb
Host smart-5a5cd2e1-540c-42c8-8911-0107e0fc7d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622485305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.1622485305
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.2380044509
Short name T176
Test name
Test status
Simulation time 26536005774 ps
CPU time 122.86 seconds
Started Jul 27 05:33:20 PM PDT 24
Finished Jul 27 05:35:23 PM PDT 24
Peak memory 249320 kb
Host smart-95fb4b7c-3b05-4095-a580-acb65bc52dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380044509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmd
s.2380044509
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/31.spi_device_intercept.4178752453
Short name T729
Test name
Test status
Simulation time 232799701 ps
CPU time 5 seconds
Started Jul 27 05:33:20 PM PDT 24
Finished Jul 27 05:33:26 PM PDT 24
Peak memory 232708 kb
Host smart-ef1fd071-b7c9-4d16-b1bb-1359813ba762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178752453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.4178752453
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.640386698
Short name T229
Test name
Test status
Simulation time 8869061600 ps
CPU time 21.23 seconds
Started Jul 27 05:33:26 PM PDT 24
Finished Jul 27 05:33:47 PM PDT 24
Peak memory 224708 kb
Host smart-771fc9b2-5541-4803-ad49-ed2e3834fb2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640386698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.640386698
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.1919469746
Short name T244
Test name
Test status
Simulation time 4982396716 ps
CPU time 10.53 seconds
Started Jul 27 05:33:21 PM PDT 24
Finished Jul 27 05:33:31 PM PDT 24
Peak memory 232728 kb
Host smart-e59fc28e-4134-49dd-81b0-1d0afaf3886c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919469746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.1919469746
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.2110185538
Short name T839
Test name
Test status
Simulation time 27704142322 ps
CPU time 22.11 seconds
Started Jul 27 05:33:25 PM PDT 24
Finished Jul 27 05:33:47 PM PDT 24
Peak memory 248576 kb
Host smart-c7f2c868-399d-4a36-998d-7d45038da5af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110185538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.2110185538
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.1537120029
Short name T430
Test name
Test status
Simulation time 1644780106 ps
CPU time 7.61 seconds
Started Jul 27 05:33:21 PM PDT 24
Finished Jul 27 05:33:29 PM PDT 24
Peak memory 220640 kb
Host smart-18e19610-dbf6-4792-9efc-ed1d858cae95
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1537120029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.1537120029
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.388091456
Short name T31
Test name
Test status
Simulation time 46912014 ps
CPU time 1.01 seconds
Started Jul 27 05:33:21 PM PDT 24
Finished Jul 27 05:33:23 PM PDT 24
Peak memory 207200 kb
Host smart-fc4ceaac-aa15-4279-bc61-7ab16c1b30c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388091456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stres
s_all.388091456
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.1233532320
Short name T506
Test name
Test status
Simulation time 1370020058 ps
CPU time 4.68 seconds
Started Jul 27 05:33:12 PM PDT 24
Finished Jul 27 05:33:17 PM PDT 24
Peak memory 216344 kb
Host smart-3c10ad4f-e66a-4edf-8505-cc875446e2ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233532320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.1233532320
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.1040196937
Short name T582
Test name
Test status
Simulation time 3004787095 ps
CPU time 8.81 seconds
Started Jul 27 05:33:09 PM PDT 24
Finished Jul 27 05:33:18 PM PDT 24
Peak memory 216340 kb
Host smart-a6993d7e-b080-48fa-9528-11bb2d8aa805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040196937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.1040196937
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.3668470186
Short name T706
Test name
Test status
Simulation time 47356544 ps
CPU time 1.67 seconds
Started Jul 27 05:33:24 PM PDT 24
Finished Jul 27 05:33:25 PM PDT 24
Peak memory 208172 kb
Host smart-bc044129-4f20-448f-a16c-d825194ff766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668470186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.3668470186
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.2858036301
Short name T378
Test name
Test status
Simulation time 16198330 ps
CPU time 0.69 seconds
Started Jul 27 05:33:21 PM PDT 24
Finished Jul 27 05:33:22 PM PDT 24
Peak memory 205992 kb
Host smart-016324ad-c464-4c3c-8e6f-4f57401d191b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858036301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.2858036301
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.340458818
Short name T542
Test name
Test status
Simulation time 5660190592 ps
CPU time 19.32 seconds
Started Jul 27 05:33:21 PM PDT 24
Finished Jul 27 05:33:41 PM PDT 24
Peak memory 232828 kb
Host smart-911d91d0-4454-4c8a-b86c-365d3f9593ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340458818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.340458818
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.1526192069
Short name T681
Test name
Test status
Simulation time 15107941 ps
CPU time 0.7 seconds
Started Jul 27 05:33:23 PM PDT 24
Finished Jul 27 05:33:24 PM PDT 24
Peak memory 205480 kb
Host smart-9b32cfb4-37e1-4c47-9f18-2c51829d0178
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526192069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
1526192069
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.3871167685
Short name T744
Test name
Test status
Simulation time 641922357 ps
CPU time 5.24 seconds
Started Jul 27 05:33:23 PM PDT 24
Finished Jul 27 05:33:28 PM PDT 24
Peak memory 232776 kb
Host smart-0d4f00e8-56f2-4369-a4dc-5427e23ff6ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871167685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.3871167685
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.919226982
Short name T846
Test name
Test status
Simulation time 22953340 ps
CPU time 0.73 seconds
Started Jul 27 05:33:26 PM PDT 24
Finished Jul 27 05:33:27 PM PDT 24
Peak memory 206736 kb
Host smart-d07a2dd6-e2e4-42a0-804a-7c33bc1b6833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919226982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.919226982
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.662504884
Short name T733
Test name
Test status
Simulation time 1631888496 ps
CPU time 10.07 seconds
Started Jul 27 05:33:21 PM PDT 24
Finished Jul 27 05:33:32 PM PDT 24
Peak memory 237072 kb
Host smart-30aac355-9326-47cf-86df-78348b633357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662504884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.662504884
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.2521092
Short name T203
Test name
Test status
Simulation time 318859480743 ps
CPU time 175.09 seconds
Started Jul 27 05:33:19 PM PDT 24
Finished Jul 27 05:36:15 PM PDT 24
Peak memory 252844 kb
Host smart-99474db9-c03e-42cc-89fa-904a6adf33ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.2521092
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.177676860
Short name T877
Test name
Test status
Simulation time 300625368690 ps
CPU time 644.21 seconds
Started Jul 27 05:33:22 PM PDT 24
Finished Jul 27 05:44:07 PM PDT 24
Peak memory 270028 kb
Host smart-8f8ae517-148a-4d1b-b063-78bc55266598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177676860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idle
.177676860
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.3500943228
Short name T747
Test name
Test status
Simulation time 289142144 ps
CPU time 5.04 seconds
Started Jul 27 05:33:22 PM PDT 24
Finished Jul 27 05:33:27 PM PDT 24
Peak memory 224640 kb
Host smart-91b6fc65-9c89-4e1f-97a7-38a9dfb54535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500943228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.3500943228
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.703191505
Short name T98
Test name
Test status
Simulation time 261162451650 ps
CPU time 214.15 seconds
Started Jul 27 05:33:25 PM PDT 24
Finished Jul 27 05:37:00 PM PDT 24
Peak memory 250036 kb
Host smart-5184a5eb-bed4-4f3e-b6cf-03f59addf9a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703191505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmds
.703191505
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_intercept.3359350340
Short name T195
Test name
Test status
Simulation time 1797455604 ps
CPU time 6.88 seconds
Started Jul 27 05:33:20 PM PDT 24
Finished Jul 27 05:33:27 PM PDT 24
Peak memory 224608 kb
Host smart-ff593fc0-3455-4ab3-9afa-cac2623ef6d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359350340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.3359350340
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.587139710
Short name T428
Test name
Test status
Simulation time 235683428 ps
CPU time 4.9 seconds
Started Jul 27 05:33:24 PM PDT 24
Finished Jul 27 05:33:29 PM PDT 24
Peak memory 224652 kb
Host smart-e7c958be-bdfa-426d-bb61-5f659334c954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587139710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.587139710
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.1776401379
Short name T447
Test name
Test status
Simulation time 3291631529 ps
CPU time 13.92 seconds
Started Jul 27 05:33:24 PM PDT 24
Finished Jul 27 05:33:38 PM PDT 24
Peak memory 248944 kb
Host smart-4382d462-3a5a-4e16-9f31-c3c6216af310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776401379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.1776401379
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.1550718981
Short name T868
Test name
Test status
Simulation time 1282993235 ps
CPU time 3.91 seconds
Started Jul 27 05:33:25 PM PDT 24
Finished Jul 27 05:33:29 PM PDT 24
Peak memory 232728 kb
Host smart-be1eec91-c6e8-431a-b982-891fdbe89750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550718981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.1550718981
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.2021227136
Short name T755
Test name
Test status
Simulation time 299389827 ps
CPU time 3.92 seconds
Started Jul 27 05:33:25 PM PDT 24
Finished Jul 27 05:33:29 PM PDT 24
Peak memory 223260 kb
Host smart-915211a8-f762-49e8-a261-e102e89254ed
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2021227136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.2021227136
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.4098994078
Short name T56
Test name
Test status
Simulation time 14494446329 ps
CPU time 104.38 seconds
Started Jul 27 05:33:22 PM PDT 24
Finished Jul 27 05:35:07 PM PDT 24
Peak memory 273444 kb
Host smart-ab8c1501-5085-41cd-883a-58c9711bbb74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098994078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.4098994078
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.1864215216
Short name T997
Test name
Test status
Simulation time 525465886 ps
CPU time 4.88 seconds
Started Jul 27 05:33:21 PM PDT 24
Finished Jul 27 05:33:26 PM PDT 24
Peak memory 216440 kb
Host smart-6a39cf91-f97d-4aac-bcc2-9ba1ba76af7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864215216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.1864215216
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.2036163181
Short name T327
Test name
Test status
Simulation time 3057451038 ps
CPU time 4.68 seconds
Started Jul 27 05:33:22 PM PDT 24
Finished Jul 27 05:33:27 PM PDT 24
Peak memory 216404 kb
Host smart-4a48782b-1bf8-45f3-a404-5f10a85215b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036163181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.2036163181
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.1463985991
Short name T567
Test name
Test status
Simulation time 15392908 ps
CPU time 0.78 seconds
Started Jul 27 05:33:26 PM PDT 24
Finished Jul 27 05:33:27 PM PDT 24
Peak memory 206056 kb
Host smart-cd71b243-5d5a-4c80-9e23-3d8fc148599e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463985991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.1463985991
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.4211491819
Short name T610
Test name
Test status
Simulation time 240101496 ps
CPU time 0.92 seconds
Started Jul 27 05:33:21 PM PDT 24
Finished Jul 27 05:33:23 PM PDT 24
Peak memory 206088 kb
Host smart-b51929fe-6e00-4a13-a994-5c468414f89a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211491819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.4211491819
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.658106203
Short name T475
Test name
Test status
Simulation time 341947572 ps
CPU time 4.1 seconds
Started Jul 27 05:33:26 PM PDT 24
Finished Jul 27 05:33:30 PM PDT 24
Peak memory 224828 kb
Host smart-7f7dd498-b18e-4583-be9b-4091be0f5caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658106203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.658106203
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.2495644331
Short name T939
Test name
Test status
Simulation time 15059854 ps
CPU time 0.72 seconds
Started Jul 27 05:33:31 PM PDT 24
Finished Jul 27 05:33:32 PM PDT 24
Peak memory 205544 kb
Host smart-ffab1b5b-374d-4c9e-a75b-506b949d0d71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495644331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
2495644331
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.1930988617
Short name T866
Test name
Test status
Simulation time 31865448 ps
CPU time 2.38 seconds
Started Jul 27 05:33:35 PM PDT 24
Finished Jul 27 05:33:37 PM PDT 24
Peak memory 232456 kb
Host smart-1510ef9b-7cab-4aa1-8fcb-c4ef88b78f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930988617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.1930988617
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.3150858950
Short name T85
Test name
Test status
Simulation time 43164831 ps
CPU time 0.81 seconds
Started Jul 27 05:33:26 PM PDT 24
Finished Jul 27 05:33:27 PM PDT 24
Peak memory 206716 kb
Host smart-79addd41-0911-4b00-ac3f-cece6811e97a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150858950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.3150858950
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.3710587370
Short name T508
Test name
Test status
Simulation time 10053675889 ps
CPU time 25.98 seconds
Started Jul 27 05:33:32 PM PDT 24
Finished Jul 27 05:33:58 PM PDT 24
Peak memory 250336 kb
Host smart-fbac78a7-67de-47a0-9f7f-5498d0621fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710587370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.3710587370
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.2280655931
Short name T636
Test name
Test status
Simulation time 1908397584 ps
CPU time 19.58 seconds
Started Jul 27 05:33:32 PM PDT 24
Finished Jul 27 05:33:51 PM PDT 24
Peak memory 237628 kb
Host smart-d6167c74-0fae-4653-ad2a-0f0676eb21f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280655931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.2280655931
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.2359354665
Short name T204
Test name
Test status
Simulation time 3594874129 ps
CPU time 75.18 seconds
Started Jul 27 05:33:32 PM PDT 24
Finished Jul 27 05:34:47 PM PDT 24
Peak memory 249252 kb
Host smart-ed2f85d1-4c75-4120-8a82-c0065e391619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359354665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.2359354665
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.969986641
Short name T393
Test name
Test status
Simulation time 70093675 ps
CPU time 3.62 seconds
Started Jul 27 05:33:32 PM PDT 24
Finished Jul 27 05:33:36 PM PDT 24
Peak memory 224600 kb
Host smart-fa9d3d7b-3d18-4cca-b2ac-29524376dab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969986641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.969986641
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.2051871091
Short name T181
Test name
Test status
Simulation time 7016349983 ps
CPU time 87.03 seconds
Started Jul 27 05:33:32 PM PDT 24
Finished Jul 27 05:34:59 PM PDT 24
Peak memory 253176 kb
Host smart-bbf976af-54f3-45fd-bb97-7e5534749ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051871091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmd
s.2051871091
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_intercept.3907140893
Short name T769
Test name
Test status
Simulation time 60064265 ps
CPU time 2.59 seconds
Started Jul 27 05:33:22 PM PDT 24
Finished Jul 27 05:33:25 PM PDT 24
Peak memory 232848 kb
Host smart-a54ae0c7-dbea-4d78-992b-128a4008eb8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907140893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.3907140893
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.3703170953
Short name T83
Test name
Test status
Simulation time 1321922799 ps
CPU time 9.23 seconds
Started Jul 27 05:33:32 PM PDT 24
Finished Jul 27 05:33:41 PM PDT 24
Peak memory 224692 kb
Host smart-f910d945-c5ff-4180-9414-cdd81384db99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703170953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.3703170953
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.93899308
Short name T4
Test name
Test status
Simulation time 880912540 ps
CPU time 5.49 seconds
Started Jul 27 05:33:24 PM PDT 24
Finished Jul 27 05:33:30 PM PDT 24
Peak memory 234904 kb
Host smart-f66f8b81-07fd-4683-8b96-00c67824c76d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93899308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swap.93899308
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.3776830339
Short name T829
Test name
Test status
Simulation time 3277345125 ps
CPU time 6.48 seconds
Started Jul 27 05:33:21 PM PDT 24
Finished Jul 27 05:33:28 PM PDT 24
Peak memory 224644 kb
Host smart-4f9f855c-5788-477c-aea6-5d5b9bbb197c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776830339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.3776830339
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.89845936
Short name T612
Test name
Test status
Simulation time 613463064 ps
CPU time 5.75 seconds
Started Jul 27 05:33:39 PM PDT 24
Finished Jul 27 05:33:45 PM PDT 24
Peak memory 223228 kb
Host smart-bfb8e151-878f-4407-89a2-79bcab4c101b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=89845936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_direc
t.89845936
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.3497792968
Short name T967
Test name
Test status
Simulation time 96246861046 ps
CPU time 411.68 seconds
Started Jul 27 05:33:32 PM PDT 24
Finished Jul 27 05:40:23 PM PDT 24
Peak memory 254800 kb
Host smart-fcfe2b56-9960-4601-a39a-06dd7fe18b20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497792968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.3497792968
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.49539299
Short name T626
Test name
Test status
Simulation time 978775020 ps
CPU time 6.29 seconds
Started Jul 27 05:33:21 PM PDT 24
Finished Jul 27 05:33:28 PM PDT 24
Peak memory 216412 kb
Host smart-6a52c5a0-7689-489d-ba75-5ff898b2e752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49539299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.49539299
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.649227183
Short name T783
Test name
Test status
Simulation time 34376023480 ps
CPU time 8.73 seconds
Started Jul 27 05:33:20 PM PDT 24
Finished Jul 27 05:33:29 PM PDT 24
Peak memory 216348 kb
Host smart-61341be8-df56-437e-9c8c-2b4b32095024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649227183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.649227183
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.638313466
Short name T390
Test name
Test status
Simulation time 19151538 ps
CPU time 1.1 seconds
Started Jul 27 05:33:27 PM PDT 24
Finished Jul 27 05:33:28 PM PDT 24
Peak memory 207912 kb
Host smart-7eec3d59-c35f-4932-8563-d432d1ba1447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638313466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.638313466
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.2253354801
Short name T316
Test name
Test status
Simulation time 66506810 ps
CPU time 0.85 seconds
Started Jul 27 05:33:22 PM PDT 24
Finished Jul 27 05:33:23 PM PDT 24
Peak memory 206048 kb
Host smart-91adb070-bf58-408b-a462-43ebd50bf162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253354801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.2253354801
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.2666744039
Short name T926
Test name
Test status
Simulation time 1277428010 ps
CPU time 7.42 seconds
Started Jul 27 05:33:29 PM PDT 24
Finished Jul 27 05:33:37 PM PDT 24
Peak memory 224676 kb
Host smart-74d5f4a1-eb99-4685-a78a-61b771753628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666744039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.2666744039
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.102711342
Short name T9
Test name
Test status
Simulation time 82815923 ps
CPU time 0.82 seconds
Started Jul 27 05:33:34 PM PDT 24
Finished Jul 27 05:33:35 PM PDT 24
Peak memory 205532 kb
Host smart-7463cabe-e3cc-4b1d-9358-fd5510c8fd6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102711342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.102711342
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.2458527012
Short name T764
Test name
Test status
Simulation time 72779747 ps
CPU time 2.77 seconds
Started Jul 27 05:33:33 PM PDT 24
Finished Jul 27 05:33:36 PM PDT 24
Peak memory 224540 kb
Host smart-15e63651-02b2-48a4-851c-503d8f7ea368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458527012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.2458527012
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.1085759293
Short name T861
Test name
Test status
Simulation time 31514803 ps
CPU time 0.79 seconds
Started Jul 27 05:33:32 PM PDT 24
Finished Jul 27 05:33:33 PM PDT 24
Peak memory 206944 kb
Host smart-19d3a0bb-2a72-4548-8030-310b656b027d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085759293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.1085759293
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.824239148
Short name T346
Test name
Test status
Simulation time 12746882487 ps
CPU time 114.42 seconds
Started Jul 27 05:33:32 PM PDT 24
Finished Jul 27 05:35:27 PM PDT 24
Peak memory 252520 kb
Host smart-5e0b0e89-926c-453b-840e-e896b6412c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824239148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.824239148
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.4117515820
Short name T296
Test name
Test status
Simulation time 39512751391 ps
CPU time 383.69 seconds
Started Jul 27 05:33:30 PM PDT 24
Finished Jul 27 05:39:54 PM PDT 24
Peak memory 262604 kb
Host smart-a64237d6-b478-4278-b25f-fd7f963e27d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117515820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.4117515820
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.2458686539
Short name T264
Test name
Test status
Simulation time 21024365617 ps
CPU time 120.86 seconds
Started Jul 27 05:33:33 PM PDT 24
Finished Jul 27 05:35:34 PM PDT 24
Peak memory 255656 kb
Host smart-0df6ea6a-1974-4ff2-8147-d4719f9e3d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458686539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.2458686539
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.645655681
Short name T352
Test name
Test status
Simulation time 796264964 ps
CPU time 9.14 seconds
Started Jul 27 05:33:34 PM PDT 24
Finished Jul 27 05:33:43 PM PDT 24
Peak memory 224672 kb
Host smart-3e591746-751d-4d71-abe0-ab1cbef0acb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645655681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.645655681
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.3302567849
Short name T190
Test name
Test status
Simulation time 2142559129 ps
CPU time 37.14 seconds
Started Jul 27 05:33:33 PM PDT 24
Finished Jul 27 05:34:10 PM PDT 24
Peak memory 252208 kb
Host smart-b9515a67-d4a1-422b-809c-994cdbff715b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302567849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmd
s.3302567849
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/34.spi_device_intercept.4020689142
Short name T623
Test name
Test status
Simulation time 818789794 ps
CPU time 12.08 seconds
Started Jul 27 05:33:33 PM PDT 24
Finished Jul 27 05:33:46 PM PDT 24
Peak memory 224596 kb
Host smart-3e3f6bc2-1d66-439f-8ae7-082c4a2d5b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020689142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.4020689142
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.678479275
Short name T748
Test name
Test status
Simulation time 77896849 ps
CPU time 2.7 seconds
Started Jul 27 05:33:35 PM PDT 24
Finished Jul 27 05:33:38 PM PDT 24
Peak memory 233100 kb
Host smart-46005b1e-37af-467b-a0b4-0c7908a00b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678479275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.678479275
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.1492482297
Short name T663
Test name
Test status
Simulation time 1087363467 ps
CPU time 6.65 seconds
Started Jul 27 05:33:32 PM PDT 24
Finished Jul 27 05:33:39 PM PDT 24
Peak memory 224624 kb
Host smart-bac6d03e-e074-40cf-ad8d-018af6c38fcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492482297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.1492482297
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.543337500
Short name T982
Test name
Test status
Simulation time 9155989750 ps
CPU time 14.65 seconds
Started Jul 27 05:33:36 PM PDT 24
Finished Jul 27 05:33:51 PM PDT 24
Peak memory 232888 kb
Host smart-6e0b924c-d103-43c9-9569-7825431f9f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543337500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.543337500
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.1952028283
Short name T555
Test name
Test status
Simulation time 157400691 ps
CPU time 4.82 seconds
Started Jul 27 05:33:33 PM PDT 24
Finished Jul 27 05:33:37 PM PDT 24
Peak memory 223380 kb
Host smart-7e128952-bc28-4c32-ad06-f17466c30e03
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1952028283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.1952028283
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.1014310592
Short name T288
Test name
Test status
Simulation time 17652712178 ps
CPU time 28.27 seconds
Started Jul 27 05:33:31 PM PDT 24
Finished Jul 27 05:33:59 PM PDT 24
Peak memory 216476 kb
Host smart-095ae549-019e-49e2-a576-d56e21af8722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014310592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.1014310592
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.3920627304
Short name T14
Test name
Test status
Simulation time 1576165083 ps
CPU time 9.05 seconds
Started Jul 27 05:33:35 PM PDT 24
Finished Jul 27 05:33:45 PM PDT 24
Peak memory 216376 kb
Host smart-9eb47e10-1fc7-449a-a00f-6b29f954008e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920627304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.3920627304
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.2930621147
Short name T716
Test name
Test status
Simulation time 84141188 ps
CPU time 1.62 seconds
Started Jul 27 05:33:34 PM PDT 24
Finished Jul 27 05:33:36 PM PDT 24
Peak memory 216388 kb
Host smart-9528638a-c52b-43a9-9eb8-50b49e3f09cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930621147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.2930621147
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.3772155877
Short name T592
Test name
Test status
Simulation time 56264442 ps
CPU time 0.77 seconds
Started Jul 27 05:33:35 PM PDT 24
Finished Jul 27 05:33:36 PM PDT 24
Peak memory 206296 kb
Host smart-e8befdad-fef8-4d23-bb30-9be69d1a0da0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772155877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.3772155877
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.24246963
Short name T563
Test name
Test status
Simulation time 593862858 ps
CPU time 6.59 seconds
Started Jul 27 05:33:32 PM PDT 24
Finished Jul 27 05:33:39 PM PDT 24
Peak memory 224528 kb
Host smart-bca8a779-9629-4f25-9bd1-428c5f0081ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24246963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.24246963
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.2388908816
Short name T766
Test name
Test status
Simulation time 14096546 ps
CPU time 0.74 seconds
Started Jul 27 05:33:49 PM PDT 24
Finished Jul 27 05:33:50 PM PDT 24
Peak memory 205320 kb
Host smart-80f8146d-437d-4f0f-bf6e-484e0b595790
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388908816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
2388908816
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.2895246815
Short name T431
Test name
Test status
Simulation time 246173367 ps
CPU time 3.57 seconds
Started Jul 27 05:33:33 PM PDT 24
Finished Jul 27 05:33:37 PM PDT 24
Peak memory 224560 kb
Host smart-9d413652-261d-4422-a976-f3adbcf2e9f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895246815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.2895246815
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.628636654
Short name T812
Test name
Test status
Simulation time 18024159 ps
CPU time 0.8 seconds
Started Jul 27 05:33:31 PM PDT 24
Finished Jul 27 05:33:32 PM PDT 24
Peak memory 206704 kb
Host smart-ada33470-d9cb-4c3e-bb1c-34eedc4b44da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628636654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.628636654
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.713994134
Short name T485
Test name
Test status
Simulation time 48126540055 ps
CPU time 85.91 seconds
Started Jul 27 05:33:33 PM PDT 24
Finished Jul 27 05:34:59 PM PDT 24
Peak memory 266556 kb
Host smart-49a0034f-80d0-4a99-8f40-eee74d677b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713994134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.713994134
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.1234548861
Short name T144
Test name
Test status
Simulation time 35006319261 ps
CPU time 58.12 seconds
Started Jul 27 05:33:44 PM PDT 24
Finished Jul 27 05:34:43 PM PDT 24
Peak memory 256696 kb
Host smart-043c59d8-8cd2-45d4-a62f-d826dc745c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234548861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.1234548861
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.3400509633
Short name T537
Test name
Test status
Simulation time 264752689 ps
CPU time 8.2 seconds
Started Jul 27 05:33:32 PM PDT 24
Finished Jul 27 05:33:41 PM PDT 24
Peak memory 232824 kb
Host smart-db81552d-dc52-4aae-bb32-a8be871e26f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400509633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.3400509633
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.3470158151
Short name T589
Test name
Test status
Simulation time 12587541286 ps
CPU time 47.46 seconds
Started Jul 27 05:33:39 PM PDT 24
Finished Jul 27 05:34:27 PM PDT 24
Peak memory 239232 kb
Host smart-508d5dcb-7a58-48e5-b2a9-e4c396c68e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470158151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmd
s.3470158151
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_intercept.4087630503
Short name T303
Test name
Test status
Simulation time 97127705 ps
CPU time 2.02 seconds
Started Jul 27 05:33:33 PM PDT 24
Finished Jul 27 05:33:35 PM PDT 24
Peak memory 223036 kb
Host smart-7830839f-a053-417d-803e-f91ab817d455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087630503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.4087630503
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.2739024773
Short name T82
Test name
Test status
Simulation time 12655454198 ps
CPU time 108.54 seconds
Started Jul 27 05:33:39 PM PDT 24
Finished Jul 27 05:35:28 PM PDT 24
Peak memory 249000 kb
Host smart-864395f1-541e-4d44-abac-87200f3d745c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739024773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.2739024773
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.2414599559
Short name T879
Test name
Test status
Simulation time 377681426 ps
CPU time 4.56 seconds
Started Jul 27 05:33:36 PM PDT 24
Finished Jul 27 05:33:41 PM PDT 24
Peak memory 239864 kb
Host smart-d848230e-8e33-45ac-b2ae-36ef64364070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414599559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.2414599559
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.584369810
Short name T995
Test name
Test status
Simulation time 7203836923 ps
CPU time 11.36 seconds
Started Jul 27 05:33:32 PM PDT 24
Finished Jul 27 05:33:44 PM PDT 24
Peak memory 232872 kb
Host smart-3faa0ee3-0a85-442d-9b6f-656aafe8ef78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584369810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.584369810
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.2109245337
Short name T707
Test name
Test status
Simulation time 4447206485 ps
CPU time 13.79 seconds
Started Jul 27 05:33:35 PM PDT 24
Finished Jul 27 05:33:49 PM PDT 24
Peak memory 220884 kb
Host smart-6f6f93b8-588e-4ba1-b837-ff29b3734391
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2109245337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.2109245337
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.1238693522
Short name T22
Test name
Test status
Simulation time 9162358230 ps
CPU time 100.83 seconds
Started Jul 27 05:33:44 PM PDT 24
Finished Jul 27 05:35:25 PM PDT 24
Peak memory 255724 kb
Host smart-bbdf89be-4b7f-4b92-bec0-84baef173ea5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238693522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.1238693522
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.793000429
Short name T50
Test name
Test status
Simulation time 2410317585 ps
CPU time 12.9 seconds
Started Jul 27 05:33:33 PM PDT 24
Finished Jul 27 05:33:46 PM PDT 24
Peak memory 216420 kb
Host smart-97660fc0-8b2e-48ef-bb18-2c29a3223a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793000429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.793000429
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.550450920
Short name T872
Test name
Test status
Simulation time 3327914633 ps
CPU time 5.19 seconds
Started Jul 27 05:33:39 PM PDT 24
Finished Jul 27 05:33:44 PM PDT 24
Peak memory 216364 kb
Host smart-0cf51aef-e793-4257-a5ec-8d08b81ad7bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550450920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.550450920
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.675012802
Short name T520
Test name
Test status
Simulation time 38146185 ps
CPU time 2.01 seconds
Started Jul 27 05:33:32 PM PDT 24
Finished Jul 27 05:33:34 PM PDT 24
Peak memory 216392 kb
Host smart-a24f3320-cc0b-453b-ae6e-6b11909086a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675012802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.675012802
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.1904801264
Short name T379
Test name
Test status
Simulation time 32379441 ps
CPU time 0.76 seconds
Started Jul 27 05:33:31 PM PDT 24
Finished Jul 27 05:33:32 PM PDT 24
Peak memory 206064 kb
Host smart-06142025-30d6-4ab6-8498-be9b9ea0ee2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904801264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.1904801264
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.2316520722
Short name T614
Test name
Test status
Simulation time 182449492 ps
CPU time 3.9 seconds
Started Jul 27 05:33:29 PM PDT 24
Finished Jul 27 05:33:33 PM PDT 24
Peak memory 232872 kb
Host smart-cc5dce35-1e2e-4c47-81be-9c36b417f6af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316520722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.2316520722
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.1395452529
Short name T517
Test name
Test status
Simulation time 29656472 ps
CPU time 0.75 seconds
Started Jul 27 05:33:48 PM PDT 24
Finished Jul 27 05:33:49 PM PDT 24
Peak memory 204744 kb
Host smart-83910f8e-75fe-4b4a-9e8b-c07cf63e9e47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395452529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
1395452529
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.456595931
Short name T683
Test name
Test status
Simulation time 1738315913 ps
CPU time 8.4 seconds
Started Jul 27 05:33:44 PM PDT 24
Finished Jul 27 05:33:52 PM PDT 24
Peak memory 224544 kb
Host smart-68b2699f-9e93-4dbc-8edc-76fae8065938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456595931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.456595931
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.3960662630
Short name T501
Test name
Test status
Simulation time 16079049 ps
CPU time 0.74 seconds
Started Jul 27 05:33:46 PM PDT 24
Finished Jul 27 05:33:47 PM PDT 24
Peak memory 205688 kb
Host smart-7992b4ea-5ef0-494b-9a2a-1555517aa798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960662630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.3960662630
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.3407735403
Short name T759
Test name
Test status
Simulation time 16547547040 ps
CPU time 49.22 seconds
Started Jul 27 05:33:45 PM PDT 24
Finished Jul 27 05:34:35 PM PDT 24
Peak memory 249516 kb
Host smart-faab2df5-2182-45cf-b662-59d11dba8414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407735403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.3407735403
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.2038296338
Short name T784
Test name
Test status
Simulation time 5631165399 ps
CPU time 31.69 seconds
Started Jul 27 05:33:45 PM PDT 24
Finished Jul 27 05:34:17 PM PDT 24
Peak memory 217704 kb
Host smart-455b5a97-3168-4824-9646-80fb1cf226ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038296338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.2038296338
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.2080742885
Short name T191
Test name
Test status
Simulation time 8214976294 ps
CPU time 50.54 seconds
Started Jul 27 05:33:44 PM PDT 24
Finished Jul 27 05:34:35 PM PDT 24
Peak memory 259188 kb
Host smart-0f00d8c4-57cb-4586-a3ba-e2b66630cba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080742885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.2080742885
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.3322901768
Short name T621
Test name
Test status
Simulation time 1302655135 ps
CPU time 9.17 seconds
Started Jul 27 05:33:46 PM PDT 24
Finished Jul 27 05:33:55 PM PDT 24
Peak memory 249176 kb
Host smart-f2462b14-097d-4c36-8ff5-c0398434a45a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322901768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.3322901768
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.3858214473
Short name T426
Test name
Test status
Simulation time 69318991339 ps
CPU time 155.35 seconds
Started Jul 27 05:33:49 PM PDT 24
Finished Jul 27 05:36:24 PM PDT 24
Peak memory 265680 kb
Host smart-d5ca84b8-be48-4a5b-ab45-d06bc1cd6153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858214473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmd
s.3858214473
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_intercept.1411510653
Short name T838
Test name
Test status
Simulation time 107779281 ps
CPU time 2.42 seconds
Started Jul 27 05:33:46 PM PDT 24
Finished Jul 27 05:33:48 PM PDT 24
Peak memory 223256 kb
Host smart-3d58ba0f-3713-4026-8a0e-2c74fc08c4be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411510653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.1411510653
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.1393115656
Short name T987
Test name
Test status
Simulation time 819809259 ps
CPU time 11.6 seconds
Started Jul 27 05:33:46 PM PDT 24
Finished Jul 27 05:33:58 PM PDT 24
Peak memory 224600 kb
Host smart-3d08556b-61c1-46cd-8997-635f16133f23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393115656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.1393115656
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.1208815984
Short name T248
Test name
Test status
Simulation time 1966713161 ps
CPU time 4.85 seconds
Started Jul 27 05:33:44 PM PDT 24
Finished Jul 27 05:33:49 PM PDT 24
Peak memory 232780 kb
Host smart-3118e03f-3a43-4d33-847f-1c0e064f1e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208815984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.1208815984
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.216423365
Short name T526
Test name
Test status
Simulation time 5671000631 ps
CPU time 4.48 seconds
Started Jul 27 05:33:49 PM PDT 24
Finished Jul 27 05:33:54 PM PDT 24
Peak memory 224564 kb
Host smart-3b4c299d-b4e1-4c6c-8ceb-6d113837246c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216423365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.216423365
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.3070309499
Short name T798
Test name
Test status
Simulation time 1013294877 ps
CPU time 6.35 seconds
Started Jul 27 05:33:44 PM PDT 24
Finished Jul 27 05:33:51 PM PDT 24
Peak memory 223048 kb
Host smart-e99ec7e1-ca71-4810-97fc-3f92e17a9bb8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3070309499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.3070309499
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.3057992760
Short name T32
Test name
Test status
Simulation time 40883628225 ps
CPU time 371.48 seconds
Started Jul 27 05:33:44 PM PDT 24
Finished Jul 27 05:39:56 PM PDT 24
Peak memory 254744 kb
Host smart-0b85bbd5-1d97-449a-b5f8-5743108714d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057992760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.3057992760
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.2451197497
Short name T142
Test name
Test status
Simulation time 2168027488 ps
CPU time 7.38 seconds
Started Jul 27 05:33:45 PM PDT 24
Finished Jul 27 05:33:52 PM PDT 24
Peak memory 216620 kb
Host smart-8ed6ed50-fe88-44d5-be4b-0a34cf0af793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451197497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.2451197497
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.606338737
Short name T138
Test name
Test status
Simulation time 27216182959 ps
CPU time 22.31 seconds
Started Jul 27 05:33:48 PM PDT 24
Finished Jul 27 05:34:10 PM PDT 24
Peak memory 216232 kb
Host smart-f0e54f0c-1860-45a1-bdb2-d4644905c34a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606338737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.606338737
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.603412227
Short name T940
Test name
Test status
Simulation time 17715356 ps
CPU time 0.76 seconds
Started Jul 27 05:33:44 PM PDT 24
Finished Jul 27 05:33:45 PM PDT 24
Peak memory 206280 kb
Host smart-28af975d-582c-499d-98b3-0ecff2e4e4e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603412227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.603412227
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.630622420
Short name T500
Test name
Test status
Simulation time 321821126 ps
CPU time 0.88 seconds
Started Jul 27 05:33:45 PM PDT 24
Finished Jul 27 05:33:46 PM PDT 24
Peak memory 207100 kb
Host smart-dbed093b-6347-40b1-8a9f-fd36cbb4659f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630622420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.630622420
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.4064571367
Short name T876
Test name
Test status
Simulation time 9518283808 ps
CPU time 14.24 seconds
Started Jul 27 05:33:46 PM PDT 24
Finished Jul 27 05:34:00 PM PDT 24
Peak memory 236880 kb
Host smart-58ae7162-640f-47c0-adde-bc141f45273a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064571367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.4064571367
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.424597808
Short name T842
Test name
Test status
Simulation time 36412644 ps
CPU time 0.72 seconds
Started Jul 27 05:33:44 PM PDT 24
Finished Jul 27 05:33:45 PM PDT 24
Peak memory 205792 kb
Host smart-628c07b7-819e-4084-b3f0-7623f38eac5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424597808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.424597808
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.1360940731
Short name T347
Test name
Test status
Simulation time 2275927013 ps
CPU time 4.2 seconds
Started Jul 27 05:33:47 PM PDT 24
Finished Jul 27 05:33:51 PM PDT 24
Peak memory 232768 kb
Host smart-f41b176f-57e9-48a1-8415-c76b5cf0668a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360940731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.1360940731
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.431055872
Short name T420
Test name
Test status
Simulation time 67933969 ps
CPU time 0.78 seconds
Started Jul 27 05:33:46 PM PDT 24
Finished Jul 27 05:33:47 PM PDT 24
Peak memory 206684 kb
Host smart-a17e12a2-0887-4c5a-9e3c-93998ee80fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431055872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.431055872
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.3290718603
Short name T963
Test name
Test status
Simulation time 46814655592 ps
CPU time 325.77 seconds
Started Jul 27 05:33:46 PM PDT 24
Finished Jul 27 05:39:12 PM PDT 24
Peak memory 268916 kb
Host smart-7d072f2a-7d01-44db-a610-9d4b6ae22db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290718603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.3290718603
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.2204376632
Short name T639
Test name
Test status
Simulation time 76070127529 ps
CPU time 639.51 seconds
Started Jul 27 05:33:46 PM PDT 24
Finished Jul 27 05:44:25 PM PDT 24
Peak memory 273508 kb
Host smart-1b7e0e20-0425-4c48-8501-8b175f2d39d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204376632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.2204376632
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.1327500936
Short name T704
Test name
Test status
Simulation time 8986775297 ps
CPU time 61.59 seconds
Started Jul 27 05:33:46 PM PDT 24
Finished Jul 27 05:34:48 PM PDT 24
Peak memory 270352 kb
Host smart-80808af9-c7ae-4f09-98c8-f68a04f6fbb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327500936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.1327500936
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.3910810881
Short name T727
Test name
Test status
Simulation time 5363852558 ps
CPU time 20.16 seconds
Started Jul 27 05:33:45 PM PDT 24
Finished Jul 27 05:34:05 PM PDT 24
Peak memory 241012 kb
Host smart-537088c0-1a6b-40a9-9530-e2699b88ac6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910810881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.3910810881
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.181296283
Short name T722
Test name
Test status
Simulation time 3346969684 ps
CPU time 35.18 seconds
Started Jul 27 05:33:46 PM PDT 24
Finished Jul 27 05:34:22 PM PDT 24
Peak memory 249296 kb
Host smart-d882c59a-46f2-473c-b831-9fa90d9cfc15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181296283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmds
.181296283
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_intercept.2218412750
Short name T81
Test name
Test status
Simulation time 2186830352 ps
CPU time 10.63 seconds
Started Jul 27 05:33:44 PM PDT 24
Finished Jul 27 05:33:55 PM PDT 24
Peak memory 232772 kb
Host smart-fb40a2df-12c4-4018-a4fe-9fc24c507044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218412750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.2218412750
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.643412879
Short name T509
Test name
Test status
Simulation time 2601037400 ps
CPU time 17.4 seconds
Started Jul 27 05:33:44 PM PDT 24
Finished Jul 27 05:34:02 PM PDT 24
Peak memory 232916 kb
Host smart-3d7551a0-675d-490a-9a41-76901ef29e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643412879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.643412879
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.186680012
Short name T260
Test name
Test status
Simulation time 301143990 ps
CPU time 5.69 seconds
Started Jul 27 05:33:43 PM PDT 24
Finished Jul 27 05:33:49 PM PDT 24
Peak memory 241060 kb
Host smart-a2c8bf5d-9bfb-4084-930b-362d034193a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186680012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swap
.186680012
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.156657944
Short name T998
Test name
Test status
Simulation time 4262097969 ps
CPU time 6.4 seconds
Started Jul 27 05:33:48 PM PDT 24
Finished Jul 27 05:33:54 PM PDT 24
Peak memory 224564 kb
Host smart-f7368205-c57e-4ada-aba7-21a70e099671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156657944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.156657944
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.3535841157
Short name T151
Test name
Test status
Simulation time 1174468404 ps
CPU time 8.28 seconds
Started Jul 27 05:33:46 PM PDT 24
Finished Jul 27 05:33:55 PM PDT 24
Peak memory 219396 kb
Host smart-136c584d-4627-4864-be7a-ea44a28526fb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3535841157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.3535841157
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.737756926
Short name T30
Test name
Test status
Simulation time 143278196 ps
CPU time 1.2 seconds
Started Jul 27 05:33:46 PM PDT 24
Finished Jul 27 05:33:48 PM PDT 24
Peak memory 207096 kb
Host smart-e3d2c660-53d5-4f84-8e8b-a34762dc53f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737756926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stres
s_all.737756926
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.1102520581
Short name T297
Test name
Test status
Simulation time 20515249234 ps
CPU time 30.25 seconds
Started Jul 27 05:33:45 PM PDT 24
Finished Jul 27 05:34:15 PM PDT 24
Peak memory 220548 kb
Host smart-c370ade8-0d23-49c3-99b3-c5e07c0036e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102520581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.1102520581
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.2078990688
Short name T382
Test name
Test status
Simulation time 10894261598 ps
CPU time 6.54 seconds
Started Jul 27 05:33:45 PM PDT 24
Finished Jul 27 05:33:52 PM PDT 24
Peak memory 216484 kb
Host smart-f18d5ade-ee9f-405f-9e05-eac7fc831f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078990688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.2078990688
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.974597733
Short name T26
Test name
Test status
Simulation time 328753656 ps
CPU time 3.55 seconds
Started Jul 27 05:33:45 PM PDT 24
Finished Jul 27 05:33:48 PM PDT 24
Peak memory 216368 kb
Host smart-4d6d202c-04f6-4249-a054-9b5175a781aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974597733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.974597733
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.2773092710
Short name T604
Test name
Test status
Simulation time 17896586 ps
CPU time 0.75 seconds
Started Jul 27 05:33:46 PM PDT 24
Finished Jul 27 05:33:47 PM PDT 24
Peak memory 206068 kb
Host smart-20cd4905-ef55-419f-9f7d-71439c932a93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773092710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.2773092710
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.569860989
Short name T512
Test name
Test status
Simulation time 285285869 ps
CPU time 4.06 seconds
Started Jul 27 05:33:46 PM PDT 24
Finished Jul 27 05:33:50 PM PDT 24
Peak memory 224568 kb
Host smart-8024af5a-0318-4578-88b8-99ce1f88a6ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569860989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.569860989
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.3185663515
Short name T932
Test name
Test status
Simulation time 14013694 ps
CPU time 0.73 seconds
Started Jul 27 05:33:57 PM PDT 24
Finished Jul 27 05:33:58 PM PDT 24
Peak memory 204972 kb
Host smart-e40ea582-5087-4be9-858b-01385dcd4148
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185663515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
3185663515
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.653273938
Short name T547
Test name
Test status
Simulation time 678621492 ps
CPU time 4.75 seconds
Started Jul 27 05:33:59 PM PDT 24
Finished Jul 27 05:34:04 PM PDT 24
Peak memory 224668 kb
Host smart-18205ba4-4ddd-4654-83ad-d484fac1ea83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653273938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.653273938
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.731795076
Short name T315
Test name
Test status
Simulation time 77076822 ps
CPU time 0.81 seconds
Started Jul 27 05:33:43 PM PDT 24
Finished Jul 27 05:33:44 PM PDT 24
Peak memory 207056 kb
Host smart-78ff82cf-40f6-4a51-bfc2-f8d94262e0d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731795076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.731795076
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.110922888
Short name T335
Test name
Test status
Simulation time 20191253913 ps
CPU time 51.29 seconds
Started Jul 27 05:33:58 PM PDT 24
Finished Jul 27 05:34:50 PM PDT 24
Peak memory 249384 kb
Host smart-6da94909-c1a0-4acd-a25e-a1b83c9cb8cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110922888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.110922888
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.1351185643
Short name T289
Test name
Test status
Simulation time 2128255284 ps
CPU time 12.38 seconds
Started Jul 27 05:33:56 PM PDT 24
Finished Jul 27 05:34:09 PM PDT 24
Peak memory 217520 kb
Host smart-3c40dab8-1bf1-4aea-9a6a-7c4f04e04116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351185643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.1351185643
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.3788088018
Short name T295
Test name
Test status
Simulation time 2624665292 ps
CPU time 24.62 seconds
Started Jul 27 05:33:58 PM PDT 24
Finished Jul 27 05:34:22 PM PDT 24
Peak memory 217932 kb
Host smart-de888396-7dd6-423a-a8b3-b4e2aec07ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788088018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.3788088018
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.3675800704
Short name T675
Test name
Test status
Simulation time 229519996 ps
CPU time 3.46 seconds
Started Jul 27 05:33:58 PM PDT 24
Finished Jul 27 05:34:01 PM PDT 24
Peak memory 232884 kb
Host smart-576d5bfb-0841-4a48-8fee-fec58497ab60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675800704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.3675800704
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.2412502687
Short name T96
Test name
Test status
Simulation time 2127931566 ps
CPU time 14.91 seconds
Started Jul 27 05:33:57 PM PDT 24
Finished Jul 27 05:34:12 PM PDT 24
Peak memory 237788 kb
Host smart-cf3c215f-b1b3-4d15-9dc4-4d05c4de8edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412502687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmd
s.2412502687
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_intercept.823597668
Short name T599
Test name
Test status
Simulation time 226676257 ps
CPU time 3.33 seconds
Started Jul 27 05:33:44 PM PDT 24
Finished Jul 27 05:33:47 PM PDT 24
Peak memory 232864 kb
Host smart-a573ffc5-5d14-4ce1-895a-469b6492b7bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823597668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.823597668
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.353181365
Short name T913
Test name
Test status
Simulation time 1864750914 ps
CPU time 26.22 seconds
Started Jul 27 05:33:49 PM PDT 24
Finished Jul 27 05:34:15 PM PDT 24
Peak memory 232576 kb
Host smart-059054dd-bcfb-416a-9086-7bbd50f028cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353181365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.353181365
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.3339103439
Short name T525
Test name
Test status
Simulation time 431919855 ps
CPU time 2.61 seconds
Started Jul 27 05:33:44 PM PDT 24
Finished Jul 27 05:33:47 PM PDT 24
Peak memory 233052 kb
Host smart-2ec91385-5361-489a-a7a2-1d1cf173bc77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339103439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.3339103439
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.3640898845
Short name T186
Test name
Test status
Simulation time 10397360528 ps
CPU time 31.58 seconds
Started Jul 27 05:33:47 PM PDT 24
Finished Jul 27 05:34:18 PM PDT 24
Peak memory 239664 kb
Host smart-29ccaf7f-b5e2-4fbf-ade4-7a18d9ddbbb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640898845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.3640898845
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.4109889061
Short name T713
Test name
Test status
Simulation time 3448254060 ps
CPU time 10.3 seconds
Started Jul 27 05:33:58 PM PDT 24
Finished Jul 27 05:34:08 PM PDT 24
Peak memory 219440 kb
Host smart-f325fb1d-fa8d-40c0-8ce3-768e45889e9f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4109889061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.4109889061
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.1088013764
Short name T878
Test name
Test status
Simulation time 1970130344 ps
CPU time 23.12 seconds
Started Jul 27 05:33:45 PM PDT 24
Finished Jul 27 05:34:08 PM PDT 24
Peak memory 216288 kb
Host smart-09ee71e5-d52b-427f-86a3-5af5fffb94a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088013764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.1088013764
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.30169416
Short name T395
Test name
Test status
Simulation time 3538936375 ps
CPU time 3.18 seconds
Started Jul 27 05:33:48 PM PDT 24
Finished Jul 27 05:33:51 PM PDT 24
Peak memory 216172 kb
Host smart-2275b97f-04e7-45a4-b2b6-7b3de3a786e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30169416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.30169416
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.2341783294
Short name T831
Test name
Test status
Simulation time 34800082 ps
CPU time 1.43 seconds
Started Jul 27 05:33:45 PM PDT 24
Finished Jul 27 05:33:47 PM PDT 24
Peak memory 216296 kb
Host smart-02fc7aee-04b0-4376-99fe-b34824863286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341783294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.2341783294
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.1898614968
Short name T91
Test name
Test status
Simulation time 56298965 ps
CPU time 0.82 seconds
Started Jul 27 05:33:45 PM PDT 24
Finished Jul 27 05:33:46 PM PDT 24
Peak memory 205996 kb
Host smart-e2d5fc88-0ce8-449f-865f-ffff71362453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898614968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.1898614968
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.1675020667
Short name T970
Test name
Test status
Simulation time 435326542 ps
CPU time 6.26 seconds
Started Jul 27 05:33:58 PM PDT 24
Finished Jul 27 05:34:04 PM PDT 24
Peak memory 224668 kb
Host smart-a752ca20-5f52-4dc2-9e94-e78af77fed9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675020667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.1675020667
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.3403094350
Short name T717
Test name
Test status
Simulation time 31744726 ps
CPU time 0.74 seconds
Started Jul 27 05:34:00 PM PDT 24
Finished Jul 27 05:34:01 PM PDT 24
Peak memory 205456 kb
Host smart-4d841e3e-44e1-45d8-947f-8810402459c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403094350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
3403094350
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.2731374473
Short name T553
Test name
Test status
Simulation time 4422166046 ps
CPU time 10.8 seconds
Started Jul 27 05:33:59 PM PDT 24
Finished Jul 27 05:34:10 PM PDT 24
Peak memory 232788 kb
Host smart-a029280a-54fb-447f-9fae-48ec2b09e29a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731374473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.2731374473
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.2550125870
Short name T345
Test name
Test status
Simulation time 14860680 ps
CPU time 0.79 seconds
Started Jul 27 05:33:57 PM PDT 24
Finished Jul 27 05:33:57 PM PDT 24
Peak memory 206680 kb
Host smart-5e5d1146-8d88-4857-a103-72b7179beae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550125870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.2550125870
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.1805365139
Short name T958
Test name
Test status
Simulation time 54801718856 ps
CPU time 138.72 seconds
Started Jul 27 05:33:58 PM PDT 24
Finished Jul 27 05:36:16 PM PDT 24
Peak memory 273260 kb
Host smart-218fd697-98ad-4740-9cb2-82b766743b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805365139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.1805365139
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.2586884599
Short name T964
Test name
Test status
Simulation time 49207009553 ps
CPU time 133.88 seconds
Started Jul 27 05:33:58 PM PDT 24
Finished Jul 27 05:36:12 PM PDT 24
Peak memory 253460 kb
Host smart-99cdeb8d-1445-4d72-bccb-1f374b6e00ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586884599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.2586884599
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.837680485
Short name T245
Test name
Test status
Simulation time 17895165693 ps
CPU time 250.37 seconds
Started Jul 27 05:33:59 PM PDT 24
Finished Jul 27 05:38:10 PM PDT 24
Peak memory 273568 kb
Host smart-0a508407-3464-4ec1-911e-c309addd4ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837680485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idle
.837680485
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.2833845760
Short name T281
Test name
Test status
Simulation time 499968458 ps
CPU time 13.16 seconds
Started Jul 27 05:33:57 PM PDT 24
Finished Jul 27 05:34:10 PM PDT 24
Peak memory 233892 kb
Host smart-6cde1347-49fe-4ed4-bf6a-59342920cc18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833845760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.2833845760
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.495762480
Short name T516
Test name
Test status
Simulation time 5210776782 ps
CPU time 73.42 seconds
Started Jul 27 05:33:57 PM PDT 24
Finished Jul 27 05:35:11 PM PDT 24
Peak memory 249244 kb
Host smart-529fd768-3904-46f3-b430-c30c4df2a6a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495762480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmds
.495762480
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/39.spi_device_intercept.3811403966
Short name T977
Test name
Test status
Simulation time 6950913343 ps
CPU time 18.51 seconds
Started Jul 27 05:33:58 PM PDT 24
Finished Jul 27 05:34:17 PM PDT 24
Peak memory 219916 kb
Host smart-0dd95610-b320-4723-818f-73b037eab93f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811403966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.3811403966
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.2825108091
Short name T360
Test name
Test status
Simulation time 892008993 ps
CPU time 13.78 seconds
Started Jul 27 05:33:58 PM PDT 24
Finished Jul 27 05:34:11 PM PDT 24
Peak memory 224672 kb
Host smart-4107663e-ee37-447b-a06e-9757b5c06d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825108091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.2825108091
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.1862205713
Short name T207
Test name
Test status
Simulation time 3116312002 ps
CPU time 15.83 seconds
Started Jul 27 05:33:57 PM PDT 24
Finished Jul 27 05:34:13 PM PDT 24
Peak memory 249180 kb
Host smart-b8bbeff7-2e4b-4f83-b6ba-73a7f7356647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862205713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.1862205713
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.12488503
Short name T140
Test name
Test status
Simulation time 20536102303 ps
CPU time 18.17 seconds
Started Jul 27 05:33:59 PM PDT 24
Finished Jul 27 05:34:17 PM PDT 24
Peak memory 224596 kb
Host smart-fe72a7f2-3b21-46f7-a854-9ada9d5aed2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12488503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.12488503
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.3277667884
Short name T734
Test name
Test status
Simulation time 523809370 ps
CPU time 6.46 seconds
Started Jul 27 05:33:57 PM PDT 24
Finished Jul 27 05:34:04 PM PDT 24
Peak memory 221828 kb
Host smart-66aeae6c-860b-4e72-8364-4a04641fcdbc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3277667884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.3277667884
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.557920004
Short name T389
Test name
Test status
Simulation time 4568532873 ps
CPU time 13.14 seconds
Started Jul 27 05:33:57 PM PDT 24
Finished Jul 27 05:34:10 PM PDT 24
Peak memory 216556 kb
Host smart-ab1cc0c4-072d-4d28-ade7-3af7bb217536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557920004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.557920004
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.3334568654
Short name T945
Test name
Test status
Simulation time 384170734 ps
CPU time 3.18 seconds
Started Jul 27 05:33:59 PM PDT 24
Finished Jul 27 05:34:02 PM PDT 24
Peak memory 216360 kb
Host smart-19cf0c4a-2f62-466c-9aaa-8fce55463ec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334568654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.3334568654
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.4108726847
Short name T369
Test name
Test status
Simulation time 325198162 ps
CPU time 2.56 seconds
Started Jul 27 05:33:58 PM PDT 24
Finished Jul 27 05:34:00 PM PDT 24
Peak memory 216332 kb
Host smart-a9eb4da5-b9b2-41e3-a29b-549a7bf20c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108726847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.4108726847
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.1236913001
Short name T317
Test name
Test status
Simulation time 60706049 ps
CPU time 0.74 seconds
Started Jul 27 05:33:57 PM PDT 24
Finished Jul 27 05:33:57 PM PDT 24
Peak memory 206032 kb
Host smart-30e336a6-fbe3-4756-924c-d0e6b73a7d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236913001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.1236913001
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.3870183083
Short name T230
Test name
Test status
Simulation time 410072143 ps
CPU time 7.13 seconds
Started Jul 27 05:33:57 PM PDT 24
Finished Jul 27 05:34:05 PM PDT 24
Peak memory 232864 kb
Host smart-04597241-0bb7-4954-b6af-1aee1c4e7337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870183083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.3870183083
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.52634029
Short name T326
Test name
Test status
Simulation time 14566895 ps
CPU time 0.77 seconds
Started Jul 27 05:31:17 PM PDT 24
Finished Jul 27 05:31:17 PM PDT 24
Peak memory 205836 kb
Host smart-5e15c5eb-8318-45db-a8ce-08239478182f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52634029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.52634029
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.3269888831
Short name T773
Test name
Test status
Simulation time 92406672 ps
CPU time 2.79 seconds
Started Jul 27 05:31:30 PM PDT 24
Finished Jul 27 05:31:33 PM PDT 24
Peak memory 232792 kb
Host smart-3edf9ae4-70ac-4509-ba1a-23785d148680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269888831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.3269888831
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.654478326
Short name T835
Test name
Test status
Simulation time 17007094 ps
CPU time 0.78 seconds
Started Jul 27 05:31:08 PM PDT 24
Finished Jul 27 05:31:09 PM PDT 24
Peak memory 206692 kb
Host smart-0a15e621-d8d2-4af9-9b88-337eefefbd84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654478326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.654478326
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.1285727978
Short name T349
Test name
Test status
Simulation time 25768876161 ps
CPU time 50.92 seconds
Started Jul 27 05:31:16 PM PDT 24
Finished Jul 27 05:32:07 PM PDT 24
Peak memory 239912 kb
Host smart-749a6e91-5319-47c3-afbb-759852eb06e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285727978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.1285727978
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.2902232614
Short name T889
Test name
Test status
Simulation time 14840151523 ps
CPU time 53.11 seconds
Started Jul 27 05:31:15 PM PDT 24
Finished Jul 27 05:32:08 PM PDT 24
Peak memory 248776 kb
Host smart-5386d2e3-bc25-47e2-bdb1-b0ae76c44a7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902232614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.2902232614
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.1606023440
Short name T381
Test name
Test status
Simulation time 1139808288 ps
CPU time 16.12 seconds
Started Jul 27 05:31:20 PM PDT 24
Finished Jul 27 05:31:36 PM PDT 24
Peak memory 224720 kb
Host smart-fed25adf-fd4f-4dc7-b870-4ffec6fc5008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606023440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.1606023440
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.312316757
Short name T464
Test name
Test status
Simulation time 112434351 ps
CPU time 4.15 seconds
Started Jul 27 05:31:17 PM PDT 24
Finished Jul 27 05:31:21 PM PDT 24
Peak memory 224628 kb
Host smart-457a15b8-843d-4070-81f5-e531d71b6e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312316757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.312316757
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.1788868376
Short name T978
Test name
Test status
Simulation time 18650459729 ps
CPU time 64.73 seconds
Started Jul 27 05:31:16 PM PDT 24
Finished Jul 27 05:32:21 PM PDT 24
Peak memory 250852 kb
Host smart-8dcc1ccf-4cbc-47d9-acfb-a0c59d3bed2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788868376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds
.1788868376
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/4.spi_device_intercept.442883173
Short name T474
Test name
Test status
Simulation time 1137051681 ps
CPU time 13.63 seconds
Started Jul 27 05:31:24 PM PDT 24
Finished Jul 27 05:31:38 PM PDT 24
Peak memory 232864 kb
Host smart-aa0b80a0-65ba-490d-8fdd-2c7d3b3254b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442883173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.442883173
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.2935492559
Short name T771
Test name
Test status
Simulation time 2363106456 ps
CPU time 8.44 seconds
Started Jul 27 05:31:19 PM PDT 24
Finished Jul 27 05:31:28 PM PDT 24
Peak memory 236636 kb
Host smart-5bfb1c96-1c4e-455a-aa41-15cd49f18ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935492559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.2935492559
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.2431585725
Short name T47
Test name
Test status
Simulation time 20904576260 ps
CPU time 17.86 seconds
Started Jul 27 05:31:17 PM PDT 24
Finished Jul 27 05:31:35 PM PDT 24
Peak memory 238592 kb
Host smart-9cf8b0dd-ee36-47a4-a7ab-a28ce9f0d6c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431585725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.2431585725
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.3982620272
Short name T558
Test name
Test status
Simulation time 14319898218 ps
CPU time 12.68 seconds
Started Jul 27 05:31:20 PM PDT 24
Finished Jul 27 05:31:32 PM PDT 24
Peak memory 232824 kb
Host smart-a0cdd048-c245-4539-935c-d059b0e34d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982620272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.3982620272
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.419137729
Short name T686
Test name
Test status
Simulation time 2505707038 ps
CPU time 8.52 seconds
Started Jul 27 05:31:18 PM PDT 24
Finished Jul 27 05:31:27 PM PDT 24
Peak memory 221752 kb
Host smart-a8bf248e-8ba8-4807-bebe-bf0982fe7092
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=419137729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_direc
t.419137729
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.3277453668
Short name T76
Test name
Test status
Simulation time 177955517 ps
CPU time 1.19 seconds
Started Jul 27 05:31:24 PM PDT 24
Finished Jul 27 05:31:25 PM PDT 24
Peak memory 235964 kb
Host smart-6f164f3f-7ab8-4a4c-9559-41eac0b95cac
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277453668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.3277453668
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.3132223687
Short name T28
Test name
Test status
Simulation time 146086749 ps
CPU time 1.02 seconds
Started Jul 27 05:31:24 PM PDT 24
Finished Jul 27 05:31:25 PM PDT 24
Peak memory 206736 kb
Host smart-749178dd-bacf-43bd-8260-71d5d115f0b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132223687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.3132223687
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.2891907278
Short name T307
Test name
Test status
Simulation time 17420200 ps
CPU time 0.73 seconds
Started Jul 27 05:31:11 PM PDT 24
Finished Jul 27 05:31:11 PM PDT 24
Peak memory 205820 kb
Host smart-3615e69b-895d-4d6d-97f2-0d4836db6d48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891907278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.2891907278
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.2402813616
Short name T936
Test name
Test status
Simulation time 8407015506 ps
CPU time 18.27 seconds
Started Jul 27 05:31:09 PM PDT 24
Finished Jul 27 05:31:28 PM PDT 24
Peak memory 216312 kb
Host smart-9b602ed3-264b-4ee8-8039-9227817a537a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402813616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.2402813616
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.3091025322
Short name T611
Test name
Test status
Simulation time 588272299 ps
CPU time 3.51 seconds
Started Jul 27 05:31:11 PM PDT 24
Finished Jul 27 05:31:15 PM PDT 24
Peak memory 216352 kb
Host smart-f8ce0b1f-dadb-4791-b335-351f804390d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091025322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.3091025322
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.3105951764
Short name T799
Test name
Test status
Simulation time 33251366 ps
CPU time 0.76 seconds
Started Jul 27 05:31:09 PM PDT 24
Finished Jul 27 05:31:10 PM PDT 24
Peak memory 206080 kb
Host smart-634ed595-94bc-40f7-8dd5-8079a2ece008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105951764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.3105951764
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.1476821442
Short name T949
Test name
Test status
Simulation time 21902359739 ps
CPU time 24.99 seconds
Started Jul 27 05:31:23 PM PDT 24
Finished Jul 27 05:31:48 PM PDT 24
Peak memory 224640 kb
Host smart-530ed3fc-9101-4bd9-b198-50d30f865729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476821442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.1476821442
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.2763856141
Short name T601
Test name
Test status
Simulation time 21289182 ps
CPU time 0.68 seconds
Started Jul 27 05:34:09 PM PDT 24
Finished Jul 27 05:34:10 PM PDT 24
Peak memory 204952 kb
Host smart-61337f32-eb2e-4062-bc81-aa305a70aa34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763856141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
2763856141
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.763900321
Short name T662
Test name
Test status
Simulation time 22108103485 ps
CPU time 13.39 seconds
Started Jul 27 05:34:00 PM PDT 24
Finished Jul 27 05:34:13 PM PDT 24
Peak memory 224672 kb
Host smart-ff958a9b-c6f1-4c28-ac7d-75f7b1c6e159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763900321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.763900321
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.2749577856
Short name T565
Test name
Test status
Simulation time 56703949 ps
CPU time 0.76 seconds
Started Jul 27 05:33:58 PM PDT 24
Finished Jul 27 05:33:59 PM PDT 24
Peak memory 205700 kb
Host smart-d304c363-689b-42d8-a530-6c6a9cf33ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749577856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.2749577856
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.445303190
Short name T455
Test name
Test status
Simulation time 2284686529 ps
CPU time 12.57 seconds
Started Jul 27 05:34:10 PM PDT 24
Finished Jul 27 05:34:23 PM PDT 24
Peak memory 234980 kb
Host smart-01f76bf1-2214-43f1-8023-dea9a74bd92d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445303190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.445303190
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.512532256
Short name T641
Test name
Test status
Simulation time 2786617574 ps
CPU time 45.53 seconds
Started Jul 27 05:34:12 PM PDT 24
Finished Jul 27 05:34:58 PM PDT 24
Peak memory 249376 kb
Host smart-120b189f-feb9-4403-892b-b4968748f8b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512532256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.512532256
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.1248394539
Short name T205
Test name
Test status
Simulation time 1964657485 ps
CPU time 38.3 seconds
Started Jul 27 05:34:09 PM PDT 24
Finished Jul 27 05:34:48 PM PDT 24
Peak memory 240712 kb
Host smart-a3f96a36-1bcf-42a1-b5a4-4d014cf7eda0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248394539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.1248394539
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.2625985938
Short name T782
Test name
Test status
Simulation time 158802379 ps
CPU time 2.82 seconds
Started Jul 27 05:33:58 PM PDT 24
Finished Jul 27 05:34:01 PM PDT 24
Peak memory 224664 kb
Host smart-de6b4cb9-a1ff-4f36-b9bc-65505e1e96ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625985938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.2625985938
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.719988566
Short name T952
Test name
Test status
Simulation time 5084132025 ps
CPU time 65.43 seconds
Started Jul 27 05:34:10 PM PDT 24
Finished Jul 27 05:35:16 PM PDT 24
Peak memory 251884 kb
Host smart-4a0d32fc-f879-41e1-a3bf-5eb48eb3f5ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719988566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmds
.719988566
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_intercept.3346437005
Short name T590
Test name
Test status
Simulation time 315694353 ps
CPU time 2.82 seconds
Started Jul 27 05:33:57 PM PDT 24
Finished Jul 27 05:34:00 PM PDT 24
Peak memory 224592 kb
Host smart-18e3761d-b2e0-4e67-9803-fc1793bdb9b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346437005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.3346437005
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.2501380697
Short name T419
Test name
Test status
Simulation time 3682059902 ps
CPU time 15.49 seconds
Started Jul 27 05:33:58 PM PDT 24
Finished Jul 27 05:34:14 PM PDT 24
Peak memory 224740 kb
Host smart-c851469d-e251-48f0-8e37-dc02f43d7868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501380697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.2501380697
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.2450408702
Short name T797
Test name
Test status
Simulation time 349716070 ps
CPU time 7.33 seconds
Started Jul 27 05:33:58 PM PDT 24
Finished Jul 27 05:34:06 PM PDT 24
Peak memory 234012 kb
Host smart-87a7ecb7-ac47-4ffa-91af-ee879b132104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450408702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.2450408702
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.1763656395
Short name T635
Test name
Test status
Simulation time 48168757338 ps
CPU time 21.31 seconds
Started Jul 27 05:33:58 PM PDT 24
Finished Jul 27 05:34:19 PM PDT 24
Peak memory 240976 kb
Host smart-14bc356a-f862-41b9-ad9a-23b3dea8203a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763656395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.1763656395
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.314369055
Short name T427
Test name
Test status
Simulation time 310188260 ps
CPU time 6.31 seconds
Started Jul 27 05:34:09 PM PDT 24
Finished Jul 27 05:34:15 PM PDT 24
Peak memory 222780 kb
Host smart-330af25b-3e70-44e5-9e8c-405afbbe1950
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=314369055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dire
ct.314369055
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.2563571170
Short name T196
Test name
Test status
Simulation time 18177980750 ps
CPU time 73.47 seconds
Started Jul 27 05:34:11 PM PDT 24
Finished Jul 27 05:35:25 PM PDT 24
Peak memory 249276 kb
Host smart-44154d92-fe90-44ad-92ab-e527ab8e16ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563571170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.2563571170
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.4087362850
Short name T598
Test name
Test status
Simulation time 3136887226 ps
CPU time 4.7 seconds
Started Jul 27 05:33:59 PM PDT 24
Finished Jul 27 05:34:03 PM PDT 24
Peak memory 216416 kb
Host smart-10fffdf3-eda1-45b0-a9bd-d589023a1e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087362850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.4087362850
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.4285275811
Short name T751
Test name
Test status
Simulation time 4058875037 ps
CPU time 5.01 seconds
Started Jul 27 05:33:59 PM PDT 24
Finished Jul 27 05:34:04 PM PDT 24
Peak memory 216452 kb
Host smart-183996cf-90fb-4423-bfe8-3b5f6ca976ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285275811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.4285275811
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.3349696380
Short name T320
Test name
Test status
Simulation time 80164892 ps
CPU time 2.14 seconds
Started Jul 27 05:33:59 PM PDT 24
Finished Jul 27 05:34:01 PM PDT 24
Peak memory 216388 kb
Host smart-ea51c8c8-0e66-4ee0-8d3e-175b458d4d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349696380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.3349696380
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.779770686
Short name T466
Test name
Test status
Simulation time 244847305 ps
CPU time 0.87 seconds
Started Jul 27 05:33:57 PM PDT 24
Finished Jul 27 05:33:58 PM PDT 24
Peak memory 206304 kb
Host smart-fb8e89fa-df67-435a-b3e8-6f16baca1ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779770686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.779770686
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.3410884101
Short name T301
Test name
Test status
Simulation time 212805186 ps
CPU time 2.5 seconds
Started Jul 27 05:34:00 PM PDT 24
Finished Jul 27 05:34:02 PM PDT 24
Peak memory 224672 kb
Host smart-09ca708c-def4-4a0e-9e1f-bd7bc22c4a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410884101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.3410884101
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.547720290
Short name T661
Test name
Test status
Simulation time 23538551 ps
CPU time 0.73 seconds
Started Jul 27 05:34:12 PM PDT 24
Finished Jul 27 05:34:13 PM PDT 24
Peak memory 205800 kb
Host smart-c8d40597-fe61-4f9f-80bb-8f7adeb622a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547720290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.547720290
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.2431752968
Short name T897
Test name
Test status
Simulation time 485947598 ps
CPU time 7.6 seconds
Started Jul 27 05:34:12 PM PDT 24
Finished Jul 27 05:34:20 PM PDT 24
Peak memory 224676 kb
Host smart-027d628f-7a6b-4912-8abb-ddc31de04bc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431752968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.2431752968
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.368509665
Short name T473
Test name
Test status
Simulation time 18938855 ps
CPU time 0.8 seconds
Started Jul 27 05:34:09 PM PDT 24
Finished Jul 27 05:34:10 PM PDT 24
Peak memory 207020 kb
Host smart-ea3c7966-fcc6-4a2c-a22f-16be77101a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368509665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.368509665
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.1553458729
Short name T535
Test name
Test status
Simulation time 146873760988 ps
CPU time 148.34 seconds
Started Jul 27 05:34:09 PM PDT 24
Finished Jul 27 05:36:37 PM PDT 24
Peak memory 253892 kb
Host smart-40be2d41-7c12-4ba6-a1d9-d82c190da263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553458729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.1553458729
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.546009214
Short name T86
Test name
Test status
Simulation time 39350356143 ps
CPU time 349.03 seconds
Started Jul 27 05:34:12 PM PDT 24
Finished Jul 27 05:40:01 PM PDT 24
Peak memory 260212 kb
Host smart-0dca0b0d-39db-4f01-804e-c24ecab1309f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546009214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.546009214
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.1366725708
Short name T867
Test name
Test status
Simulation time 4998323065 ps
CPU time 17.46 seconds
Started Jul 27 05:34:08 PM PDT 24
Finished Jul 27 05:34:26 PM PDT 24
Peak memory 241108 kb
Host smart-99cb72f4-7fd3-4165-bf94-c64d7be94ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366725708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.1366725708
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.4003975162
Short name T40
Test name
Test status
Simulation time 566409393 ps
CPU time 7.6 seconds
Started Jul 27 05:34:10 PM PDT 24
Finished Jul 27 05:34:18 PM PDT 24
Peak memory 240960 kb
Host smart-bc103094-754b-4679-a41c-5ac74304acf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003975162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.4003975162
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.3003257470
Short name T850
Test name
Test status
Simulation time 114590372366 ps
CPU time 207.64 seconds
Started Jul 27 05:34:14 PM PDT 24
Finished Jul 27 05:37:42 PM PDT 24
Peak memory 255956 kb
Host smart-50bffd23-d54c-43c6-8773-11d94255d904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003257470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmd
s.3003257470
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.847984840
Short name T468
Test name
Test status
Simulation time 823746868 ps
CPU time 6.06 seconds
Started Jul 27 05:34:10 PM PDT 24
Finished Jul 27 05:34:16 PM PDT 24
Peak memory 232784 kb
Host smart-77506d3b-09b1-40cc-9bda-3083a9f05d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847984840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.847984840
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.1173206106
Short name T836
Test name
Test status
Simulation time 658599523 ps
CPU time 11.61 seconds
Started Jul 27 05:34:10 PM PDT 24
Finished Jul 27 05:34:21 PM PDT 24
Peak memory 240744 kb
Host smart-ee495d78-1941-400b-b713-d440ee271c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173206106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.1173206106
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.1390092215
Short name T201
Test name
Test status
Simulation time 16436589299 ps
CPU time 11.22 seconds
Started Jul 27 05:34:09 PM PDT 24
Finished Jul 27 05:34:20 PM PDT 24
Peak memory 232772 kb
Host smart-5ac85fbb-fd24-4f10-a435-2d704c774e73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390092215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.1390092215
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.2218583722
Short name T483
Test name
Test status
Simulation time 777806259 ps
CPU time 5.61 seconds
Started Jul 27 05:34:09 PM PDT 24
Finished Jul 27 05:34:15 PM PDT 24
Peak memory 224596 kb
Host smart-95751d9a-73c5-4be2-bfce-1c36576ff968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218583722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.2218583722
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.3599874214
Short name T462
Test name
Test status
Simulation time 366597509 ps
CPU time 4.28 seconds
Started Jul 27 05:34:09 PM PDT 24
Finished Jul 27 05:34:13 PM PDT 24
Peak memory 223064 kb
Host smart-e29e0e33-993e-4caa-8a8c-63a99d2ba779
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3599874214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.3599874214
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.2251905766
Short name T252
Test name
Test status
Simulation time 71138982093 ps
CPU time 185.97 seconds
Started Jul 27 05:34:12 PM PDT 24
Finished Jul 27 05:37:19 PM PDT 24
Peak memory 269296 kb
Host smart-72d724ac-dbcb-48ae-adef-bf9cbdb6b1e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251905766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.2251905766
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.2336272721
Short name T294
Test name
Test status
Simulation time 23187347958 ps
CPU time 28.06 seconds
Started Jul 27 05:34:08 PM PDT 24
Finished Jul 27 05:34:37 PM PDT 24
Peak memory 216316 kb
Host smart-f26765c3-ee79-49fd-8f4f-8f467e234419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336272721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.2336272721
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.1112796632
Short name T325
Test name
Test status
Simulation time 16772981265 ps
CPU time 14.63 seconds
Started Jul 27 05:34:11 PM PDT 24
Finished Jul 27 05:34:25 PM PDT 24
Peak memory 216436 kb
Host smart-24f353f9-5298-4a21-8507-dafe1d64cbb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112796632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.1112796632
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.1775157894
Short name T350
Test name
Test status
Simulation time 259151829 ps
CPU time 3.36 seconds
Started Jul 27 05:34:12 PM PDT 24
Finished Jul 27 05:34:15 PM PDT 24
Peak memory 216260 kb
Host smart-7fe4c978-1221-4df7-b2b8-32803fdcc806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775157894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.1775157894
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.3860471148
Short name T976
Test name
Test status
Simulation time 68650013 ps
CPU time 0.72 seconds
Started Jul 27 05:34:12 PM PDT 24
Finished Jul 27 05:34:13 PM PDT 24
Peak memory 206104 kb
Host smart-516faaa0-65ec-406a-929a-ced22046b2dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860471148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.3860471148
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.1251933245
Short name T881
Test name
Test status
Simulation time 6439589904 ps
CPU time 11.53 seconds
Started Jul 27 05:34:08 PM PDT 24
Finished Jul 27 05:34:20 PM PDT 24
Peak memory 224720 kb
Host smart-5832e073-50c0-47dd-86b5-b225d557d8af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251933245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.1251933245
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.4145062649
Short name T313
Test name
Test status
Simulation time 36300894 ps
CPU time 0.72 seconds
Started Jul 27 05:34:09 PM PDT 24
Finished Jul 27 05:34:10 PM PDT 24
Peak memory 204984 kb
Host smart-9ab83b6a-ac9a-4e52-b98f-320f00017f7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145062649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
4145062649
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.2661093173
Short name T95
Test name
Test status
Simulation time 146191444 ps
CPU time 3.18 seconds
Started Jul 27 05:34:10 PM PDT 24
Finished Jul 27 05:34:13 PM PDT 24
Peak memory 224672 kb
Host smart-bd057b20-8f6b-4bce-88bd-04a51fe3b981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661093173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.2661093173
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.3000838575
Short name T992
Test name
Test status
Simulation time 25978904 ps
CPU time 0.77 seconds
Started Jul 27 05:34:13 PM PDT 24
Finished Jul 27 05:34:14 PM PDT 24
Peak memory 206984 kb
Host smart-9d2767eb-0069-4d1b-b6fe-cc5eb906f4b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000838575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.3000838575
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.2266369429
Short name T143
Test name
Test status
Simulation time 12373819556 ps
CPU time 130.08 seconds
Started Jul 27 05:34:13 PM PDT 24
Finished Jul 27 05:36:23 PM PDT 24
Peak memory 257192 kb
Host smart-e57548cd-c281-4c22-9ee8-4dc041acfa5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266369429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.2266369429
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.758274383
Short name T1000
Test name
Test status
Simulation time 34218498962 ps
CPU time 195.47 seconds
Started Jul 27 05:34:12 PM PDT 24
Finished Jul 27 05:37:28 PM PDT 24
Peak memory 256000 kb
Host smart-963c9cf8-596a-4f32-b4ca-e6518a4741f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758274383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idle
.758274383
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.1632885922
Short name T954
Test name
Test status
Simulation time 203166372 ps
CPU time 4.64 seconds
Started Jul 27 05:34:12 PM PDT 24
Finished Jul 27 05:34:17 PM PDT 24
Peak memory 233872 kb
Host smart-94b595a3-3c39-4e77-ae4f-06667ffeeca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632885922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.1632885922
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.1563782194
Short name T581
Test name
Test status
Simulation time 3614310573 ps
CPU time 27.69 seconds
Started Jul 27 05:34:11 PM PDT 24
Finished Jul 27 05:34:39 PM PDT 24
Peak memory 241020 kb
Host smart-d83476df-59ce-45d3-85a7-b072e92feadd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563782194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmd
s.1563782194
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_intercept.2625060640
Short name T536
Test name
Test status
Simulation time 5836211687 ps
CPU time 20.07 seconds
Started Jul 27 05:34:10 PM PDT 24
Finished Jul 27 05:34:30 PM PDT 24
Peak memory 224696 kb
Host smart-9e8ae339-0b96-43fa-a150-ee9453f805b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625060640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.2625060640
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.766474513
Short name T227
Test name
Test status
Simulation time 372158896 ps
CPU time 4.9 seconds
Started Jul 27 05:34:10 PM PDT 24
Finished Jul 27 05:34:15 PM PDT 24
Peak memory 232812 kb
Host smart-614f1941-1e2a-44ff-822a-15c4f83f0b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766474513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.766474513
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.1985205616
Short name T841
Test name
Test status
Simulation time 2851928229 ps
CPU time 4.53 seconds
Started Jul 27 05:34:15 PM PDT 24
Finished Jul 27 05:34:19 PM PDT 24
Peak memory 232872 kb
Host smart-f5fa3eec-f714-454e-b032-46c78337bc19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985205616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.1985205616
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.1873095225
Short name T763
Test name
Test status
Simulation time 617009931 ps
CPU time 5.78 seconds
Started Jul 27 05:34:10 PM PDT 24
Finished Jul 27 05:34:16 PM PDT 24
Peak memory 232852 kb
Host smart-782803b4-e40f-40da-960e-177c44a0b008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873095225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.1873095225
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.1351578628
Short name T458
Test name
Test status
Simulation time 1007440979 ps
CPU time 12.71 seconds
Started Jul 27 05:34:12 PM PDT 24
Finished Jul 27 05:34:25 PM PDT 24
Peak memory 219424 kb
Host smart-9938d10e-742a-4b03-903d-a17d5e8ca18d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1351578628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.1351578628
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.591472640
Short name T826
Test name
Test status
Simulation time 10846188325 ps
CPU time 66.35 seconds
Started Jul 27 05:34:14 PM PDT 24
Finished Jul 27 05:35:21 PM PDT 24
Peak memory 255024 kb
Host smart-2f19e7b2-a5e2-4675-afd0-40fc0e13d09f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591472640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stres
s_all.591472640
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.3323030871
Short name T472
Test name
Test status
Simulation time 5618504318 ps
CPU time 19.04 seconds
Started Jul 27 05:34:12 PM PDT 24
Finished Jul 27 05:34:31 PM PDT 24
Peak memory 216388 kb
Host smart-298a5e0e-eb4c-4a84-a533-4b9972ec3940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323030871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.3323030871
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.1806636560
Short name T855
Test name
Test status
Simulation time 1773514048 ps
CPU time 6.16 seconds
Started Jul 27 05:34:12 PM PDT 24
Finished Jul 27 05:34:18 PM PDT 24
Peak memory 216328 kb
Host smart-83207e57-1c1e-4b3d-8f9c-41c8b9f72ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806636560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.1806636560
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.1405919256
Short name T609
Test name
Test status
Simulation time 78247183 ps
CPU time 1.69 seconds
Started Jul 27 05:34:09 PM PDT 24
Finished Jul 27 05:34:11 PM PDT 24
Peak memory 216392 kb
Host smart-0bc2e827-e2e1-49fe-b8a8-b1ec4c0177d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405919256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.1405919256
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.2827035875
Short name T645
Test name
Test status
Simulation time 61523291 ps
CPU time 0.99 seconds
Started Jul 27 05:34:13 PM PDT 24
Finished Jul 27 05:34:14 PM PDT 24
Peak memory 207096 kb
Host smart-89c51baf-5d9c-4012-b57e-39b80f558f4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827035875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.2827035875
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.1933747396
Short name T870
Test name
Test status
Simulation time 930101738 ps
CPU time 6.59 seconds
Started Jul 27 05:34:10 PM PDT 24
Finished Jul 27 05:34:17 PM PDT 24
Peak memory 241036 kb
Host smart-515e1034-187c-490a-a3ee-45cb8691ca93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933747396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.1933747396
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.1935027641
Short name T930
Test name
Test status
Simulation time 49828708 ps
CPU time 0.7 seconds
Started Jul 27 05:34:19 PM PDT 24
Finished Jul 27 05:34:20 PM PDT 24
Peak memory 205452 kb
Host smart-3b7e6ce1-1197-4a1a-8055-fc246854a756
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935027641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
1935027641
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.739392763
Short name T710
Test name
Test status
Simulation time 647519881 ps
CPU time 4.19 seconds
Started Jul 27 05:34:12 PM PDT 24
Finished Jul 27 05:34:16 PM PDT 24
Peak memory 224656 kb
Host smart-1043605a-03c8-46da-831c-95f9a9d5bd43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739392763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.739392763
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.3148341320
Short name T63
Test name
Test status
Simulation time 13687290 ps
CPU time 0.79 seconds
Started Jul 27 05:34:11 PM PDT 24
Finished Jul 27 05:34:12 PM PDT 24
Peak memory 206556 kb
Host smart-9b1b809e-27f6-4040-a855-290f800b7d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148341320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.3148341320
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.320541722
Short name T52
Test name
Test status
Simulation time 95889191326 ps
CPU time 120.3 seconds
Started Jul 27 05:34:12 PM PDT 24
Finished Jul 27 05:36:12 PM PDT 24
Peak memory 252020 kb
Host smart-08598594-9b25-4f07-af22-23d99387af5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320541722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.320541722
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.3848002476
Short name T261
Test name
Test status
Simulation time 26956222711 ps
CPU time 208.39 seconds
Started Jul 27 05:34:12 PM PDT 24
Finished Jul 27 05:37:41 PM PDT 24
Peak memory 285108 kb
Host smart-27b01c4e-58c6-4ccf-946e-11455c3c0ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848002476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.3848002476
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.2106179881
Short name T216
Test name
Test status
Simulation time 33983336261 ps
CPU time 268.65 seconds
Started Jul 27 05:34:14 PM PDT 24
Finished Jul 27 05:38:43 PM PDT 24
Peak memory 251612 kb
Host smart-406b1b63-5af6-4611-be38-462ab677a0ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106179881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.2106179881
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.121996652
Short name T25
Test name
Test status
Simulation time 1863371558 ps
CPU time 3.46 seconds
Started Jul 27 05:34:11 PM PDT 24
Finished Jul 27 05:34:15 PM PDT 24
Peak memory 232848 kb
Host smart-93926c15-bd87-4997-8dfa-ec403c0f7e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121996652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.121996652
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.732090343
Short name T708
Test name
Test status
Simulation time 1781557629 ps
CPU time 38.31 seconds
Started Jul 27 05:34:14 PM PDT 24
Finished Jul 27 05:34:52 PM PDT 24
Peak memory 249460 kb
Host smart-0b26716f-7946-44db-b74e-70d643cd1bd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732090343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmds
.732090343
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_intercept.2891648680
Short name T892
Test name
Test status
Simulation time 1093418781 ps
CPU time 16.23 seconds
Started Jul 27 05:34:12 PM PDT 24
Finished Jul 27 05:34:29 PM PDT 24
Peak memory 232840 kb
Host smart-efb4bdbe-c2eb-4290-80da-8c1daaaf5514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891648680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.2891648680
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.3080622168
Short name T364
Test name
Test status
Simulation time 55554059 ps
CPU time 2.29 seconds
Started Jul 27 05:34:14 PM PDT 24
Finished Jul 27 05:34:16 PM PDT 24
Peak memory 224004 kb
Host smart-3bb036aa-f5be-4e72-8415-8cd08261c3a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080622168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.3080622168
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.1248754732
Short name T137
Test name
Test status
Simulation time 958256058 ps
CPU time 8.69 seconds
Started Jul 27 05:34:11 PM PDT 24
Finished Jul 27 05:34:20 PM PDT 24
Peak memory 237616 kb
Host smart-2624767e-d863-48fa-ab86-3199e1fbc15c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248754732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.1248754732
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.4028177048
Short name T883
Test name
Test status
Simulation time 15434321864 ps
CPU time 13.25 seconds
Started Jul 27 05:34:11 PM PDT 24
Finished Jul 27 05:34:25 PM PDT 24
Peak memory 224724 kb
Host smart-6d607df0-858d-4c1a-b4df-a6610f30c74d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028177048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.4028177048
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.2317801746
Short name T43
Test name
Test status
Simulation time 420333050 ps
CPU time 6.16 seconds
Started Jul 27 05:34:11 PM PDT 24
Finished Jul 27 05:34:18 PM PDT 24
Peak memory 219620 kb
Host smart-15d8b88a-667b-4ebf-915c-5aa80bc294ee
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2317801746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.2317801746
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.2749500225
Short name T674
Test name
Test status
Simulation time 27233820083 ps
CPU time 29.35 seconds
Started Jul 27 05:34:12 PM PDT 24
Finished Jul 27 05:34:41 PM PDT 24
Peak memory 216420 kb
Host smart-de96c78b-988e-4233-82c1-66f0606656fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749500225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.2749500225
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.3765949102
Short name T690
Test name
Test status
Simulation time 34658889 ps
CPU time 0.71 seconds
Started Jul 27 05:34:11 PM PDT 24
Finished Jul 27 05:34:11 PM PDT 24
Peak memory 205792 kb
Host smart-153dde39-490a-49d6-a047-624a51334d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765949102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.3765949102
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.3478513793
Short name T587
Test name
Test status
Simulation time 393055664 ps
CPU time 4.47 seconds
Started Jul 27 05:34:14 PM PDT 24
Finished Jul 27 05:34:18 PM PDT 24
Peak memory 216312 kb
Host smart-1fcee99a-df1e-41a0-b643-8b6cf448ac5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478513793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.3478513793
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.1351227807
Short name T1004
Test name
Test status
Simulation time 108786666 ps
CPU time 0.98 seconds
Started Jul 27 05:34:14 PM PDT 24
Finished Jul 27 05:34:15 PM PDT 24
Peak memory 206512 kb
Host smart-ed30dd35-4a79-4e32-9c60-d95d10b0e8a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351227807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.1351227807
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.3563172365
Short name T403
Test name
Test status
Simulation time 177065841 ps
CPU time 2.36 seconds
Started Jul 27 05:34:12 PM PDT 24
Finished Jul 27 05:34:14 PM PDT 24
Peak memory 224196 kb
Host smart-b4bbc90d-b51d-4f1a-a27f-68d62040647d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563172365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.3563172365
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.587885225
Short name T67
Test name
Test status
Simulation time 72944905 ps
CPU time 0.71 seconds
Started Jul 27 05:34:30 PM PDT 24
Finished Jul 27 05:34:31 PM PDT 24
Peak memory 204964 kb
Host smart-613422cd-0a71-4ef0-838d-6e390a1616e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587885225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.587885225
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.1988783743
Short name T513
Test name
Test status
Simulation time 1893400547 ps
CPU time 4.06 seconds
Started Jul 27 05:34:19 PM PDT 24
Finished Jul 27 05:34:23 PM PDT 24
Peak memory 232812 kb
Host smart-33592fa8-106d-497b-8200-6076388f4e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988783743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.1988783743
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.115614070
Short name T407
Test name
Test status
Simulation time 13131308 ps
CPU time 0.77 seconds
Started Jul 27 05:34:28 PM PDT 24
Finished Jul 27 05:34:29 PM PDT 24
Peak memory 206948 kb
Host smart-c6a2bd20-c843-4288-9c45-9fc6a315a41b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115614070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.115614070
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.2726341853
Short name T277
Test name
Test status
Simulation time 15188564392 ps
CPU time 118.51 seconds
Started Jul 27 05:34:22 PM PDT 24
Finished Jul 27 05:36:20 PM PDT 24
Peak memory 257476 kb
Host smart-3cc3922e-b124-4096-939d-cb575bd585c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726341853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.2726341853
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.44113779
Short name T996
Test name
Test status
Simulation time 27033690191 ps
CPU time 246.28 seconds
Started Jul 27 05:34:22 PM PDT 24
Finished Jul 27 05:38:28 PM PDT 24
Peak memory 254952 kb
Host smart-d282ea6c-b346-429b-bf04-d64f9df0c4ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44113779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.44113779
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.2377469693
Short name T456
Test name
Test status
Simulation time 165381163543 ps
CPU time 363.31 seconds
Started Jul 27 05:34:19 PM PDT 24
Finished Jul 27 05:40:22 PM PDT 24
Peak memory 255532 kb
Host smart-6c6181b7-2ec3-43c3-99a6-47b7be954262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377469693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.2377469693
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.1478181395
Short name T736
Test name
Test status
Simulation time 669010046 ps
CPU time 3.79 seconds
Started Jul 27 05:34:21 PM PDT 24
Finished Jul 27 05:34:25 PM PDT 24
Peak memory 224664 kb
Host smart-61502531-bfc4-49d9-82b9-92ec3b3b1074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478181395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.1478181395
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.2078829550
Short name T57
Test name
Test status
Simulation time 45470471880 ps
CPU time 156.94 seconds
Started Jul 27 05:34:23 PM PDT 24
Finished Jul 27 05:37:00 PM PDT 24
Peak memory 256728 kb
Host smart-ed805b74-7688-49ed-aca7-fd339f8f45b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078829550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmd
s.2078829550
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_intercept.3131641821
Short name T583
Test name
Test status
Simulation time 11317594156 ps
CPU time 28.57 seconds
Started Jul 27 05:34:25 PM PDT 24
Finished Jul 27 05:34:54 PM PDT 24
Peak memory 224580 kb
Host smart-09bdc132-9cfe-4d12-8f30-e19765d414df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131641821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.3131641821
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.3369494022
Short name T711
Test name
Test status
Simulation time 668726123 ps
CPU time 6.54 seconds
Started Jul 27 05:34:18 PM PDT 24
Finished Jul 27 05:34:25 PM PDT 24
Peak memory 224632 kb
Host smart-8b4eb71a-cb78-4320-9025-6c85f692c975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369494022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.3369494022
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.1952625617
Short name T591
Test name
Test status
Simulation time 4004542873 ps
CPU time 7.65 seconds
Started Jul 27 05:34:22 PM PDT 24
Finished Jul 27 05:34:30 PM PDT 24
Peak memory 232892 kb
Host smart-b198b7ee-ba3a-40aa-abcc-7c5dd754ec1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952625617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.1952625617
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.189571567
Short name T333
Test name
Test status
Simulation time 92959008 ps
CPU time 2.07 seconds
Started Jul 27 05:34:21 PM PDT 24
Finished Jul 27 05:34:23 PM PDT 24
Peak memory 223140 kb
Host smart-e8b94fa0-15ec-4128-83e5-4ab8c1ecb7d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189571567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.189571567
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.577965874
Short name T898
Test name
Test status
Simulation time 5125656329 ps
CPU time 7.56 seconds
Started Jul 27 05:34:21 PM PDT 24
Finished Jul 27 05:34:29 PM PDT 24
Peak memory 218380 kb
Host smart-99dda08e-452e-4db4-9ba2-bd94bebb583e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=577965874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dire
ct.577965874
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.330290502
Short name T416
Test name
Test status
Simulation time 1706852291 ps
CPU time 25.92 seconds
Started Jul 27 05:34:19 PM PDT 24
Finished Jul 27 05:34:45 PM PDT 24
Peak memory 241088 kb
Host smart-3ac6ca8b-c8ec-4d7b-907e-5a4f3a65acfc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330290502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stres
s_all.330290502
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.2974828892
Short name T864
Test name
Test status
Simulation time 2327554429 ps
CPU time 23.99 seconds
Started Jul 27 05:34:20 PM PDT 24
Finished Jul 27 05:34:44 PM PDT 24
Peak memory 216664 kb
Host smart-35e1cf25-ffb3-43b0-9688-e773cf5f760f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974828892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.2974828892
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.1919463447
Short name T429
Test name
Test status
Simulation time 2255702206 ps
CPU time 9.05 seconds
Started Jul 27 05:34:20 PM PDT 24
Finished Jul 27 05:34:29 PM PDT 24
Peak memory 216492 kb
Host smart-f1228164-b3de-481a-9114-c25677919d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919463447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.1919463447
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.3533682365
Short name T694
Test name
Test status
Simulation time 209696844 ps
CPU time 1.65 seconds
Started Jul 27 05:34:20 PM PDT 24
Finished Jul 27 05:34:22 PM PDT 24
Peak memory 208084 kb
Host smart-ba99a503-7f5a-487f-8dc1-ee52b75061ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533682365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.3533682365
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.2283843424
Short name T692
Test name
Test status
Simulation time 174256189 ps
CPU time 0.72 seconds
Started Jul 27 05:34:20 PM PDT 24
Finished Jul 27 05:34:21 PM PDT 24
Peak memory 206076 kb
Host smart-2fb2f8ef-04d0-4bdf-be8e-af88648955ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283843424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.2283843424
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.6207475
Short name T559
Test name
Test status
Simulation time 133869741 ps
CPU time 3.3 seconds
Started Jul 27 05:34:27 PM PDT 24
Finished Jul 27 05:34:30 PM PDT 24
Peak memory 224568 kb
Host smart-679493ba-f288-46b8-8332-4c5b8935827b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6207475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.6207475
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.337988772
Short name T887
Test name
Test status
Simulation time 40843175 ps
CPU time 0.73 seconds
Started Jul 27 05:34:22 PM PDT 24
Finished Jul 27 05:34:23 PM PDT 24
Peak memory 205500 kb
Host smart-0dc11d11-e8cf-413d-ad87-392ff7b94b2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337988772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.337988772
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.2303865190
Short name T532
Test name
Test status
Simulation time 1533854712 ps
CPU time 13.62 seconds
Started Jul 27 05:34:29 PM PDT 24
Finished Jul 27 05:34:43 PM PDT 24
Peak memory 224840 kb
Host smart-2f76ca80-1bbd-4332-9e99-c14de8638f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303865190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.2303865190
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.1435780886
Short name T384
Test name
Test status
Simulation time 44528886 ps
CPU time 0.78 seconds
Started Jul 27 05:34:23 PM PDT 24
Finished Jul 27 05:34:23 PM PDT 24
Peak memory 207032 kb
Host smart-53c7345d-8003-4977-a474-e0bdd77f4c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435780886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.1435780886
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.407415238
Short name T989
Test name
Test status
Simulation time 13961037815 ps
CPU time 51.56 seconds
Started Jul 27 05:34:32 PM PDT 24
Finished Jul 27 05:35:24 PM PDT 24
Peak memory 256328 kb
Host smart-4e516390-6a5f-43e3-aab7-20d7878bda06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407415238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.407415238
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.3422444918
Short name T266
Test name
Test status
Simulation time 3239334124 ps
CPU time 88.98 seconds
Started Jul 27 05:34:22 PM PDT 24
Finished Jul 27 05:35:51 PM PDT 24
Peak memory 261612 kb
Host smart-184e5edf-3f16-4ac7-9ce1-1b9c8d5e4f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422444918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.3422444918
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.3507383130
Short name T714
Test name
Test status
Simulation time 46242322063 ps
CPU time 101.9 seconds
Started Jul 27 05:34:25 PM PDT 24
Finished Jul 27 05:36:07 PM PDT 24
Peak memory 238188 kb
Host smart-277046f2-6de0-4eb3-85a1-10ef5868f524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507383130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.3507383130
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.775240703
Short name T794
Test name
Test status
Simulation time 1942820976 ps
CPU time 13.21 seconds
Started Jul 27 05:34:21 PM PDT 24
Finished Jul 27 05:34:34 PM PDT 24
Peak memory 241048 kb
Host smart-e88e0a9c-eddc-41c5-996a-757332e41baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775240703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.775240703
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.590907356
Short name T922
Test name
Test status
Simulation time 17783623079 ps
CPU time 179.43 seconds
Started Jul 27 05:34:21 PM PDT 24
Finished Jul 27 05:37:20 PM PDT 24
Peak memory 261768 kb
Host smart-41d85154-9633-4b9c-a12c-b31929e0b99a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590907356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmds
.590907356
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_intercept.2835429647
Short name T544
Test name
Test status
Simulation time 88977296 ps
CPU time 2.53 seconds
Started Jul 27 05:34:19 PM PDT 24
Finished Jul 27 05:34:22 PM PDT 24
Peak memory 232792 kb
Host smart-2f1b74c7-3b47-4c33-9f99-0a06885fd0ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835429647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.2835429647
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.2977332394
Short name T250
Test name
Test status
Simulation time 1268522204 ps
CPU time 10.8 seconds
Started Jul 27 05:34:21 PM PDT 24
Finished Jul 27 05:34:32 PM PDT 24
Peak memory 224612 kb
Host smart-6004dc95-ca56-4012-944f-cc1f2c8c4907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977332394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.2977332394
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.1072138903
Short name T13
Test name
Test status
Simulation time 2609201272 ps
CPU time 4.93 seconds
Started Jul 27 05:34:20 PM PDT 24
Finished Jul 27 05:34:25 PM PDT 24
Peak memory 224652 kb
Host smart-d7bd1ddc-2220-4ac1-a04a-6a279a67d6be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072138903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.1072138903
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.1324053705
Short name T775
Test name
Test status
Simulation time 1684011346 ps
CPU time 9.09 seconds
Started Jul 27 05:34:23 PM PDT 24
Finished Jul 27 05:34:32 PM PDT 24
Peak memory 232756 kb
Host smart-6f28e049-16df-4bfb-8913-54a82fbcb54b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324053705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.1324053705
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.2145263381
Short name T42
Test name
Test status
Simulation time 299747885 ps
CPU time 4.25 seconds
Started Jul 27 05:34:29 PM PDT 24
Finished Jul 27 05:34:33 PM PDT 24
Peak memory 219576 kb
Host smart-65ab4267-2f2c-402f-af74-a800ab6e6a14
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2145263381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.2145263381
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.3090598030
Short name T16
Test name
Test status
Simulation time 279921376 ps
CPU time 1.13 seconds
Started Jul 27 05:34:21 PM PDT 24
Finished Jul 27 05:34:22 PM PDT 24
Peak memory 206928 kb
Host smart-f8c76e86-36ce-4d62-9312-3f0fad96f5e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090598030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.3090598030
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.2477224093
Short name T494
Test name
Test status
Simulation time 3913783092 ps
CPU time 24.39 seconds
Started Jul 27 05:34:22 PM PDT 24
Finished Jul 27 05:34:47 PM PDT 24
Peak memory 216476 kb
Host smart-18250c07-41ab-4e78-9ff6-d44a42d939dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477224093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.2477224093
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.140306655
Short name T438
Test name
Test status
Simulation time 1374183808 ps
CPU time 6.32 seconds
Started Jul 27 05:34:20 PM PDT 24
Finished Jul 27 05:34:26 PM PDT 24
Peak memory 216428 kb
Host smart-e623be23-3041-493e-bc96-f9bfd8179d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140306655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.140306655
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.4251009437
Short name T400
Test name
Test status
Simulation time 13754132 ps
CPU time 0.69 seconds
Started Jul 27 05:34:21 PM PDT 24
Finished Jul 27 05:34:21 PM PDT 24
Peak memory 205740 kb
Host smart-9b62b3be-549a-4a31-b67c-3414b2094f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251009437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.4251009437
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.4153181045
Short name T671
Test name
Test status
Simulation time 66341129 ps
CPU time 0.96 seconds
Started Jul 27 05:34:29 PM PDT 24
Finished Jul 27 05:34:30 PM PDT 24
Peak memory 206084 kb
Host smart-f8792d14-6dc6-47fe-b363-4d285ef007b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153181045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.4153181045
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.2998780913
Short name T700
Test name
Test status
Simulation time 471695936 ps
CPU time 3.96 seconds
Started Jul 27 05:34:21 PM PDT 24
Finished Jul 27 05:34:25 PM PDT 24
Peak memory 232800 kb
Host smart-19a6b4a9-9757-4544-b476-21d32ddd69ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998780913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.2998780913
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.469689753
Short name T732
Test name
Test status
Simulation time 23625587 ps
CPU time 0.75 seconds
Started Jul 27 05:35:01 PM PDT 24
Finished Jul 27 05:35:02 PM PDT 24
Peak memory 204984 kb
Host smart-c3f39291-f5af-4e03-906d-6600dc335b7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469689753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.469689753
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.4037943498
Short name T242
Test name
Test status
Simulation time 282376475 ps
CPU time 2.81 seconds
Started Jul 27 05:34:35 PM PDT 24
Finished Jul 27 05:34:38 PM PDT 24
Peak memory 224600 kb
Host smart-fc6cae23-91ee-4a20-a25b-8719c3d5daf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037943498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.4037943498
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.3775659175
Short name T59
Test name
Test status
Simulation time 19727443 ps
CPU time 0.83 seconds
Started Jul 27 05:34:25 PM PDT 24
Finished Jul 27 05:34:26 PM PDT 24
Peak memory 206712 kb
Host smart-3481c38a-0fa4-4b14-9227-09d175e61fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775659175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.3775659175
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.28072089
Short name T267
Test name
Test status
Simulation time 16328683214 ps
CPU time 93.41 seconds
Started Jul 27 05:34:36 PM PDT 24
Finished Jul 27 05:36:09 PM PDT 24
Peak memory 268648 kb
Host smart-ac0f84bd-6056-4929-9429-1c3923de8abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28072089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.28072089
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.4220131946
Short name T241
Test name
Test status
Simulation time 22569675681 ps
CPU time 228.87 seconds
Started Jul 27 05:34:32 PM PDT 24
Finished Jul 27 05:38:21 PM PDT 24
Peak memory 252768 kb
Host smart-c772e77e-8b2e-49c5-8dae-eaf8bcb266c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220131946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.4220131946
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.694421491
Short name T857
Test name
Test status
Simulation time 16984079299 ps
CPU time 48.12 seconds
Started Jul 27 05:34:33 PM PDT 24
Finished Jul 27 05:35:21 PM PDT 24
Peak memory 235492 kb
Host smart-f23046fc-4391-4d1c-9756-96b2f011fa72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694421491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idle
.694421491
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.3526007972
Short name T596
Test name
Test status
Simulation time 1768616756 ps
CPU time 8.1 seconds
Started Jul 27 05:34:36 PM PDT 24
Finished Jul 27 05:34:44 PM PDT 24
Peak memory 224664 kb
Host smart-7795b62b-95eb-45fa-929e-3b7f21bcc323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526007972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.3526007972
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.1593257452
Short name T49
Test name
Test status
Simulation time 3544805883 ps
CPU time 62.77 seconds
Started Jul 27 05:34:35 PM PDT 24
Finished Jul 27 05:35:38 PM PDT 24
Peak memory 249320 kb
Host smart-baa6ecd3-81a9-4aa1-acf2-12276852d407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593257452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmd
s.1593257452
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.88042600
Short name T222
Test name
Test status
Simulation time 13600828293 ps
CPU time 26.83 seconds
Started Jul 27 05:34:22 PM PDT 24
Finished Jul 27 05:34:49 PM PDT 24
Peak memory 224728 kb
Host smart-8e378cf2-b950-4d18-8c41-df05eb24d06a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88042600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.88042600
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.1090588724
Short name T366
Test name
Test status
Simulation time 1979311146 ps
CPU time 21.05 seconds
Started Jul 27 05:34:29 PM PDT 24
Finished Jul 27 05:34:50 PM PDT 24
Peak memory 233100 kb
Host smart-49141c79-7ab0-4b99-a3e7-e2996be349e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090588724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.1090588724
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.2546389613
Short name T486
Test name
Test status
Simulation time 5062673199 ps
CPU time 6.12 seconds
Started Jul 27 05:34:29 PM PDT 24
Finished Jul 27 05:34:35 PM PDT 24
Peak memory 224896 kb
Host smart-646fc163-8577-44d0-93e8-264cc3bcf3ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546389613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.2546389613
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.1903466732
Short name T225
Test name
Test status
Simulation time 3927841662 ps
CPU time 10.94 seconds
Started Jul 27 05:34:33 PM PDT 24
Finished Jul 27 05:34:44 PM PDT 24
Peak memory 240664 kb
Host smart-cf67a63a-2ad0-45c7-a0cd-d34520172b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903466732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.1903466732
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.3354279990
Short name T445
Test name
Test status
Simulation time 554984917 ps
CPU time 7.27 seconds
Started Jul 27 05:34:32 PM PDT 24
Finished Jul 27 05:34:40 PM PDT 24
Peak memory 220444 kb
Host smart-7ab671f8-baa6-421a-8eca-ccdaaf759c98
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3354279990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.3354279990
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.3942828291
Short name T719
Test name
Test status
Simulation time 3680132264 ps
CPU time 32.96 seconds
Started Jul 27 05:34:22 PM PDT 24
Finished Jul 27 05:34:55 PM PDT 24
Peak memory 216576 kb
Host smart-136ae43d-f457-4d95-82fb-da5e2851d442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942828291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.3942828291
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.2000040778
Short name T139
Test name
Test status
Simulation time 2353888698 ps
CPU time 10 seconds
Started Jul 27 05:34:25 PM PDT 24
Finished Jul 27 05:34:35 PM PDT 24
Peak memory 216328 kb
Host smart-66226f9c-1de3-4d5e-b382-0dbb0c68d097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000040778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.2000040778
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.2741993270
Short name T709
Test name
Test status
Simulation time 51272461 ps
CPU time 1.16 seconds
Started Jul 27 05:34:24 PM PDT 24
Finished Jul 27 05:34:26 PM PDT 24
Peak memory 207496 kb
Host smart-4d172b06-6b87-4f12-92a2-07cab5382547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741993270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.2741993270
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.3478672013
Short name T413
Test name
Test status
Simulation time 12700934 ps
CPU time 0.71 seconds
Started Jul 27 05:34:29 PM PDT 24
Finished Jul 27 05:34:30 PM PDT 24
Peak memory 205928 kb
Host smart-0c319fb7-fca3-471d-b925-108f0a6301e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478672013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.3478672013
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.2162545392
Short name T956
Test name
Test status
Simulation time 2858886394 ps
CPU time 7.03 seconds
Started Jul 27 05:34:23 PM PDT 24
Finished Jul 27 05:34:30 PM PDT 24
Peak memory 232776 kb
Host smart-7e22c9e8-6b36-44ba-a441-6ef108699663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162545392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.2162545392
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.3343397323
Short name T618
Test name
Test status
Simulation time 17127646 ps
CPU time 0.72 seconds
Started Jul 27 05:34:31 PM PDT 24
Finished Jul 27 05:34:32 PM PDT 24
Peak memory 204992 kb
Host smart-561cb3ff-1331-4b30-8f8e-dcb8e2207d0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343397323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
3343397323
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.896472165
Short name T79
Test name
Test status
Simulation time 274797412 ps
CPU time 4.46 seconds
Started Jul 27 05:34:36 PM PDT 24
Finished Jul 27 05:34:40 PM PDT 24
Peak memory 224656 kb
Host smart-fd1ffa4e-8cb9-4e17-b4d3-3bc3b8441d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896472165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.896472165
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.1728458821
Short name T664
Test name
Test status
Simulation time 40906831 ps
CPU time 0.79 seconds
Started Jul 27 05:34:33 PM PDT 24
Finished Jul 27 05:34:34 PM PDT 24
Peak memory 206576 kb
Host smart-ed96a9c0-6c5b-433f-9df0-464bc4eac6ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728458821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.1728458821
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.2067515226
Short name T644
Test name
Test status
Simulation time 119896994363 ps
CPU time 180.01 seconds
Started Jul 27 05:34:36 PM PDT 24
Finished Jul 27 05:37:36 PM PDT 24
Peak memory 250324 kb
Host smart-f7be1e21-92ba-47f8-ad3a-47ff9d3fe3a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067515226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.2067515226
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.3183317924
Short name T789
Test name
Test status
Simulation time 92494419702 ps
CPU time 288.6 seconds
Started Jul 27 05:34:33 PM PDT 24
Finished Jul 27 05:39:22 PM PDT 24
Peak memory 251312 kb
Host smart-6c79295d-c737-46c6-a215-b2df0caea46f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183317924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.3183317924
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.1585706262
Short name T273
Test name
Test status
Simulation time 111582214423 ps
CPU time 211.08 seconds
Started Jul 27 05:34:54 PM PDT 24
Finished Jul 27 05:38:25 PM PDT 24
Peak memory 255160 kb
Host smart-7c52005c-1935-4632-92df-9b6c2ecbc346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585706262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.1585706262
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.175610723
Short name T282
Test name
Test status
Simulation time 282404120 ps
CPU time 8.45 seconds
Started Jul 27 05:34:31 PM PDT 24
Finished Jul 27 05:34:40 PM PDT 24
Peak memory 232852 kb
Host smart-6c703bd9-f643-42cf-9d4a-ba5149369c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175610723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.175610723
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.811400954
Short name T811
Test name
Test status
Simulation time 13917329236 ps
CPU time 64.18 seconds
Started Jul 27 05:34:31 PM PDT 24
Finished Jul 27 05:35:35 PM PDT 24
Peak memory 249264 kb
Host smart-87007ba5-4f18-482a-9d1c-cd1b53ac0855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811400954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmds
.811400954
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_intercept.1895247460
Short name T232
Test name
Test status
Simulation time 1284566241 ps
CPU time 5.63 seconds
Started Jul 27 05:34:35 PM PDT 24
Finished Jul 27 05:34:41 PM PDT 24
Peak memory 224588 kb
Host smart-26324984-e473-45df-af88-929961619b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895247460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.1895247460
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.3149266327
Short name T699
Test name
Test status
Simulation time 2409088417 ps
CPU time 24.54 seconds
Started Jul 27 05:34:33 PM PDT 24
Finished Jul 27 05:34:58 PM PDT 24
Peak memory 241080 kb
Host smart-e8fa2b1c-b539-4853-888f-e3c339444fc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149266327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.3149266327
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.3959698762
Short name T215
Test name
Test status
Simulation time 526502645 ps
CPU time 6.22 seconds
Started Jul 27 05:34:33 PM PDT 24
Finished Jul 27 05:34:40 PM PDT 24
Peak memory 224592 kb
Host smart-96f3e04f-2fd0-4c25-9363-d03c3442b406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959698762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.3959698762
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.3421406219
Short name T78
Test name
Test status
Simulation time 294170381 ps
CPU time 4.06 seconds
Started Jul 27 05:34:32 PM PDT 24
Finished Jul 27 05:34:37 PM PDT 24
Peak memory 232852 kb
Host smart-b3decddb-5131-4253-9da7-e234e8011ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421406219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.3421406219
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.1497227083
Short name T518
Test name
Test status
Simulation time 191824000 ps
CPU time 5.15 seconds
Started Jul 27 05:34:36 PM PDT 24
Finished Jul 27 05:34:41 PM PDT 24
Peak memory 223160 kb
Host smart-3aba5605-3c5c-4dbc-a5e0-9c6e217fd190
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1497227083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.1497227083
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.2234651627
Short name T159
Test name
Test status
Simulation time 7372669606 ps
CPU time 58.38 seconds
Started Jul 27 05:34:33 PM PDT 24
Finished Jul 27 05:35:32 PM PDT 24
Peak memory 248444 kb
Host smart-e53be053-8663-45df-909c-e580922ee95d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234651627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.2234651627
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.3304545063
Short name T890
Test name
Test status
Simulation time 5168577990 ps
CPU time 29.83 seconds
Started Jul 27 05:34:34 PM PDT 24
Finished Jul 27 05:35:04 PM PDT 24
Peak memory 216348 kb
Host smart-f2ca3a01-7535-4160-8f1f-f9ae56647216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304545063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.3304545063
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.4260639913
Short name T92
Test name
Test status
Simulation time 7360467717 ps
CPU time 12.01 seconds
Started Jul 27 05:34:33 PM PDT 24
Finished Jul 27 05:34:45 PM PDT 24
Peak memory 216408 kb
Host smart-023b70eb-e64c-4fd7-9bcb-b49c8a56664d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260639913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.4260639913
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.1493649814
Short name T600
Test name
Test status
Simulation time 99924528 ps
CPU time 1.58 seconds
Started Jul 27 05:34:31 PM PDT 24
Finished Jul 27 05:34:33 PM PDT 24
Peak memory 216364 kb
Host smart-09e45329-0537-4199-bc14-7e4d6cd522ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493649814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.1493649814
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.1277341770
Short name T344
Test name
Test status
Simulation time 55688339 ps
CPU time 0.84 seconds
Started Jul 27 05:34:53 PM PDT 24
Finished Jul 27 05:34:54 PM PDT 24
Peak memory 205968 kb
Host smart-2e180be6-aed1-4b72-aefb-0b0f2ac9eee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277341770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.1277341770
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.2544208880
Short name T119
Test name
Test status
Simulation time 431170764 ps
CPU time 2.26 seconds
Started Jul 27 05:35:06 PM PDT 24
Finished Jul 27 05:35:08 PM PDT 24
Peak memory 224576 kb
Host smart-4039e5e1-593b-45e7-8b97-becdf13889b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544208880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.2544208880
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.809468423
Short name T433
Test name
Test status
Simulation time 13060416 ps
CPU time 0.72 seconds
Started Jul 27 05:34:43 PM PDT 24
Finished Jul 27 05:34:44 PM PDT 24
Peak memory 205500 kb
Host smart-99a61f94-94b3-4863-aa7d-e0f23dcc8cac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809468423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.809468423
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.3513623648
Short name T689
Test name
Test status
Simulation time 1320305636 ps
CPU time 4.9 seconds
Started Jul 27 05:34:35 PM PDT 24
Finished Jul 27 05:34:41 PM PDT 24
Peak memory 224592 kb
Host smart-c386982c-ae61-4e60-8738-92174f4da640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513623648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.3513623648
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.78926758
Short name T788
Test name
Test status
Simulation time 14616911 ps
CPU time 0.81 seconds
Started Jul 27 05:34:36 PM PDT 24
Finished Jul 27 05:34:37 PM PDT 24
Peak memory 206616 kb
Host smart-34401777-e68f-4c40-82d0-932bee3615e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78926758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.78926758
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.1488357749
Short name T985
Test name
Test status
Simulation time 3103774586 ps
CPU time 62.33 seconds
Started Jul 27 05:34:32 PM PDT 24
Finished Jul 27 05:35:34 PM PDT 24
Peak memory 257428 kb
Host smart-1c2fb7fd-d2b8-4132-9b5e-263957864530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488357749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.1488357749
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.4187732533
Short name T742
Test name
Test status
Simulation time 54002857347 ps
CPU time 172.59 seconds
Started Jul 27 05:34:34 PM PDT 24
Finished Jul 27 05:37:27 PM PDT 24
Peak memory 253656 kb
Host smart-af424799-9225-49f7-a158-aaa49f1cd371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187732533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.4187732533
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.3940993929
Short name T414
Test name
Test status
Simulation time 26559781644 ps
CPU time 48.89 seconds
Started Jul 27 05:35:15 PM PDT 24
Finished Jul 27 05:36:04 PM PDT 24
Peak memory 240040 kb
Host smart-8e3d12ba-c2f4-4fc5-8b4f-75d8455b7a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940993929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.3940993929
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.2120177953
Short name T834
Test name
Test status
Simulation time 1002919969 ps
CPU time 6.78 seconds
Started Jul 27 05:34:32 PM PDT 24
Finished Jul 27 05:34:39 PM PDT 24
Peak memory 224568 kb
Host smart-9c1e7fbb-0743-4d9e-b9a0-7f50aafc3830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120177953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.2120177953
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.539041890
Short name T1003
Test name
Test status
Simulation time 103161991 ps
CPU time 0.77 seconds
Started Jul 27 05:34:34 PM PDT 24
Finished Jul 27 05:34:35 PM PDT 24
Peak memory 215808 kb
Host smart-8aebac76-518b-4164-b191-83494bf5a775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539041890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmds
.539041890
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_intercept.3306814952
Short name T575
Test name
Test status
Simulation time 1947407834 ps
CPU time 9.53 seconds
Started Jul 27 05:34:50 PM PDT 24
Finished Jul 27 05:35:00 PM PDT 24
Peak memory 224564 kb
Host smart-316f7b60-5bd1-4a12-b7bd-40deb1d06136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306814952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.3306814952
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.2800103879
Short name T819
Test name
Test status
Simulation time 1559037414 ps
CPU time 10.6 seconds
Started Jul 27 05:34:36 PM PDT 24
Finished Jul 27 05:34:47 PM PDT 24
Peak memory 232788 kb
Host smart-b5cc9db9-0cf3-43e9-a441-0c118aa9214d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800103879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.2800103879
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.937525680
Short name T743
Test name
Test status
Simulation time 3209602484 ps
CPU time 13 seconds
Started Jul 27 05:34:32 PM PDT 24
Finished Jul 27 05:34:45 PM PDT 24
Peak memory 248432 kb
Host smart-823089be-ad7d-404f-a6c3-801457afb810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937525680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swap
.937525680
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.3312132664
Short name T569
Test name
Test status
Simulation time 4033117204 ps
CPU time 8.49 seconds
Started Jul 27 05:34:33 PM PDT 24
Finished Jul 27 05:34:42 PM PDT 24
Peak memory 239652 kb
Host smart-a1b77d69-3dc1-48e7-9eb0-10ef7a40ce3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312132664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.3312132664
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.1147994137
Short name T460
Test name
Test status
Simulation time 218103959 ps
CPU time 3.38 seconds
Started Jul 27 05:34:36 PM PDT 24
Finished Jul 27 05:34:40 PM PDT 24
Peak memory 220368 kb
Host smart-37e920ec-5397-49c1-b0d5-1f6d3fa2cafe
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1147994137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.1147994137
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.3225806145
Short name T650
Test name
Test status
Simulation time 19482273490 ps
CPU time 189.45 seconds
Started Jul 27 05:34:41 PM PDT 24
Finished Jul 27 05:37:50 PM PDT 24
Peak memory 256432 kb
Host smart-84be2214-f582-4d2e-b869-a1fc8aea0692
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225806145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.3225806145
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.2168283324
Short name T852
Test name
Test status
Simulation time 8588731258 ps
CPU time 49.65 seconds
Started Jul 27 05:34:31 PM PDT 24
Finished Jul 27 05:35:21 PM PDT 24
Peak memory 216448 kb
Host smart-4151912f-a162-4a8a-8338-8fe0f602a9aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168283324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.2168283324
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.2207927957
Short name T959
Test name
Test status
Simulation time 1615868654 ps
CPU time 5.95 seconds
Started Jul 27 05:34:31 PM PDT 24
Finished Jul 27 05:34:37 PM PDT 24
Peak memory 216424 kb
Host smart-0bf4b9a7-1369-43b1-9d35-7f181614a8ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207927957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.2207927957
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.403611551
Short name T418
Test name
Test status
Simulation time 320201671 ps
CPU time 1.32 seconds
Started Jul 27 05:34:33 PM PDT 24
Finished Jul 27 05:34:35 PM PDT 24
Peak memory 216360 kb
Host smart-56d52247-62c6-4a5c-9327-0513f5bd1412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403611551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.403611551
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.3917889759
Short name T776
Test name
Test status
Simulation time 21628560 ps
CPU time 0.73 seconds
Started Jul 27 05:34:33 PM PDT 24
Finished Jul 27 05:34:34 PM PDT 24
Peak memory 205948 kb
Host smart-fa3f314e-c887-49f4-bc16-b8f24367e3d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917889759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.3917889759
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.3320628888
Short name T808
Test name
Test status
Simulation time 437526061 ps
CPU time 5 seconds
Started Jul 27 05:34:32 PM PDT 24
Finished Jul 27 05:34:37 PM PDT 24
Peak memory 232840 kb
Host smart-18b42ed3-c5c6-4d0c-be7a-b7cd432970eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320628888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.3320628888
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.225095034
Short name T359
Test name
Test status
Simulation time 24991410 ps
CPU time 0.75 seconds
Started Jul 27 05:34:43 PM PDT 24
Finished Jul 27 05:34:44 PM PDT 24
Peak memory 205532 kb
Host smart-5566831c-ecea-4793-bb67-de0ad28bce28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225095034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.225095034
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.3919400803
Short name T993
Test name
Test status
Simulation time 3443650029 ps
CPU time 35.2 seconds
Started Jul 27 05:34:45 PM PDT 24
Finished Jul 27 05:35:20 PM PDT 24
Peak memory 232924 kb
Host smart-164a83e5-9ac7-4c6c-91e0-3aa2f0f239e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919400803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.3919400803
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.2939642541
Short name T507
Test name
Test status
Simulation time 51230554 ps
CPU time 0.8 seconds
Started Jul 27 05:34:39 PM PDT 24
Finished Jul 27 05:34:40 PM PDT 24
Peak memory 206712 kb
Host smart-65bf5a3a-7955-4bcd-a95c-3f20e18e7eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939642541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.2939642541
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.3559909521
Short name T219
Test name
Test status
Simulation time 4719572514 ps
CPU time 61.62 seconds
Started Jul 27 05:34:42 PM PDT 24
Finished Jul 27 05:35:44 PM PDT 24
Peak memory 255128 kb
Host smart-2f947732-a1b1-4322-927f-8a324884c48d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559909521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.3559909521
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.2844865963
Short name T515
Test name
Test status
Simulation time 2388649548 ps
CPU time 7.74 seconds
Started Jul 27 05:34:41 PM PDT 24
Finished Jul 27 05:34:48 PM PDT 24
Peak memory 217832 kb
Host smart-fc4e0d83-f381-4e73-a60e-0457bb0b22c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844865963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.2844865963
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.1279135196
Short name T1
Test name
Test status
Simulation time 8945673668 ps
CPU time 14.14 seconds
Started Jul 27 05:34:41 PM PDT 24
Finished Jul 27 05:34:55 PM PDT 24
Peak memory 217676 kb
Host smart-640ef942-3e75-428c-ae0b-a2c83d0eb4d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279135196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.1279135196
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.759769523
Short name T324
Test name
Test status
Simulation time 923247796 ps
CPU time 6.81 seconds
Started Jul 27 05:35:15 PM PDT 24
Finished Jul 27 05:35:22 PM PDT 24
Peak memory 249176 kb
Host smart-edace5df-0d7b-4082-8849-4c8254cbcae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759769523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.759769523
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_intercept.3280630178
Short name T220
Test name
Test status
Simulation time 795574948 ps
CPU time 11.18 seconds
Started Jul 27 05:34:40 PM PDT 24
Finished Jul 27 05:34:51 PM PDT 24
Peak memory 224684 kb
Host smart-8de645fa-71a9-47c9-b22f-5b4b0864b93c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280630178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.3280630178
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.861684328
Short name T493
Test name
Test status
Simulation time 39126176805 ps
CPU time 88.56 seconds
Started Jul 27 05:34:44 PM PDT 24
Finished Jul 27 05:36:13 PM PDT 24
Peak memory 240460 kb
Host smart-76f725f8-d009-4f07-b859-3e8d7a69f7a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861684328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.861684328
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.2019272111
Short name T223
Test name
Test status
Simulation time 254068066 ps
CPU time 4.78 seconds
Started Jul 27 05:34:39 PM PDT 24
Finished Jul 27 05:34:44 PM PDT 24
Peak memory 224616 kb
Host smart-deaa8bef-0b6d-40a1-9349-41ed7d73ad65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019272111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.2019272111
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.1960485920
Short name T640
Test name
Test status
Simulation time 33262576268 ps
CPU time 24.27 seconds
Started Jul 27 05:34:49 PM PDT 24
Finished Jul 27 05:35:13 PM PDT 24
Peak memory 232756 kb
Host smart-28b4dd56-647f-4d34-96fd-738a11e25b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960485920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.1960485920
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.2144528075
Short name T80
Test name
Test status
Simulation time 2902734425 ps
CPU time 7.25 seconds
Started Jul 27 05:34:40 PM PDT 24
Finished Jul 27 05:34:47 PM PDT 24
Peak memory 220456 kb
Host smart-7cf61671-bc96-4d0d-8da8-21daa90f820b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2144528075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.2144528075
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.1341135183
Short name T937
Test name
Test status
Simulation time 9117266626 ps
CPU time 25.97 seconds
Started Jul 27 05:34:42 PM PDT 24
Finished Jul 27 05:35:08 PM PDT 24
Peak memory 216348 kb
Host smart-1e3b22e6-8201-49a4-a18d-7edb3f12db97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341135183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.1341135183
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.1056664038
Short name T931
Test name
Test status
Simulation time 6608071976 ps
CPU time 5.44 seconds
Started Jul 27 05:34:39 PM PDT 24
Finished Jul 27 05:34:44 PM PDT 24
Peak memory 216300 kb
Host smart-9657dd55-1928-41d6-bf39-11c6cb35f551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056664038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.1056664038
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.3544223344
Short name T740
Test name
Test status
Simulation time 158474855 ps
CPU time 1.85 seconds
Started Jul 27 05:34:44 PM PDT 24
Finished Jul 27 05:34:46 PM PDT 24
Peak memory 216380 kb
Host smart-3f6870c4-130a-4cfe-b68d-1ddfd2b615d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544223344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.3544223344
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.416295929
Short name T886
Test name
Test status
Simulation time 50804561 ps
CPU time 0.7 seconds
Started Jul 27 05:34:44 PM PDT 24
Finished Jul 27 05:34:45 PM PDT 24
Peak memory 206028 kb
Host smart-c0d1fb39-50e6-4cb1-9f24-b3d53bc36e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416295929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.416295929
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.3538973448
Short name T398
Test name
Test status
Simulation time 22573588240 ps
CPU time 12.83 seconds
Started Jul 27 05:34:40 PM PDT 24
Finished Jul 27 05:34:53 PM PDT 24
Peak memory 229700 kb
Host smart-33b67dd7-73de-4b54-93c7-bc679b9d6014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538973448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.3538973448
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.677699242
Short name T376
Test name
Test status
Simulation time 13945815 ps
CPU time 0.73 seconds
Started Jul 27 05:31:21 PM PDT 24
Finished Jul 27 05:31:21 PM PDT 24
Peak memory 205008 kb
Host smart-9ca220aa-92df-484c-8fab-1658a6db0d59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677699242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.677699242
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.3471691652
Short name T174
Test name
Test status
Simulation time 947184293 ps
CPU time 8.02 seconds
Started Jul 27 05:31:24 PM PDT 24
Finished Jul 27 05:31:32 PM PDT 24
Peak memory 224616 kb
Host smart-8da0ac3d-82dc-4415-97d4-74fa2d345938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471691652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.3471691652
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.3258206012
Short name T338
Test name
Test status
Simulation time 127542844 ps
CPU time 0.78 seconds
Started Jul 27 05:31:16 PM PDT 24
Finished Jul 27 05:31:17 PM PDT 24
Peak memory 207000 kb
Host smart-a0e39d01-892a-4dd6-8494-8100d3bee30b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258206012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.3258206012
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.113374224
Short name T677
Test name
Test status
Simulation time 16689830976 ps
CPU time 142.61 seconds
Started Jul 27 05:31:30 PM PDT 24
Finished Jul 27 05:33:53 PM PDT 24
Peak memory 263944 kb
Host smart-37435927-e51a-4d89-94e5-af2ec8065d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113374224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.113374224
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.3108307789
Short name T778
Test name
Test status
Simulation time 1966446327 ps
CPU time 35.19 seconds
Started Jul 27 05:31:21 PM PDT 24
Finished Jul 27 05:31:56 PM PDT 24
Peak memory 249308 kb
Host smart-8c0459f7-a7b3-4fd0-9e02-f3f003d9da6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108307789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.3108307789
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.737005488
Short name T311
Test name
Test status
Simulation time 378225559 ps
CPU time 5.9 seconds
Started Jul 27 05:31:17 PM PDT 24
Finished Jul 27 05:31:23 PM PDT 24
Peak memory 233112 kb
Host smart-8e172652-dbb5-463e-a655-8150d2c05a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737005488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.737005488
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.4217458709
Short name T228
Test name
Test status
Simulation time 19267762947 ps
CPU time 170.16 seconds
Started Jul 27 05:31:24 PM PDT 24
Finished Jul 27 05:34:14 PM PDT 24
Peak memory 252576 kb
Host smart-4fbfa246-e7e4-43c3-b88b-b5688c2f927b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217458709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds
.4217458709
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_intercept.1834351848
Short name T189
Test name
Test status
Simulation time 14293638546 ps
CPU time 17.95 seconds
Started Jul 27 05:31:19 PM PDT 24
Finished Jul 27 05:31:37 PM PDT 24
Peak memory 224596 kb
Host smart-7d89cb3c-f226-4131-8188-10fd4af12020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834351848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.1834351848
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.2713702827
Short name T684
Test name
Test status
Simulation time 93182355599 ps
CPU time 182.48 seconds
Started Jul 27 05:31:14 PM PDT 24
Finished Jul 27 05:34:17 PM PDT 24
Peak memory 224660 kb
Host smart-8990b976-f50d-441a-8b96-50c90035fab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713702827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.2713702827
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.718908333
Short name T659
Test name
Test status
Simulation time 5219193921 ps
CPU time 16.27 seconds
Started Jul 27 05:31:18 PM PDT 24
Finished Jul 27 05:31:34 PM PDT 24
Peak memory 232904 kb
Host smart-3135a78e-ea73-4a54-abe6-496afbe17069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718908333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap.
718908333
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.1831866982
Short name T715
Test name
Test status
Simulation time 31637289 ps
CPU time 2.48 seconds
Started Jul 27 05:31:23 PM PDT 24
Finished Jul 27 05:31:25 PM PDT 24
Peak memory 232480 kb
Host smart-bde1fb6f-cda7-490b-89c8-7b75aca3487b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831866982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.1831866982
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.4208733129
Short name T552
Test name
Test status
Simulation time 224107169 ps
CPU time 4.7 seconds
Started Jul 27 05:31:18 PM PDT 24
Finished Jul 27 05:31:22 PM PDT 24
Peak memory 220980 kb
Host smart-e9cc81c7-a35c-4beb-a907-3b8860de8b72
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4208733129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.4208733129
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.3928829910
Short name T979
Test name
Test status
Simulation time 131205432 ps
CPU time 1.09 seconds
Started Jul 27 05:31:18 PM PDT 24
Finished Jul 27 05:31:19 PM PDT 24
Peak memory 207220 kb
Host smart-2700aed3-f681-454d-8be8-1613f6840b89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928829910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.3928829910
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.2321867860
Short name T602
Test name
Test status
Simulation time 41182742 ps
CPU time 0.74 seconds
Started Jul 27 05:31:25 PM PDT 24
Finished Jul 27 05:31:25 PM PDT 24
Peak memory 205816 kb
Host smart-6c70e059-42b2-449e-b86b-e1c89c050097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321867860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.2321867860
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.3654871355
Short name T136
Test name
Test status
Simulation time 4464951909 ps
CPU time 12.3 seconds
Started Jul 27 05:31:19 PM PDT 24
Finished Jul 27 05:31:31 PM PDT 24
Peak memory 216336 kb
Host smart-46b410d2-b045-4555-b2cb-bc2768cfd3af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654871355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.3654871355
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.904968512
Short name T351
Test name
Test status
Simulation time 113683753 ps
CPU time 1.04 seconds
Started Jul 27 05:31:25 PM PDT 24
Finished Jul 27 05:31:26 PM PDT 24
Peak memory 207548 kb
Host smart-9b201455-98f2-4021-bc77-573e1a8830ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904968512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.904968512
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.154673584
Short name T578
Test name
Test status
Simulation time 64569048 ps
CPU time 0.82 seconds
Started Jul 27 05:31:29 PM PDT 24
Finished Jul 27 05:31:30 PM PDT 24
Peak memory 206024 kb
Host smart-8afebe84-37af-47e5-b2fe-8ef53bf31787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154673584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.154673584
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.1565059933
Short name T394
Test name
Test status
Simulation time 8266707692 ps
CPU time 15.4 seconds
Started Jul 27 05:31:19 PM PDT 24
Finished Jul 27 05:31:35 PM PDT 24
Peak memory 232840 kb
Host smart-f0cd5862-1ac7-443b-bf1d-46702a330613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565059933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.1565059933
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.1169351508
Short name T572
Test name
Test status
Simulation time 31346431 ps
CPU time 0.7 seconds
Started Jul 27 05:31:23 PM PDT 24
Finished Jul 27 05:31:24 PM PDT 24
Peak memory 204924 kb
Host smart-ddea7436-e164-4c05-9ecc-c2c082ad2d57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169351508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.1
169351508
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.3539903825
Short name T660
Test name
Test status
Simulation time 114992129 ps
CPU time 3.13 seconds
Started Jul 27 05:31:21 PM PDT 24
Finished Jul 27 05:31:24 PM PDT 24
Peak memory 224700 kb
Host smart-d701d230-a21e-4c7c-91f1-9adcb0145495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539903825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.3539903825
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.1912319836
Short name T319
Test name
Test status
Simulation time 22452871 ps
CPU time 0.84 seconds
Started Jul 27 05:31:19 PM PDT 24
Finished Jul 27 05:31:20 PM PDT 24
Peak memory 206584 kb
Host smart-e5c01df3-c78a-4e9c-8841-97b0330e53f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912319836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.1912319836
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.1083702533
Short name T528
Test name
Test status
Simulation time 62754871370 ps
CPU time 139.92 seconds
Started Jul 27 05:31:16 PM PDT 24
Finished Jul 27 05:33:36 PM PDT 24
Peak memory 252112 kb
Host smart-799ce690-78b7-4097-9335-212325b043f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083702533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.1083702533
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.866950634
Short name T549
Test name
Test status
Simulation time 5593142025 ps
CPU time 52.3 seconds
Started Jul 27 05:31:30 PM PDT 24
Finished Jul 27 05:32:22 PM PDT 24
Peak memory 261096 kb
Host smart-e660953f-ddf8-48da-9eb1-3b95d5c50040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866950634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.866950634
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.2093757276
Short name T199
Test name
Test status
Simulation time 22899534057 ps
CPU time 100.17 seconds
Started Jul 27 05:31:18 PM PDT 24
Finished Jul 27 05:32:58 PM PDT 24
Peak memory 257136 kb
Host smart-650f32d4-b354-4c05-8faa-b58b90738450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093757276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.2093757276
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.3288454214
Short name T929
Test name
Test status
Simulation time 1354677158 ps
CPU time 19.98 seconds
Started Jul 27 05:31:23 PM PDT 24
Finished Jul 27 05:31:43 PM PDT 24
Peak memory 224620 kb
Host smart-3d0b716b-c275-474b-b14b-775734dbaa6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288454214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.3288454214
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.1722381281
Short name T274
Test name
Test status
Simulation time 9149730457 ps
CPU time 118.85 seconds
Started Jul 27 05:31:22 PM PDT 24
Finished Jul 27 05:33:21 PM PDT 24
Peak memory 255492 kb
Host smart-c8dd3089-f947-46cc-93ae-705b4ff7c430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722381281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds
.1722381281
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/6.spi_device_intercept.1104184469
Short name T608
Test name
Test status
Simulation time 6377703562 ps
CPU time 11.93 seconds
Started Jul 27 05:31:24 PM PDT 24
Finished Jul 27 05:31:36 PM PDT 24
Peak memory 232920 kb
Host smart-890f12f2-29ec-4c6b-8b4a-c3e25d479b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104184469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.1104184469
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.1873573097
Short name T915
Test name
Test status
Simulation time 1530626540 ps
CPU time 5.79 seconds
Started Jul 27 05:31:16 PM PDT 24
Finished Jul 27 05:31:22 PM PDT 24
Peak memory 232820 kb
Host smart-263394b4-1fd2-455d-b743-56bf545a78cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873573097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.1873573097
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.478830828
Short name T726
Test name
Test status
Simulation time 5189651964 ps
CPU time 7.79 seconds
Started Jul 27 05:31:17 PM PDT 24
Finished Jul 27 05:31:25 PM PDT 24
Peak memory 240444 kb
Host smart-aed7198a-50ab-4fd3-8711-fad80023d944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478830828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap.
478830828
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.2816436436
Short name T377
Test name
Test status
Simulation time 75875419 ps
CPU time 2.3 seconds
Started Jul 27 05:31:17 PM PDT 24
Finished Jul 27 05:31:20 PM PDT 24
Peak memory 223904 kb
Host smart-79e3cdbb-13ed-4d4b-9dd0-e9b51d05f242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816436436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.2816436436
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.2335876481
Short name T943
Test name
Test status
Simulation time 1339599189 ps
CPU time 7.75 seconds
Started Jul 27 05:31:21 PM PDT 24
Finished Jul 27 05:31:29 PM PDT 24
Peak memory 223352 kb
Host smart-b555cef5-280f-46f7-9c5d-329776ac9062
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2335876481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.2335876481
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.2201853118
Short name T718
Test name
Test status
Simulation time 19193585501 ps
CPU time 113.08 seconds
Started Jul 27 05:31:17 PM PDT 24
Finished Jul 27 05:33:10 PM PDT 24
Peak memory 251276 kb
Host smart-f3a78528-5930-41e3-a312-85430bc31d0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201853118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.2201853118
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.1804814243
Short name T815
Test name
Test status
Simulation time 840953779 ps
CPU time 9.03 seconds
Started Jul 27 05:31:20 PM PDT 24
Finished Jul 27 05:31:29 PM PDT 24
Peak memory 219412 kb
Host smart-dafd22b7-a857-4aa9-b9a7-fa4833250891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804814243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.1804814243
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.4241117649
Short name T354
Test name
Test status
Simulation time 473837082 ps
CPU time 1.26 seconds
Started Jul 27 05:31:24 PM PDT 24
Finished Jul 27 05:31:26 PM PDT 24
Peak memory 207072 kb
Host smart-055600a6-e187-4f35-9e62-443b32ad92a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241117649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.4241117649
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.2993099657
Short name T974
Test name
Test status
Simulation time 401412255 ps
CPU time 9.54 seconds
Started Jul 27 05:31:19 PM PDT 24
Finished Jul 27 05:31:28 PM PDT 24
Peak memory 216216 kb
Host smart-4ac4c85b-1c41-407e-92b9-0838f790f0b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993099657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.2993099657
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.2577444856
Short name T432
Test name
Test status
Simulation time 168375895 ps
CPU time 0.83 seconds
Started Jul 27 05:31:24 PM PDT 24
Finished Jul 27 05:31:26 PM PDT 24
Peak memory 206012 kb
Host smart-5b9b62db-888a-456e-b90d-6a2aa63c028e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577444856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.2577444856
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.1570274291
Short name T893
Test name
Test status
Simulation time 17375966599 ps
CPU time 15.47 seconds
Started Jul 27 05:31:30 PM PDT 24
Finished Jul 27 05:31:46 PM PDT 24
Peak memory 224604 kb
Host smart-844f592e-2458-4384-9485-8317360e4f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570274291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.1570274291
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.3391343182
Short name T585
Test name
Test status
Simulation time 59863877 ps
CPU time 0.72 seconds
Started Jul 27 05:31:40 PM PDT 24
Finished Jul 27 05:31:41 PM PDT 24
Peak memory 205828 kb
Host smart-3da6c70b-c5ab-4183-bce1-2cba7848befc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391343182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.3
391343182
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.2518066307
Short name T60
Test name
Test status
Simulation time 3883286287 ps
CPU time 8.03 seconds
Started Jul 27 05:31:28 PM PDT 24
Finished Jul 27 05:31:36 PM PDT 24
Peak memory 224592 kb
Host smart-b09be3a5-f619-4cf1-b375-f379c2aecf6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518066307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.2518066307
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.769159096
Short name T12
Test name
Test status
Simulation time 19951184 ps
CPU time 0.77 seconds
Started Jul 27 05:31:31 PM PDT 24
Finished Jul 27 05:31:32 PM PDT 24
Peak memory 206740 kb
Host smart-2f2b614a-813f-4f07-ac8b-e16924c68e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769159096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.769159096
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.2107209495
Short name T556
Test name
Test status
Simulation time 42773253 ps
CPU time 0.82 seconds
Started Jul 27 05:31:30 PM PDT 24
Finished Jul 27 05:31:31 PM PDT 24
Peak memory 216100 kb
Host smart-739abcd4-98aa-4c32-8b1b-992a8c745f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107209495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.2107209495
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.3470445169
Short name T396
Test name
Test status
Simulation time 15616730089 ps
CPU time 62.98 seconds
Started Jul 27 05:31:28 PM PDT 24
Finished Jul 27 05:32:31 PM PDT 24
Peak memory 250776 kb
Host smart-c95f76be-cbfc-4a1b-a29b-3a4645f153a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470445169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.3470445169
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.458035871
Short name T651
Test name
Test status
Simulation time 28867169010 ps
CPU time 77.14 seconds
Started Jul 27 05:31:28 PM PDT 24
Finished Jul 27 05:32:46 PM PDT 24
Peak memory 257444 kb
Host smart-1c2df84a-c7b8-4423-8e3a-7f11425cc7eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458035871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle.
458035871
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.2235135021
Short name T738
Test name
Test status
Simulation time 6345981563 ps
CPU time 24.11 seconds
Started Jul 27 05:31:30 PM PDT 24
Finished Jul 27 05:31:54 PM PDT 24
Peak memory 249208 kb
Host smart-c0422c32-be36-428a-bdf8-f8c6a3218e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235135021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.2235135021
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.3046616187
Short name T860
Test name
Test status
Simulation time 750032616 ps
CPU time 14.26 seconds
Started Jul 27 05:31:28 PM PDT 24
Finished Jul 27 05:31:42 PM PDT 24
Peak memory 232860 kb
Host smart-809de165-d387-47a8-8896-5be682dcf984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046616187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds
.3046616187
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.573973598
Short name T238
Test name
Test status
Simulation time 1199877927 ps
CPU time 5.1 seconds
Started Jul 27 05:31:28 PM PDT 24
Finished Jul 27 05:31:34 PM PDT 24
Peak memory 224892 kb
Host smart-ece6bb8a-f865-405c-b74d-dd6b77ec60bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573973598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.573973598
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.228471039
Short name T339
Test name
Test status
Simulation time 14293340197 ps
CPU time 41.59 seconds
Started Jul 27 05:31:30 PM PDT 24
Finished Jul 27 05:32:12 PM PDT 24
Peak memory 241068 kb
Host smart-57f14224-18b7-4537-9881-df3a049612dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228471039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.228471039
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.4222085215
Short name T214
Test name
Test status
Simulation time 640307094 ps
CPU time 4.3 seconds
Started Jul 27 05:31:30 PM PDT 24
Finished Jul 27 05:31:34 PM PDT 24
Peak memory 224612 kb
Host smart-9423a7a5-559c-48c4-b907-e6fe10a92a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222085215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.4222085215
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.1176328824
Short name T597
Test name
Test status
Simulation time 589520856 ps
CPU time 5.7 seconds
Started Jul 27 05:31:27 PM PDT 24
Finished Jul 27 05:31:33 PM PDT 24
Peak memory 232800 kb
Host smart-5dc67831-e4c2-4136-989f-c404db62c5c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176328824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.1176328824
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.2941830843
Short name T566
Test name
Test status
Simulation time 819664636 ps
CPU time 11.51 seconds
Started Jul 27 05:31:25 PM PDT 24
Finished Jul 27 05:31:37 PM PDT 24
Peak memory 220228 kb
Host smart-6a6de58a-eeb9-400a-ae7f-fecbb87577bf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2941830843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.2941830843
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.2996533806
Short name T271
Test name
Test status
Simulation time 20245435887 ps
CPU time 113.25 seconds
Started Jul 27 05:31:40 PM PDT 24
Finished Jul 27 05:33:34 PM PDT 24
Peak memory 265672 kb
Host smart-f26bfb35-d1f6-4414-9ac3-63e0772f962c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996533806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.2996533806
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.18990740
Short name T768
Test name
Test status
Simulation time 1513672660 ps
CPU time 20.89 seconds
Started Jul 27 05:31:28 PM PDT 24
Finished Jul 27 05:31:49 PM PDT 24
Peak memory 216372 kb
Host smart-a503a378-70a4-441a-871d-b119f31e30ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18990740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.18990740
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.484609628
Short name T443
Test name
Test status
Simulation time 8846163528 ps
CPU time 4.69 seconds
Started Jul 27 05:31:29 PM PDT 24
Finished Jul 27 05:31:33 PM PDT 24
Peak memory 216416 kb
Host smart-c49fdf84-feb8-4bb1-a152-6170aaaa4450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484609628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.484609628
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.4020129858
Short name T801
Test name
Test status
Simulation time 104010884 ps
CPU time 1.2 seconds
Started Jul 27 05:31:29 PM PDT 24
Finished Jul 27 05:31:30 PM PDT 24
Peak memory 216352 kb
Host smart-5bdb42a7-ae2e-4603-a027-5e3909b4dc9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020129858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.4020129858
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.4142148034
Short name T665
Test name
Test status
Simulation time 105394553 ps
CPU time 1.06 seconds
Started Jul 27 05:31:27 PM PDT 24
Finished Jul 27 05:31:29 PM PDT 24
Peak memory 207100 kb
Host smart-f0ebd26b-6d11-4350-87e6-5e6180ba5af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142148034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.4142148034
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.2599136805
Short name T653
Test name
Test status
Simulation time 442641939 ps
CPU time 2.48 seconds
Started Jul 27 05:31:27 PM PDT 24
Finished Jul 27 05:31:30 PM PDT 24
Peak memory 224124 kb
Host smart-5dc13b17-7943-433e-a7f0-25d4b19c6d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599136805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.2599136805
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.3470843934
Short name T467
Test name
Test status
Simulation time 18299043 ps
CPU time 0.77 seconds
Started Jul 27 05:31:50 PM PDT 24
Finished Jul 27 05:31:51 PM PDT 24
Peak memory 205560 kb
Host smart-e8a9b0b8-43cb-45f4-873c-b5db1076b64d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470843934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.3
470843934
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.578466463
Short name T439
Test name
Test status
Simulation time 75632850 ps
CPU time 2.34 seconds
Started Jul 27 05:31:41 PM PDT 24
Finished Jul 27 05:31:43 PM PDT 24
Peak memory 224580 kb
Host smart-13450844-bd57-474d-a1ee-151373baa4c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578466463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.578466463
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.2849778894
Short name T337
Test name
Test status
Simulation time 28120163 ps
CPU time 0.79 seconds
Started Jul 27 05:31:41 PM PDT 24
Finished Jul 27 05:31:42 PM PDT 24
Peak memory 205624 kb
Host smart-4b4eb1f3-3bdb-4a9d-9a85-52b38be80a66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849778894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.2849778894
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.2865104713
Short name T353
Test name
Test status
Simulation time 15395353801 ps
CPU time 73.43 seconds
Started Jul 27 05:31:54 PM PDT 24
Finished Jul 27 05:33:07 PM PDT 24
Peak memory 249384 kb
Host smart-cc68faf2-d26f-47e3-ae03-c568bd3ba9a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865104713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.2865104713
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.1937571085
Short name T210
Test name
Test status
Simulation time 71305839014 ps
CPU time 144.98 seconds
Started Jul 27 05:31:53 PM PDT 24
Finished Jul 27 05:34:18 PM PDT 24
Peak memory 241052 kb
Host smart-8e7a2724-a008-45cd-952a-971d0d23897f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937571085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.1937571085
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.4249049792
Short name T530
Test name
Test status
Simulation time 3326475241 ps
CPU time 8.24 seconds
Started Jul 27 05:31:53 PM PDT 24
Finished Jul 27 05:32:02 PM PDT 24
Peak memory 217724 kb
Host smart-7f74d4a0-e249-4e4b-9c94-66b77a087c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249049792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.4249049792
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.727279595
Short name T442
Test name
Test status
Simulation time 372801263 ps
CPU time 6.05 seconds
Started Jul 27 05:31:39 PM PDT 24
Finished Jul 27 05:31:46 PM PDT 24
Peak memory 232856 kb
Host smart-c0c0195d-6cee-4e0e-80b9-18fee6444a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727279595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.727279595
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.3874826107
Short name T218
Test name
Test status
Simulation time 14570081852 ps
CPU time 39.37 seconds
Started Jul 27 05:31:41 PM PDT 24
Finished Jul 27 05:32:21 PM PDT 24
Peak memory 249548 kb
Host smart-d76799cb-56e7-4ae2-9e1d-1bee3e94e677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874826107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds
.3874826107
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/8.spi_device_intercept.3859578364
Short name T965
Test name
Test status
Simulation time 292265305 ps
CPU time 2.11 seconds
Started Jul 27 05:31:41 PM PDT 24
Finished Jul 27 05:31:43 PM PDT 24
Peak memory 223896 kb
Host smart-94018c52-a5da-4288-b6c9-b354de4b859a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859578364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.3859578364
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.620911984
Short name T1005
Test name
Test status
Simulation time 4052569154 ps
CPU time 17.92 seconds
Started Jul 27 05:31:41 PM PDT 24
Finished Jul 27 05:31:59 PM PDT 24
Peak memory 241088 kb
Host smart-6727b524-0fd7-4cba-bb5e-afea8e4d84cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620911984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.620911984
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.2379673798
Short name T705
Test name
Test status
Simulation time 4628772757 ps
CPU time 6.7 seconds
Started Jul 27 05:31:43 PM PDT 24
Finished Jul 27 05:31:50 PM PDT 24
Peak memory 233132 kb
Host smart-1b6e343b-a20c-4f2c-abc1-82e6db8d3770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379673798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.2379673798
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.3779997614
Short name T329
Test name
Test status
Simulation time 7308535122 ps
CPU time 8.81 seconds
Started Jul 27 05:31:42 PM PDT 24
Finished Jul 27 05:31:52 PM PDT 24
Peak memory 232852 kb
Host smart-8084d667-cb28-44f8-9691-862fb48f3769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779997614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.3779997614
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.4283081049
Short name T728
Test name
Test status
Simulation time 146942375 ps
CPU time 3.88 seconds
Started Jul 27 05:31:39 PM PDT 24
Finished Jul 27 05:31:43 PM PDT 24
Peak memory 221080 kb
Host smart-27947dac-2f39-4e4c-9c6c-1ba956eee87f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4283081049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.4283081049
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.3233796362
Short name T213
Test name
Test status
Simulation time 6791950116 ps
CPU time 111.12 seconds
Started Jul 27 05:31:52 PM PDT 24
Finished Jul 27 05:33:44 PM PDT 24
Peak memory 263388 kb
Host smart-0234c362-b0b0-4f16-b42c-9d377d9a95eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233796362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.3233796362
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.2344549518
Short name T853
Test name
Test status
Simulation time 2749553280 ps
CPU time 14.31 seconds
Started Jul 27 05:31:42 PM PDT 24
Finished Jul 27 05:31:57 PM PDT 24
Peak memory 216400 kb
Host smart-6da7297e-f366-40ec-ad73-7394ee96aed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344549518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.2344549518
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.1956859727
Short name T459
Test name
Test status
Simulation time 6421332581 ps
CPU time 4.51 seconds
Started Jul 27 05:31:41 PM PDT 24
Finished Jul 27 05:31:46 PM PDT 24
Peak memory 216464 kb
Host smart-039da921-8178-4ce2-aa71-1d7d6f9358be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956859727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.1956859727
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.2722208358
Short name T680
Test name
Test status
Simulation time 122994326 ps
CPU time 1 seconds
Started Jul 27 05:31:40 PM PDT 24
Finished Jul 27 05:31:41 PM PDT 24
Peak memory 207976 kb
Host smart-1740dce2-09b7-4d1c-954c-7568a6d414b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722208358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.2722208358
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.2220982505
Short name T871
Test name
Test status
Simulation time 82716641 ps
CPU time 0.78 seconds
Started Jul 27 05:31:43 PM PDT 24
Finished Jul 27 05:31:44 PM PDT 24
Peak memory 206016 kb
Host smart-6ba28d0e-0156-45fc-82b5-2348cfbc71c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220982505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.2220982505
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.2716553335
Short name T793
Test name
Test status
Simulation time 785685114 ps
CPU time 8.66 seconds
Started Jul 27 05:31:43 PM PDT 24
Finished Jul 27 05:31:52 PM PDT 24
Peak memory 240760 kb
Host smart-2d84ae75-9c24-4c59-ba73-9512fa0a5830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716553335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.2716553335
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.4154735102
Short name T406
Test name
Test status
Simulation time 14976287 ps
CPU time 0.74 seconds
Started Jul 27 05:31:51 PM PDT 24
Finished Jul 27 05:31:52 PM PDT 24
Peak memory 204872 kb
Host smart-655b88fa-7578-402b-9529-8f1303a3035c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154735102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.4
154735102
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.3597417044
Short name T584
Test name
Test status
Simulation time 1688454150 ps
CPU time 6.36 seconds
Started Jul 27 05:31:52 PM PDT 24
Finished Jul 27 05:31:59 PM PDT 24
Peak memory 224608 kb
Host smart-1f47a7c7-e5d7-49b4-ab35-99124ec8c25c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597417044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.3597417044
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.986527748
Short name T11
Test name
Test status
Simulation time 34220659 ps
CPU time 0.77 seconds
Started Jul 27 05:31:55 PM PDT 24
Finished Jul 27 05:31:56 PM PDT 24
Peak memory 206940 kb
Host smart-a7a6cda6-5ed6-4602-aea3-6c3b559145e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986527748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.986527748
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.2747459720
Short name T498
Test name
Test status
Simulation time 751903836 ps
CPU time 7.97 seconds
Started Jul 27 05:31:55 PM PDT 24
Finished Jul 27 05:32:03 PM PDT 24
Peak memory 236332 kb
Host smart-68e7acdc-82ec-4667-b663-b0b440bc4858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747459720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.2747459720
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.3503482844
Short name T909
Test name
Test status
Simulation time 3178310428 ps
CPU time 77.5 seconds
Started Jul 27 05:31:55 PM PDT 24
Finished Jul 27 05:33:13 PM PDT 24
Peak memory 254948 kb
Host smart-f2a42243-d55c-4707-86df-812ccc6c4d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503482844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.3503482844
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.1904721290
Short name T188
Test name
Test status
Simulation time 26110834363 ps
CPU time 280.85 seconds
Started Jul 27 05:31:55 PM PDT 24
Finished Jul 27 05:36:36 PM PDT 24
Peak memory 255868 kb
Host smart-2b22057e-9442-4b61-a670-9a7c7ba115e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904721290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.1904721290
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.1720095010
Short name T869
Test name
Test status
Simulation time 2183235122 ps
CPU time 5.05 seconds
Started Jul 27 05:31:52 PM PDT 24
Finished Jul 27 05:31:57 PM PDT 24
Peak memory 232892 kb
Host smart-4d27cf3e-b916-4454-a15c-8ac3b902d82f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720095010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.1720095010
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.2349941100
Short name T944
Test name
Test status
Simulation time 70830573256 ps
CPU time 294.86 seconds
Started Jul 27 05:31:53 PM PDT 24
Finished Jul 27 05:36:48 PM PDT 24
Peak memory 259304 kb
Host smart-28456114-9d01-48cf-bdb2-d18963ed4e4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349941100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds
.2349941100
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.2650690887
Short name T470
Test name
Test status
Simulation time 3741903595 ps
CPU time 7.74 seconds
Started Jul 27 05:31:52 PM PDT 24
Finished Jul 27 05:32:00 PM PDT 24
Peak memory 232764 kb
Host smart-cf05eac0-7406-4e0e-ab2e-976267b5f8f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650690887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.2650690887
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.2852430622
Short name T206
Test name
Test status
Simulation time 23298196090 ps
CPU time 32.59 seconds
Started Jul 27 05:31:53 PM PDT 24
Finished Jul 27 05:32:26 PM PDT 24
Peak memory 224664 kb
Host smart-570484e4-d14d-4583-bb25-ac00bbd65737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852430622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.2852430622
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.1483483932
Short name T134
Test name
Test status
Simulation time 4016062926 ps
CPU time 9.25 seconds
Started Jul 27 05:31:55 PM PDT 24
Finished Jul 27 05:32:05 PM PDT 24
Peak memory 224868 kb
Host smart-320c2fe2-d8eb-4011-9966-0e9898f1518c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483483932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.1483483932
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.2468479088
Short name T984
Test name
Test status
Simulation time 4704668506 ps
CPU time 13.43 seconds
Started Jul 27 05:31:51 PM PDT 24
Finished Jul 27 05:32:05 PM PDT 24
Peak memory 233928 kb
Host smart-9dac8597-99d2-4e2b-aa3d-86d39a27419c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468479088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.2468479088
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.2239831241
Short name T492
Test name
Test status
Simulation time 1058597670 ps
CPU time 11.81 seconds
Started Jul 27 05:31:55 PM PDT 24
Finished Jul 27 05:32:07 PM PDT 24
Peak memory 220860 kb
Host smart-a2485679-f389-4f63-9477-03cb8d672fe9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2239831241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.2239831241
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.1618048137
Short name T807
Test name
Test status
Simulation time 87787543 ps
CPU time 1.02 seconds
Started Jul 27 05:31:52 PM PDT 24
Finished Jul 27 05:31:53 PM PDT 24
Peak memory 207188 kb
Host smart-cab91cf3-be0d-4ac4-9778-f5716fc3d513
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618048137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.1618048137
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.262216593
Short name T774
Test name
Test status
Simulation time 12093871015 ps
CPU time 32.5 seconds
Started Jul 27 05:31:53 PM PDT 24
Finished Jul 27 05:32:26 PM PDT 24
Peak memory 216620 kb
Host smart-afc24e29-dae1-48d6-9ea6-bbaab99b44b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262216593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.262216593
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.3149137334
Short name T957
Test name
Test status
Simulation time 1300196229 ps
CPU time 6.31 seconds
Started Jul 27 05:31:51 PM PDT 24
Finished Jul 27 05:31:58 PM PDT 24
Peak memory 216324 kb
Host smart-bb30692b-b5d7-47f9-baf0-13e99d10ef4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149137334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.3149137334
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.1350084574
Short name T925
Test name
Test status
Simulation time 139607472 ps
CPU time 1.14 seconds
Started Jul 27 05:31:52 PM PDT 24
Finished Jul 27 05:31:53 PM PDT 24
Peak memory 207944 kb
Host smart-a30f02df-9b5e-4097-950d-f5f57e198c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350084574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.1350084574
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.1917174405
Short name T980
Test name
Test status
Simulation time 28600317 ps
CPU time 0.81 seconds
Started Jul 27 05:31:51 PM PDT 24
Finished Jul 27 05:31:52 PM PDT 24
Peak memory 206076 kb
Host smart-4a6c85b7-a044-4ce3-8491-02a8fc262dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917174405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.1917174405
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.2950990316
Short name T44
Test name
Test status
Simulation time 14627741954 ps
CPU time 12.08 seconds
Started Jul 27 05:31:52 PM PDT 24
Finished Jul 27 05:32:05 PM PDT 24
Peak memory 224548 kb
Host smart-908fe9bb-fac4-4890-80d8-1741a314cc36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950990316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.2950990316
Directory /workspace/9.spi_device_upload/latest
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